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diff --git a/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss b/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss index 4f29e5f1..f5bb0a3 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss +++ b/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss @@ -50,12 +50,24 @@ Where: /sys/bus/pci/devices/<dev>/ccissX/cXdY/raid_level Date: August 2009 Kernel Version: 2.6.31 Contact: iss_storagedev@hp.com Description: Displays the RAID level of logical drive Y of controller X. Where: /sys/bus/pci/devices/<dev>/ccissX/cXdY/usage_count Date: August 2009 Kernel Version: 2.6.31 Contact: iss_storagedev@hp.com Description: Displays the usage count (number of opens) of logical drive Y of controller X. + +Where: /sys/bus/pci/devices/<dev>/ccissX/resettable +Date: February 2011 +Kernel Version: 2.6.38 +Contact: iss_storagedev@hp.com +Description: Value of 1 indicates the controller can honor the reset_devices + kernel parameter. Value of 0 indicates reset_devices cannot be + honored. This is to allow, for example, kexec tools to be able + to warn the user if they designate an unresettable device as + a dump device, as kdump requires resetting the device in order + to work reliably. + diff --git a/Documentation/ABI/testing/sysfs-driver-samsung-laptop b/Documentation/ABI/testing/sysfs-driver-samsung-laptop new file mode 100644 index 0000000..0a81023 --- a/dev/null +++ b/Documentation/ABI/testing/sysfs-driver-samsung-laptop @@ -0,0 +1,19 @@ +What: /sys/devices/platform/samsung/performance_level +Date: January 1, 2010 +KernelVersion: 2.6.33 +Contact: Greg Kroah-Hartman <gregkh@suse.de> +Description: Some Samsung laptops have different "performance levels" + that are can be modified by a function key, and by this + sysfs file. These values don't always make a whole lot + of sense, but some users like to modify them to keep + their fans quiet at all costs. Reading from this file + will show the current performance level. Writing to the + file can change this value. + Valid options: + "silent" + "normal" + "overclock" + Note that not all laptops support all of these options. + Specifically, not all support the "overclock" option, + and it's still unknown if this value even changes + anything, other than making the user feel a bit better. diff --git a/Documentation/ABI/testing/sysfs-platform-asus-wmi b/Documentation/ABI/testing/sysfs-platform-asus-wmi new file mode 100644 index 0000000..2e7df91 --- a/dev/null +++ b/Documentation/ABI/testing/sysfs-platform-asus-wmi @@ -0,0 +1,31 @@ +What: /sys/devices/platform/<platform>/cpufv +Date: Oct 2010 +KernelVersion: 2.6.37 +Contact: "Corentin Chary" <corentincj@iksaif.net> +Description: + Change CPU clock configuration (write-only). + There are three available clock configuration: + * 0 -> Super Performance Mode + * 1 -> High Performance Mode + * 2 -> Power Saving Mode + +What: /sys/devices/platform/<platform>/camera +Date: Jan 2010 +KernelVersion: 2.6.39 +Contact: "Corentin Chary" <corentincj@iksaif.net> +Description: + Control the camera. 1 means on, 0 means off. + +What: /sys/devices/platform/<platform>/cardr +Date: Jan 2010 +KernelVersion: 2.6.39 +Contact: "Corentin Chary" <corentincj@iksaif.net> +Description: + Control the card reader. 1 means on, 0 means off. + +What: /sys/devices/platform/<platform>/touchpad +Date: Jan 2010 +KernelVersion: 2.6.39 +Contact: "Corentin Chary" <corentincj@iksaif.net> +Description: + Control the card touchpad. 1 means on, 0 means off. diff --git a/Documentation/ABI/testing/sysfs-platform-eeepc-wmi b/Documentation/ABI/testing/sysfs-platform-eeepc-wmi deleted file mode 100644 index e4b5fef..0000000 --- a/Documentation/ABI/testing/sysfs-platform-eeepc-wmi +++ b/dev/null @@ -1,10 +0,0 @@ -What: /sys/devices/platform/eeepc-wmi/cpufv -Date: Oct 2010 -KernelVersion: 2.6.37 -Contact: "Corentin Chary" <corentincj@iksaif.net> -Description: - Change CPU clock configuration (write-only). - There are three available clock configuration: - * 0 -> Super Performance Mode - * 1 -> High Performance Mode - * 2 -> Power Saving Mode diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile index 2deb069..8436b01 100644 --- a/Documentation/DocBook/Makefile +++ b/Documentation/DocBook/Makefile @@ -46,25 +46,24 @@ pdfdocs: $(PDF) HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS))) htmldocs: $(HTML) xmldoclinks $(call build_main_index) $(call build_images) MAN := $(patsubst %.xml, %.9, $(BOOKS)) mandocs: $(MAN) build_images = mkdir -p $(objtree)/Documentation/DocBook/media/ && \ cp $(srctree)/Documentation/DocBook/dvb/*.png \ $(srctree)/Documentation/DocBook/v4l/*.gif \ - $(srctree)/Documentation/DocBook/v4l/*.png \ $(objtree)/Documentation/DocBook/media/ xmldoclinks: ifneq ($(objtree),$(srctree)) for dep in dvb media-entities.tmpl media-indices.tmpl v4l; do \ rm -f $(objtree)/Documentation/DocBook/$$dep \ && ln -s $(srctree)/Documentation/DocBook/$$dep $(objtree)/Documentation/DocBook/ \ || exit; \ done endif installmandocs: mandocs diff --git a/Documentation/DocBook/rapidio.tmpl b/Documentation/DocBook/rapidio.tmpl index 54eb26b..5047936 100644 --- a/Documentation/DocBook/rapidio.tmpl +++ b/Documentation/DocBook/rapidio.tmpl @@ -124,25 +124,24 @@ </sect1> <sect1 id="Driver_functionality"><title>Driver functionality</title> !Idrivers/rapidio/rio.c !Idrivers/rapidio/rio-access.c </sect1> <sect1 id="Device_model_support"><title>Device model support</title> !Idrivers/rapidio/rio-driver.c </sect1> <sect1 id="Sysfs_support"><title>Sysfs support</title> !Idrivers/rapidio/rio-sysfs.c </sect1> <sect1 id="PPC32_support"><title>PPC32 support</title> -!Earch/powerpc/sysdev/fsl_rio.c !Iarch/powerpc/sysdev/fsl_rio.c </sect1> </chapter> <chapter id="credits"> <title>Credits</title> <para> The following people have contributed to the RapidIO subsystem directly or indirectly: <orderedlist> <listitem><para>Matt Porter<email>mporter@kernel.crashing.org</email></para></listitem> <listitem><para>Randy Vinson<email>rvinson@mvista.com</email></para></listitem> diff --git a/Documentation/development-process/1.Intro b/Documentation/development-process/1.Intro index 8cc2cba..9b61448 100644 --- a/Documentation/development-process/1.Intro +++ b/Documentation/development-process/1.Intro @@ -47,31 +47,31 @@ development process; this section offers a number of tips on how to avoid problems at this important stage. Developers are cautioned against assuming that the job is done when a patch is merged into the mainline. Section 7 introduces a couple of "advanced" topics: managing patches with git and reviewing patches posted by others. Section 8 concludes the document with pointers to sources for more information on kernel development. 1.2: WHAT THIS DOCUMENT IS ABOUT -The Linux kernel, at over 6 million lines of code and well over 1000 active -contributors, is one of the largest and most active free software projects -in existence. Since its humble beginning in 1991, this kernel has evolved -into a best-of-breed operating system component which runs on pocket-sized -digital music players, desktop PCs, the largest supercomputers in -existence, and all types of systems in between. It is a robust, efficient, -and scalable solution for almost any situation. +The Linux kernel, at over 8 million lines of code and well over 1000 +contributors to each release, is one of the largest and most active free +software projects in existence. Since its humble beginning in 1991, this +kernel has evolved into a best-of-breed operating system component which +runs on pocket-sized digital music players, desktop PCs, the largest +supercomputers in existence, and all types of systems in between. It is a +robust, efficient, and scalable solution for almost any situation. With the growth of Linux has come an increase in the number of developers (and companies) wishing to participate in its development. Hardware vendors want to ensure that Linux supports their products well, making those products attractive to Linux users. Embedded systems vendors, who use Linux as a component in an integrated product, want Linux to be as capable and well-suited to the task at hand as possible. Distributors and other software vendors who base their products on Linux have a clear interest in the capabilities, performance, and reliability of the Linux kernel. And end users, too, will often wish to change Linux to make it better suit their needs. @@ -106,25 +106,25 @@ frustrating experience. There is a lot of material here, but the effort involved in reading it will be repaid in short order. The development community is always in need of developers who will help to make the kernel better; the following text should help you - or those who work for you - join our community. 1.3: CREDITS This document was written by Jonathan Corbet, corbet@lwn.net. It has been improved by comments from Johannes Berg, James Berry, Alex Chiang, Roland Dreier, Randy Dunlap, Jake Edge, Jiri Kosina, Matt Mackall, Arthur Marsh, Amanda McPherson, Andrew Morton, Andrew Price, Tsugikazu Shibata, and -Jochen Voß. +Jochen Voß. This work was supported by the Linux Foundation; thanks especially to Amanda McPherson, who saw the value of this effort and made it all happen. 1.4: THE IMPORTANCE OF GETTING CODE INTO THE MAINLINE Some companies and developers occasionally wonder why they should bother learning how to work with the kernel community and get their code into the mainline kernel (the "mainline" being the kernel maintained by Linus Torvalds and used as a base by Linux distributors). In the short term, contributing code can look like an avoidable expense; it seems easier to @@ -212,25 +212,25 @@ include: users to get support from the community. - Support is also harder for distributors of binary-only modules, who must provide a version of the module for every distribution and every kernel version they wish to support. Dozens of builds of a single module can be required to provide reasonably comprehensive coverage, and your users will have to upgrade your module separately every time they upgrade their kernel. - Everything that was said above about code review applies doubly to closed-source code. Since this code is not available at all, it cannot have been reviewed by the community and will, beyond doubt, have serious - problems. + problems. Makers of embedded systems, in particular, may be tempted to disregard much of what has been said in this section in the belief that they are shipping a self-contained product which uses a frozen kernel version and requires no more development after its release. This argument misses the value of widespread code review and the value of allowing your users to add capabilities to your product. But these products, too, have a limited commercial life, after which a new version must be released. At that point, vendors whose code is in the mainline and well maintained will be much better positioned to get the new product ready for market quickly. diff --git a/Documentation/development-process/2.Process b/Documentation/development-process/2.Process index 911a451..4823577 100644 --- a/Documentation/development-process/2.Process +++ b/Documentation/development-process/2.Process @@ -5,141 +5,147 @@ with relatively small numbers of users and developers involved. With a user base in the millions and with some 2,000 developers involved over the course of one year, the kernel has since had to evolve a number of processes to keep development happening smoothly. A solid understanding of how the process works is required in order to be an effective part of it. 2.1: THE BIG PICTURE The kernel developers use a loosely time-based release process, with a new major kernel release happening every two or three months. The recent release history looks like this: - 2.6.26 July 13, 2008 - 2.6.25 April 16, 2008 - 2.6.24 January 24, 2008 - 2.6.23 October 9, 2007 - 2.6.22 July 8, 2007 - 2.6.21 April 25, 2007 - 2.6.20 February 4, 2007 + 2.6.38 March 14, 2011 + 2.6.37 January 4, 2011 + 2.6.36 October 20, 2010 + 2.6.35 August 1, 2010 + 2.6.34 May 15, 2010 + 2.6.33 February 24, 2010 Every 2.6.x release is a major kernel release with new features, internal -API changes, and more. A typical 2.6 release can contain over 10,000 +API changes, and more. A typical 2.6 release can contain nearly 10,000 changesets with changes to several hundred thousand lines of code. 2.6 is thus the leading edge of Linux kernel development; the kernel uses a rolling development model which is continually integrating major changes. A relatively straightforward discipline is followed with regard to the merging of patches for each release. At the beginning of each development cycle, the "merge window" is said to be open. At that time, code which is deemed to be sufficiently stable (and which is accepted by the development community) is merged into the mainline kernel. The bulk of changes for a new development cycle (and all of the major changes) will be merged during this time, at a rate approaching 1,000 changes ("patches," or "changesets") per day. (As an aside, it is worth noting that the changes integrated during the merge window do not come out of thin air; they have been collected, tested, and staged ahead of time. How that process works will be described in detail later on). -The merge window lasts for two weeks. At the end of this time, Linus -Torvalds will declare that the window is closed and release the first of -the "rc" kernels. For the kernel which is destined to be 2.6.26, for -example, the release which happens at the end of the merge window will be -called 2.6.26-rc1. The -rc1 release is the signal that the time to merge -new features has passed, and that the time to stabilize the next kernel has -begun. +The merge window lasts for approximately two weeks. At the end of this +time, Linus Torvalds will declare that the window is closed and release the +first of the "rc" kernels. For the kernel which is destined to be 2.6.40, +for example, the release which happens at the end of the merge window will +be called 2.6.40-rc1. The -rc1 release is the signal that the time to +merge new features has passed, and that the time to stabilize the next +kernel has begun. Over the next six to ten weeks, only patches which fix problems should be submitted to the mainline. On occasion a more significant change will be allowed, but such occasions are rare; developers who try to merge new features outside of the merge window tend to get an unfriendly reception. As a general rule, if you miss the merge window for a given feature, the best thing to do is to wait for the next development cycle. (An occasional exception is made for drivers for previously-unsupported hardware; if they touch no in-tree code, they cannot cause regressions and should be safe to add at any time). As fixes make their way into the mainline, the patch rate will slow over time. Linus releases new -rc kernels about once a week; a normal series will get up to somewhere between -rc6 and -rc9 before the kernel is considered to be sufficiently stable and the final 2.6.x release is made. At that point the whole process starts over again. -As an example, here is how the 2.6.25 development cycle went (all dates in -2008): - - January 24 2.6.24 stable release - February 10 2.6.25-rc1, merge window closes - February 15 2.6.25-rc2 - February 24 2.6.25-rc3 - March 4 2.6.25-rc4 - March 9 2.6.25-rc5 - March 16 2.6.25-rc6 - March 25 2.6.25-rc7 - April 1 2.6.25-rc8 - April 11 2.6.25-rc9 - April 16 2.6.25 stable release +As an example, here is how the 2.6.38 development cycle went (all dates in +2011): + + January 4 2.6.37 stable release + January 18 2.6.38-rc1, merge window closes + January 21 2.6.38-rc2 + February 1 2.6.38-rc3 + February 7 2.6.38-rc4 + February 15 2.6.38-rc5 + February 21 2.6.38-rc6 + March 1 2.6.38-rc7 + March 7 2.6.38-rc8 + March 14 2.6.38 stable release How do the developers decide when to close the development cycle and create the stable release? The most significant metric used is the list of regressions from previous releases. No bugs are welcome, but those which break systems which worked in the past are considered to be especially serious. For this reason, patches which cause regressions are looked upon unfavorably and are quite likely to be reverted during the stabilization -period. +period. The developers' goal is to fix all known regressions before the stable release is made. In the real world, this kind of perfection is hard to achieve; there are just too many variables in a project of this size. There comes a point where delaying the final release just makes the problem worse; the pile of changes waiting for the next merge window will grow larger, creating even more regressions the next time around. So most 2.6.x kernels go out with a handful of known regressions though, hopefully, none of them are serious. Once a stable release is made, its ongoing maintenance is passed off to the -"stable team," currently comprised of Greg Kroah-Hartman and Chris Wright. -The stable team will release occasional updates to the stable release using -the 2.6.x.y numbering scheme. To be considered for an update release, a -patch must (1) fix a significant bug, and (2) already be merged into the -mainline for the next development kernel. Continuing our 2.6.25 example, -the history (as of this writing) is: - - May 1 2.6.25.1 - May 6 2.6.25.2 - May 9 2.6.25.3 - May 15 2.6.25.4 - June 7 2.6.25.5 - June 9 2.6.25.6 - June 16 2.6.25.7 - June 21 2.6.25.8 - June 24 2.6.25.9 - -Stable updates for a given kernel are made for approximately six months; -after that, the maintenance of stable releases is solely the responsibility -of the distributors which have shipped that particular kernel. +"stable team," currently consisting of Greg Kroah-Hartman. The stable team +will release occasional updates to the stable release using the 2.6.x.y +numbering scheme. To be considered for an update release, a patch must (1) +fix a significant bug, and (2) already be merged into the mainline for the +next development kernel. Kernels will typically receive stable updates for +a little more than one development cycle past their initial release. So, +for example, the 2.6.36 kernel's history looked like: + + October 10 2.6.36 stable release + November 22 2.6.36.1 + December 9 2.6.36.2 + January 7 2.6.36.3 + February 17 2.6.36.4 + +2.6.36.4 was the final stable update for the 2.6.36 release. + +Some kernels are designated "long term" kernels; they will receive support +for a longer period. As of this writing, the current long term kernels +and their maintainers are: + + 2.6.27 Willy Tarreau (Deep-frozen stable kernel) + 2.6.32 Greg Kroah-Hartman + 2.6.35 Andi Kleen (Embedded flag kernel) + +The selection of a kernel for long-term support is purely a matter of a +maintainer having the need and the time to maintain that release. There +are no known plans for long-term support for any specific upcoming +release. 2.2: THE LIFECYCLE OF A PATCH Patches do not go directly from the developer's keyboard into the mainline kernel. There is, instead, a somewhat involved (if somewhat informal) process designed to ensure that each patch is reviewed for quality and that each patch implements a change which is desirable to have in the mainline. This process can happen quickly for minor fixes, or, in the case of large and controversial changes, go on for years. Much developer frustration comes from a lack of understanding of this process or from attempts to -circumvent it. +circumvent it. In the hopes of reducing that frustration, this document will describe how a patch gets into the kernel. What follows below is an introduction which describes the process in a somewhat idealized way. A much more detailed treatment will come in later sections. The stages that a patch goes through are, generally: - Design. This is where the real requirements for the patch - and the way those requirements will be met - are laid out. Design work is often done without involving the community, but it is better to do this work in the open if at all possible; it can save a lot of time redesigning @@ -184,26 +190,26 @@ The stages that a patch goes through are, generally: continue to take responsibility for the code if it is to remain useful in the longer term. One of the largest mistakes made by kernel developers (or their employers) is to try to cut the process down to a single "merging into the mainline" step. This approach invariably leads to frustration for everybody involved. 2.3: HOW PATCHES GET INTO THE KERNEL There is exactly one person who can merge patches into the mainline kernel -repository: Linus Torvalds. But, of the over 12,000 patches which went -into the 2.6.25 kernel, only 250 (around 2%) were directly chosen by Linus +repository: Linus Torvalds. But, of the over 9,500 patches which went +into the 2.6.38 kernel, only 112 (around 1.3%) were directly chosen by Linus himself. The kernel project has long since grown to a size where no single developer could possibly inspect and select every patch unassisted. The way the kernel developers have addressed this growth is through the use of a lieutenant system built around a chain of trust. The kernel code base is logically broken down into a set of subsystems: networking, specific architecture support, memory management, video devices, etc. Most subsystems have a designated maintainer, a developer who has overall responsibility for the code within that subsystem. These subsystem maintainers are the gatekeepers (in a loose way) for the portion of the kernel they manage; they are the ones who will (usually) accept a patch for inclusion into the mainline kernel. @@ -220,117 +226,114 @@ the patches they have selected for merging from their repositories. If Linus agrees, the stream of patches will flow up into his repository, becoming part of the mainline kernel. The amount of attention that Linus pays to specific patches received in a pull operation varies. It is clear that, sometimes, he looks quite closely. But, as a general rule, Linus trusts the subsystem maintainers to not send bad patches upstream. Subsystem maintainers, in turn, can pull patches from other maintainers. For example, the networking tree is built from patches which accumulated first in trees dedicated to network device drivers, wireless networking, etc. This chain of repositories can be arbitrarily long, though it rarely exceeds two or three links. Since each maintainer in the chain trusts those managing lower-level trees, this process is known as the "chain of -trust." +trust." Clearly, in a system like this, getting patches into the kernel depends on finding the right maintainer. Sending patches directly to Linus is not normally the right way to go. 2.4: NEXT TREES The chain of subsystem trees guides the flow of patches into the kernel, but it also raises an interesting question: what if somebody wants to look at all of the patches which are being prepared for the next merge window? Developers will be interested in what other changes are pending to see whether there are any conflicts to worry about; a patch which changes a core kernel function prototype, for example, will conflict with any other patches which use the older form of that function. Reviewers and testers want access to the changes in their integrated form before all of those changes land in the mainline kernel. One could pull changes from all of the interesting subsystem trees, but that would be a big and error-prone job. The answer comes in the form of -next trees, where subsystem trees are collected for testing and review. The older of these trees, maintained by Andrew Morton, is called "-mm" (for memory management, which is how it got started). The -mm tree integrates patches from a long list of subsystem -trees; it also has some patches aimed at helping with debugging. +trees; it also has some patches aimed at helping with debugging. Beyond that, -mm contains a significant collection of patches which have been selected by Andrew directly. These patches may have been posted on a mailing list, or they may apply to a part of the kernel for which there is no designated subsystem tree. As a result, -mm operates as a sort of subsystem tree of last resort; if there is no other obvious path for a patch into the mainline, it is likely to end up in -mm. Miscellaneous patches which accumulate in -mm will eventually either be forwarded on to an appropriate subsystem tree or be sent directly to Linus. In a typical -development cycle, approximately 10% of the patches going into the mainline -get there via -mm. +development cycle, approximately 5-10% of the patches going into the +mainline get there via -mm. The current -mm patch is available in the "mmotm" (-mm of the moment) directory at: http://userweb.kernel.org/~akpm/mmotm/ Use of the MMOTM tree is likely to be a frustrating experience, though; there is a definite chance that it will not even compile. -The other -next tree, started more recently, is linux-next, maintained by +The primary tree for next-cycle patch merging is linux-next, maintained by Stephen Rothwell. The linux-next tree is, by design, a snapshot of what the mainline is expected to look like after the next merge window closes. Linux-next trees are announced on the linux-kernel and linux-next mailing lists when they are assembled; they can be downloaded from: http://www.kernel.org/pub/linux/kernel/people/sfr/linux-next/ Some information about linux-next has been gathered at: http://linux.f-seidel.de/linux-next/pmwiki/ -How the linux-next tree will fit into the development process is still -changing. As of this writing, the first full development cycle involving -linux-next (2.6.26) is coming to an end; thus far, it has proved to be a -valuable resource for finding and fixing integration problems before the -beginning of the merge window. See http://lwn.net/Articles/287155/ for -more information on how linux-next has worked to set up the 2.6.27 merge -window. - -Some developers have begun to suggest that linux-next should be used as the -target for future development as well. The linux-next tree does tend to be -far ahead of the mainline and is more representative of the tree into which -any new work will be merged. The downside to this idea is that the -volatility of linux-next tends to make it a difficult development target. -See http://lwn.net/Articles/289013/ for more information on this topic, and -stay tuned; much is still in flux where linux-next is involved. +Linux-next has become an integral part of the kernel development process; +all patches merged during a given merge window should really have found +their way into linux-next some time before the merge window opens. + 2.4.1: STAGING TREES -The kernel source tree now contains the drivers/staging/ directory, where +The kernel source tree contains the drivers/staging/ directory, where many sub-directories for drivers or filesystems that are on their way to being added to the kernel tree live. They remain in drivers/staging while they still need more work; once complete, they can be moved into the kernel proper. This is a way to keep track of drivers that aren't up to Linux kernel coding or quality standards, but people may want to use them and track development. -Greg Kroah-Hartman currently (as of 2.6.36) maintains the staging tree. -Drivers that still need work are sent to him, with each driver having -its own subdirectory in drivers/staging/. Along with the driver source -files, a TODO file should be present in the directory as well. The TODO -file lists the pending work that the driver needs for acceptance into -the kernel proper, as well as a list of people that should be Cc'd for any -patches to the driver. Staging drivers that don't currently build should -have their config entries depend upon CONFIG_BROKEN. Once they can -be successfully built without outside patches, CONFIG_BROKEN can be removed. +Greg Kroah-Hartman currently maintains the staging tree. Drivers that +still need work are sent to him, with each driver having its own +subdirectory in drivers/staging/. Along with the driver source files, a +TODO file should be present in the directory as well. The TODO file lists +the pending work that the driver needs for acceptance into the kernel +proper, as well as a list of people that should be Cc'd for any patches to +the driver. Current rules require that drivers contributed to staging +must, at a minimum, compile properly. + +Staging can be a relatively easy way to get new drivers into the mainline +where, with luck, they will come to the attention of other developers and +improve quickly. Entry into staging is not the end of the story, though; +code in staging which is not seeing regular progress will eventually be +removed. Distributors also tend to be relatively reluctant to enable +staging drivers. So staging is, at best, a stop on the way toward becoming +a proper mainline driver. + 2.5: TOOLS As can be seen from the above text, the kernel development process depends heavily on the ability to herd collections of patches in various directions. The whole thing would not work anywhere near as well as it does without suitably powerful tools. Tutorials on how to use these tools are well beyond the scope of this document, but there is space for a few pointers. By far the dominant source code management system used by the kernel community is git. Git is one of a number of distributed version control @@ -338,29 +341,25 @@ systems being developed in the free software community. It is well tuned for kernel development, in that it performs quite well when dealing with large repositories and large numbers of patches. It also has a reputation for being difficult to learn and use, though it has gotten better over time. Some sort of familiarity with git is almost a requirement for kernel developers; even if they do not use it for their own work, they'll need git to keep up with what other developers (and the mainline) are doing. Git is now packaged by almost all Linux distributions. There is a home page at: http://git-scm.com/ -That page has pointers to documentation and tutorials. One should be -aware, in particular, of the Kernel Hacker's Guide to git, which has -information specific to kernel development: - - http://linux.yyz.us/git-howto.html +That page has pointers to documentation and tutorials. Among the kernel developers who do not use git, the most popular choice is almost certainly Mercurial: http://www.selenic.com/mercurial/ Mercurial shares many features with git, but it provides an interface which many find easier to use. The other tool worth knowing about is Quilt: http://savannah.nongnu.org/projects/quilt/ @@ -399,25 +398,25 @@ development community comes together as a whole; developers who avoid this list will miss important information. There are a few hints which can help with linux-kernel survival: - Have the list delivered to a separate folder, rather than your main mailbox. One must be able to ignore the stream for sustained periods of time. - Do not try to follow every conversation - nobody else does. It is important to filter on both the topic of interest (though note that long-running conversations can drift away from the original subject without changing the email subject line) and the people who are - participating. + participating. - Do not feed the trolls. If somebody is trying to stir up an angry response, ignore them. - When responding to linux-kernel email (or that on other lists) preserve the Cc: header for all involved. In the absence of a strong reason (such as an explicit request), you should never remove recipients. Always make sure that the person you are responding to is in the Cc: list. This convention also makes it unnecessary to explicitly ask to be copied on replies to your postings. - Search the list archives (and the net as a whole) before asking diff --git a/Documentation/development-process/3.Early-stage b/Documentation/development-process/3.Early-stage index 307a159..f87ba7b 100644 --- a/Documentation/development-process/3.Early-stage +++ b/Documentation/development-process/3.Early-stage @@ -101,26 +101,26 @@ the kernel community's standards. Some examples include: of this code (now called mac80211) was delayed for over a year. - The Reiser4 filesystem included a number of capabilities which, in the core kernel developers' opinion, should have been implemented in the virtual filesystem layer instead. It also included features which could not easily be implemented without exposing the system to user-caused deadlocks. The late revelation of these problems - and refusal to address some of them - has caused Reiser4 to stay out of the mainline kernel. - The AppArmor security module made use of internal virtual filesystem data structures in ways which were considered to be unsafe and - unreliable. This code has since been significantly reworked, but - remains outside of the mainline. + unreliable. This concern (among others) kept AppArmor out of the + mainline for years. In each of these cases, a great deal of pain and extra work could have been avoided with some early discussion with the kernel developers. 3.3: WHO DO YOU TALK TO? When developers decide to take their plans public, the next question will be: where do we start? The answer is to find the right mailing list(s) and the right maintainer. For mailing lists, the best approach is to look in the MAINTAINERS file for a relevant place to post. If there is a suitable subsystem list, posting there is often preferable to posting on @@ -129,46 +129,63 @@ relevant subsystem and the environment may be more supportive. Finding maintainers can be a bit harder. Again, the MAINTAINERS file is the place to start. That file tends to not always be up to date, though, and not all subsystems are represented there. The person listed in the MAINTAINERS file may, in fact, not be the person who is actually acting in that role currently. So, when there is doubt about who to contact, a useful trick is to use git (and "git log" in particular) to see who is currently active within the subsystem of interest. Look at who is writing patches, and who, if anybody, is attaching Signed-off-by lines to those patches. Those are the people who will be best placed to help with a new development project. +The task of finding the right maintainer is sometimes challenging enough +that the kernel developers have added a script to ease the process: + + .../scripts/get_maintainer.pl + +This script will return the current maintainer(s) for a given file or +directory when given the "-f" option. If passed a patch on the +command line, it will list the maintainers who should probably receive +copies of the patch. There are a number of options regulating how hard +get_maintainer.pl will search for maintainers; please be careful about +using the more aggressive options as you may end up including developers +who have no real interest in the code you are modifying. + If all else fails, talking to Andrew Morton can be an effective way to track down a maintainer for a specific piece of code. 3.4: WHEN TO POST? If possible, posting your plans during the early stages can only be helpful. Describe the problem being solved and any plans that have been made on how the implementation will be done. Any information you can provide can help the development community provide useful input on the project. One discouraging thing which can happen at this stage is not a hostile reaction, but, instead, little or no reaction at all. The sad truth of the matter is (1) kernel developers tend to be busy, (2) there is no shortage of people with grand plans and little code (or even prospect of code) to back them up, and (3) nobody is obligated to review or comment on ideas -posted by others. If a request-for-comments posting yields little in the -way of comments, do not assume that it means there is no interest in the -project. Unfortunately, you also cannot assume that there are no problems -with your idea. The best thing to do in this situation is to proceed, -keeping the community informed as you go. +posted by others. Beyond that, high-level designs often hide problems +which are only reviewed when somebody actually tries to implement those +designs; for that reason, kernel developers would rather see the code. + +If a request-for-comments posting yields little in the way of comments, do +not assume that it means there is no interest in the project. +Unfortunately, you also cannot assume that there are no problems with your +idea. The best thing to do in this situation is to proceed, keeping the +community informed as you go. 3.5: GETTING OFFICIAL BUY-IN If your work is being done in a corporate environment - as most Linux kernel work is - you must, obviously, have permission from suitably empowered managers before you can post your company's plans or code to a public mailing list. The posting of code which has not been cleared for release under a GPL-compatible license can be especially problematic; the sooner that a company's management and legal staff can agree on the posting of a kernel development project, the better off everybody involved will be. diff --git a/Documentation/development-process/4.Coding b/Documentation/development-process/4.Coding index 2278693..f3f1a46 100644 --- a/Documentation/development-process/4.Coding +++ b/Documentation/development-process/4.Coding @@ -122,24 +122,29 @@ however, can actually reduce performance. Since their code is replicated at each call site, they end up bloating the size of the compiled kernel. That, in turn, creates pressure on the processor's memory caches, which can slow execution dramatically. Inline functions, as a rule, should be quite small and relatively rare. The cost of a function call, after all, is not that high; the creation of large numbers of inline functions is a classic example of premature optimization. In general, kernel programmers ignore cache effects at their peril. The classic time/space tradeoff taught in beginning data structures classes often does not apply to contemporary hardware. Space *is* time, in that a larger program will run slower than one which is more compact. +More recent compilers take an increasingly active role in deciding whether +a given function should actually be inlined or not. So the liberal +placement of "inline" keywords may not just be excessive; it could also be +irrelevant. + * Locking In May, 2006, the "Devicescape" networking stack was, with great fanfare, released under the GPL and made available for inclusion in the mainline kernel. This donation was welcome news; support for wireless networking in Linux was considered substandard at best, and the Devicescape stack offered the promise of fixing that situation. Yet, this code did not actually make it into the mainline until June, 2007 (2.6.22). What happened? This code showed a number of signs of having been developed behind @@ -276,61 +281,70 @@ code responds when things go badly. See Documentation/fault-injection/fault-injection.text for more information on how to use this facility. Other kinds of errors can be found with the "sparse" static analysis tool. With sparse, the programmer can be warned about confusion between user-space and kernel-space addresses, mixture of big-endian and small-endian quantities, the passing of integer values where a set of bit flags is expected, and so on. Sparse must be installed separately (it can be found at https://sparse.wiki.kernel.org/index.php/Main_Page if your distributor does not package it); it can then be run on the code by adding "C=1" to your make command. +The "Coccinelle" tool (http://coccinelle.lip6.fr/) is able to find a wide +variety of potential coding problems; it can also propose fixes for those +problems. Quite a few "semantic patches" for the kernel have been packaged +under the scripts/coccinelle directory; running "make coccicheck" will run +through those semantic patches and report on any problems found. See +Documentation/coccinelle.txt for more information. + Other kinds of portability errors are best found by compiling your code for other architectures. If you do not happen to have an S/390 system or a Blackfin development board handy, you can still perform the compilation step. A large set of cross compilers for x86 systems can be found at http://www.kernel.org/pub/tools/crosstool/ Some time spent installing and using these compilers will help avoid embarrassment later. 4.3: DOCUMENTATION Documentation has often been more the exception than the rule with kernel development. Even so, adequate documentation will help to ease the merging of new code into the kernel, make life easier for other developers, and will be helpful for your users. In many cases, the addition of documentation has become essentially mandatory. The first piece of documentation for any patch is its associated changelog. Log entries should describe the problem being solved, the form of the solution, the people who worked on the patch, any relevant effects on performance, and anything else that might be needed to -understand the patch. +understand the patch. Be sure that the changelog says *why* the patch is +worth applying; a surprising number of developers fail to provide that +information. Any code which adds a new user-space interface - including new sysfs or /proc files - should include documentation of that interface which enables user-space developers to know what they are working with. See Documentation/ABI/README for a description of how this documentation should be formatted and what information needs to be provided. The file Documentation/kernel-parameters.txt describes all of the kernel's boot-time parameters. Any patch which adds new parameters should add the appropriate entries to this file. Any new configuration options must be accompanied by help text which -clearly explains the options and when the user might want to select them. +clearly explains the options and when the user might want to select them. Internal API information for many subsystems is documented by way of specially-formatted comments; these comments can be extracted and formatted in a number of ways by the "kernel-doc" script. If you are working within a subsystem which has kerneldoc comments, you should maintain them and add them, as appropriate, for externally-available functions. Even in areas which have not been so documented, there is no harm in adding kerneldoc comments for the future; indeed, this can be a useful activity for beginning kernel developers. The format of these comments, along with some information on how to create kerneldoc templates can be found in the file Documentation/kernel-doc-nano-HOWTO.txt. @@ -363,22 +377,23 @@ developer, you are empowered to make such changes. There are, of course, some catches. API changes can be made, but they need to be well justified. So any patch making an internal API change should be accompanied by a description of what the change is and why it is necessary. This kind of change should also be broken out into a separate patch, rather than buried within a larger patch. The other catch is that a developer who changes an internal API is generally charged with the task of fixing any code within the kernel tree which is broken by the change. For a widely-used function, this duty can lead to literally hundreds or thousands of changes - many of which are likely to conflict with work being done by other developers. Needless to say, this can be a large job, so it is best to be sure that the -justification is solid. +justification is solid. Note that the Coccinelle tool can help with +wide-ranging API changes. When making an incompatible API change, one should, whenever possible, ensure that code which has not been updated is caught by the compiler. This will help you to be sure that you have found all in-tree uses of that interface. It will also alert developers of out-of-tree code that there is a change that they need to respond to. Supporting out-of-tree code is not something that kernel developers need to be worried about, but we also do not have to make life harder for out-of-tree developers than it needs to be. diff --git a/Documentation/development-process/5.Posting b/Documentation/development-process/5.Posting index f622c1e..903a254 100644 --- a/Documentation/development-process/5.Posting +++ b/Documentation/development-process/5.Posting @@ -51,30 +51,33 @@ sending patches to the development community. These include: As a general rule, putting in some extra thought before posting code almost always pays back the effort in short order. 5.3: PATCH PREPARATION The preparation of patches for posting can be a surprising amount of work, but, once again, attempting to save time here is not generally advisable even in the short term. Patches must be prepared against a specific version of the kernel. As a general rule, a patch should be based on the current mainline as found in -Linus's git tree. It may become necessary to make versions against -mm, -linux-next, or a subsystem tree, though, to facilitate wider testing and -review. Depending on the area of your patch and what is going on -elsewhere, basing a patch against these other trees can require a -significant amount of work resolving conflicts and dealing with API -changes. +Linus's git tree. When basing on mainline, start with a well-known release +point - a stable or -rc release - rather than branching off the mainline at +an arbitrary spot. + +It may become necessary to make versions against -mm, linux-next, or a +subsystem tree, though, to facilitate wider testing and review. Depending +on the area of your patch and what is going on elsewhere, basing a patch +against these other trees can require a significant amount of work +resolving conflicts and dealing with API changes. Only the most simple changes should be formatted as a single patch; everything else should be made as a logical series of changes. Splitting up patches is a bit of an art; some developers spend a long time figuring out how to do it in the way that the community expects. There are a few rules of thumb, however, which can help considerably: - The patch series you post will almost certainly not be the series of changes found in your working revision control system. Instead, the changes you have made need to be considered in their final form, then split apart in ways which make sense. The developers are interested in discrete, self-contained changes, not the path you took to get to those @@ -91,29 +94,29 @@ rules of thumb, however, which can help considerably: changes in the same patch. If a single patch fixes a critical security bug, rearranges a few structures, and reformats the code, there is a good chance that it will be passed over and the important fix will be lost. - Each patch should yield a kernel which builds and runs properly; if your patch series is interrupted in the middle, the result should still be a working kernel. Partial application of a patch series is a common scenario when the "git bisect" tool is used to find regressions; if the result is a broken kernel, you will make life harder for developers and users who are engaging in the noble work of tracking down problems. - - Do not overdo it, though. One developer recently posted a set of edits + - Do not overdo it, though. One developer once posted a set of edits to a single file as 500 separate patches - an act which did not make him the most popular person on the kernel mailing list. A single patch can be reasonably large as long as it still contains a single *logical* - change. + change. - It can be tempting to add a whole new infrastructure with a series of patches, but to leave that infrastructure unused until the final patch in the series enables the whole thing. This temptation should be avoided if possible; if that series adds regressions, bisection will finger the last patch as the one which caused the problem, even though the real bug is elsewhere. Whenever possible, a patch which adds new code should make that code active immediately. Working to create the perfect patch series can be a frustrating process which takes quite a bit of time and thought after the "real work" has been done. When done properly, though, it is time well spent. @@ -153,25 +156,26 @@ bear in mind that a number of different people will be reading your words. These include subsystem maintainers and reviewers who need to decide whether the patch should be included, distributors and other maintainers trying to decide whether a patch should be backported to other kernels, bug hunters wondering whether the patch is responsible for a problem they are chasing, users who want to know how the kernel has changed, and more. A good changelog conveys the needed information to all of these people in the most direct and concise way possible. To that end, the summary line should describe the effects of and motivation for the change as well as possible given the one-line constraint. The detailed description can then amplify on those topics and provide any needed additional information. If the patch fixes a bug, cite the commit -which introduced the bug if possible. If a problem is associated with +which introduced the bug if possible (and please provide both the commit ID +and the title when citing commits). If a problem is associated with specific log or compiler output, include that output to help others searching for a solution to the same problem. If the change is meant to support other changes coming in later patch, say so. If internal APIs are changed, detail those changes and how other developers should respond. In general, the more you can put yourself into the shoes of everybody who will be reading your changelog, the better that changelog (and the kernel as a whole) will be. Needless to say, the changelog should be the text used when committing the change to a revision control system. It will be followed by: - The patch itself, in the unified ("-u") patch format. Using the "-p" @@ -221,25 +225,25 @@ Be careful in the addition of tags to your patches: only Cc: is appropriate for addition without the explicit permission of the person named. 5.5: SENDING THE PATCH Before you mail your patches, there are a couple of other things you should take care of: - Are you sure that your mailer will not corrupt the patches? Patches which have had gratuitous white-space changes or line wrapping performed by the mail client will not apply at the other end, and often will not be examined in any detail. If there is any doubt at all, mail the patch - to yourself and convince yourself that it shows up intact. + to yourself and convince yourself that it shows up intact. Documentation/email-clients.txt has some helpful hints on making specific mail clients work for sending patches. - Are you sure your patch is free of silly mistakes? You should always run patches through scripts/checkpatch.pl and address the complaints it comes up with. Please bear in mind that checkpatch.pl, while being the embodiment of a fair amount of thought about what kernel patches should look like, is not smarter than you. If fixing a checkpatch.pl complaint would make the code worse, don't do it. Patches should always be sent as plain text. Please do not send them as @@ -278,26 +282,26 @@ is possible to send patches directly to Linus Torvalds and have him merge them, things are not normally done that way. Linus is busy, and there are subsystem maintainers who watch over specific parts of the kernel. Usually you will be wanting that maintainer to merge your patches. If there is no obvious maintainer, Andrew Morton is often the patch target of last resort. Patches need good subject lines. The canonical format for a patch line is something like: [PATCH nn/mm] subsys: one-line description of the patch where "nn" is the ordinal number of the patch, "mm" is the total number of patches in the series, and "subsys" is the name of the affected subsystem. -Clearly, nn/mm can be omitted for a single, standalone patch. +Clearly, nn/mm can be omitted for a single, standalone patch. If you have a significant series of patches, it is customary to send an introductory description as part zero. This convention is not universally followed though; if you use it, remember that information in the introduction does not make it into the kernel changelogs. So please ensure that the patches, themselves, have complete changelog information. In general, the second and following parts of a multi-part patch should be sent as a reply to the first part so that they all thread together at the receiving end. Tools like git and quilt have commands to mail out a set of patches with the proper threading. If you have a long series, though, and -are using git, please provide the --no-chain-reply-to option to avoid +are using git, please stay away from the --chain-reply-to option to avoid creating exceptionally deep nesting. diff --git a/Documentation/development-process/6.Followthrough b/Documentation/development-process/6.Followthrough index a8fba3d8..41d324a 100644 --- a/Documentation/development-process/6.Followthrough +++ b/Documentation/development-process/6.Followthrough @@ -57,24 +57,29 @@ thank them, and describe how you will answer their questions. Note that you do not have to agree with every change suggested by reviewers. If you believe that the reviewer has misunderstood your code, explain what is really going on. If you have a technical objection to a suggested change, describe it and justify your solution to the problem. If your explanations make sense, the reviewer will accept them. Should your explanation not prove persuasive, though, especially if others start to agree with the reviewer, take some time to think things over again. It can be easy to become blinded by your own solution to a problem to the point that you don't realize that something is fundamentally wrong or, perhaps, you're not even solving the right problem. +Andrew Morton has suggested that every review comment which does not result +in a code change should result in an additional code comment instead; that +can help future reviewers avoid the questions which came up the first time +around. + One fatal mistake is to ignore review comments in the hope that they will go away. They will not go away. If you repost code without having responded to the comments you got the time before, you're likely to find that your patches go nowhere. Speaking of reposting code: please bear in mind that reviewers are not going to remember all the details of the code you posted the last time around. So it is always a good idea to remind reviewers of previously raised issues and how you dealt with them; the patch changelog is a good place for this kind of information. Reviewers should not have to search through list archives to familiarize themselves with what was said last time; if you help them get a running start, they will be in a better mood @@ -91,38 +96,37 @@ be hopelessly blocked. Appealing to Andrew should not be done lightly, though, and not before all other alternatives have been explored. And bear in mind, of course, that he may not agree with you either. 6.2: WHAT HAPPENS NEXT If a patch is considered to be a good thing to add to the kernel, and once most of the review issues have been resolved, the next step is usually entry into a subsystem maintainer's tree. How that works varies from one subsystem to the next; each maintainer has his or her own way of doing things. In particular, there may be more than one tree - one, perhaps, dedicated to patches planned for the next merge window, and another for -longer-term work. +longer-term work. For patches applying to areas for which there is no obvious subsystem tree (memory management patches, for example), the default tree often ends up being -mm. Patches which affect multiple subsystems can also end up going through the -mm tree. Inclusion into a subsystem tree can bring a higher level of visibility to a patch. Now other developers working with that tree will get the patch by -default. Subsystem trees typically feed into -mm and linux-next as well, -making their contents visible to the development community as a whole. At -this point, there's a good chance that you will get more comments from a -new set of reviewers; these comments need to be answered as in the previous -round. +default. Subsystem trees typically feed linux-next as well, making their +contents visible to the development community as a whole. At this point, +there's a good chance that you will get more comments from a new set of +reviewers; these comments need to be answered as in the previous round. What may also happen at this point, depending on the nature of your patch, is that conflicts with work being done by others turn up. In the worst case, heavy patch conflicts can result in some work being put on the back burner so that the remaining patches can be worked into shape and merged. Other times, conflict resolution will involve working with the other developers and, possibly, moving some patches between trees to ensure that everything applies cleanly. This work can be a pain, but count your blessings: before the advent of the linux-next tree, these conflicts often only turned up during the merge window and had to be addressed in a hurry. Now they can be resolved at leisure, before the merge window opens. diff --git a/Documentation/development-process/7.AdvancedTopics b/Documentation/development-process/7.AdvancedTopics index 8371794..26dc3fa 100644 --- a/Documentation/development-process/7.AdvancedTopics +++ b/Documentation/development-process/7.AdvancedTopics @@ -110,44 +110,44 @@ so that you don't have to do the same work twice. One of the biggest recurring complaints about tools like git is this: the mass movement of patches from one repository to another makes it easy to slip in ill-advised changes which go into the mainline below the review radar. Kernel developers tend to get unhappy when they see that kind of thing happening; putting up a git tree with unreviewed or off-topic patches can affect your ability to get trees pulled in the future. Quoting Linus: You can send me patches, but for me to pull a git patch from you, I need to know that you know what you're doing, and I need to be able to trust things *without* then having to go and check every individual change by hand. -(http://lwn.net/Articles/224135/). +(http://lwn.net/Articles/224135/). To avoid this kind of situation, ensure that all patches within a given branch stick closely to the associated topic; a "driver fixes" branch should not be making changes to the core memory management code. And, most importantly, do not use a git tree to bypass the review process. Post an occasional summary of the tree to the relevant list, and, when the time is right, request that the tree be included in linux-next. If and when others start to send patches for inclusion into your tree, don't forget to review them. Also ensure that you maintain the correct authorship information; the git "am" tool does its best in this regard, but you may have to add a "From:" line to the patch if it has been relayed to you via a third party. When requesting a pull, be sure to give all the relevant information: where your tree is, what branch to pull, and what changes will result from the pull. The git request-pull command can be helpful in this regard; it will format the request as other developers expect, and will also check to be -sure that you have remembered to push those changes to the public server. +sure that you have remembered to push those changes to the public server. 7.2: REVIEWING PATCHES Some readers will certainly object to putting this section with "advanced topics" on the grounds that even beginning kernel developers should be reviewing patches. It is certainly true that there is no better way to learn how to program in the kernel environment than by looking at code posted by others. In addition, reviewers are forever in short supply; by looking at code you can make a significant contribution to the process as a whole. diff --git a/Documentation/dynamic-debug-howto.txt b/Documentation/dynamic-debug-howto.txt index e6c4b75..f959909 100644 --- a/Documentation/dynamic-debug-howto.txt +++ b/Documentation/dynamic-debug-howto.txt @@ -1,41 +1,41 @@ Introduction ============ This document describes how to use the dynamic debug (ddebug) feature. Dynamic debug is designed to allow you to dynamically enable/disable kernel code to obtain additional kernel information. Currently, if -CONFIG_DYNAMIC_DEBUG is set, then all pr_debug()/dev_debug() calls can be +CONFIG_DYNAMIC_DEBUG is set, then all pr_debug()/dev_dbg() calls can be dynamically enabled per-callsite. Dynamic debug has even more useful features: * Simple query language allows turning on and off debugging statements by matching any combination of: - source filename - function name - line number (including ranges of line numbers) - module name - format string * Provides a debugfs control file: <debugfs>/dynamic_debug/control which can be read to display the complete list of known debug statements, to help guide you Controlling dynamic debug Behaviour =================================== -The behaviour of pr_debug()/dev_debug()s are controlled via writing to a +The behaviour of pr_debug()/dev_dbg()s are controlled via writing to a control file in the 'debugfs' filesystem. Thus, you must first mount the debugfs filesystem, in order to make use of this feature. Subsequently, we refer to the control file as: <debugfs>/dynamic_debug/control. For example, if you want to enable printing from source file 'svcsock.c', line 1603 you simply do: nullarbor:~ # echo 'file svcsock.c line 1603 +p' > <debugfs>/dynamic_debug/control If you make a mistake with the syntax, the write will fail thus: nullarbor:~ # echo 'file svcsock.c wtf 1 +p' > <debugfs>/dynamic_debug/control diff --git a/Documentation/hwmon/f71882fg b/Documentation/hwmon/f71882fg index 4d0bc70..df02245 100644 --- a/Documentation/hwmon/f71882fg +++ b/Documentation/hwmon/f71882fg @@ -1,44 +1,63 @@ Kernel driver f71882fg ====================== Supported chips: + * Fintek F71808E + Prefix: 'f71808e' + Addresses scanned: none, address read from Super I/O config space + Datasheet: Not public * Fintek F71858FG Prefix: 'f71858fg' Addresses scanned: none, address read from Super I/O config space Datasheet: Available from the Fintek website * Fintek F71862FG and F71863FG Prefix: 'f71862fg' Addresses scanned: none, address read from Super I/O config space Datasheet: Available from the Fintek website * Fintek F71869F and F71869E Prefix: 'f71869' Addresses scanned: none, address read from Super I/O config space Datasheet: Available from the Fintek website * Fintek F71882FG and F71883FG Prefix: 'f71882fg' Addresses scanned: none, address read from Super I/O config space Datasheet: Available from the Fintek website * Fintek F71889FG Prefix: 'f71889fg' Addresses scanned: none, address read from Super I/O config space Datasheet: Available from the Fintek website * Fintek F71889ED Prefix: 'f71889ed' Addresses scanned: none, address read from Super I/O config space Datasheet: Should become available on the Fintek website soon + * Fintek F71889A + Prefix: 'f71889a' + Addresses scanned: none, address read from Super I/O config space + Datasheet: Should become available on the Fintek website soon * Fintek F8000 Prefix: 'f8000' Addresses scanned: none, address read from Super I/O config space Datasheet: Not public + * Fintek F81801U + Prefix: 'f71889fg' + Addresses scanned: none, address read from Super I/O config space + Datasheet: Not public + Note: This is the 64-pin variant of the F71889FG, they have the + same device ID and are fully compatible as far as hardware + monitoring is concerned. + * Fintek F81865F + Prefix: 'f81865f' + Addresses scanned: none, address read from Super I/O config space + Datasheet: Available from the Fintek website Author: Hans de Goede <hdegoede@redhat.com> Description ----------- Fintek F718xx/F8000 Super I/O chips include complete hardware monitoring capabilities. They can monitor up to 9 voltages, 4 fans and 3 temperature sensors. These chips also have fan controlling features, using either DC or PWM, in diff --git a/Documentation/laptops/sony-laptop.txt b/Documentation/laptops/sony-laptop.txt index 23ce7d3..2bd4e82 100644 --- a/Documentation/laptops/sony-laptop.txt +++ b/Documentation/laptops/sony-laptop.txt @@ -5,25 +5,26 @@ Sony Notebook Control Driver (SNC) Readme This mini-driver drives the SNC and SPIC device present in the ACPI BIOS of the Sony Vaio laptops. This driver mixes both devices functions under the same (hopefully consistent) interface. This also means that the sonypi driver is obsoleted by sony-laptop now. Fn keys (hotkeys): ------------------ Some models report hotkeys through the SNC or SPIC devices, such events are reported both through the ACPI subsystem as acpi events and through the INPUT subsystem. See the logs of acpid or /proc/acpi/event and /proc/bus/input/devices to find out what those events are and which input -devices are created by the driver. +devices are created by the driver. Additionally, loading the driver with the +debug option will report all events in the kernel log. Backlight control: ------------------ If your laptop model supports it, you will find sysfs files in the /sys/class/backlight/sony/ directory. You will be able to query and set the current screen brightness: brightness get/set screen brightness (an integer between 0 and 7) actual_brightness reading from this file will query the HW to get real brightness value max_brightness the maximum brightness value @@ -55,37 +56,60 @@ Example usage: # echo "1" > /sys/devices/platform/sony-laptop/brightness_default sets the lowest screen brightness for the next and later reboots, # echo "8" > /sys/devices/platform/sony-laptop/brightness_default sets the highest screen brightness for the next and later reboots, # cat /sys/devices/platform/sony-laptop/brightness_default retrieves the value. # echo "0" > /sys/devices/platform/sony-laptop/audiopower powers off the sound card, # echo "1" > /sys/devices/platform/sony-laptop/audiopower powers on the sound card. + +RFkill control: +--------------- +More recent Vaio models expose a consistent set of ACPI methods to +control radio frequency emitting devices. If you are a lucky owner of +such a laptop you will find the necessary rfkill devices under +/sys/class/rfkill. Check those starting with sony-* in + # grep . /sys/class/rfkill/*/{state,name} + + Development: ------------ If you want to help with the development of this driver (and you are not afraid of any side effects doing strange things with your ACPI BIOS could have on your laptop), load the driver and pass the option 'debug=1'. REPEAT: DON'T DO THIS IF YOU DON'T LIKE RISKY BUSINESS. In your kernel logs you will find the list of all ACPI methods -the SNC device has on your laptop. You can see the GCDP/GCDP methods -used to pwer on/off the CD drive, but there are others. +the SNC device has on your laptop. + +* For new models you will see a long list of meaningless method names, +reading the DSDT table source should reveal that: +(1) the SNC device uses an internal capability lookup table +(2) SN00 is used to find values in the lookup table +(3) SN06 and SN07 are used to call into the real methods based on + offsets you can obtain iterating the table using SN00 +(4) SN02 used to enable events. +Some values in the capability lookup table are more or less known, see +the code for all sony_call_snc_handle calls, others are more obscure. + +* For old models you can see the GCDP/GCDP methods used to pwer on/off +the CD drive, but there are others and they are usually different from +model to model. I HAVE NO IDEA WHAT THOSE METHODS DO. The sony-laptop driver creates, for some of those methods (the most current ones found on several Vaio models), an entry under /sys/devices/platform/sony-laptop, just like the 'cdpower' one. You can create other entries corresponding to your own laptop methods by further editing the source (see the 'sony_nc_values' table, and add a new entry to this table with your get/set method names using the SNC_HANDLE_NAMES macro). Your mission, should you accept it, is to try finding out what @@ -99,18 +123,17 @@ See also http://www.linux.it/~malattia/wiki/index.php/Sony_drivers for other useful info. Bugs/Limitations: ----------------- * This driver is not based on official documentation from Sony (because there is none), so there is no guarantee this driver will work at all, or do the right thing. Although this hasn't happened to me, this driver could do very bad things to your laptop, including permanent damage. * The sony-laptop and sonypi drivers do not interact at all. In the - future, sonypi could use sony-laptop to do (part of) its business. + future, sonypi will be removed and replaced by sony-laptop. * spicctrl, which is the userspace tool used to communicate with the - sonypi driver (through /dev/sonypi) does not try to use the - sony-laptop driver. In the future, spicctrl could try sonypi first, - and if it isn't present, try sony-laptop instead. + sonypi driver (through /dev/sonypi) is deprecated as well since all + its features are now available under the sysfs tree via sony-laptop. diff --git a/MAINTAINERS b/MAINTAINERS index 4fb9017..6b4b9cd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -539,28 +539,26 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers) W: http://blackfin.uclinux.org/ S: Supported F: sound/soc/blackfin/* AOA (Apple Onboard Audio) ALSA DRIVER M: Johannes Berg <johannes@sipsolutions.net> L: linuxppc-dev@lists.ozlabs.org L: alsa-devel@alsa-project.org (moderated for non-subscribers) S: Maintained F: sound/aoa/ APM DRIVER -M: Stephen Rothwell <sfr@canb.auug.org.au> L: linux-laptop@vger.kernel.org -W: http://www.canb.auug.org.au/~sfr/ -S: Supported +S: Orphan F: arch/x86/kernel/apm_32.c F: include/linux/apm_bios.h APPLE BCM5974 MULTITOUCH DRIVER M: Henrik Rydberg <rydberg@euromail.se> L: linux-input@vger.kernel.org S: Maintained F: drivers/input/mouse/bcm5974.c APPLE SMC DRIVER M: Henrik Rydberg <rydberg@euromail.se> L: lm-sensors@lm-sensors.org @@ -1150,47 +1148,39 @@ M: Marek Vasut <marek.vasut@gmail.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-pxa/z2.c F: arch/arm/mach-pxa/include/mach/z2.h ASC7621 HARDWARE MONITOR DRIVER M: George Joseph <george.joseph@fairview5.com> L: lm-sensors@lm-sensors.org S: Maintained F: Documentation/hwmon/asc7621 F: drivers/hwmon/asc7621.c -ASUS ACPI EXTRAS DRIVER +ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS M: Corentin Chary <corentincj@iksaif.net> -M: Karol Kozimor <sziwan@users.sourceforge.net> L: acpi4asus-user@lists.sourceforge.net L: platform-driver-x86@vger.kernel.org W: http://acpi4asus.sf.net S: Maintained -F: drivers/platform/x86/asus_acpi.c +F: drivers/platform/x86/asus*.c +F: drivers/platform/x86/eeepc*.c ASUS ASB100 HARDWARE MONITOR DRIVER M: "Mark M. Hoffman" <mhoffman@lightlink.com> L: lm-sensors@lm-sensors.org S: Maintained F: drivers/hwmon/asb100.c -ASUS LAPTOP EXTRAS DRIVER -M: Corentin Chary <corentincj@iksaif.net> -L: acpi4asus-user@lists.sourceforge.net -L: platform-driver-x86@vger.kernel.org -W: http://acpi4asus.sf.net -S: Maintained -F: drivers/platform/x86/asus-laptop.c - ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API M: Dan Williams <dan.j.williams@intel.com> W: http://sourceforge.net/projects/xscaleiop S: Supported F: Documentation/crypto/async-tx-api.txt F: crypto/async_tx/ F: drivers/dma/ F: include/linux/dmaengine.h F: include/linux/async_tx.h AT24 EEPROM DRIVER M: Wolfram Sang <w.sang@pengutronix.de> @@ -2407,40 +2397,24 @@ M: Tim Small <tim@buttersideup.com> L: bluesmoke-devel@lists.sourceforge.net (moderated for non-subscribers) W: bluesmoke.sourceforge.net S: Maintained F: drivers/edac/r82600_edac.c EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch <clemens@ladisch.de> L: alsa-devel@alsa-project.org (moderated for non-subscribers) T: git git://git.alsa-project.org/alsa-kernel.git S: Maintained F: sound/usb/misc/ua101.c -EEEPC LAPTOP EXTRAS DRIVER -M: Corentin Chary <corentincj@iksaif.net> -L: acpi4asus-user@lists.sourceforge.net -L: platform-driver-x86@vger.kernel.org -W: http://acpi4asus.sf.net -S: Maintained -F: drivers/platform/x86/eeepc-laptop.c - -EEEPC WMI EXTRAS DRIVER -M: Corentin Chary <corentincj@iksaif.net> -L: acpi4asus-user@lists.sourceforge.net -L: platform-driver-x86@vger.kernel.org -W: http://acpi4asus.sf.net -S: Maintained -F: drivers/platform/x86/eeepc-wmi.c - EFIFB FRAMEBUFFER DRIVER L: linux-fbdev@vger.kernel.org M: Peter Jones <pjones@redhat.com> S: Maintained F: drivers/video/efifb.c EFS FILESYSTEM W: http://aeschi.ch.eu.org/efs/ S: Orphan F: fs/efs/ EHCA (IBM GX bus InfiniBand adapter) DRIVER @@ -6624,24 +6598,25 @@ F: drivers/net/wireless/zd1201.* USB ZR364XX DRIVER M: Antoine Jacquet <royale@zerezo.com> L: linux-usb@vger.kernel.org L: linux-media@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git W: http://royale.zerezo.com/zr364xx/ S: Maintained F: Documentation/video4linux/zr364xx.txt F: drivers/media/video/zr364xx.c USER-MODE LINUX (UML) M: Jeff Dike <jdike@addtoit.com> +M: Richard Weinberger <richard@nod.at> L: user-mode-linux-devel@lists.sourceforge.net L: user-mode-linux-user@lists.sourceforge.net W: http://user-mode-linux.sourceforge.net S: Maintained F: Documentation/uml/ F: arch/um/ F: fs/hostfs/ F: fs/hppfs/ USERSPACE I/O (UIO) M: "Hans J. Koch" <hjk@linutronix.de> M: Greg Kroah-Hartman <gregkh@suse.de> diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index cc31bec..bd4160c 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -2,24 +2,25 @@ config ALPHA bool default y select HAVE_AOUT select HAVE_IDE select HAVE_OPROFILE select HAVE_SYSCALL_WRAPPERS select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select HAVE_DMA_ATTRS select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE select AUTO_IRQ_AFFINITY if SMP + select GENERIC_IRQ_SHOW select GENERIC_HARDIRQS_NO_DEPRECATED help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, now Hewlett-Packard. The Alpha Linux project has a home page at <http://www.alphalinux.org/>. config 64BIT def_bool y config MMU bool diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index a19d600..381431a 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -58,86 +58,39 @@ int irq_select_affinity(unsigned int irq) while (!cpu_possible(cpu) || !cpumask_test_cpu(cpu, irq_default_affinity)) cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0); last_cpu = cpu; cpumask_copy(data->affinity, cpumask_of(cpu)); chip->irq_set_affinity(data, cpumask_of(cpu), false); return 0; } #endif /* CONFIG_SMP */ -int -show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { int j; - int irq = *(loff_t *) v; - struct irqaction * action; - struct irq_desc *desc; - unsigned long flags; #ifdef CONFIG_SMP - if (irq == 0) { - seq_puts(p, " "); - for_each_online_cpu(j) - seq_printf(p, "CPU%d ", j); - seq_putc(p, '\n'); - } -#endif - - if (irq < ACTUAL_NR_IRQS) { - desc = irq_to_desc(irq); - - if (!desc) - return 0; - - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - seq_printf(p, "%3d: ", irq); -#ifndef CONFIG_SMP - seq_printf(p, "%10u ", kstat_irqs(irq)); -#else - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); + seq_puts(p, "IPI: "); + for_each_online_cpu(j) + seq_printf(p, "%10lu ", cpu_data[j].ipi_count); + seq_putc(p, '\n'); #endif - seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); - seq_printf(p, " %c%s", - (action->flags & IRQF_DISABLED)?'+':' ', - action->name); - - for (action=action->next; action; action = action->next) { - seq_printf(p, ", %c%s", - (action->flags & IRQF_DISABLED)?'+':' ', - action->name); - } - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (irq == ACTUAL_NR_IRQS) { -#ifdef CONFIG_SMP - seq_puts(p, "IPI: "); - for_each_online_cpu(j) - seq_printf(p, "%10lu ", cpu_data[j].ipi_count); - seq_putc(p, '\n'); -#endif - seq_puts(p, "PMI: "); - for_each_online_cpu(j) - seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); - seq_puts(p, " Performance Monitoring\n"); - seq_printf(p, "ERR: %10lu\n", irq_err_count); - } + seq_puts(p, "PMI: "); + for_each_online_cpu(j) + seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); + seq_puts(p, " Performance Monitoring\n"); + seq_printf(p, "ERR: %10lu\n", irq_err_count); return 0; } /* * handle_irq handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific * handlers). */ #define MAX_ILLEGAL_IRQS 16 void diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c index 411ca11..1479dc6 100644 --- a/arch/alpha/kernel/irq_alpha.c +++ b/arch/alpha/kernel/irq_alpha.c @@ -219,25 +219,25 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr, * processed by PALcode, and comes in via entInt vector 1. */ struct irqaction timer_irqaction = { .handler = timer_interrupt, .flags = IRQF_DISABLED, .name = "timer", }; void __init init_rtc_irq(void) { - set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip, + irq_set_chip_and_handler_name(RTC_IRQ, &no_irq_chip, handle_simple_irq, "RTC"); setup_irq(RTC_IRQ, &timer_irqaction); } /* Dummy irqactions. */ struct irqaction isa_cascade_irqaction = { .handler = no_action, .name = "isa-cascade" }; struct irqaction timer_cascade_irqaction = { .handler = no_action, diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index c7cc981..e1861c7 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c @@ -83,25 +83,25 @@ init_i8259a_irqs(void) { static struct irqaction cascade = { .handler = no_action, .name = "cascade", }; long i; outb(0xff, 0x21); /* mask all of 8259A-1 */ outb(0xff, 0xA1); /* mask all of 8259A-2 */ for (i = 0; i < 16; i++) { - set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); } setup_irq(2, &cascade); } #if defined(CONFIG_ALPHA_GENERIC) # define IACK_SC alpha_mv.iack_sc #elif defined(CONFIG_ALPHA_APECS) # define IACK_SC APECS_IACK_SC #elif defined(CONFIG_ALPHA_LCA) # define IACK_SC LCA_IACK_SC diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c index b30227f..13c97a5 100644 --- a/arch/alpha/kernel/irq_pyxis.c +++ b/arch/alpha/kernel/irq_pyxis.c @@ -93,18 +93,18 @@ init_pyxis_irqs(unsigned long ignore_mask) long i; *(vulp)PYXIS_INT_MASK = 0; /* disable all */ *(vulp)PYXIS_INT_REQ = -1; /* flush all */ mb(); /* Send -INTA pulses to clear any pending interrupts ...*/ *(vuip) CIA_IACK_SC; for (i = 16; i < 48; ++i) { if ((ignore_mask >> i) & 1) continue; - set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } setup_irq(16+7, &isa_cascade_irqaction); } diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c index 82a47bb..a79fa30 100644 --- a/arch/alpha/kernel/irq_srm.c +++ b/arch/alpha/kernel/irq_srm.c @@ -42,23 +42,23 @@ static struct irq_chip srm_irq_type = { }; void __init init_srm_irqs(long max, unsigned long ignore_mask) { long i; if (NR_IRQS <= 16) return; for (i = 16; i < max; ++i) { if (i < 64 && ((ignore_mask >> i) & 1)) continue; - set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } void srm_device_interrupt(unsigned long vector) { int irq = (vector - 0x800) >> 4; handle_irq(irq); } diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c index 88d95e8..0e14399 100644 --- a/arch/alpha/kernel/sys_alcor.c +++ b/arch/alpha/kernel/sys_alcor.c @@ -116,25 +116,25 @@ alcor_init_irq(void) *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ for (i = 16; i < 48; ++i) { /* On Alcor, at least, lines 20..30 are not connected and can generate spurious interrupts if we turn them on while IRQ probing. */ if (i >= 16+20 && i <= 16+30) continue; - set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; init_i8259a_irqs(); common_init_isa_dma(); setup_irq(16+31, &isa_cascade_irqaction); } /* diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 57eb630..c8c112d 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c @@ -96,26 +96,26 @@ common_init_irq(void (*srm_dev_int)(unsigned long v)) if (alpha_using_srm) { alpha_mv.device_interrupt = srm_dev_int; init_srm_irqs(35, 0); } else { long i; outb(0xff, 0x804); outb(0xff, 0x805); outb(0xff, 0x806); for (i = 16; i < 35; ++i) { - set_irq_chip_and_handler(i, &cabriolet_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &cabriolet_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } common_init_isa_dma(); setup_irq(16+4, &isa_cascade_irqaction); } #ifndef CONFIG_ALPHA_PC164 static void __init cabriolet_init_irq(void) { diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 481df4e..5ac00fd 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c @@ -261,25 +261,25 @@ clipper_srm_device_interrupt(unsigned long vector) * to scale down the vector reported, we just use it. * * Eg IRQ 24 is DRIR bit 8, etc, etc */ handle_irq(irq); } static void __init init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - set_irq_chip_and_handler(i, ops, handle_level_irq); + irq_set_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } static void __init dp264_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c index 402e908..a7a23b4 100644 --- a/arch/alpha/kernel/sys_eb64p.c +++ b/arch/alpha/kernel/sys_eb64p.c @@ -109,25 +109,25 @@ eb64p_init_irq(void) alpha_mv = cabriolet_mv; alpha_mv.init_irq(); return; } #endif /* GENERIC */ outb(0xff, 0x26); outb(0xff, 0x27); init_i8259a_irqs(); for (i = 16; i < 32; ++i) { - set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } common_init_isa_dma(); setup_irq(16+5, &isa_cascade_irqaction); } /* * PCI Fixup configuration. * * There are two 8 bit external summary registers as follows: * diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c index 0b44a54..a60cd5b 100644 --- a/arch/alpha/kernel/sys_eiger.c +++ b/arch/alpha/kernel/sys_eiger.c @@ -129,25 +129,25 @@ eiger_init_irq(void) outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = eiger_srm_device_interrupt; for (i = 16; i < 128; i += 16) eiger_update_irq_hw(i, -1); init_i8259a_irqs(); for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } static int __init eiger_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { u8 irq_orig; /* The SRM console has already calculated out the IRQ value's for option cards. As this works lets just read in the value already set and change it to a useable value by Linux. diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index 00341b7..7f1a87f1 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c @@ -162,29 +162,29 @@ jensen_device_interrupt(unsigned long vector) last_cc = cc; } #endif handle_irq(irq); } static void __init jensen_init_irq(void) { init_i8259a_irqs(); - set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); - set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); + irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); common_init_isa_dma(); } static void __init jensen_init_arch(void) { struct pci_controller *hose; #ifdef CONFIG_PCI static struct pci_dev fake_isa_bridge = { .dma_mask = 0xffffffffUL, }; isa_bridge = &fake_isa_bridge; diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index e619107..388b99d 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -267,58 +267,58 @@ init_io7_irqs(struct io7 *io7, spin_lock(&io7->irq_lock); /* set up the error irqs */ io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid); io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid); io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid); io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid); io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid); /* Set up the lsi irqs. */ for (i = 0; i < 128; ++i) { - set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); + irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } /* Disable the implemented irqs in hardware. */ for (i = 0; i < 0x60; ++i) init_one_io7_lsi(io7, i, boot_cpuid); init_one_io7_lsi(io7, 0x74, boot_cpuid); init_one_io7_lsi(io7, 0x75, boot_cpuid); /* Set up the msi irqs. */ for (i = 128; i < (128 + 512); ++i) { - set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); + irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } for (i = 0; i < 16; ++i) init_one_io7_msi(io7, i, boot_cpuid); spin_unlock(&io7->irq_lock); } static void __init marvel_init_irq(void) { int i; struct io7 *io7 = NULL; /* Reserve the legacy irqs. */ for (i = 0; i < 16; ++i) { - set_irq_chip_and_handler(i, &marvel_legacy_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &marvel_legacy_irq_type, + handle_level_irq); } /* Init the io7 irqs. */ for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type); } static int marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { struct pci_controller *hose = dev->sysdata; struct io7_port *io7_port = hose->sysdata; diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index cf7f43d..0e6e469 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c @@ -89,25 +89,26 @@ mikasa_device_interrupt(unsigned long vector) static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { - set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &mikasa_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } init_i8259a_irqs(); common_init_isa_dma(); } /* * PCI Fixup configuration. * * Summary @ 0x536: diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 92bc188..a00ac70 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c @@ -118,25 +118,26 @@ noritake_srm_device_interrupt(unsigned long vector) static void __init noritake_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = noritake_srm_device_interrupt; outw(0, 0x54a); outw(0, 0x54c); for (i = 16; i < 48; ++i) { - set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &noritake_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } init_i8259a_irqs(); common_init_isa_dma(); } /* * PCI Fixup configuration. * * Summary @ 0x542, summary register #1: diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index 936d414..7f52161 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c @@ -171,25 +171,26 @@ rawhide_init_irq(void) for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0; for (hose = hose_head; hose; hose = hose->next) { unsigned int h = hose->index; unsigned int mask = hose_irq_masks[h]; cached_irq_masks[h] = mask; *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; } for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &rawhide_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } init_i8259a_irqs(); common_init_isa_dma(); } /* * PCI Fixup configuration. * * Summary @ MCPCIA_PCI0_INT_REQ: * Bit Meaning diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c index cea22a6..216d94d 100644 --- a/arch/alpha/kernel/sys_rx164.c +++ b/arch/alpha/kernel/sys_rx164.c @@ -90,25 +90,25 @@ rx164_device_interrupt(unsigned long vector) handle_irq(16+i); } } } static void __init rx164_init_irq(void) { long i; rx164_update_irq_hw(0); for (i = 16; i < 40; ++i) { - set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } init_i8259a_irqs(); common_init_isa_dma(); setup_irq(16+20, &isa_cascade_irqaction); } /* * The RX164 changed its interrupt routing between pass1 and pass2... diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index a349538..da714e4 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c @@ -509,26 +509,26 @@ sable_lynx_srm_device_interrupt(unsigned long vector) printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n", __func__, vector, bit, irq); #endif handle_irq(irq); } static void __init sable_lynx_init_irq(int nr_of_irqs) { long i; for (i = 0; i < nr_of_irqs; ++i) { - set_irq_chip_and_handler(i, &sable_lynx_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i, &sable_lynx_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } common_init_isa_dma(); } static void __init sable_lynx_init_pci(void) { common_init_pci(); } diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c index 42a5331..a31f8cd 100644 --- a/arch/alpha/kernel/sys_takara.c +++ b/arch/alpha/kernel/sys_takara.c @@ -129,25 +129,26 @@ takara_init_irq(void) ctlreg &= ~0x8000; outl(ctlreg, 0x500); /* Enable the PCI interrupt register. */ ctlreg = 0x05107c00; outl(ctlreg, 0x500); } for (i = 16; i < 128; i += 16) takara_update_irq_hw(i, -1); for (i = 16; i < 128; ++i) { - set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &takara_irq_type, + handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } common_init_isa_dma(); } /* * The Takara has PCI devices 1, 2, and 3 configured to slots 20, * 19, and 18 respectively, in the default configuration. They can * also be jumpered to slots 8, 7, and 6 respectively, which is fun * because the SIO ISA bridge can also be slot 7. However, the SIO diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c index 8c13a0c..fea0e46 100644 --- a/arch/alpha/kernel/sys_titan.c +++ b/arch/alpha/kernel/sys_titan.c @@ -170,25 +170,25 @@ titan_srm_device_interrupt(unsigned long vector) int irq; irq = (vector - 0x800) >> 4; handle_irq(irq); } static void __init init_titan_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { - set_irq_chip_and_handler(i, ops, handle_level_irq); + irq_set_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } static struct irq_chip titan_irq_type = { .name = "TITAN", .irq_unmask = titan_enable_irq, .irq_mask = titan_disable_irq, .irq_mask_ack = titan_disable_irq, .irq_set_affinity = titan_set_irq_affinity, }; diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c index ca60a38..d3cb28b 100644 --- a/arch/alpha/kernel/sys_wildfire.c +++ b/arch/alpha/kernel/sys_wildfire.c @@ -174,35 +174,35 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias); outb(0, DMA2_MASK_REG + io_bias); #endif #if 0 /* ??? Not sure how to do this, yet... */ init_i8259a_irqs(); /* ??? */ #endif for (i = 0; i < 16; ++i) { if (i == 2) continue; - set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } - set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(36 + irq_bias, IRQ_LEVEL); for (i = 40; i < 64; ++i) { - set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, - handle_level_irq); + irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, + handle_level_irq); irq_set_status_flags(i + irq_bias, IRQ_LEVEL); } setup_irq(32+irq_bias, &isa_enable); } static void __init wildfire_init_irq(void) { int qbbno, pcano; #if 1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 93d595a..7c0effb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -19,24 +19,25 @@ config ARM select HAVE_GENERIC_DMA_COHERENT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO select HAVE_KERNEL_LZMA select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ + select GENERIC_IRQ_SHOW help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and handhelds such as the Compaq IPAQ. ARM-based PCs are no longer manufactured, but legacy ARM-based PC hardware remains popular in Europe. There is an ARM Linux project with a web page at <http://www.arm.linux.org.uk/>. config HAVE_PWM bool config MIGHT_HAVE_PCI @@ -2000,24 +2001,25 @@ config ARTHUR Acorn RISC OS/Arthur binaries under Linux. This code is still very experimental; if this sounds frightening, say N and sleep in peace. You can also say M here to compile this support as a module (which will be called arthur). endmenu menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 def_bool y endmenu source "net/Kconfig" source "drivers/Kconfig" source "fs/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index cb6b041..f70ec7d 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -204,26 +204,26 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) if (gic_arch_extn.irq_set_wake) ret = gic_arch_extn.irq_set_wake(d, on); return ret; } #else #define gic_set_wake NULL #endif static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct gic_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct gic_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, gic_irq; unsigned long status; /* primary controller ack'ing */ chip->irq_ack(&desc->irq_data); spin_lock(&irq_controller_lock); status = readl(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); gic_irq = (status & 0x3ff); if (gic_irq == 1023) @@ -248,27 +248,27 @@ static struct irq_chip gic_chip = { .irq_set_type = gic_set_type, .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity, #endif .irq_set_wake = gic_set_wake, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) { if (gic_nr >= MAX_GIC_NR) BUG(); - if (set_irq_data(irq, &gic_data[gic_nr]) != 0) + if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) BUG(); - set_irq_chained_handler(irq, gic_handle_cascade_irq); + irq_set_chained_handler(irq, gic_handle_cascade_irq); } static void __init gic_dist_init(struct gic_chip_data *gic, unsigned int irq_start) { unsigned int gic_irqs, irq_limit, i; void __iomem *base = gic->dist_base; u32 cpumask = 1 << smp_processor_id(); cpumask |= cpumask << 8; cpumask |= cpumask << 16; @@ -310,27 +310,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic, /* * Limit number of interrupts registered to the platform maximum */ irq_limit = gic->irq_offset + gic_irqs; if (WARN_ON(irq_limit > NR_IRQS)) irq_limit = NR_IRQS; /* * Setup the Linux IRQ subsystem. */ for (i = irq_start; i < irq_limit; i++) { - set_irq_chip(i, &gic_chip); - set_irq_chip_data(i, gic); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); + irq_set_chip_data(i, gic); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } writel(1, base + GIC_DIST_CTRL); } static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) { void __iomem *dist_base = gic->dist_base; void __iomem *base = gic->cpu_base; int i; @@ -373,25 +372,25 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start, void __cpuinit gic_secondary_init(unsigned int gic_nr) { BUG_ON(gic_nr >= MAX_GIC_NR); gic_cpu_init(&gic_data[gic_nr]); } void __cpuinit gic_enable_ppi(unsigned int irq) { unsigned long flags; local_irq_save(flags); - irq_to_desc(irq)->status |= IRQ_NOPROBE; + irq_set_status_flags(irq, IRQ_NOPROBE); gic_unmask_irq(irq_get_irq_data(irq)); local_irq_restore(flags); } #ifdef CONFIG_SMP void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { unsigned long map = *cpus_addr(*mask); /* this always happens on GIC0 */ writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); } diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index fcddd48..7a21927 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -79,26 +79,26 @@ static struct irq_chip it8152_irq_chip = { void it8152_init_irq(void) { int irq; __raw_writel((0xffff), IT8152_INTC_PDCNIMR); __raw_writel((0), IT8152_INTC_PDCNIRR); __raw_writel((0xffff), IT8152_INTC_LPCNIMR); __raw_writel((0), IT8152_INTC_LPCNIRR); __raw_writel((0xffff), IT8152_INTC_LDCNIMR); __raw_writel((0), IT8152_INTC_LDCNIRR); for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { - set_irq_chip(irq, &it8152_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &it8152_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { int bits_pd, bits_lp, bits_ld; int i; while (1) { /* Read all */ bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index a026a6b..b55c362 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -131,25 +131,25 @@ static struct locomo_dev_info locomo_devices[] = { }, { .devid = LOCOMO_DEVID_SPI, .irq = {}, .name = "locomo-spi", .offset = LOCOMO_SPI, .length = 0x30, }, }; static void locomo_handler(unsigned int irq, struct irq_desc *desc) { - struct locomo *lchip = get_irq_chip_data(irq); + struct locomo *lchip = irq_get_chip_data(irq); int req, i; /* Acknowledge the parent IRQ */ desc->irq_data.chip->irq_ack(&desc->irq_data); /* check why this interrupt was generated */ req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; if (req) { /* generate the next interrupt(s) */ irq = lchip->irq_base; for (i = 0; i <= 3; i++, irq++) { @@ -188,33 +188,32 @@ static struct irq_chip locomo_chip = { .irq_ack = locomo_ack_irq, .irq_mask = locomo_mask_irq, .irq_unmask = locomo_unmask_irq, }; static void locomo_setup_irq(struct locomo *lchip) { int irq = lchip->irq_base; /* * Install handler for IRQ_LOCOMO_HW. */ - set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); - set_irq_chip_data(lchip->irq, lchip); - set_irq_chained_handler(lchip->irq, locomo_handler); + irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(lchip->irq, lchip); + irq_set_chained_handler(lchip->irq, locomo_handler); /* Install handlers for IRQ_LOCOMO_* */ for ( ; irq <= lchip->irq_base + 3; irq++) { - set_irq_chip(irq, &locomo_chip); - set_irq_chip_data(irq, lchip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); + irq_set_chip_data(irq, lchip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } static void locomo_dev_release(struct device *_dev) { struct locomo_dev *dev = LOCOMO_DEV(_dev); kfree(dev); } @@ -467,26 +466,26 @@ __locomo_probe(struct device *me, struct resource *mem, int irq) static int locomo_remove_child(struct device *dev, void *data) { device_unregister(dev); return 0; } static void __locomo_remove(struct locomo *lchip) { device_for_each_child(lchip->dev, NULL, locomo_remove_child); if (lchip->irq != NO_IRQ) { - set_irq_chained_handler(lchip->irq, NULL); - set_irq_data(lchip->irq, NULL); + irq_set_chained_handler(lchip->irq, NULL); + irq_set_handler_data(lchip->irq, NULL); } iounmap(lchip->base); kfree(lchip); } static int locomo_probe(struct platform_device *dev) { struct resource *mem; int irq; mem = platform_get_resource(dev, IORESOURCE_MEM, 0); diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index eb9796b..a12b33c 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -193,25 +193,25 @@ void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) size[0] = sz; } /* * SA1111 interrupt support. Since clearing an IRQ while there are * active IRQs causes the interrupt output to pulse, the upper levels * will call us again if there are more interrupts to process. */ static void sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int stat0, stat1, i; - struct sa1111 *sachip = get_irq_data(irq); + struct sa1111 *sachip = irq_get_handler_data(irq); void __iomem *mapbase = sachip->base + SA1111_INTC; stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); desc->irq_data.chip->irq_ack(&desc->irq_data); sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); if (stat0 == 0 && stat1 == 0) { @@ -463,43 +463,43 @@ static void sa1111_setup_irq(struct sa1111 *sachip) * specifies that S0ReadyInt and S1ReadyInt should be '1'. */ sa1111_writel(0, irqbase + SA1111_INTPOL0); sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) | SA1111_IRQMASK_HI(IRQ_S1_READY_NINT), irqbase + SA1111_INTPOL1); /* clear all IRQs */ sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { - set_irq_chip(irq, &sa1111_low_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_low_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { - set_irq_chip(irq, &sa1111_high_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_high_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Register SA1111 interrupt */ - set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); - set_irq_data(sachip->irq, sachip); - set_irq_chained_handler(sachip->irq, sa1111_irq_handler); + irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler_data(sachip->irq, sachip); + irq_set_chained_handler(sachip->irq, sa1111_irq_handler); } /* * Bring the SA1111 out of reset. This requires a set procedure: * 1. nRESET asserted (by hardware) * 2. CLK turned on from SA1110 * 3. nRESET deasserted * 4. VCO turned on, PLL_BYPASS turned off * 5. Wait lock time, then assert RCLKEn * 7. PCR set to allow clocking of individual functions * * Until we've done this, the only registers we can access are: @@ -806,26 +806,26 @@ static void __sa1111_remove(struct sa1111 *sachip) device_for_each_child(sachip->dev, NULL, sa1111_remove_one); /* disable all IRQs */ sa1111_writel(0, irqbase + SA1111_INTEN0); sa1111_writel(0, irqbase + SA1111_INTEN1); sa1111_writel(0, irqbase + SA1111_WAKEEN0); sa1111_writel(0, irqbase + SA1111_WAKEEN1); clk_disable(sachip->clk); if (sachip->irq != NO_IRQ) { - set_irq_chained_handler(sachip->irq, NULL); - set_irq_data(sachip->irq, NULL); + irq_set_chained_handler(sachip->irq, NULL); + irq_set_handler_data(sachip->irq, NULL); release_mem_region(sachip->phys + SA1111_INTC, 512); } iounmap(sachip->base); clk_put(sachip->clk); kfree(sachip); } /* * According to the "Intel StrongARM SA-1111 Microprocessor Companion * Chip Specification Update" (June 2000), erratum #7, there is a diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index ae5fe72..113085a 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -296,27 +296,27 @@ static void __init vic_clear_interrupts(void __iomem *base) } } static void __init vic_set_irq_sources(void __iomem *base, unsigned int irq_start, u32 vic_sources) { unsigned int i; for (i = 0; i < 32; i++) { if (vic_sources & (1 << i)) { unsigned int irq = irq_start + i; - set_irq_chip(irq, &vic_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &vic_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } } /* * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. * The original cell has 32 interrupts, while the modified one has 64, * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case * the probe function is called twice, with base set to offset 000 * and 020 within the page. We call this "second block". */ diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h index 5586b7c..a71b417 100644 --- a/arch/arm/include/asm/hw_irq.h +++ b/arch/arm/include/asm/hw_irq.h @@ -1,29 +1,21 @@ /* * Nothing to see here yet */ #ifndef _ARCH_ARM_HW_IRQ_H #define _ARCH_ARM_HW_IRQ_H static inline void ack_bad_irq(int irq) { extern unsigned long irq_err_count; irq_err_count++; } -/* - * Obsolete inline function for calling irq descriptor handlers. - */ -static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - desc->handle_irq(irq, desc); -} - void set_irq_flags(unsigned int irq, unsigned int flags); #define IRQF_VALID (1 << 0) #define IRQF_PROBE (1 << 1) #define IRQF_NOAUTOEN (1 << 2) #define ARCH_IRQ_INIT_FLAGS (IRQ_NOREQUEST | IRQ_NOPROBE) #endif diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d86fcd4..e4ee050 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -150,49 +150,24 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev) dev->class &= 0xff; dev->class |= PCI_CLASS_BRIDGE_HOST << 8; for (i = 0; i < PCI_NUM_RESOURCES; i++) { dev->resource[i].start = 0; dev->resource[i].end = 0; dev->resource[i].flags = 0; } } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); /* - * Same as above. The PrPMC800 carrier board for the PrPMC1100 - * card maps the host-bridge @ 00:01:00 for some reason and it - * ends up getting scanned. Note that we only want to do this - * fixup when we find the IXP4xx on a PrPMC system, which is why - * we check the machine type. We could be running on a board - * with an IXP4xx target device and we don't want to kill the - * resources in that case. - */ -static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) -{ - int i; - - if (machine_is_prpmc1100()) { - dev->class &= 0xff; - dev->class |= PCI_CLASS_BRIDGE_HOST << 8; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); - -/* * PCI IDE controllers use non-standard I/O port decoding, respect it. */ static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) { struct resource *r; int i; if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) return; for (i = 0; i < PCI_NUM_RESOURCES; i++) { r = dev->resource + i; diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 2ad62df..d165001 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -1034,26 +1034,26 @@ ecard_probe(int slot, card_type_t type) for (i = 0; i < ARRAY_SIZE(blacklist); i++) if (blacklist[i].manufacturer == ec->cid.manufacturer && blacklist[i].product == ec->cid.product) { ec->card_desc = blacklist[i].type; break; } /* * hook the interrupt handlers */ if (slot < 8) { ec->irq = 32 + slot; - set_irq_chip(ec->irq, &ecard_chip); - set_irq_handler(ec->irq, handle_level_irq); + irq_set_chip_and_handler(ec->irq, &ecard_chip, + handle_level_irq); set_irq_flags(ec->irq, IRQF_VALID); } #ifdef IO_EC_MEMC8_BASE if (slot == 8) ec->irq = 11; #endif #ifdef CONFIG_ARCH_RPC /* On RiscPC, only first two slots have DMA capability */ if (slot < 2) ec->dma = 2 + slot; #endif @@ -1094,25 +1094,25 @@ static int __init ecard_init(void) for (slot = 0; slot < 8; slot ++) { if (ecard_probe(slot, ECARD_EASI) == -ENODEV) ecard_probe(slot, ECARD_IOC); } #ifdef IO_EC_MEMC8_BASE ecard_probe(8, ECARD_IOC); #endif irqhw = ecard_probeirqhw(); - set_irq_chained_handler(IRQ_EXPANSIONCARD, + irq_set_chained_handler(IRQ_EXPANSIONCARD, irqhw ? ecard_irqexp_handler : ecard_irq_handler); ecard_proc_init(); return 0; } subsys_initcall(ecard_init); /* * ECARD "bus" */ diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 3535d37..83bbad0 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -42,81 +42,36 @@ #include <asm/mach/irq.h> #include <asm/mach/time.h> /* * No architecture-specific irq_finish function defined in arm/arch/irqs.h. */ #ifndef irq_finish #define irq_finish(irq) do { } while (0) #endif unsigned long irq_err_count; -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, cpu; - struct irq_desc *desc; - struct irqaction * action; - unsigned long flags; - int prec, n; - - for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++) - n *= 10; - -#ifdef CONFIG_SMP - if (prec < 4) - prec = 4; -#endif - - if (i == 0) { - char cpuname[12]; - - seq_printf(p, "%*s ", prec, ""); - for_each_present_cpu(cpu) { - sprintf(cpuname, "CPU%d", cpu); - seq_printf(p, " %10s", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < nr_irqs) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - - seq_printf(p, "%*d: ", prec, i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == nr_irqs) { #ifdef CONFIG_FIQ - show_fiq_list(p, prec); + show_fiq_list(p, prec); #endif #ifdef CONFIG_SMP - show_ipi_list(p, prec); + show_ipi_list(p, prec); #endif #ifdef CONFIG_LOCAL_TIMERS - show_local_irqs(p, prec); + show_local_irqs(p, prec); #endif - seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); - } + seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; } /* * do_IRQ handles all hardware IRQ's. Decoded IRQs should not * come via this function. Instead, they should provide their * own 'handler' */ asmlinkage void __exception_irq_entry asm_do_IRQ(unsigned int irq, struct pt_regs *regs) { struct pt_regs *old_regs = set_irq_regs(regs); @@ -135,42 +90,39 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs) generic_handle_irq(irq); } /* AT91 specific workaround */ irq_finish(irq); irq_exit(); set_irq_regs(old_regs); } void set_irq_flags(unsigned int irq, unsigned int iflags) { - struct irq_desc *desc; - unsigned long flags; + unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (irq >= nr_irqs) { printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); return; } - desc = irq_to_desc(irq); - raw_spin_lock_irqsave(&desc->lock, flags); - desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (iflags & IRQF_VALID) - desc->status &= ~IRQ_NOREQUEST; + clr |= IRQ_NOREQUEST; if (iflags & IRQF_PROBE) - desc->status &= ~IRQ_NOPROBE; + clr |= IRQ_NOPROBE; if (!(iflags & IRQF_NOAUTOEN)) - desc->status &= ~IRQ_NOAUTOEN; - raw_spin_unlock_irqrestore(&desc->lock, flags); + clr |= IRQ_NOAUTOEN; + /* Order is clear bits in "clr" then set bits in "set" */ + irq_modify_status(irq, clr, set & ~clr); } void __init init_IRQ(void) { machine_desc->init_irq(); } #ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs(void) { nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; return nr_irqs; diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index d1f775e..9ffbf3a 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -63,25 +63,25 @@ static struct platform_device at91_usbh_device = { .resource = usbh_resources, .num_resources = ARRAY_SIZE(usbh_resources), }; void __init at91_add_device_usbh(struct at91_usbh_data *data) { int i; if (!data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (data->vbus_pin[i]) at91_set_gpio_output(data->vbus_pin[i], 0); } usbh_data = *data; platform_device_register(&at91_usbh_device); } #else void __init at91_add_device_usbh(struct at91_usbh_data *data) {} @@ -148,25 +148,25 @@ static struct platform_device at91_usba_udc_device = { .name = "atmel_usba_udc", .id = -1, .dev = { .platform_data = &usba_udc_data.pdata, }, .resource = usba_udc_resources, .num_resources = ARRAY_SIZE(usba_udc_resources), }; void __init at91_add_device_usba(struct usba_platform_data *data) { if (cpu_is_at91cap9_revB()) { - set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | AT91_MATRIX_UDPHS_BYPASS_LOCK); } else at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS); /* * Invalid pins are 0 on AT91, but the usba driver is shared * with AVR32, which use negative values instead. Once/if * gpio_is_valid() is ported to AT91, revisit this code. */ usba_udc_data.pdata.vbus_pin = -EINVAL; @@ -852,25 +852,25 @@ static struct platform_device at91_lcdc_device = { .platform_data = &lcdc_data, }, .resource = lcdc_resources, .num_resources = ARRAY_SIZE(lcdc_resources), }; void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index af818a2..4615528 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -278,25 +278,25 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) { unsigned mask = pin_to_mask(d->irq); unsigned bank = (d->irq - PIN_BASE) / 32; if (unlikely(bank >= MAX_GPIO_BANKS)) return -EINVAL; if (state) wakeups[bank] |= mask; else wakeups[bank] &= ~mask; - set_irq_wake(gpio_chip[bank].bank->id, state); + irq_set_irq_wake(gpio_chip[bank].bank->id, state); return 0; } void at91_gpio_suspend(void) { int i; for (i = 0; i < gpio_banks; i++) { void __iomem *pio = gpio_chip[i].regbase; backups[i] = __raw_readl(pio + PIO_IMR); @@ -366,79 +366,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) { switch (type) { case IRQ_TYPE_NONE: case IRQ_TYPE_EDGE_BOTH: return 0; default: return -EINVAL; } } static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, .irq_set_type = gpio_irq_type, .irq_set_wake = gpio_irq_set_wake, }; static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { unsigned pin; - struct irq_desc *gpio; - struct at91_gpio_chip *at91_gpio; - void __iomem *pio; + struct irq_data *idata = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(idata); + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); + void __iomem *pio = at91_gpio->regbase; u32 isr; - at91_gpio = get_irq_chip_data(irq); - pio = at91_gpio->regbase; - /* temporarily mask (level sensitive) parent IRQ */ - desc->irq_data.chip->irq_ack(&desc->irq_data); + chip->irq_ack(idata); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. * When there none are pending, we're finished unless we need * to process multiple banks (like ID_PIOCDE on sam9263). */ isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); if (!isr) { if (!at91_gpio->next) break; at91_gpio = at91_gpio->next; pio = at91_gpio->regbase; continue; } pin = at91_gpio->chip.base; - gpio = &irq_desc[pin]; while (isr) { - if (isr & 1) { - if (unlikely(gpio->depth)) { - /* - * The core ARM interrupt handler lazily disables IRQs so - * another IRQ must be generated before it actually gets - * here to be disabled on the GPIO controller. - */ - gpio_irq_mask(irq_get_irq_data(pin)); - } - else - generic_handle_irq(pin); - } + if (isr & 1) + generic_handle_irq(pin); pin++; - gpio++; isr >>= 1; } } - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chip->irq_unmask(idata); /* now it may re-trigger */ } /*--------------------------------------------------------------------------*/ #ifdef CONFIG_DEBUG_FS static int at91_gpio_show(struct seq_file *s, void *unused) { int bank, j; /* print heading */ @@ -509,44 +496,44 @@ void __init at91_gpio_irq_setup(void) unsigned pioc, pin; struct at91_gpio_chip *this, *prev; for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; pioc++ < gpio_banks; prev = this, this++) { unsigned id = this->bank->id; unsigned i; __raw_writel(~0, this->regbase + PIO_IDR); for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { - lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); + irq_set_lockdep_class(pin, &gpio_lock_class); /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. */ - set_irq_chip(pin, &gpio_irqchip); - set_irq_handler(pin, handle_simple_irq); + irq_set_chip_and_handler(pin, &gpio_irqchip, + handle_simple_irq); set_irq_flags(pin, IRQF_VALID); } /* The toplevel handler handles one bank of GPIOs, except * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in * the list, so we only set up that handler. */ if (prev && prev->next == this) continue; - set_irq_chip_data(id, this); - set_irq_chained_handler(id, gpio_irq_handler); + irq_set_chip_data(id, this); + irq_set_chained_handler(id, gpio_irq_handler); } pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); } /* gpiolib support */ static int at91_gpiolib_direction_input(struct gpio_chip *chip, unsigned offset) { struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); void __iomem *pio = at91_gpio->regbase; unsigned mask = 1 << offset; diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h index 2d9b0af..be510cf 100644 --- a/arch/arm/mach-at91/include/mach/at572d940hf.h +++ b/arch/arm/mach-at91/include/mach/at572d940hf.h @@ -80,25 +80,25 @@ #define AT572D940HF_BASE_SPI1 0xfffcc000 #define AT572D940HF_BASE_SSC3 0xfffd0000 #define AT572D940HF_BASE_TWI1 0xfffd4000 #define AT572D940HF_BASE_EMAC 0xfffd8000 #define AT572D940HF_BASE_CAN0 0xfffdc000 #define AT572D940HF_BASE_CAN1 0xfffe0000 #define AT91_BASE_SYS 0xffffea00 /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index b56d6b3a..9665265e 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -134,26 +134,25 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) unsigned int i; /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. */ for (i = 0; i < NR_AIC_IRQS; i++) { /* Put irq number in Source Vector Register: */ at91_sys_write(AT91_AIC_SVR(i), i); /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); - set_irq_chip(i, &at91_aic_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ if (i < 8) at91_sys_write(AT91_AIC_EOICR, 0); } /* * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU */ at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index 84dcda0..c48feaf 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -84,44 +84,44 @@ static struct irq_chip bcmring_irq2_chip = { .name = "ARM-SINTC", .irq_ack = bcmring_mask_irq2, .irq_mask = bcmring_mask_irq2, .irq_unmask = bcmring_unmask_irq2, }; static void vic_init(void __iomem *base, struct irq_chip *chip, unsigned int irq_start, unsigned int vic_sources) { unsigned int i; for (i = 0; i < 32; i++) { unsigned int irq = irq_start + i; - set_irq_chip(irq, chip); - set_irq_chip_data(irq, base); + irq_set_chip(irq, chip); + irq_set_chip_data(irq, base); if (vic_sources & (1 << i)) { - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } writel(0, base + INTCHW_INTSELECT); writel(0, base + INTCHW_INTENABLE); writel(~0, base + INTCHW_INTENCLEAR); writel(0, base + INTCHW_IRQSTATUS); writel(~0, base + INTCHW_SOFTINTCLEAR); } void __init bcmring_init_irq(void) { vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip, IRQ_INTC0_START, IRQ_INTC0_VALID_MASK); vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip, IRQ_INTC1_START, IRQ_INTC1_VALID_MASK); vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip, IRQ_SINTC_START, IRQ_SINTC_VALID_MASK); /* special cases */ if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO0, handle_simple_irq); + irq_set_handler(IRQ_GPIO0, handle_simple_irq); } if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO1, handle_simple_irq); + irq_set_handler(IRQ_GPIO1, handle_simple_irq); } } diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 86da7a1..c2eceee 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c @@ -103,31 +103,31 @@ static void int2_unmask(struct irq_data *d) static struct irq_chip int2_chip = { .irq_ack = int2_ack, .irq_mask = int2_mask, .irq_unmask = int2_unmask, }; void __init clps711x_init_irq(void) { unsigned int i; for (i = 0; i < NR_IRQS; i++) { if (INT1_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int1_chip); + irq_set_chip_and_handler(i, &int1_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } if (INT2_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int2_chip); + irq_set_chip_and_handler(i, &int2_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } /* * Disable interrupts */ clps_writel(0, INTMR1); clps_writel(0, INTMR2); /* * Clear down any pending interrupts diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 9abc80a..f83152d 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -158,20 +158,20 @@ void __init cp_intc_init(void) * are mapped to nIRQ. */ for (i = 0; i < num_reg; i++) cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); } if (host_map) for (i = 0; host_map[i] != -1; i++) cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); /* Set up genirq dispatching for cp_intc */ for (i = 0; i < num_irq; i++) { - set_irq_chip(i, &cp_intc_irq_chip); + irq_set_chip(i, &cp_intc_irq_chip); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); } /* Enable global interrupt */ cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); } diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 20d66e5..a0b8388 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -53,25 +53,25 @@ static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) ptr = gpio_base + 0x88; else if (gpio < 32 * 5) ptr = gpio_base + 0xb0; else ptr = NULL; return ptr; } static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) { struct davinci_gpio_regs __iomem *g; - g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); + g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); return g; } static int __init davinci_gpio_irq_setup(void); /*--------------------------------------------------------------------------*/ /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ static inline int __davinci_direction(struct gpio_chip *chip, unsigned offset, bool out, int value) { @@ -199,72 +199,63 @@ pure_initcall(davinci_gpio_setup); * used as output pins ... which is convenient for testing. * * NOTE: The first few GPIOs also have direct INTC hookups in addition * to their GPIOBNK0 irq, with a bit less overhead. * * All those INTC hookups (direct, plus several IRQ banks) can also * serve as EDMA event triggers. */ static void gpio_irq_disable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); } static void gpio_irq_enable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); - unsigned status = irq_desc[d->irq].status; + u32 mask = (u32) irq_data_get_irq_handler_data(d); + unsigned status = irqd_get_trigger_type(d); status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (!status) status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (status & IRQ_TYPE_EDGE_FALLING) __raw_writel(mask, &g->set_falling); if (status & IRQ_TYPE_EDGE_RISING) __raw_writel(mask, &g->set_rising); } static int gpio_irq_type(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[d->irq].status |= trigger; - - /* don't enable the IRQ if it's currently disabled */ - if (irq_desc[d->irq].depth == 0) { - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); - } return 0; } static struct irq_chip gpio_irqchip = { .name = "GPIO", .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, + .flags = IRQCHIP_SET_TYPE_MASKED, }; static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g = irq2regs(irq); u32 mask = 0xffff; /* we only care about one bank */ if (irq & 1) mask <<= 16; @@ -276,25 +267,25 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) int n; int res; /* ack any irqs */ status = __raw_readl(&g->intstat) & mask; if (!status) break; __raw_writel(status, &g->intstat); if (irq & 1) status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)get_irq_data(irq); + n = (int)irq_get_handler_data(irq); while (status) { res = ffs(status); n += res; generic_handle_irq(n - 1); status >>= res; } } desc->irq_data.chip->irq_unmask(&desc->irq_data); /* now it may re-trigger */ } static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) @@ -314,25 +305,25 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) /* NOTE: we assume for now that only irqs in the first gpio_chip * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). */ if (offset < soc_info->gpio_unbanked) return soc_info->gpio_irq + offset; else return -ENODEV; } static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) ? &g->set_falling : &g->clr_falling); __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) ? &g->set_rising : &g->clr_rising); return 0; } @@ -386,68 +377,68 @@ static int __init davinci_gpio_irq_setup(void) * controller only handling trigger modes. We currently assume no * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. */ if (soc_info->gpio_unbanked) { static struct irq_chip gpio_irqchip_unbanked; /* pass "bank 0" GPIO IRQs to AINTC */ chips[0].chip.to_irq = gpio_to_irq_unbanked; binten = BIT(0); /* AINTC handles mask/unmask; GPIO handles triggering */ irq = bank_irq; - gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); + gpio_irqchip_unbanked = *irq_get_chip(irq); gpio_irqchip_unbanked.name = "GPIO-AINTC"; gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; /* default trigger: both edges */ g = gpio2regs(0); __raw_writel(~0, &g->set_falling); __raw_writel(~0, &g->set_rising); /* set the direct IRQs up to use that irqchip */ for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { - set_irq_chip(irq, &gpio_irqchip_unbanked); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_chip_data(irq, (__force void *) g); - irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; + irq_set_chip(irq, &gpio_irqchip_unbanked); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_chip_data(irq, (__force void *)g); + irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); } goto done; } /* * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we * then chain through our own handler. */ for (gpio = 0, irq = gpio_to_irq(0), bank = 0; gpio < ngpio; bank++, bank_irq++) { unsigned i; /* disabled by default, enabled only as needed */ g = gpio2regs(gpio); __raw_writel(~0, &g->clr_falling); __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ - set_irq_chained_handler(bank_irq, gpio_irq_handler); - set_irq_chip_data(bank_irq, (__force void *) g); - set_irq_data(bank_irq, (void *) irq); + irq_set_chained_handler(bank_irq, gpio_irq_handler); + irq_set_chip_data(bank_irq, (__force void *)g); + irq_set_handler_data(bank_irq, (void *)irq); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { - set_irq_chip(irq, &gpio_irqchip); - set_irq_chip_data(irq, (__force void *) g); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip(irq, &gpio_irqchip); + irq_set_chip_data(irq, (__force void *)g); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } binten |= BIT(bank); } done: /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ __raw_writel(binten, gpio_base + 0x08); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5e05c9b..e6269a6 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -145,20 +145,20 @@ void __init davinci_irq_init(void) for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { unsigned j; u32 pri; for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) pri |= (*davinci_def_priorities & 0x07) << j; davinci_irq_writel(pri, i); } /* set up genirq dispatch for ARM INTC */ for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { - set_irq_chip(i, &davinci_irq_chip_0); + irq_set_chip(i, &davinci_irq_chip_0); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); if (i != IRQ_TINT1_TINT34) - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); else - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); } } diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index e5fcdd3..b20ec9a 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -127,25 +127,25 @@ /* MPP, GPIO, Reset Sampling */ #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) #define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420) #define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) +#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) #define DOVE_SPI_GPIO_SEL (1 << 5) #define DOVE_UART1_GPIO_SEL (1 << 4) #define DOVE_AU1_GPIO_SEL (1 << 3) #define DOVE_CAM_GPIO_SEL (1 << 2) #define DOVE_SD1_GPIO_SEL (1 << 1) #define DOVE_SD0_GPIO_SEL (1 << 0) /* Power Management */ #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) /* Real Time Clock */ diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 101707f..f07fd16 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -77,55 +77,53 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) unsigned long cause = readl(PMU_INTERRUPT_CAUSE); cause &= readl(PMU_INTERRUPT_MASK); if (cause == 0) { do_bad_IRQ(irq, desc); return; } for (irq = 0; irq < NR_PMU_IRQS; irq++) { if (!(cause & (1 << irq))) continue; irq = pmu_to_irq(irq); - desc = irq_desc + irq; - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } void __init dove_init_irq(void) { int i; orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* * Initialize gpiolib for GPIOs 0-71. */ orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START); - set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32); - set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64); /* * Mask and clear PMU interrupts */ writel(0, PMU_INTERRUPT_MASK); writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { - set_irq_chip(i, &pmu_irq_chip); - set_irq_handler(i, handle_level_irq); - irq_desc[i].status |= IRQ_LEVEL; + irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); + irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); } diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 71db2bd..c66c763 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -138,27 +138,24 @@ static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) *mpp_ctrl |= sel << num; dove_mpp_gpio_mode(start, end, gpio_mode); } void __init dove_mpp_conf(unsigned int *mpp_list) { u32 mpp_ctrl[MPP_NR_REGS]; u32 pmu_mpp_ctrl = 0; u32 pmu_sig_ctrl[PMU_SIG_REGS]; int i; - /* Initialize gpiolib. */ - orion_gpio_init(); - for (i = 0; i < MPP_NR_REGS; i++) mpp_ctrl[i] = readl(MPP_CTRL(i)); for (i = 0; i < PMU_SIG_REGS; i++) pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i)); pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL); dove_mpp_dump_regs(); for ( ; *mpp_list != MPP_END; mpp_list++) { unsigned int num = MPP_NUM(*mpp_list); diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 7df083f..087bc77 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -57,26 +57,26 @@ static void __init ebsa110_init_irq(void) unsigned int irq; local_irq_save(flags); __raw_writeb(0xff, IRQ_MCLR); __raw_writeb(0x55, IRQ_MSET); __raw_writeb(0x00, IRQ_MSET); if (__raw_readb(IRQ_MASK) != 0x55) while (1); __raw_writeb(0xff, IRQ_MCLR); /* clear all interrupt enables */ local_irq_restore(flags); for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &ebsa110_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ebsa110_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } static struct map_desc ebsa110_io_desc[] __initdata = { /* * sparse external-decode ISAIO space */ { /* IRQ_STAT/IRQ_MCLR */ .virtual = IRQ_STAT, .pfn = __phys_to_pfn(TRICK4_PHYS), .length = PGDIR_SIZE, diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 34e071d..180b8a9 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -108,39 +108,39 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; generic_handle_irq(gpio_irq); } static void ep93xx_gpio_irq_ack(struct irq_data *d) { int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ep93xx_gpio_update_int_params(port); } __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); } static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; ep93xx_gpio_update_int_params(port); __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); } static void ep93xx_gpio_irq_mask(struct irq_data *d) { int line = irq_to_gpio(d->irq); int port = line >> 3; @@ -156,105 +156,113 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) gpio_int_unmasked[port] |= 1 << (line & 7); ep93xx_gpio_update_int_params(port); } /* * gpio_int_type1 controls whether the interrupt is level (0) or * edge (1) triggered, while gpio_int_type2 controls whether it * triggers on low/falling (0) or high/rising (1). */ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_desc + d->irq; const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); + irq_flow_handler_t handler; gpio_direction_input(gpio); switch (type) { case IRQ_TYPE_EDGE_RISING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: gpio_int_type1[port] |= port_mask; /* set initial polarity based on current input level */ if (gpio_get_value(gpio)) gpio_int_type2[port] &= ~port_mask; /* falling */ else gpio_int_type2[port] |= port_mask; /* rising */ - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; default: pr_err("failed to set irq type %d for gpio %d\n", type, gpio); return -EINVAL; } - gpio_int_enabled[port] |= port_mask; + __irq_set_handler_locked(d->irq, handler); - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type & IRQ_TYPE_SENSE_MASK; + gpio_int_enabled[port] |= port_mask; ep93xx_gpio_update_int_params(port); return 0; } static struct irq_chip ep93xx_gpio_irq_chip = { .name = "GPIO", .irq_ack = ep93xx_gpio_irq_ack, .irq_mask_ack = ep93xx_gpio_irq_mask_ack, .irq_mask = ep93xx_gpio_irq_mask, .irq_unmask = ep93xx_gpio_irq_unmask, .irq_set_type = ep93xx_gpio_irq_type, }; void __init ep93xx_gpio_init_irq(void) { int gpio_irq; for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { - set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); - set_irq_handler(gpio_irq, handle_level_irq); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); set_irq_flags(gpio_irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, + ep93xx_gpio_ab_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, + ep93xx_gpio_f_irq_handler); } /************************************************************************* * gpiolib interface for EP93xx on-chip GPIOs *************************************************************************/ struct ep93xx_gpio_chip { struct gpio_chip chip; void __iomem *data_reg; void __iomem *data_dir_reg; }; diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index a021b52..e849f67 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -11,24 +11,29 @@ if ARCH_EXYNOS4 config CPU_EXYNOS4210 bool select S3C_PL330_DMA help Enable EXYNOS4210 CPU support config EXYNOS4_MCT bool "Kernel timer support by MCT" help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS4_DEV_AHCI + bool + help + Compile in platform device definitions for AHCI + config EXYNOS4_DEV_PD bool help Compile in platform device definitions for Power Domain config EXYNOS4_DEV_SYSMMU bool help Common setup code for SYSTEM MMU in EXYNOS4 config EXYNOS4_SETUP_I2C1 bool @@ -125,27 +130,27 @@ config MACH_SMDKV310 select EXYNOS4_SETUP_SDHCI help Machine support for Samsung SMDKV310 config MACH_ARMLEX4210 bool "ARMLEX4210" select CPU_EXYNOS4210 select S3C_DEV_RTC select S3C_DEV_WDT select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select EXYNOS4_DEV_AHCI select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI - select SATA_AHCI_PLATFORM help Machine support for Samsung ARMLEX4210 based on EXYNOS4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_EXYNOS4210 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 select S3C_DEV_I2C5 select S5P_DEV_ONENAND diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index b8f0e7d..9be104f 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -30,27 +30,27 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o # device support obj-y += dev-audio.o +obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S index 58bbd04..a442ef8 100644 --- a/arch/arm/mach-exynos4/include/mach/debug-macro.S +++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S @@ -12,24 +12,24 @@ /* pull in the relevant register and map files. */ #include <mach/map.h> /* note, for the boot process to work we have to keep the UART * virtual address aligned to an 1MiB boundary for the L1 * mapping the head code makes. We keep the UART virtual address * aligned and add in the offset when we load the value here. */ .macro addruart, rp, rv - ldreq \rp, = S3C_PA_UART - ldrne \rv, = S3C_VA_UART + ldr \rp, = S3C_PA_UART + ldr \rv, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) #endif .endm #define fifo_full fifo_full_s5pv210 #define fifo_level fifo_level_s5pv210 #include <plat/debug-macro.S> diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 31618d9..f488b66 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c @@ -45,26 +45,26 @@ static void combiner_mask_irq(struct irq_data *data) __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); } static void combiner_unmask_irq(struct irq_data *data) { u32 mask = 1 << (data->irq % 32); __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); } static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct combiner_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct combiner_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, combiner_irq; unsigned long status; /* primary controller ack'ing */ chip->irq_ack(&desc->irq_data); spin_lock(&irq_controller_lock); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); spin_unlock(&irq_controller_lock); status &= chip_data->irq_mask; if (status == 0) @@ -84,44 +84,43 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) } static struct irq_chip combiner_chip = { .name = "COMBINER", .irq_mask = combiner_mask_irq, .irq_unmask = combiner_unmask_irq, }; void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) { if (combiner_nr >= MAX_COMBINER_NR) BUG(); - if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) + if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) BUG(); - set_irq_chained_handler(irq, combiner_handle_cascade_irq); + irq_set_chained_handler(irq, combiner_handle_cascade_irq); } void __init combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start) { unsigned int i; if (combiner_nr >= MAX_COMBINER_NR) BUG(); combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].irq_offset = irq_start; combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); /* Disable all interrupts */ __raw_writel(combiner_data[combiner_nr].irq_mask, base + COMBINER_ENABLE_CLEAR); /* Setup the Linux IRQ subsystem */ for (i = irq_start; i < combiner_data[combiner_nr].irq_offset + MAX_IRQ_IN_COMBINER; i++) { - set_irq_chip(i, &combiner_chip); - set_irq_chip_data(i, &combiner_data[combiner_nr]); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); + irq_set_chip_data(i, &combiner_data[combiner_nr]); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c index 4f7ad4a..9d87d2a 100644 --- a/arch/arm/mach-exynos4/irq-eint.c +++ b/arch/arm/mach-exynos4/irq-eint.c @@ -181,49 +181,50 @@ static inline void exynos4_irq_demux_eint(unsigned int start) status &= ~(1 << irq); } } static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) { exynos4_irq_demux_eint(IRQ_EINT(16)); exynos4_irq_demux_eint(IRQ_EINT(24)); } static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) { - u32 *irq_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + u32 *irq_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); chip->irq_mask(&desc->irq_data); if (chip->irq_ack) chip->irq_ack(&desc->irq_data); generic_handle_irq(*irq_data); chip->irq_unmask(&desc->irq_data); } int __init exynos4_init_irq_eint(void) { int irq; for (irq = 0 ; irq <= 31 ; irq++) { - set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); - set_irq_handler(IRQ_EINT(irq), handle_level_irq); + irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, + handle_level_irq); set_irq_flags(IRQ_EINT(irq), IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); + irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); for (irq = 0 ; irq <= 15 ; irq++) { eint0_15_data[irq] = IRQ_EINT(irq); - set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); - set_irq_chained_handler(exynos4_get_irq_nr(irq), + irq_set_handler_data(exynos4_get_irq_nr(irq), + &eint0_15_data[irq]); + irq_set_chained_handler(exynos4_get_irq_nr(irq), exynos4_irq_eint0_15); } return 0; } arch_initcall(exynos4_init_irq_eint); diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index 25a2568..e645f7a 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c @@ -116,25 +116,25 @@ static struct resource smdkc210_smsc911x_resources[] = { .start = EXYNOS4_PA_SROM_BANK(1), .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = IRQ_EINT(5), .end = IRQ_EINT(5), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, }; static struct platform_device smdkc210_smsc911x = { .name = "smsc911x", .id = -1, .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources), .resource = smdkc210_smsc911x_resources, .dev = { diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 88e0275..1526764 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -118,25 +118,25 @@ static struct resource smdkv310_smsc911x_resources[] = { .start = EXYNOS4_PA_SROM_BANK(1), .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = IRQ_EINT(5), .end = IRQ_EINT(5), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, }; static struct platform_device smdkv310_smsc911x = { .name = "smsc911x", .id = -1, .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources), .resource = smdkv310_smsc911x_resources, .dev = { diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 84c5f25..38a44f9 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -93,26 +93,25 @@ static struct irq_chip fb_chip = { static void __init __fb_init_irq(void) { unsigned int irq; /* * setup DC21285 IRQs */ *CSR_IRQ_DISABLE = -1; *CSR_FIQ_DISABLE = -1; for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } void __init footbridge_init_irq(void) { __fb_init_irq(); if (!footbridge_cfn_mode()) return; if (machine_is_ebsa285()) diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index a921fe9..5f1f986 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -21,25 +21,25 @@ static cycle_t cksrc_dc21285_read(struct clocksource *cs) { return cs->mask - *CSR_TIMER2_VALUE; } static int cksrc_dc21285_enable(struct clocksource *cs) { *CSR_TIMER2_LOAD = cs->mask; *CSR_TIMER2_CLR = 0; *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; return 0; } -static int cksrc_dc21285_disable(struct clocksource *cs) +static void cksrc_dc21285_disable(struct clocksource *cs) { *CSR_TIMER2_CNTL = 0; } static struct clocksource cksrc_dc21285 = { .name = "dc21285_timer2", .rating = 200, .read = cksrc_dc21285_read, .enable = cksrc_dc21285_enable, .disable = cksrc_dc21285_disable, .mask = CLOCKSOURCE_MASK(24), .flags = CLOCK_SOURCE_IS_CONTINUOUS, diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index de7a5cb..c3a0abb 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -142,40 +142,40 @@ void __init isa_init_irq(unsigned int host_irq) outb(0x0b, PIC_HI); if (inb(PIC_MASK_LO) == 0xf5 && inb(PIC_MASK_HI) == 0xfa) { outb(0xff, PIC_MASK_LO);/* mask all IRQs */ outb(0xff, PIC_MASK_HI);/* mask all IRQs */ } else { printk(KERN_INFO "IRQ: ISA PIC not found\n"); host_irq = (unsigned int)-1; } if (host_irq != (unsigned int)-1) { for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { - set_irq_chip(irq, &isa_lo_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_lo_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { - set_irq_chip(irq, &isa_hi_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_hi_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } request_resource(&ioport_resource, &pic1_resource); request_resource(&ioport_resource, &pic2_resource); setup_irq(IRQ_ISA_CASCADE, &irq_cascade); - set_irq_chained_handler(host_irq, isa_irq_handler); + irq_set_chained_handler(host_irq, isa_irq_handler); /* * On the NetWinder, don't automatically * enable ISA IRQ11 when it is requested. * There appears to be a missing pull-up * resistor on this line. */ if (machine_is_netwinder()) set_irq_flags(_ISA_IRQ(11), IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); } } diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fa3d333..fdc7ef1 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -118,38 +118,36 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) __raw_writel(reg_type, base + GPIO_INT_TYPE); __raw_writel(reg_level, base + GPIO_INT_LEVEL); __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); gpio_ack_irq(d->irq); return 0; } static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { + unsigned int port = (unsigned int)irq_desc_get_handler_data(desc); unsigned int gpio_irq_no, irq_stat; - unsigned int port = (unsigned int)get_irq_data(irq); irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); gpio_irq_no = GPIO_IRQ_BASE + port * 32; for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { if ((irq_stat & 1) == 0) continue; - BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); - irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, - &irq_desc[gpio_irq_no]); + generic_handle_irq(gpio_irq_no); } } static struct irq_chip gpio_irq_chip = { .name = "GPIO", .irq_ack = gpio_ack_irq, .irq_mask = gpio_mask_irq, .irq_unmask = gpio_unmask_irq, .irq_set_type = gpio_set_irq_type, }; static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, @@ -210,23 +208,23 @@ static struct gpio_chip gemini_gpio_chip = { void __init gemini_gpio_init(void) { int i, j; for (i = 0; i < GPIO_PORT_NUM; i++) { /* disable, unmask and clear all interrupts */ __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN); __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK); __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR); for (j = GPIO_IRQ_BASE + i * 32; j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_edge_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_edge_irq); set_irq_flags(j, IRQF_VALID); } - set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); - set_irq_data(IRQ_GPIO(i), (void *)i); + irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler); + irq_set_handler_data(IRQ_GPIO(i), (void *)i); } BUG_ON(gpiochip_add(&gemini_gpio_chip)); } diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 96bc227..9485a8f 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -72,31 +72,31 @@ void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; /* * Disable arch_idle() by default since it is buggy * For more info see arch/arm/mach-gemini/include/mach/system.h */ disable_hlt(); request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &gemini_irq_chip); + irq_set_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } /* Disable all interrupts */ __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); /* Set interrupt mode */ __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); } diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 1f28c90..51d4e44 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -190,47 +190,47 @@ void __init h720x_init_irq (void) /* Mask global irq's */ CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; /* Mask all multiplexed irq's */ CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; /* Initialize global IRQ's, fast path */ for (irq = 0; irq < NR_GLBL_IRQS; irq++) { - set_irq_chip(irq, &h720x_global_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &h720x_global_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Initialize multiplexed IRQ's, slow path */ for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); - set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); - set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); - set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); + irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); + irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); + irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); + irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); #ifdef CONFIG_CPU_H7202 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); + irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); #endif /* Enable multiplexed irq's */ CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; } static struct map_desc h720x_io_desc[] __initdata = { { .virtual = IO_VIRT, .pfn = __phys_to_pfn(IO_PHYS), .length = IO_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index ac3f914..c37d570 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -132,31 +132,36 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc) * Timer interrupt handler */ static irqreturn_t h7202_timer_interrupt(int irq, void *dev_id) { h7202_timerx_demux_handler(0, NULL); return IRQ_HANDLED; } /* * mask multiplexed timer IRQs */ -static void inline mask_timerx_irq(struct irq_data *d) +static void inline __mask_timerx_irq(unsigned int irq) { unsigned int bit; - bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); + bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; } +static void inline mask_timerx_irq(struct irq_data *d) +{ + __mask_timerx_irq(d->irq); +} + /* * unmask multiplexed timer IRQs */ static void inline unmask_timerx_irq(struct irq_data *d) { unsigned int bit; bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; } static struct irq_chip h7202_timerx_chip = { .irq_ack = mask_timerx_irq, @@ -187,30 +192,30 @@ struct sys_timer h7202_timer = { .init = h7202_init_time, .offset = h720x_gettimeoffset, }; void __init h7202_init_irq (void) { int irq; CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0; for (irq = IRQ_TIMER1; irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { - mask_timerx_irq(irq); - set_irq_chip(irq, &h7202_timerx_chip); - set_irq_handler(irq, handle_edge_irq); + __mask_timerx_irq(irq); + irq_set_chip_and_handler(irq, &h7202_timerx_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); + irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); h720x_init_irq(); } void __init init_hw_h7202(void) { /* Enable clocks */ CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE; CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; #ifdef CONFIG_H7202_SERIAL23 diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index a233470..bc73970 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -215,26 +215,26 @@ void __init iop13xx_init_irq(void) /* treat all as IRQ */ write_intstr_0(0); write_intstr_1(0); write_intstr_2(0); write_intstr_3(0); /* initialize the interrupt vector generator */ write_intbase(INTBASE); write_intsize(INTSIZE_4); for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) - set_irq_chip(i, &iop13xx_irqchip1); + irq_set_chip(i, &iop13xx_irqchip1); else if (i < 64) - set_irq_chip(i, &iop13xx_irqchip2); + irq_set_chip(i, &iop13xx_irqchip2); else if (i < 96) - set_irq_chip(i, &iop13xx_irqchip3); + irq_set_chip(i, &iop13xx_irqchip3); else - set_irq_chip(i, &iop13xx_irqchip4); + irq_set_chip(i, &iop13xx_irqchip4); - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } iop13xx_msi_init(); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index c9c02e3..560d5b2 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -109,25 +109,25 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) do { j = find_first_bit(&status, 32); (write_imipr[i])(1 << j); /* write back to clear bit */ generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i)); status = (read_imipr[i])(); } while (status); } } void __init iop13xx_msi_init(void) { - set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); + irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); } /* * Dynamic irq allocate and deallocation */ int create_irq(void) { int irq, pos; again: pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); irq = IRQ_IOP13XX_MSI_0 + pos; @@ -169,25 +169,25 @@ static struct irq_chip iop13xx_msi_chip = { .irq_mask = mask_msi_irq, .irq_unmask = unmask_msi_irq, }; int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) { int id, irq = create_irq(); struct msi_msg msg; if (irq < 0) return irq; - set_irq_msi(irq, desc); + irq_set_msi_desc(irq, desc); msg.address_hi = 0x0; msg.address_lo = IOP13XX_MU_MIMR_PCI; id = iop13xx_cpu_id(); msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); return 0; } diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d3426a1..d7ee278 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -59,17 +59,16 @@ void __init iop32x_init_irq(void) iop_init_cp6_handler(); intctl_write(0); intstr_write(0); if (machine_is_glantank() || machine_is_iq80321() || machine_is_iq31244() || machine_is_n2100() || machine_is_em7210()) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ext_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 0ff2f74..f7f5d3e 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -101,17 +101,18 @@ void __init iop33x_init_irq(void) iop_init_cp6_handler(); intctl0_write(0); intctl1_write(0); intstr0_write(0); intstr1_write(0); intbase_write(0); intsize_write(1); if (machine_is_iq80331()) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, + (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 5fc4e06..4068166 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c @@ -467,50 +467,50 @@ void __init ixp2000_init_irq(void) /* clear PCI interrupt sources */ ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0); /* * Certain bits in the IRQ status register of the * IXP2000 are reserved. Instead of trying to map * things non 1:1 from bit position to IRQ number, * we mark the reserved IRQs as invalid. This makes * our mask/unmask code much simpler. */ for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & IXP2000_VALID_ERR_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_err_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } - set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { - set_irq_chip(irq, &ixp2000_GPIO_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); /* * Enable PCI irqs. The actual PCI[AB] decoding is done in * entry-macro.S, so we don't need a chained handler for the * PCI interrupt source. */ ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { - set_irq_chip(irq, &ixp2000_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 7d90d3f..235638f 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -149,31 +149,31 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne ixp2000_init_irq(); if (!ixdp2x00_master_npu()) return; board_irq_stat = stat_reg; board_irq_mask = mask_reg; board_irq_count = nr_of_irqs; *board_irq_mask = 0xffffffff; for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { - set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } /* Hook into PCI interrupt */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); } /************************************************************************* * IXDP2x00 memory map *************************************************************************/ static struct map_desc ixdp2x00_io_desc __initdata = { .virtual = IXDP2X00_VIRT_CPLD_BASE, .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE), .length = IXDP2X00_CPLD_SIZE, .type = MT_DEVICE }; diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 34b1b2a..84835b2 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -106,34 +106,34 @@ void __init ixdp2x01_init_irq(void) if (machine_is_ixdp2401()) valid_irq_mask = IXDP2401_VALID_IRQ_MASK; else valid_irq_mask = IXDP2801_VALID_IRQ_MASK; /* Mask all interrupts from CPLD, disable simulation */ ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0); for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { if (irq & valid_irq_mask) { - set_irq_chip(irq, &ixdp2x01_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else { set_irq_flags(irq, 0); } } /* Hook into PCI interrupts */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); } /************************************************************************* * IXDP2x01 memory map *************************************************************************/ static struct map_desc ixdp2x01_io_desc __initdata = { .virtual = IXDP2X01_VIRT_CPLD_BASE, .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE), .length = IXDP2X01_CPLD_REGION_SIZE, .type = MT_DEVICE }; diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 9c8a339..a1bee33 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -280,30 +280,30 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc) } static struct irq_chip ixp23xx_pci_irq_chip = { .irq_ack = ixp23xx_pci_irq_mask, .irq_mask = ixp23xx_pci_irq_mask, .irq_unmask = ixp23xx_pci_irq_unmask }; static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) { switch (type) { case IXP23XX_IRQ_LEVEL: - set_irq_chip(irq, &ixp23xx_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, + handle_level_irq); break; case IXP23XX_IRQ_EDGE: - set_irq_chip(irq, &ixp23xx_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, + handle_edge_irq); break; } set_irq_flags(irq, IRQF_VALID); } void __init ixp23xx_init_irq(void) { int irq; /* Route everything to IRQ */ *IXP23XX_INTR_SEL1 = 0x0; *IXP23XX_INTR_SEL2 = 0x0; @@ -315,30 +315,30 @@ void __init ixp23xx_init_irq(void) *IXP23XX_INTR_EN2 = 0x0; *IXP23XX_INTR_EN3 = 0x0; *IXP23XX_INTR_EN4 = 0x0; /* * Configure all IRQs for level-sensitive operation */ for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) { ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL); } for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { - set_irq_chip(irq, &ixp23xx_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); + irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); } /************************************************************************* * Timer-tick functions for IXP23xx *************************************************************************/ #define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC) static unsigned long next_jiffy_time; static unsigned long ixp23xx_gettimeoffset(void) diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 181116a..8dcba17 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -127,42 +127,42 @@ void __init ixdp2351_init_irq(void) *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1; *IXDP2351_CPLD_INTA_SIM_REG = 0; *IXDP2351_CPLD_INTB_SIM_REG = 0; ixp23xx_init_irq(); for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE); irq < IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM); irq++) { if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_inta_chip); + irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, + handle_level_irq); } } for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE); irq < IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM); irq++) { if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_intb_chip); + irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, + handle_level_irq); } } - set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); - set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); } /* * IXDP2351 PCI */ /* * This board does not do normal PCI IRQ routing, or any * sort of swizzling, so we just need to check where on the * bus the device is and figure out what CPLD pin it is * being routed to. */ diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index 76c61ba..8fe0c62 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -101,26 +101,26 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } break; default: return NO_IRQ; } return NO_IRQ; } static void __init roadrunner_pci_preinit(void) { - set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); ixp23xx_pci_preinit(); } static struct hw_pci roadrunner_pci __initdata = { .nr_controllers = 1, .preinit = roadrunner_pci_preinit, .setup = ixp23xx_pci_setup, .scan = ixp23xx_pci_scan_bus, .map_irq = roadrunner_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b5..162043f 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -30,28 +30,28 @@ #define AVILA_MAX_DEV 4 #define LOFT_MAX_DEV 6 #define IRQ_LINES 4 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 11 #define INTB 10 #define INTC 9 #define INTD 8 void __init avila_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[IRQ_LINES] = { IXP4XX_GPIO_IRQ(INTA), IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD) }; diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9fd8942..ed19bc3 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -243,26 +243,26 @@ void __init ixp4xx_init_irq(void) *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { /* Route upper 32 sources to IRQ instead of FIQ */ *IXP4XX_ICLR2 = 0x00; /* Disable upper 32 interrupts */ *IXP4XX_ICMR2 = 0x00; } /* Default to all level triggered */ for(i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ixp4xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ixp4xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } /************************************************************************* * IXP4xx timer tick * We use OS timer1 on the CPU for the timer tick and the timestamp * counter as a source of real clock ticks to account for missed jiffies. *************************************************************************/ static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id) diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8..37fda7d 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -23,26 +23,26 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #define SLOT0_DEVID 14 #define SLOT1_DEVID 15 /* PCI controller GPIO to IRQ pin mappings */ #define SLOT0_INTA 6 #define SLOT1_INTA 11 void __init coyote_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == SLOT0_DEVID) return IXP4XX_GPIO_IRQ(SLOT0_INTA); else if (slot == SLOT1_DEVID) return IXP4XX_GPIO_IRQ(SLOT1_INTA); else return -1; } diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed..c761201 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -26,30 +26,30 @@ #define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 11 #define INTB 10 #define INTC 9 #define INTD 8 #define INTE 7 #define INTF 6 void __init dsmg600_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[MAX_DEV][IRQ_LINES] = { { IXP4XX_GPIO_IRQ(INTE), -1, -1 }, { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD) }, { IXP4XX_GPIO_IRQ(INTF), -1, -1 }, }; diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c9..44ccde9 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -23,27 +23,27 @@ #include <asm/mach-types.h> #define MAX_DEV 3 #define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 6 #define INTB 7 #define INTC 5 void __init fsg_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[IRQ_LINES] = { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTA), }; int irq = -1; diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 7e93a09..fc11241 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -20,26 +20,26 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/irq.h> #include <asm/mach-types.h> #include <mach/hardware.h> #include <asm/mach/pci.h> void __init gateway7001_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init gateway7001_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 1) return IRQ_IXP4XX_GPIO11; else if (slot == 2) return IRQ_IXP4XX_GPIO10; else return -1; } diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index d0e4861..3e8c0e3 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -411,49 +411,49 @@ static void __init gmlr_init(void) device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ if (hw_bits & CFG_HW_HAS_EEPROM) device_tab[devices++] = &device_i2c; /* max index 6 */ gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1); set_control(CONTROL_EEPROM_WC_N, 1); set_control(CONTROL_PCI_RESET_N, 1); output_control(); msleep(1); /* Wait for PCI devices to initialize */ flash_resource.start = IXP4XX_EXP_BUS_BASE(0); flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; platform_add_devices(device_tab, devices); } #ifdef CONFIG_PCI static void __init gmlr_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static void __init gmlr_pci_postinit(void) { if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && (hw_bits & CFG_HW_USB_PORTS) < 5) { /* need to adjust number of USB ports on NEC chip */ u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { value &= ~7; value |= (hw_bits & CFG_HW_USB_PORTS); diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c33..38cc072 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -34,26 +34,26 @@ #define SLOT1_DEVID 1 #define INTA 10 /* slot 1 has INTA and INTB crossed */ #define INTB 11 /* * Slot 0 isn't actually populated with a card connector but * we initialize it anyway in case a future version has the * slot populated or someone with good soldering skills has * some free time. */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int rc = -1; if ((slot == SLOT0_DEVID && pin == 1) || (slot == SLOT1_DEVID && pin == 2)) rc = IXP4XX_GPIO_IRQ(INTA); else if ((slot == SLOT0_DEVID && pin == 2) || diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a..58f4004 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -27,28 +27,28 @@ #define MAX_DEV 4 #define IRQ_LINES 4 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 11 #define INTB 10 #define INTC 9 #define INTD 8 void __init ixdp425_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[IRQ_LINES] = { IXP4XX_GPIO_IRQ(INTA), IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD) }; diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 4ed7ac6..e64f6d0 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -16,26 +16,26 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/irq.h> #include <asm/mach-types.h> #include <mach/hardware.h> #include <asm/mach/pci.h> void __init ixdpg425_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init ixdpg425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 12 || slot == 13) return IRQ_IXP4XX_GPIO7; else if (slot == 14) return IRQ_IXP4XX_GPIO6; else return -1; } diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34..428d120 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -24,29 +24,29 @@ #define MAX_DEV 3 #define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 11 #define INTB 10 #define INTC 9 #define INTD 8 #define INTE 7 void __init nas100d_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[MAX_DEV][IRQ_LINES] = { { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), IXP4XX_GPIO_IRQ(INTE) }, }; diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90..2e85f76 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -23,27 +23,27 @@ #define MAX_DEV 3 #define IRQ_LINES 3 /* PCI controller GPIO to IRQ pin mappings */ #define INTA 11 #define INTB 10 #define INTC 9 #define INTD 8 void __init nslu2_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[IRQ_LINES] = { IXP4XX_GPIO_IRQ(INTA), IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), }; if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index f3111c6..03bdec5 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -29,26 +29,26 @@ void __init vulcan_pci_preinit(void) { #ifndef CONFIG_IXP4XX_INDIRECT_PCI /* * Cardbus bridge wants way more than the SoC can actually offer, * and leaves the whole PCI bus in a mess. Artificially limit it * to 8MB per region. Of course indirect mode doesn't have this * limitation... */ pci_cardbus_mem_size = SZ_8M; pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", (int)(pci_cardbus_mem_size >> 20)); #endif - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 1) return IXP4XX_GPIO_IRQ(INTA); if (slot == 2) return IXP4XX_GPIO_IRQ(INTB); return -1; diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 9b59ed0..17f3cf5 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -20,26 +20,26 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/irq.h> #include <asm/mach-types.h> #include <mach/hardware.h> #include <asm/mach/pci.h> void __init wg302v2_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } static int __init wg302v2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 1) return IRQ_IXP4XX_GPIO8; else if (slot == 2) return IRQ_IXP4XX_GPIO9; else return -1; } diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index cbdb586..05d193a 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -26,23 +26,24 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } void __init kirkwood_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* * Initialize gpiolib for GPIOs 0-49. */ orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, + gpio_irq_handler); } diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 55fbf71..31e4565 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c @@ -71,25 +71,25 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) return -EINVAL; local_irq_save(flags); /* set pin as input */ x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); x &= ~IOPM(pin); __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); local_irq_restore(flags); /* Set IRQ triggering type */ - set_irq_type(gpio_irq[pin], type); + irq_set_irq_type(gpio_irq[pin], type); /* enable interrupt mode */ ks8695_gpio_mode(pin, 0); return 0; } EXPORT_SYMBOL(ks8695_gpio_interrupt); /* .... Generic GPIO interface .............................................. */ diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 7998cca..a78092d 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -106,30 +106,30 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) ctrl &= ~IOPC_IOEINT2TM; ctrl |= IOPC_IOEINT2_MODE(mode); break; case KS8695_IRQ_EXTERN3: ctrl &= ~IOPC_IOEINT3TM; ctrl |= IOPC_IOEINT3_MODE(mode); break; default: return -EINVAL; } if (level_triggered) { - set_irq_chip(d->irq, &ks8695_irq_level_chip); - set_irq_handler(d->irq, handle_level_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip, + handle_level_irq); } else { - set_irq_chip(d->irq, &ks8695_irq_edge_chip); - set_irq_handler(d->irq, handle_edge_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip, + handle_edge_irq); } __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); return 0; } static struct irq_chip ks8695_irq_level_chip = { .irq_ack = ks8695_irq_mask, .irq_mask = ks8695_irq_mask, .irq_unmask = ks8695_irq_unmask, .irq_set_type = ks8695_irq_set_type, }; @@ -149,27 +149,29 @@ void __init ks8695_init_irq(void) __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC); __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN); for (irq = 0; irq < NR_IRQS; irq++) { switch (irq) { /* Level-triggered interrupts */ case KS8695_IRQ_BUS_ERROR: case KS8695_IRQ_UART_MODEM_STATUS: case KS8695_IRQ_UART_LINE_STATUS: case KS8695_IRQ_UART_RX: case KS8695_IRQ_COMM_TX: case KS8695_IRQ_COMM_RX: - set_irq_chip(irq, &ks8695_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_level_chip, + handle_level_irq); break; /* Edge-triggered interrupts */ default: /* clear pending bit */ ks8695_irq_ack(irq_get_irq_data(irq)); - set_irq_chip(irq, &ks8695_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_edge_chip, + handle_edge_irq); } set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 316ecbf..4eae566 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -281,25 +281,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ __lpc32xx_set_irq_type(d->irq, 1, 0); break; /* Other modes are not supported */ default: return -EINVAL; } /* Ok to use the level handler for all types */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); return 0; } static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) { unsigned long eventreg; if (lpc32xx_events[d->irq].mask != 0) { eventreg = __raw_readl(lpc32xx_events[d->irq]. event_group->enab_reg); @@ -381,42 +381,42 @@ void __init lpc32xx_init_irq(void) /* Setup SIC1 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); /* Setup SIC2 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); /* Configure supported IRQ's */ for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &lpc32xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &lpc32xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* Set default mappings */ lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0); lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32); lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64); /* mask all interrupts except SUBIRQ */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); __raw_writel(0, LPC32XX_CLKPWR_INT_ER); __raw_writel(0, LPC32XX_CLKPWR_PIN_ER); /* * Default wake activation polarities, all pin sources are low edge * triggered */ __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT | LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT | diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index fa03703..d21c544 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -101,57 +101,57 @@ SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); static void init_mux_irq(struct irq_chip *chip, int start, int num) { int irq; for (irq = start; num > 0; irq++, num--) { struct irq_data *d = irq_get_irq_data(irq); /* mask and clear the IRQ */ chip->irq_mask(d); if (chip->irq_ack) chip->irq_ack(d); - set_irq_chip(irq, chip); + irq_set_chip(irq, chip); set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); } } void __init mmp2_init_icu(void) { int irq; for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); + irq_set_chip(irq, &icu_irq_chip); set_irq_flags(irq, IRQF_VALID); switch (irq) { case IRQ_MMP2_PMIC_MUX: case IRQ_MMP2_RTC_MUX: case IRQ_MMP2_TWSI_MUX: case IRQ_MMP2_MISC_MUX: case IRQ_MMP2_SSP_MUX: break; default: - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); break; } } /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register * to be written to clear the interrupt */ pmic_irq_chip.irq_ack = pmic_irq_ack; init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); - set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); - set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); - set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); + irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); } diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index f86b450..89706a0 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c @@ -39,17 +39,16 @@ static struct irq_chip icu_irq_chip = { .name = "icu_irq", .irq_ack = icu_mask_irq, .irq_mask = icu_mask_irq, .irq_unmask = icu_unmask_irq, }; void __init icu_init_irq(void) { int irq; for (irq = 0; irq < 64; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 1993721..35c7cee 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -44,25 +44,25 @@ static void __init msm8960_init_irq(void) /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); if (machine_is_msm8960_rumi3()) writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet * as they are configured as level, which does not play nice with * handle_percpu_irq. */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } static struct platform_device *sim_devices[] __initdata = { &msm8960_device_uart_gsbi2, }; static struct platform_device *rumi3_devices[] __initdata = { &msm8960_device_uart_gsbi5, }; static void __init msm8960_sim_init(void) diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index b3c55f1..1163b6f 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -47,25 +47,25 @@ static void __init msm8x60_init_irq(void) /* RUMI does not adhere to GIC spec by enabling STIs by default. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. */ if (!machine_is_msm8x60_sim()) writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet * as they are configured as level, which does not play nice with * handle_percpu_irq. */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } static void __init msm8x60_init(void) { } MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") .map_io = msm8x60_map_io, .init_irq = msm8x60_init_irq, .init_machine = msm8x60_init, .timer = &msm_timer, diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 31117a4..87e1d01 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -205,29 +205,29 @@ static struct irq_chip trout_gpio_irq_chip = { .irq_mask = trout_gpio_irq_mask, .irq_unmask = trout_gpio_irq_unmask, .irq_set_wake = trout_gpio_irq_set_wake, }; /* * Called from the processor-specific init to enable GPIO pin support. */ int __init trout_init_gpio(void) { int i; for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { - set_irq_chip(i, &trout_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &trout_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) gpiochip_add(&msm_gpio_banks[i].chip); - set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); - set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); - set_irq_wake(MSM_GPIO_TO_INT(17), 1); + irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); + irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); + irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1); return 0; } postcore_initcall(trout_init_gpio); diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c index 44be846..f7a9724 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c @@ -165,22 +165,22 @@ static struct msm_mmc_platform_data trout_sdslot_data = { .status = trout_sdslot_status, .translate_vdd = trout_sdslot_switchvdd, }; int __init trout_init_mmc(unsigned int sys_rev) { sdslot_vreg_enabled = 0; vreg_sdslot = vreg_get(0, "gp6"); if (IS_ERR(vreg_sdslot)) return PTR_ERR(vreg_sdslot); - set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); + irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); if (!opt_disable_sdcard) msm_add_sdcc(2, &trout_sdslot_data, TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0); else printk(KERN_INFO "trout: SD-Card interface disabled\n"); return 0; } diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index 0de19ec..56a964e 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -221,77 +221,77 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio) else set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); if (intstat || val == val2) return; } while (loop_limit-- > 0); pr_err("dual-edge irq failed to stabilize, " "interrupts dropped. %#08x != %#08x\n", val, val2); } -static void msm_gpio_irq_ack(unsigned int irq) +static void msm_gpio_irq_ack(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); if (test_bit(gpio, msm_gpio.dual_edge_irqs)) msm_gpio_update_dual_edge_pos(gpio); } -static void msm_gpio_irq_mask(unsigned int irq) +static void msm_gpio_irq_mask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); __clear_bit(gpio, msm_gpio.enabled_irqs); spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static void msm_gpio_irq_unmask(unsigned int irq) +static void msm_gpio_irq_unmask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); __set_bit(gpio, msm_gpio.enabled_irqs); set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; uint32_t bits; spin_lock_irqsave(&tlmm_lock, irq_flags); bits = readl(GPIO_INTR_CFG(gpio)); if (flow_type & IRQ_TYPE_EDGE_BOTH) { bits |= BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) __set_bit(gpio, msm_gpio.dual_edge_irqs); else __clear_bit(gpio, msm_gpio.dual_edge_irqs); } else { bits &= ~BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); __clear_bit(gpio, msm_gpio.dual_edge_irqs); } if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) bits |= BIT(INTR_POL_CTL); else bits &= ~BIT(INTR_POL_CTL); writel(bits, GPIO_INTR_CFG(gpio)); if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) msm_gpio_update_dual_edge_pos(gpio); @@ -300,94 +300,95 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) return 0; } /* * When the summary IRQ is raised, any number of GPIO lines may be high. * It is the job of the summary handler to find all those GPIO lines * which have been set as summary IRQ lines and which are triggered, * and to call their interrupt handlers. */ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) { + struct irq_data *data = irq_desc_get_irq_data(desc); unsigned long i; for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); i < NR_GPIO_IRQS; i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, i)); } - desc->chip->ack(irq); + data->chip->irq_ack(data); } -static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); if (on) { if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); set_bit(gpio, msm_gpio.wake_irqs); } else { clear_bit(gpio, msm_gpio.wake_irqs); if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); } return 0; } static struct irq_chip msm_gpio_irq_chip = { .name = "msmgpio", - .mask = msm_gpio_irq_mask, - .unmask = msm_gpio_irq_unmask, - .ack = msm_gpio_irq_ack, - .set_type = msm_gpio_irq_set_type, - .set_wake = msm_gpio_irq_set_wake, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, }; static int __devinit msm_gpio_probe(struct platform_device *dev) { int i, irq, ret; bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); msm_gpio.gpio_chip.label = dev->name; ret = gpiochip_add(&msm_gpio.gpio_chip); if (ret < 0) return ret; for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); - set_irq_chip(irq, &msm_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, msm_summary_irq_handler); return 0; } static int __devexit msm_gpio_remove(struct platform_device *dev) { int ret = gpiochip_remove(&msm_gpio.gpio_chip); if (ret < 0) return ret; - set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); return 0; } static struct platform_driver msm_gpio_driver = { .probe = msm_gpio_probe, .remove = __devexit_p(msm_gpio_remove), .driver = { .name = "msmgpio", .owner = THIS_MODULE, }, }; diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 176af9d..5ea273b 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -284,28 +284,28 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned long irq_flags; struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d); unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); unsigned val, mask = BIT(offset); spin_lock_irqsave(&msm_chip->lock, irq_flags); val = readl(msm_chip->regs.int_edge); if (flow_type & IRQ_TYPE_EDGE_BOTH) { writel(val | mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { writel(val & ~mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { msm_chip->both_edge_detect |= mask; msm_gpio_update_both_edge_detect(msm_chip); } else { msm_chip->both_edge_detect &= ~mask; val = readl(msm_chip->regs.int_pos); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) writel(val | mask, msm_chip->regs.int_pos); else writel(val & ~mask, msm_chip->regs.int_pos); } @@ -345,32 +345,32 @@ static struct irq_chip msm_gpio_irq_chip = { .irq_set_type = msm_gpio_irq_set_type, }; static int __init msm_init_gpio(void) { int i, j = 0; for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ >= msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; - set_irq_chip_data(i, &msm_gpio_chips[j]); - set_irq_chip(i, &msm_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_data(i, &msm_gpio_chips[j]); + irq_set_chip_and_handler(i, &msm_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { spin_lock_init(&msm_gpio_chips[i].lock); writel(0, msm_gpio_chips[i].regs.int_en); gpiochip_add(&msm_gpio_chips[i].chip); } - set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); - set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); - set_irq_wake(INT_GPIO_GROUP1, 1); - set_irq_wake(INT_GPIO_GROUP2, 2); + irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); + irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); + irq_set_irq_wake(INT_GPIO_GROUP1, 1); + irq_set_irq_wake(INT_GPIO_GROUP2, 2); return 0; } postcore_initcall(msm_init_gpio); diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 68c28bb..1b54f80 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c @@ -304,29 +304,29 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) polarity = msm_irq_shadow_reg[index].int_polarity; if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) polarity |= b; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) polarity &= ~b; writel(polarity, preg); msm_irq_shadow_reg[index].int_polarity = polarity; type = msm_irq_shadow_reg[index].int_type; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type |= b; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { type &= ~b; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(type, treg); msm_irq_shadow_reg[index].int_type = type; return 0; } static struct irq_chip msm_irq_chip = { .name = "msm", .irq_disable = msm_irq_mask, .irq_ack = msm_irq_ack, .irq_mask = msm_irq_mask, .irq_unmask = msm_irq_unmask, @@ -348,17 +348,16 @@ void __init msm_init_irq(void) msm_irq_write_all_regs(VIC_INT_SELECT0, 0); /* disable all INTs */ msm_irq_write_all_regs(VIC_INT_EN0, 0); /* don't use vic */ writel(0, VIC_CONFIG); /* enable interrupt controller */ writel(3, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 0b27d89..ea514be 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -91,29 +91,29 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0); void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0); int b = 1 << (d->irq & 31); if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) writel(readl(preg) | b, preg); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) writel(readl(preg) & (~b), preg); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } return 0; } static struct irq_chip msm_irq_chip = { .name = "msm", .irq_ack = msm_irq_ack, .irq_mask = msm_irq_mask, .irq_unmask = msm_irq_unmask, .irq_set_wake = msm_irq_set_wake, .irq_set_type = msm_irq_set_type, }; @@ -136,17 +136,16 @@ void __init msm_init_irq(void) /* disable all INTs */ writel(0, VIC_INT_EN0); writel(0, VIC_INT_EN1); /* don't use 1136 vic */ writel(0, VIC_CONFIG); /* enable interrupt controller */ writel(1, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index 11b54c7..689e78c 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -96,28 +96,28 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) val = readl(sirc_regs.int_polarity); if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) val |= mask; else val &= ~mask; writel(val, sirc_regs.int_polarity); val = readl(sirc_regs.int_type); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { val |= mask; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { val &= ~mask; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(val, sirc_regs.int_type); return 0; } /* Finds the pending interrupt on the passed cascade irq and redrives it */ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int reg = 0; unsigned int sirq; @@ -149,25 +149,24 @@ static struct irq_chip sirc_irq_chip = { .irq_set_wake = sirc_irq_set_wake, .irq_set_type = sirc_irq_set_type, }; void __init msm_init_sirc(void) { int i; int_enable = 0; wake_enable = 0; for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { - set_irq_chip(i, &sirc_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { - set_irq_chained_handler(sirc_reg_table[i].cascade_irq, + irq_set_chained_handler(sirc_reg_table[i].cascade_irq, sirc_irq_handler); - set_irq_wake(sirc_reg_table[i].cascade_irq, 1); + irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1); } return; } diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 08da497..3e24431 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -29,17 +29,17 @@ void __init mv78xx0_init_irq(void) orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 4e4b780..3d095d6 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -190,30 +190,29 @@ static void __init mx31ads_init_expio(void) printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); /* * Configure INT line as GPIO input */ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); /* disable the interrupt and clear the status */ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); __raw_writew(0xFFFF, PBC_INTSTATUS_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); + irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); } #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 /* This section defines setup for the Wolfson Microelectronics * 1133-EV1 PMU/audio board. When other PMU boards are supported the * regulator definitions may be shared with them, but for now they can * only be used with this board so would generate warnings about * unused statics and some of the configuration is specific to this * module. */ /* CPU */ diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index e83ffad..4a85505 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -203,19 +203,19 @@ void __init eukrea_mbimx51_baseboard_init(void) gpio_direction_output(MBIMX51_LED2, 1); gpio_free(MBIMX51_LED2); gpio_request(MBIMX51_LED3, "LED3"); gpio_direction_output(MBIMX51_LED3, 1); gpio_free(MBIMX51_LED3); platform_add_devices(devices, ARRAY_SIZE(devices)); imx51_add_imx_keypad(&mbimx51_map_data); gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_direction_input(MBIMX51_TSC2007_GPIO); - set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); imx51_add_sdhci_esdhc_imx(0, NULL); imx51_add_sdhci_esdhc_imx(1, NULL); } diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index 51a67fc..868af8f 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -563,26 +563,28 @@ static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { { .id = MC13892_VUSB, .init_data = &vusb_init }, { .id = MC13892_GPO1, .init_data = &gpo1_init }, { .id = MC13892_GPO2, .init_data = &gpo2_init }, { .id = MC13892_GPO3, .init_data = &gpo3_init }, { .id = MC13892_GPO4, .init_data = &gpo4_init }, { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, }; static struct mc13xxx_platform_data mx51_efika_mc13892_data = { .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR, - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, + .regulators = { + .num_regulators = ARRAY_SIZE(mx51_efika_regulators), + .regulators = mx51_efika_regulators, + }, }; static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { { .modalias = "m25p80", .max_speed_hz = 25000000, .bus_num = 0, .chip_select = 1, .platform_data = &mx51_efika_spi_flash_data, .irq = -1, }, { diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 56fa2ed..2c950fe 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -127,25 +127,25 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) else __mxs_clrl(pin_mask, pin_addr); clear_gpio_irqstatus(port, gpio & 0x1f); return 0; } /* MXS has one interrupt *per* gpio port */ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); + struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); u32 gpio_irq_no_base = port->virtual_irq_start; desc->irq_data.chip->irq_ack(&desc->irq_data); irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & __raw_readl(port->base + PINCTRL_IRQEN(port->id)); while (irq_stat != 0) { int irqoffset = fls(irq_stat) - 1; generic_handle_irq(gpio_irq_no_base + irqoffset); irq_stat &= ~(1 << irqoffset); } @@ -256,32 +256,32 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) pr_info("MXS GPIO hardware\n"); for (i = 0; i < cnt; i++) { /* disable the interrupt and clear the status */ __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i)); __raw_writel(0, port[i].base + PINCTRL_IRQEN(i)); /* clear address has to be used to clear IRQSTAT bits */ __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i)); for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); /* register gpio chip */ port[i].chip.direction_input = mxs_gpio_direction_input; port[i].chip.direction_output = mxs_gpio_direction_output; port[i].chip.get = mxs_gpio_get; port[i].chip.set = mxs_gpio_set; port[i].chip.to_irq = mxs_gpio_to_irq; port[i].chip.base = i * 32; port[i].chip.ngpio = 32; /* its a serious configuration bug when it fails */ BUG_ON(gpiochip_add(&port[i].chip) < 0); diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 0f4c120..23ca9d0 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c @@ -65,17 +65,16 @@ static struct irq_chip mxs_icoll_chip = { void __init icoll_init_irq(void) { int i; /* * Interrupt Collector reset, which initializes the priority * for each irq to level 0. */ mxs_reset_block(icoll_base + HW_ICOLL_CTRL); for (i = 0; i < MXS_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxs_icoll_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } } diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 29ffa75..00023b5 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -162,28 +162,28 @@ static struct irq_chip netx_hif_chip = { .irq_mask = netx_hif_mask_irq, .irq_unmask = netx_hif_unmask_irq, .irq_set_type = netx_hif_irq_type, }; void __init netx_init_irq(void) { int irq; vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { - set_irq_chip(irq, &netx_hif_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &netx_hif_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); - set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); + irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); } static int __init netx_init(void) { return platform_add_devices(devices, ARRAY_SIZE(devices)); } subsys_initcall(netx_init); diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0c0d524..e27687d 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -98,37 +98,37 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, void __init board_a9m9750dev_init_irq(void) { u32 eic; int i; if (gpio_request(11, "board a9m9750dev extirq2") == 0) ns9360_gpio_configure(11, 0, 1); else printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", __func__); for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { - set_irq_chip(i, &a9m9750dev_fpga_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* IRQ_NS9XXX_EXT2: level sensitive + active low */ eic = __raw_readl(SYS_EIC(2)); REGSET(eic, SYS_EIC, PLTY, AL); REGSET(eic, SYS_EIC, LVEDG, LEVEL); __raw_writel(eic, SYS_EIC(2)); - set_irq_chained_handler(IRQ_NS9XXX_EXT2, - a9m9750dev_fpga_demux_handler); + irq_set_chained_handler(IRQ_NS9XXX_EXT2, + a9m9750dev_fpga_demux_handler); } void __init board_a9m9750dev_init_machine(void) { u32 reg; /* setup static CS0: memory base ... */ reg = __raw_readl(SYS_SMCSSMB(0)); REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); __raw_writel(reg, SYS_SMCSSMB(0)); /* ... and mask */ diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h index f7e9196..19ca6de 100644 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ b/arch/arm/mach-ns9xxx/include/mach/board.h @@ -5,30 +5,28 @@ * All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ #ifndef __ASM_ARCH_BOARD_H #define __ASM_ARCH_BOARD_H #include <asm/mach-types.h> #define board_is_a9m9750dev() (0 \ - || machine_is_cc9p9360dev() \ || machine_is_cc9p9750dev() \ ) #define board_is_a9mvali() (0 \ - || machine_is_cc9p9360val() \ || machine_is_cc9p9750val() \ ) #define board_is_jscc9p9210() (0 \ || machine_is_cc9p9210js() \ ) #define board_is_jscc9p9215() (0 \ || machine_is_cc9p9215js() \ ) #define board_is_jscc9p9360() (0 \ diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h index f851a6b..628e975 100644 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ b/arch/arm/mach-ns9xxx/include/mach/module.h @@ -9,52 +9,47 @@ * the Free Software Foundation. */ #ifndef __ASM_ARCH_MODULE_H #define __ASM_ARCH_MODULE_H #include <asm/mach-types.h> #define module_is_cc7ucamry() (0 \ || machine_is_cc7ucamry() \ ) #define module_is_cc9c() (0 \ - || machine_is_cc9c() \ ) #define module_is_cc9p9210() (0 \ || machine_is_cc9p9210() \ || machine_is_cc9p9210js() \ ) #define module_is_cc9p9215() (0 \ || machine_is_cc9p9215() \ || machine_is_cc9p9215js() \ ) #define module_is_cc9p9360() (0 \ - || machine_is_a9m9360() \ || machine_is_cc9p9360dev() \ || machine_is_cc9p9360js() \ - || machine_is_cc9p9360val() \ ) #define module_is_cc9p9750() (0 \ || machine_is_a9m9750() \ - || machine_is_cc9p9750dev() \ || machine_is_cc9p9750js() \ || machine_is_cc9p9750val() \ ) #define module_is_ccw9c() (0 \ - || machine_is_ccw9c() \ ) #define module_is_inc20otter() (0 \ || machine_is_inc20otter() \ ) #define module_is_otter() (0 \ || machine_is_otter() \ ) #endif /* ifndef __ASM_ARCH_MODULE_H */ diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 389fa5c..37ab0a2 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -22,104 +22,53 @@ #define irq2prio(i) (i) #define prio2irq(p) (p) static void ns9xxx_mask_irq(struct irq_data *d) { /* XXX: better use cpp symbols */ int prio = irq2prio(d->irq); u32 ic = __raw_readl(SYS_IC(prio / 4)); ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); __raw_writel(ic, SYS_IC(prio / 4)); } -static void ns9xxx_ack_irq(struct irq_data *d) +static void ns9xxx_eoi_irq(struct irq_data *d) { __raw_writel(0, SYS_ISRADDR); } -static void ns9xxx_maskack_irq(struct irq_data *d) -{ - ns9xxx_mask_irq(d); - ns9xxx_ack_irq(d); -} - static void ns9xxx_unmask_irq(struct irq_data *d) { /* XXX: better use cpp symbols */ int prio = irq2prio(d->irq); u32 ic = __raw_readl(SYS_IC(prio / 4)); ic |= 1 << (7 + 8 * (3 - (prio & 3))); __raw_writel(ic, SYS_IC(prio / 4)); } static struct irq_chip ns9xxx_chip = { - .irq_ack = ns9xxx_ack_irq, + .irq_eoi = ns9xxx_eoi_irq, .irq_mask = ns9xxx_mask_irq, - .irq_mask_ack = ns9xxx_maskack_irq, .irq_unmask = ns9xxx_unmask_irq, }; -#if 0 -#define handle_irq handle_level_irq -#else -static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) -{ - struct irqaction *action; - irqreturn_t action_ret; - - raw_spin_lock(&desc->lock); - - BUG_ON(desc->status & IRQ_INPROGRESS); - - desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); - kstat_incr_irqs_this_cpu(irq, desc); - - action = desc->action; - if (unlikely(!action || (desc->status & IRQ_DISABLED))) - goto out_mask; - - desc->status |= IRQ_INPROGRESS; - raw_spin_unlock(&desc->lock); - - action_ret = handle_IRQ_event(irq, action); - - /* XXX: There is no direct way to access noirqdebug, so check - * unconditionally for spurious irqs... - * Maybe this function should go to kernel/irq/chip.c? */ - note_interrupt(irq, desc, action_ret); - - raw_spin_lock(&desc->lock); - desc->status &= ~IRQ_INPROGRESS; - - if (desc->status & IRQ_DISABLED) -out_mask: - desc->irq_data.chip->irq_mask(&desc->irq_data); - - /* ack unconditionally to unmask lower prio irqs */ - desc->irq_data.chip->irq_ack(&desc->irq_data); - - raw_spin_unlock(&desc->lock); -} -#define handle_irq handle_prio_irq -#endif - void __init ns9xxx_init_irq(void) { int i; /* disable all IRQs */ for (i = 0; i < 8; ++i) __raw_writel(prio2irq(4 * i) << 24 | prio2irq(4 * i + 1) << 16 | prio2irq(4 * i + 2) << 8 | prio2irq(4 * i + 3), SYS_IC(i)); for (i = 0; i < 32; ++i) __raw_writel(prio2irq(i), SYS_IVA(i)); for (i = 0; i <= 31; ++i) { - set_irq_chip(i, &ns9xxx_chip); - set_irq_handler(i, handle_irq); + irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq); set_irq_flags(i, IRQF_VALID); + irq_set_status_flags(i, IRQ_LEVEL); } } diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index 1f8a05a..aa279f2 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c @@ -50,17 +50,17 @@ static struct irq_chip nuc93x_irq_chip = { .irq_ack = nuc93x_irq_ack, .irq_mask = nuc93x_irq_mask, .irq_unmask = nuc93x_irq_unmask, }; void __init nuc93x_init_irq(void) { int irqno; __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { - set_irq_chip(irqno, &nuc93x_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc93x_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7c5e211..e68dfde 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -267,25 +267,25 @@ static void __init osk_init_smc91x(void) l |= 0x3; omap_writel(l, EMIFS_CCS(1)); } static void __init osk_init_cf(void) { omap_cfg_reg(M7_1610_GPIO62); if ((gpio_request(62, "cf_irq")) < 0) { printk("Error requesting gpio 62 for CF irq\n"); return; } /* the CF I/O IRQ is really active-low */ - set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } static void __init osk_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); } static struct omap_usb_config osk_usb_config __initdata = { /* has usb host connector (A) ... for development it can also * be used, with a NONSTANDARD gender-bending cable/dongle, as * a peripheral. @@ -473,43 +473,43 @@ static void __init osk_mistral_init(void) gpio_direction_output(11, 0); } else pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ gpio_request(6, "ts_busy"); gpio_direction_input(6); omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ gpio_request(4, "ts_int"); gpio_direction_input(4); - set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); spi_register_board_info(mistral_boardinfo, ARRAY_SIZE(mistral_boardinfo)); /* the sideways button (SW1) is for use as a "wakeup" button * * NOTE: The Mistral board has the wakeup button (SW1) wired * to the LCD 3.3V rail, which is powered down during suspend. * To allow this button to wake up the omap, work around this * HW bug by rewiring SW1 to use the main 3.3V rail. */ omap_cfg_reg(N15_1610_MPUIO2); if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) { int ret = 0; int irq = gpio_to_irq(OMAP_MPUIO(2)); gpio_direction_input(OMAP_MPUIO(2)); - set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_PM /* share the IRQ in case someone wants to use the * button for more than wakeup from system sleep. */ ret = request_irq(irq, &osk_mistral_wake_interrupt, IRQF_SHARED, "mistral_wakeup", &osk_mistral_wake_interrupt); if (ret != 0) { gpio_free(OMAP_MPUIO(2)); printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", ret); diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7bbbe7..45f01d2 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -247,30 +247,30 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel palmz71_config[] __initdata = { {OMAP_TAG_LCD, &palmz71_lcd_config}, }; static irqreturn_t palmz71_powercable(int irq, void *dev_id) { if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { printk(KERN_INFO "PM: Power cable connected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_FALLING); } else { printk(KERN_INFO "PM: Power cable disconnected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_RISING); } return IRQ_HANDLED; } static void __init omap_mpu_wdt_mode(int mode) { if (mode) omap_writew(0x8000, OMAP_WDT_TIMER_MODE); else { omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bdc0ac8..65d2420 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -270,28 +270,28 @@ static void __init voiceblue_init(void) gpio_set_value(7, 0); mdelay(50); /* 50ms until PHY ready */ /* smc91x interrupt pin */ gpio_request(8, "SMC91x irq"); /* 16C554 reset*/ gpio_request(6, "16C554 reset"); gpio_direction_output(6, 0); /* 16C554 interrupt pins */ gpio_request(12, "16C554 irq"); gpio_request(13, "16C554 irq"); gpio_request(14, "16C554 irq"); gpio_request(15, "16C554 irq"); - set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); omap_board_config = voiceblue_config; omap_board_config_size = ARRAY_SIZE(voiceblue_config); omap_serial_init(); omap1_usb_init(&voiceblue_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); /* There is a good chance board is going up, so enable power LED * (it is connected through invertor) */ omap_writeb(0x00, OMAP_LPG1_LCR); omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0ace799..cddbf8b 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -147,42 +147,42 @@ void omap1510_fpga_init_irq(void) __raw_writeb(0, OMAP1510_FPGA_IMR_LO); __raw_writeb(0, OMAP1510_FPGA_IMR_HI); __raw_writeb(0, INNOVATOR_FPGA_IMR2); for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) { if (i == OMAP1510_INT_FPGA_TS) { /* * The touchscreen interrupt is level-sensitive, so * we'll use the regular mask_ack routine for it. */ - set_irq_chip(i, &omap_fpga_irq_ack); + irq_set_chip(i, &omap_fpga_irq_ack); } else { /* * All FPGA interrupts except the touchscreen are * edge-sensitive, so we won't mask them. */ - set_irq_chip(i, &omap_fpga_irq); + irq_set_chip(i, &omap_fpga_irq); } - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } /* * The FPGA interrupt line is connected to GPIO13. Claim this pin for * the ARM. * * NOTE: For general GPIO/MPUIO access and interrupts, please see * gpio.[ch] */ res = gpio_request(13, "FPGA irq"); if (res) { pr_err("%s failed to get gpio\n", __func__); return; } gpio_direction_input(13); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); } diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 731dd33..5d3da7a 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -221,26 +221,26 @@ void __init omap_init_irq(void) /* Enable interrupts in global mask */ if (cpu_is_omap7xx()) irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); /* Install the interrupt handlers for each bank */ for (i = 0; i < irq_bank_count; i++) { for (j = i * 32; j < (i + 1) * 32; j++) { int irq_trigger; irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); - set_irq_chip(j, &omap_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &omap_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } } /* Unmask level 2 handler */ if (cpu_is_omap7xx()) omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ)); else if (cpu_is_omap15xx()) omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ)); else if (cpu_is_omap16xx()) omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ)); diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c936c6d..f3a7b10 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -276,37 +276,24 @@ static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) { struct omap2_hsmmc_info *c; omap2_hsmmc_init(controllers); for (c = controllers; c->mmc; c++) omap4_twl6030_hsmmc_set_late_init(c->dev); return 0; } -static struct regulator_init_data omap4_panda_vaux1 = { - .constraints = { - .min_uV = 1000000, - .max_uV = 3000000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - static struct regulator_init_data omap4_panda_vaux2 = { .constraints = { .min_uV = 1200000, .max_uV = 2800000, .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, }; @@ -344,37 +331,24 @@ static struct regulator_init_data omap4_panda_vpp = { .constraints = { .min_uV = 1800000, .max_uV = 2500000, .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, }; -static struct regulator_init_data omap4_panda_vusim = { - .constraints = { - .min_uV = 1200000, - .max_uV = 2900000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - static struct regulator_init_data omap4_panda_vana = { .constraints = { .min_uV = 2100000, .max_uV = 2100000, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, }; static struct regulator_init_data omap4_panda_vcxio = { @@ -415,30 +389,28 @@ static struct regulator_init_data omap4_panda_clk32kg = { .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS, }, }; static struct twl4030_platform_data omap4_panda_twldata = { .irq_base = TWL6030_IRQ_BASE, .irq_end = TWL6030_IRQ_END, /* Regulators */ .vmmc = &omap4_panda_vmmc, .vpp = &omap4_panda_vpp, - .vusim = &omap4_panda_vusim, .vana = &omap4_panda_vana, .vcxio = &omap4_panda_vcxio, .vdac = &omap4_panda_vdac, .vusb = &omap4_panda_vusb, - .vaux1 = &omap4_panda_vaux1, .vaux2 = &omap4_panda_vaux2, .vaux3 = &omap4_panda_vaux3, .clk32kg = &omap4_panda_clk32kg, .usb = &omap4_usbphy_data, }; static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { { I2C_BOARD_INFO("twl6030", 0x48), .flags = I2C_CLIENT_WAKE, .irq = OMAP44XX_IRQ_SYS_1N, .platform_data = &omap4_panda_twldata, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e978514..84d1b73 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -57,25 +57,25 @@ static int __init omap3_l3_init(void) l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); oh = omap_hwmod_lookup(oh_name); if (!oh) pr_err("could not look up %s\n", oh_name); od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, NULL, 0, 0); WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); - return PTR_ERR(od); + return IS_ERR(od) ? PTR_ERR(od) : 0; } postcore_initcall(omap3_l3_init); static int __init omap4_l3_init(void) { int l, i; struct omap_hwmod *oh[3]; struct omap_device *od; char oh_name[L3_MODULES_MAX_LEN]; /* * To avoid code running on other OMAPs in diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 6741743..130034b 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -684,38 +684,42 @@ static void __init gpmc_mem_init(void) if (!gpmc_cs_mem_enabled(cs)) continue; gpmc_cs_get_memconf(cs, &base, &size); if (gpmc_cs_insert_mem(cs, base, size) < 0) BUG(); } } static int __init gpmc_init(void) { u32 l, irq; int cs, ret = -EINVAL; + int gpmc_irq; char *ck = NULL; if (cpu_is_omap24xx()) { ck = "core_l3_ck"; if (cpu_is_omap2420()) l = OMAP2420_GPMC_BASE; else l = OMAP34XX_GPMC_BASE; + gpmc_irq = INT_34XX_GPMC_IRQ; } else if (cpu_is_omap34xx()) { ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; + gpmc_irq = INT_34XX_GPMC_IRQ; } else if (cpu_is_omap44xx()) { ck = "gpmc_ck"; l = OMAP44XX_GPMC_BASE; + gpmc_irq = OMAP44XX_IRQ_GPMC; } if (WARN_ON(!ck)) return ret; gpmc_l3_clk = clk_get(NULL, ck); if (IS_ERR(gpmc_l3_clk)) { printk(KERN_ERR "Could not get GPMC clock %s\n", ck); BUG(); } gpmc_base = ioremap(l, SZ_4K); @@ -730,44 +734,43 @@ static int __init gpmc_init(void) l = gpmc_read_reg(GPMC_REVISION); printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Set smart idle mode and automatic L3 clock gating */ l = gpmc_read_reg(GPMC_SYSCONFIG); l &= 0x03 << 3; l |= (0x02 << 3) | (1 << 0); gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); /* initalize the irq_chained */ irq = OMAP_GPMC_IRQ_BASE; for (cs = 0; cs < GPMC_CS_NUM; cs++) { - set_irq_handler(irq, handle_simple_irq); + irq_set_chip_and_handler(irq, &dummy_irq_chip, + handle_simple_irq); set_irq_flags(irq, IRQF_VALID); irq++; } - ret = request_irq(INT_34XX_GPMC_IRQ, + ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", - INT_34XX_GPMC_IRQ, ret); + gpmc_irq, ret); return ret; } postcore_initcall(gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { u8 cs; - if (irq != INT_34XX_GPMC_IRQ) - return IRQ_HANDLED; /* check cs to invoke the irq */ cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); return IRQ_HANDLED; } #ifdef CONFIG_ARCH_OMAP3 static struct omap3_gpmc_regs gpmc_context; void omap3_gpmc_save_context(void) diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bc524b9..237e453 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -214,26 +214,25 @@ void __init omap_init_irq(void) } omap_irq_bank_init_one(bank); nr_of_irqs += bank->nr_irqs; nr_banks++; } printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); for (i = 0; i < nr_of_irqs; i++) { - set_irq_chip(i, &omap_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } } #ifdef CONFIG_ARCH_OMAP3 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; void omap_intc_save_context(void) { int ind = 0, i = 0; for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { struct omap_irq_bank *bank = irq_banks + ind; diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c index 265bff3..5f2da756 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.c +++ b/arch/arm/mach-omap2/omap_l3_smx.c @@ -217,68 +217,65 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) /* clear the error log register */ omap3_l3_writell(base, L3_ERROR_LOG, error); return ret; } static int __init omap3_l3_probe(struct platform_device *pdev) { struct omap3_l3 *l3; struct resource *res; int ret; - int irq; l3 = kzalloc(sizeof(*l3), GFP_KERNEL); if (!l3) { ret = -ENOMEM; goto err0; } platform_set_drvdata(pdev, l3); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "couldn't find resource\n"); ret = -ENODEV; goto err1; } l3->rt = ioremap(res->start, resource_size(res)); if (!(l3->rt)) { dev_err(&pdev->dev, "ioremap failed\n"); ret = -ENOMEM; goto err2; } - irq = platform_get_irq(pdev, 0); - ret = request_irq(irq, omap3_l3_app_irq, + l3->debug_irq = platform_get_irq(pdev, 0); + ret = request_irq(l3->debug_irq, omap3_l3_app_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING, "l3-debug-irq", l3); if (ret) { dev_err(&pdev->dev, "couldn't request debug irq\n"); goto err3; } - l3->debug_irq = irq; - irq = platform_get_irq(pdev, 1); - ret = request_irq(irq, omap3_l3_app_irq, + l3->app_irq = platform_get_irq(pdev, 1); + ret = request_irq(l3->app_irq, omap3_l3_app_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING, "l3-app-irq", l3); if (ret) { dev_err(&pdev->dev, "couldn't request app irq\n"); goto err4; } - l3->app_irq = irq; goto err0; err4: err3: iounmap(l3->rt); err2: err1: kfree(l3); err0: return ret; } diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index c10a117..b7d4591 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -204,38 +204,38 @@ __initcall(db88f5281_7seg_init); ****************************************************************************/ void __init db88f5281_pci_preinit(void) { int pin; /* * Configure PCI GPIO IRQ pins */ pin = DB88F5281_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield to " "set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); } pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield " "to set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); } } static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ed85891..43cf8bc 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -25,17 +25,17 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3); } void __init orion5x_init_irq(void) { orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); /* * Initialize gpiolib for GPIOs 0-31. */ orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); - set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 67ec695..4fc4677 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -139,38 +139,38 @@ __initcall(rd88f5182_dbgled_init); ****************************************************************************/ void __init rd88f5182_pci_preinit(void) { int pin; /* * Configure PCI GPIO IRQ pins */ pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; if (gpio_request(pin, "PCI IntA") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); } pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; if (gpio_request(pin, "PCI IntB") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); } } static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 5653ee6..6160041 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -79,25 +79,25 @@ static struct platform_device tsp2_nor_flash = { #define TSP2_PCI_SLOT0_IRQ_PIN 11 void __init tsp2_pci_preinit(void) { int pin; /* * Configure PCI GPIO IRQ pins */ pin = TSP2_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "tsp2_pci_preinit failed " "to set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "tsp2_pci_preinit failed to " "gpio_request %d\n", pin); } } static int __init tsp2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8bbd27e..f0f43e1 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -108,39 +108,39 @@ static struct platform_device qnap_ts209_nor_flash = { #define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 void __init qnap_ts209_pci_preinit(void) { int pin; /* * Configure PCI GPIO IRQ pins */ pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to " "set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " "%d\n", pin); } pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed " "to set_irq_type pin %d\n", pin); gpio_free(pin); } } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request " "%d\n", pin); } } static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index c69c180..7608c7a 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c @@ -49,65 +49,65 @@ static void pnx4008_unmask_irq(struct irq_data *d) static void pnx4008_mask_ack_irq(struct irq_data *d) { __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ } static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) { switch (type) { case IRQ_TYPE_EDGE_RISING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; /* IRQ_TYPE_EDGE_BOTH is not supported */ default: printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type); return -1; } return 0; } static struct irq_chip pnx4008_irq_chip = { .irq_ack = pnx4008_mask_ack_irq, .irq_mask = pnx4008_mask_irq, .irq_unmask = pnx4008_unmask_irq, .irq_set_type = pnx4008_set_irq_type, }; void __init pnx4008_init_irq(void) { unsigned int i; /* configure IRQ's */ for (i = 0; i < NR_IRQS; i++) { set_irq_flags(i, IRQF_VALID); - set_irq_chip(i, &pnx4008_irq_chip); + irq_set_chip(i, &pnx4008_irq_chip); pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); } /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N), pnx4008_irq_type[SUB1_IRQ_N]); pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N), pnx4008_irq_type[SUB2_IRQ_N]); pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N), pnx4008_irq_type[SUB1_FIQ_N]); pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N), pnx4008_irq_type[SUB2_FIQ_N]); diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d2af733..38dea05 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -518,31 +518,31 @@ static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) pending = __raw_readl(BALLOON3_INT_CONTROL_REG) & balloon3_irq_enabled; } while (pending); } static void __init balloon3_init_irq(void) { int irq; pxa27x_init_irq(); /* setup extra Balloon3 irqs */ for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { - set_irq_chip(irq, &balloon3_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &balloon3_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); - set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); + irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); pr_debug("%s: chained handler installed - irq %d automatically " "enabled\n", __func__, BALLOON3_AUX_NIRQ); } /****************************************************************************** * GPIO expander ******************************************************************************/ #if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE) static struct pcf857x_platform_data balloon3_pcf857x_pdata = { .gpio_base = BALLOON3_PCF_GPIO_BASE, .n_latch = 0, diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index a2380cd..8b1a309 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -61,27 +61,28 @@ static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) /* clear our parent irq */ desc->irq_data.chip->irq_ack(&desc->irq_data); it8152_irq_demux(irq, desc); } void __cmx2xx_pci_init_irq(int irq_gpio) { it8152_init_irq(); cmx2xx_it8152_irq_gpio = irq_gpio; - set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); + irq_set_chained_handler(gpio_to_irq(irq_gpio), + cmx2xx_it8152_irq_demux); } #ifdef CONFIG_PM static unsigned long sleep_save_ite[10]; void __cmx2xx_pci_suspend(void) { /* save ITE state */ sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index bfca7ed..06d0a03 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -756,25 +756,25 @@ static struct i2c_board_info cm_x300_pmic_info = { .irq = IRQ_WAKEUP0, .platform_data = &cm_x300_da9030_info, }; static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = { .use_pio = 1, }; static void __init cm_x300_init_da9030(void) { pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); i2c_register_board_info(1, &cm_x300_pmic_info, 1); - set_irq_wake(IRQ_WAKEUP0, 1); + irq_set_irq_wake(IRQ_WAKEUP0, 1); } static void __init cm_x300_init_wi2wi(void) { int bt_reset, wlan_en; int err; if (system_rev < 130) { wlan_en = 77; bt_reset = 78; } else { wlan_en = 71; diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 2693e3c..6251e3f 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -128,27 +128,27 @@ static struct irq_chip pxa_low_gpio_chip = { }; static void __init pxa_init_low_gpio_irq(set_wake_t fn) { int irq; /* clear edge detection on GPIO 0 and 1 */ GFER0 &= ~0x3; GRER0 &= ~0x3; GEDR0 = 0x3; for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { - set_irq_chip(irq, &pxa_low_gpio_chip); - set_irq_chip_data(irq, irq_base(0)); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, + handle_edge_irq); + irq_set_chip_data(irq, irq_base(0)); set_irq_flags(irq, IRQF_VALID); } pxa_low_gpio_chip.irq_set_wake = fn; } void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i, n; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); @@ -156,27 +156,27 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) for (n = 0; n < irq_nr; n += 32) { void __iomem *base = irq_base(n >> 5); __raw_writel(0, base + ICMR); /* disable all IRQs */ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { /* initialize interrupt priority */ if (cpu_has_ipr()) __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); irq = PXA_IRQ(i); - set_irq_chip(irq, &pxa_internal_irq_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID); } } /* only unmasked interrupts kick us out of idle */ __raw_writel(1, irq_base(0) + ICCR); pxa_internal_irq_chip.irq_set_wake = fn; pxa_init_low_gpio_irq(fn); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c9a3e77..6307f70 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -140,30 +140,30 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) static void __init lpd270_init_irq(void) { int irq; pxa27x_init_irq(); __raw_writew(0, LPD270_INT_MASK); __raw_writew(0, LPD270_INT_STATUS); /* setup extra LogicPD PXA270 irqs */ for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { - set_irq_chip(irq, &lpd270_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lpd270_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM static int lpd270_irq_resume(struct sys_device *dev) { __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); return 0; } static struct sysdev_class lpd270_irq_sysclass = { .name = "cpld_irq", diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index dca20de..0fea945 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -156,31 +156,31 @@ static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc) pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; } while (pending); } static void __init lubbock_init_irq(void) { int irq; pxa25x_init_irq(); /* setup extra lubbock irqs */ for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { - set_irq_chip(irq, &lubbock_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lubbock_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM static int lubbock_irq_resume(struct sys_device *dev) { LUB_IRQ_MASK_EN = lubbock_irq_enabled; return 0; } static struct sysdev_class lubbock_irq_sysclass = { .name = "cpld_irq", diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f954222..29b6e7a 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -157,39 +157,39 @@ static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) pending = MST_INTSETCLR & mainstone_irq_enabled; } while (pending); } static void __init mainstone_init_irq(void) { int irq; pxa27x_init_irq(); /* setup extra Mainstone irqs */ for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { - set_irq_chip(irq, &mainstone_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &mainstone_irq_chip, + handle_level_irq); if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); else set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } set_irq_flags(MAINSTONE_IRQ(8), 0); set_irq_flags(MAINSTONE_IRQ(12), 0); MST_INTMSKENA = 0; MST_INTSETCLR = 0; - set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM static int mainstone_irq_resume(struct sys_device *dev) { MST_INTMSKENA = mainstone_irq_enabled; return 0; } static struct sysdev_class mainstone_irq_sysclass = { .name = "cpld_irq", diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9dbf3cc..4d01205 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -272,34 +272,34 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(irq); } pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled; } while (pending); } static void __init pcm990_init_irq(void) { int irq; /* setup extra PCM990 irqs */ for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { - set_irq_chip(irq, &pcm990_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pcm990_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ PCM990_INTSETCLR = 0xFF; - set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); - set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); + irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); + irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); } static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, void *data) { int err; err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED, "MMC card detect", data); if (err) printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC " "card detect IRQ\n"); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f374247..8dd1073 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -353,26 +353,26 @@ static struct irq_chip pxa_ext_wakeup_chip = { .name = "WAKEUP", .irq_ack = pxa_ack_ext_wakeup, .irq_mask = pxa_mask_ext_wakeup, .irq_unmask = pxa_unmask_ext_wakeup, .irq_set_type = pxa_set_ext_wakeup_type, }; static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) { int irq; for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { - set_irq_chip(irq, &pxa_ext_wakeup_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID); } pxa_ext_wakeup_chip.irq_set_wake = fn; } void __init pxa3xx_init_irq(void) { /* enable CP6 access */ u32 value; __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); value |= (1 << 6); diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 1227921..aa70331 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -301,32 +301,32 @@ static struct irq_chip viper_irq_chip = { }; static void __init viper_init_irq(void) { int level; int isa_irq; pxa25x_init_irq(); /* setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { isa_irq = viper_bit_to_irq(level); - set_irq_chip(isa_irq, &viper_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &viper_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), + irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), viper_irq_handler); - set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); } /* Flat Panel */ static struct pxafb_mode_info fb_mode_info[] = { { .pixclock = 157500, .xres = 320, .yres = 240, .bpp = 16, diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 730f51e..139aa7f 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -127,40 +127,41 @@ static struct irq_chip zeus_irq_chip = { .irq_unmask = zeus_unmask_irq, }; static void __init zeus_init_irq(void) { int level; int isa_irq; pxa27x_init_irq(); /* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported at the moment. */ - set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); - set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), + IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); /* Setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { isa_irq = zeus_bit_to_irq(level); - set_irq_chip(isa_irq, &zeus_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); + irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); } /* * Platform devices */ /* Flash */ static struct resource zeus_mtd_resources[] = { [0] = { /* NOR Flash (up to 64MB) */ .start = ZEUS_FLASH_PHYS, .end = ZEUS_FLASH_PHYS + SZ_64M - 1, diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index d29cd9b..2e1b530 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -124,39 +124,39 @@ void __init rpc_init_irq(void) for (irq = 0; irq < NR_IRQS; irq++) { flags = IRQF_VALID; if (irq <= 6 || (irq >= 9 && irq <= 15)) flags |= IRQF_PROBE; if (irq == 21 || (irq >= 16 && irq <= 19) || irq == IRQ_KEYBOARDTX) flags |= IRQF_NOAUTOEN; switch (irq) { case 0 ... 7: - set_irq_chip(irq, &iomd_a_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_a_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 8 ... 15: - set_irq_chip(irq, &iomd_b_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_b_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 16 ... 21: - set_irq_chip(irq, &iomd_dma_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_dma_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 64 ... 71: - set_irq_chip(irq, &iomd_fiq_chip); + irq_set_chip(irq, &iomd_fiq_chip); set_irq_flags(irq, IRQF_VALID); break; } } init_FIQ(); } diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 606cb6b..bc53d2d 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -138,29 +138,29 @@ bast_irq_pc104_demux(unsigned int irq, static __init int bast_irq_init(void) { unsigned int i; if (machine_is_bast()) { printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n"); /* zap all the IRQs */ __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); + irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); /* register our IRQs */ for (i = 0; i < 4; i++) { unsigned int irqno = bast_pc104_irqs[i]; - set_irq_chip(irqno, &bast_pc104_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &bast_pc104_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } return 0; } arch_initcall(bast_irq_init); diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index eddb52b..f3355d2 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -166,45 +166,45 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) __raw_writel(pwrcfg, S3C2412_PWRCFG); return s3c_irq_chip.irq_set_wake(data, state); } static struct irq_chip s3c2412_irq_rtc_chip; static int s3c2412_irq_add(struct sys_device *sysdev) { unsigned int irqno; for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } /* add demux support for CF/SDI */ - set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_cfsdi); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } /* change RTC IRQ's set wake method */ s3c2412_irq_rtc_chip = s3c_irq_chip; s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; - set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); + irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); return 0; } static struct sysdev_driver s3c2412_irq_driver = { .add = s3c2412_irq_add, .suspend = s3c24xx_irq_suspend, .resume = s3c24xx_irq_resume, }; static int s3c2412_irq_init(void) { diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 680fe38..77b38f2 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -193,31 +193,29 @@ static struct irq_chip s3c2416_irq_uart3 = { }; /* IRQ initialisation code */ static int __init s3c2416_add_sub(unsigned int base, void (*demux)(unsigned int, struct irq_desc *), struct irq_chip *chip, unsigned int start, unsigned int end) { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } return 0; } static int __init s3c2416_irq_add(struct sys_device *sysdev) { printk(KERN_INFO "S3C2416: IRQ Support\n"); s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd, IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4); diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index acad442..eb1cc0f 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c @@ -91,31 +91,31 @@ static struct irq_chip s3c_irq_wdtac97 = { .irq_unmask = s3c_irq_wdtac97_unmask, .irq_ack = s3c_irq_wdtac97_ack, }; static int s3c2440_irq_add(struct sys_device *sysdev) { unsigned int irqno; printk("S3C2440: IRQ Support\n"); /* add new chained handler for wdt, ac7 */ - set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); - set_irq_handler(IRQ_WDT, handle_level_irq); - set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { - set_irq_chip(irqno, &s3c_irq_wdtac97); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } return 0; } static struct sysdev_driver s3c2440_irq_driver = { .add = s3c2440_irq_add, }; static int s3c2440_irq_init(void) { diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 83daf4e..de07c2f 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -86,37 +86,37 @@ s3c_irq_cam_ack(struct irq_data *data) } static struct irq_chip s3c_irq_cam = { .irq_mask = s3c_irq_cam_mask, .irq_unmask = s3c_irq_cam_unmask, .irq_ack = s3c_irq_cam_ack, }; static int s3c244x_irq_add(struct sys_device *sysdev) { unsigned int irqno; - set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); - set_irq_handler(IRQ_NFCON, handle_level_irq); + irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, + handle_level_irq); set_irq_flags(IRQ_NFCON, IRQF_VALID); /* add chained handler for camera */ - set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); - set_irq_handler(IRQ_CAM, handle_level_irq); - set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); + irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - set_irq_chip(irqno, &s3c_irq_cam); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_cam, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } return 0; } static struct sysdev_driver s3c2440_irq_driver = { .add = s3c244x_irq_add, .suspend = s3c24xx_irq_suspend, .resume = s3c24xx_irq_resume, }; diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index c7820f9..83ecb11 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -221,31 +221,29 @@ static struct irq_chip s3c2443_irq_cam = { }; /* IRQ initialisation code */ static int __init s3c2443_add_sub(unsigned int base, void (*demux)(unsigned int, struct irq_desc *), struct irq_chip *chip, unsigned int start, unsigned int end) { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } return 0; } static int __init s3c2443_irq_add(struct sys_device *sysdev) { printk("S3C2443: IRQ Support\n"); s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam, IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P); diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 2ead818..4d203be 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c @@ -188,27 +188,26 @@ static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) } static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) { s3c_irq_demux_eint(20, 27); } static int __init s3c64xx_init_irq_eint(void) { int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { - set_irq_chip(irq, &s3c_irq_eint); - set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); + irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); - set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); - set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); - set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); + irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); + irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); + irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); + irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); return 0; } arch_initcall(s3c64xx_init_irq_eint); diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c index b8d02eb..a5c0095 100644 --- a/arch/arm/mach-s5p64x0/cpu.c +++ b/arch/arm/mach-s5p64x0/cpu.c @@ -110,25 +110,25 @@ void __init s5p6440_map_io(void) s3c_adc_setname("s3c64xx-adc"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); } void __init s5p6450_map_io(void) { /* initialize any device information early */ s3c_adc_setname("s3c64xx-adc"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); - iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc)); + iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); } /* * s5p64x0_init_clocks * * register and setup the CPU clocks */ void __init s5p6440_init_clocks(int xtal) { printk(KERN_DEBUG "%s: initializing clocks\n", __func__); diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 26710b3..b9f9ec3 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -90,27 +90,27 @@ #define IRQ_I2S0 S5P_IRQ_VIC2(16) #define IRQ_I2S1 S5P_IRQ_VIC2(17) #define IRQ_I2S2 S5P_IRQ_VIC2(18) #define IRQ_AC97 S5P_IRQ_VIC2(19) #define IRQ_PCM0 S5P_IRQ_VIC2(20) #define IRQ_PCM1 S5P_IRQ_VIC2(21) #define IRQ_SPDIF S5P_IRQ_VIC2(22) #define IRQ_ADC S5P_IRQ_VIC2(23) #define IRQ_PENDN S5P_IRQ_VIC2(24) #define IRQ_TC IRQ_PENDN #define IRQ_KEYPAD S5P_IRQ_VIC2(25) #define IRQ_CG S5P_IRQ_VIC2(26) -#define IRQ_SEC S5P_IRQ_VIC2(27) -#define IRQ_SECRX S5P_IRQ_VIC2(28) -#define IRQ_SECTX S5P_IRQ_VIC2(29) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_PCM2 S5P_IRQ_VIC2(29) #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) /* VIC3: Etc */ #define IRQ_IPC S5P_IRQ_VIC3(0) #define IRQ_HOSTIF S5P_IRQ_VIC3(1) #define IRQ_HSMMC3 S5P_IRQ_VIC3(2) #define IRQ_CEC S5P_IRQ_VIC3(3) #define IRQ_TSI S5P_IRQ_VIC3(4) #define IRQ_MDNIE0 S5P_IRQ_VIC3(5) #define IRQ_MDNIE1 S5P_IRQ_VIC3(6) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index bc08ac4..c6a9e86 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -35,25 +35,24 @@ #include <plat/regs-srom.h> #include <plat/gpio-cfg.h> #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/adc.h> #include <plat/ts.h> #include <plat/ata.h> #include <plat/iic.h> #include <plat/keypad.h> #include <plat/pm.h> #include <plat/fb.h> -#include <plat/gpio-cfg.h> #include <plat/s5p-time.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) #define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8 diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 98d7806..7f3da4b 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -87,25 +87,25 @@ static struct flash_platform_data cerf_flash_data = { .nr_parts = ARRAY_SIZE(cerf_partitions), }; static struct resource cerf_flash_resource = { .start = SA1100_CS0_PHYS, .end = SA1100_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; static void __init cerf_init_irq(void) { sa1100_init_irq(); - set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); } static struct map_desc cerf_io_desc[] __initdata = { { /* Crystal Ethernet Chip */ .virtual = 0xf0000000, .pfn = __phys_to_pfn(0x08000000), .length = 0x00100000, .type = MT_DEVICE } }; static void __init cerf_map_io(void) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3d85dfa..423ddb3 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -314,37 +314,37 @@ void __init sa1100_init_irq(void) /* clear all GPIO edge detects */ GFER = 0; GRER = 0; GEDR = -1; /* * Whatever the doc says, this has to be set for the wait-on-irq * instruction to work... on a SA1100 rev 9 at least. */ ICCR = 1; for (irq = 0; irq <= 10; irq++) { - set_irq_chip(irq, &sa1100_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = 12; irq <= 31; irq++) { - set_irq_chip(irq, &sa1100_normal_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &sa1100_normal_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = 32; irq <= 48; irq++) { - set_irq_chip(irq, &sa1100_high_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Install handler for GPIO 11-27 edge detect interrupts */ - set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); - set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); + irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); + irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); sa1100_init_gpio(); } diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4aad01f..b4fa53a 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -136,43 +136,43 @@ static u_int neponset_get_mctrl(struct uart_port *port) static struct sa1100_port_fns neponset_port_fns __devinitdata = { .set_mctrl = neponset_set_mctrl, .get_mctrl = neponset_get_mctrl, }; static int __devinit neponset_probe(struct platform_device *dev) { sa1100_register_uart_fns(&neponset_port_fns); /* * Install handler for GPIO25. */ - set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); + irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); /* * We would set IRQ_GPIO25 to be a wake-up IRQ, but * unfortunately something on the Neponset activates * this IRQ on sleep (ethernet?) */ #if 0 enable_irq_wake(IRQ_GPIO25); #endif /* * Setup other Neponset IRQs. SA1111 will be done by the * generic SA1111 code. */ - set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); - set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); /* * Disable GPIO 0/1 drivers so the buttons work on the module. */ NCR_0 = NCR_GP01_OFF; return 0; } #ifdef CONFIG_PM diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 42b8040..65161f2 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -133,21 +133,21 @@ static void __init pleb_map_io(void) * Fix expansion memory timing for network card */ MECR = ((2<<10) | (2<<5) | (2<<0)); /* * Enable the SMC ethernet controller */ GPDR |= GPIO_ETH0_EN; /* set to output */ GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */ GPDR &= ~GPIO_ETH0_IRQ; - set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); } MACHINE_START(PLEB, "PLEB") .map_io = pleb_map_io, .init_irq = sa1100_init_irq, .timer = &sa1100_timer, .init_machine = pleb_init, MACHINE_END diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index 831fc66..5dce13e 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c @@ -71,26 +71,25 @@ static struct irqaction cascade; static struct irq_chip fb_chip = { .name = "XT-PIC", .irq_ack = shark_ack_8259A_irq, .irq_mask = shark_disable_8259A_irq, .irq_unmask = shark_enable_8259A_irq, }; void __init shark_init_irq(void) { int irq; for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* init master interrupt controller */ outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/ outb(0x00, 0x21); /* Vector base */ outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ outb(0x0A, 0x20); /* init slave interrupt controller */ outb(0x11, 0xA0); /* Start init sequence, edge triggered */ outb(0x08, 0xA1); /* Vector base */ diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a94f29d..08cc451 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -1246,25 +1246,25 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYOUT0, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT4, NULL); gpio_request(GPIO_FN_KEYIN0_136, NULL); gpio_request(GPIO_FN_KEYIN1_135, NULL); gpio_request(GPIO_FN_KEYIN2_134, NULL); gpio_request(GPIO_FN_KEYIN3_133, NULL); gpio_request(GPIO_FN_KEYIN4, NULL); /* enable TouchScreen */ - set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ28; i2c_register_board_info(1, &tsc_device, 1); /* LCDC0 */ lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; lcdc_info.ch[0].interface_type = RGB24; lcdc_info.ch[0].clock_divider = 1; lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; lcdc_info.ch[0].lcd_size_cfg.width = 44; lcdc_info.ch[0].lcd_size_cfg.height = 79; @@ -1302,25 +1302,25 @@ static void __init ap4evb_init(void) gpio_request(GPIO_PORT151, NULL); /* LCDDON */ gpio_direction_output(GPIO_PORT151, 1); lcdc_info.clock_source = LCDC_CLK_BUS; lcdc_info.ch[0].interface_type = RGB18; lcdc_info.ch[0].clock_divider = 3; lcdc_info.ch[0].flags = 0; lcdc_info.ch[0].lcd_size_cfg.width = 152; lcdc_info.ch[0].lcd_size_cfg.height = 91; /* enable TouchScreen */ - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ7; i2c_register_board_info(0, &tsc_device, 1); #endif /* CONFIG_AP4EVB_QHD */ /* CEU */ /* * TODO: reserve memory for V4L2 DMA buffers, when a suitable API * becomes available */ diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 49bc074..f0d0af1 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1115,33 +1115,33 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_FSIBCK, NULL); __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 119600000)); clk_put(clk); } /* enable Keypad */ gpio_request(GPIO_FN_IRQ9_42, NULL); - set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); /* enable Touchscreen */ gpio_request(GPIO_FN_IRQ7_40, NULL); - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); /* enable Accelerometer */ gpio_request(GPIO_FN_IRQ21, NULL); - set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); /* enable SDHI0 */ gpio_request(GPIO_FN_SDHICD0, NULL); gpio_request(GPIO_FN_SDHIWP0, NULL); gpio_request(GPIO_FN_SDHICMD0, NULL); gpio_request(GPIO_FN_SDHICLK0, NULL); gpio_request(GPIO_FN_SDHID0_3, NULL); gpio_request(GPIO_FN_SDHID0_2, NULL); gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); #if !defined(CONFIG_MMC_SH_MMCIF) diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 2fe9704..cc442d1 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -412,29 +412,29 @@ static struct resource intcs_resources[] __initdata = { }; static struct intc_desc intcs_desc __initdata = { .name = "sh7367-intcs", .resource = intcs_resources, .num_resources = ARRAY_SIZE(intcs_resources), .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, intcs_prio_registers, NULL, NULL), }; static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); } void __init sh7367_init_irq(void) { void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index ca5f9d1..7a4960f 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -592,29 +592,29 @@ static struct resource intcs_resources[] __initdata = { static struct intc_desc intcs_desc __initdata = { .name = "sh7372-intcs", .force_enable = ENABLED_INTCS, .resource = intcs_resources, .num_resources = ARRAY_SIZE(intcs_resources), .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, intcs_prio_registers, NULL, NULL), }; static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); } void __init sh7372_init_irq(void) { void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index dd56838..fe45154 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -617,30 +617,30 @@ static struct resource intcs_resources[] __initdata = { static struct intc_desc intcs_desc __initdata = { .name = "sh7377-intcs", .resource = intcs_resources, .num_resources = ARRAY_SIZE(intcs_resources), .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, intcs_prio_registers, NULL, NULL), }; static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); } #define INTEVTSA 0xFFD20100 void __init sh7377_init_irq(void) { void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); - set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); + irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); + irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); } diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index aa9231f..209fa5c 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c @@ -93,19 +93,19 @@ void __init tcc8k_init_irq(void) PIC1_MEN1 = 0x00000003; PIC1_MEN = 0x00000003; /* let all IRQs be level triggered */ PIC0_TMODE = 0xffffffff; PIC1_TMODE = 0xffffffff; /* all IRQs are IRQs (not FIQs) */ PIC0_IRQSEL = 0xffffffff; PIC1_IRQSEL = 0xffffffff; for (irqno = 0; irqno < NR_IRQS; irqno++) { if (irqno < 32) - set_irq_chip(irqno, &tcc8000_irq_chip0); + irq_set_chip(irqno, &tcc8000_irq_chip0); else - set_irq_chip(irqno, &tcc8000_irq_chip1); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip(irqno, &tcc8000_irq_chip1); + irq_set_handler(irqno, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 12090a2..76a3f65 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -199,41 +199,41 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) } spin_lock_irqsave(&bank->lvl_lock[port], flags); val = __raw_readl(GPIO_INT_LVL(gpio)); val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); val |= lvl_type << GPIO_BIT(gpio); __raw_writel(val, GPIO_INT_LVL(gpio)); spin_unlock_irqrestore(&bank->lvl_lock[port], flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); return 0; } static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { struct tegra_gpio_bank *bank; int port; int pin; int unmasked = 0; desc->irq_data.chip->irq_ack(&desc->irq_data); - bank = get_irq_data(irq); + bank = irq_get_handler_data(irq); for (port = 0; port < 4; port++) { int gpio = tegra_gpio_compose(bank->bank, port, 0); unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) & __raw_readl(GPIO_INT_ENB(gpio)); u32 lvl = __raw_readl(GPIO_INT_LVL(gpio)); for_each_set_bit(pin, &sta, 8) { __raw_writel(1 << pin, GPIO_INT_CLR(gpio)); /* if gpio is edge triggered, clear condition * before executing the hander so that we don't @@ -266,70 +266,51 @@ void tegra_gpio_resume(void) for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { unsigned int gpio = (b<<5) | (p<<3); __raw_writel(bank->cnf[p], GPIO_CNF(gpio)); __raw_writel(bank->out[p], GPIO_OUT(gpio)); __raw_writel(bank->oe[p], GPIO_OE(gpio)); __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); } } local_irq_restore(flags); - - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc || (desc->status & IRQ_WAKEUP)) - continue; - enable_irq(i); - } } void tegra_gpio_suspend(void) { unsigned long flags; int b, p, i; - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc) - continue; - if (desc->status & IRQ_WAKEUP) { - int gpio = i - INT_GPIO_BASE; - pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); - continue; - } - disable_irq(i); - } - local_irq_save(flags); for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { unsigned int gpio = (b<<5) | (p<<3); bank->cnf[p] = __raw_readl(GPIO_CNF(gpio)); bank->out[p] = __raw_readl(GPIO_OUT(gpio)); bank->oe[p] = __raw_readl(GPIO_OE(gpio)); bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio)); bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio)); } } local_irq_restore(flags); } static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) { struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); - return set_irq_wake(bank->irq, enable); + return irq_set_irq_wake(bank->irq, enable); } #endif static struct irq_chip tegra_gpio_irq_chip = { .name = "GPIO", .irq_ack = tegra_gpio_irq_ack, .irq_mask = tegra_gpio_irq_mask, .irq_unmask = tegra_gpio_irq_unmask, .irq_set_type = tegra_gpio_irq_set_type, #ifdef CONFIG_PM .irq_set_wake = tegra_gpio_wake_enable, #endif @@ -350,36 +331,36 @@ static int __init tegra_gpio_init(void) for (i = 0; i < 7; i++) { for (j = 0; j < 4; j++) { int gpio = tegra_gpio_compose(i, j, 0); __raw_writel(0x00, GPIO_INT_ENB(gpio)); } } gpiochip_add(&tegra_gpio_chip); for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; - lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); - set_irq_chip_data(i, bank); - set_irq_chip(i, &tegra_gpio_irq_chip); - set_irq_handler(i, handle_simple_irq); + irq_set_lockdep_class(i, &gpio_lock_class); + irq_set_chip_data(i, bank); + irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, + handle_simple_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { bank = &tegra_gpio_banks[i]; - set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); + irq_set_handler_data(bank->irq, bank); for (j = 0; j < 4; j++) spin_lock_init(&bank->lvl_lock[j]); } return 0; } postcore_initcall(tegra_gpio_init); void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) { diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index dfbc219..4330d89 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -135,27 +135,26 @@ static struct irq_chip tegra_irq = { void __init tegra_init_irq(void) { struct irq_chip *gic; unsigned int i; int irq; tegra_init_legacy_irq(); gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - gic = get_irq_chip(29); + gic = irq_get_chip(29); tegra_gic_unmask_irq = gic->irq_unmask; tegra_gic_mask_irq = gic->irq_mask; tegra_gic_ack_irq = gic->irq_ack; #ifdef CONFIG_SMP tegra_irq.irq_set_affinity = gic->irq_set_affinity; #endif for (i = 0; i < INT_MAIN_NR; i++) { irq = INT_PRI_BASE + i; - set_irq_chip(irq, &tegra_irq); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 203b986..5862601 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -14,24 +14,25 @@ config UX500_SOC_DB5500 bool "DB5500" config UX500_SOC_DB8500 bool "DB8500" endmenu menu "Ux500 target platform" config MACH_U8500 bool "U8500 Development platform" depends on UX500_SOC_DB8500 + select TPS6105X help Include support for the mop500 development platform. config MACH_U5500 bool "U5500 Development platform" depends on UX500_SOC_DB5500 help Include support for the U5500 development platform. endmenu config UX500_DEBUG_UART int "Ux500 UART to use for low-level debug" diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 875c91b..9ed0f90 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -4,24 +4,48 @@ * License Terms: GNU General Public License v2 * * Authors: Sundar Iyer <sundar.iyer@stericsson.com> * Bengt Jonsson <bengt.g.jonsson@stericsson.com> * * MOP500 board specific initialization for regulators */ #include <linux/kernel.h> #include <linux/regulator/machine.h> #include <linux/regulator/ab8500.h> #include "board-mop500-regulators.h" +/* + * TPS61052 regulator + */ +static struct regulator_consumer_supply tps61052_vaudio_consumers[] = { + /* + * Boost converter supply to raise voltage on audio speaker, this + * is actually connected to three pins, VInVhfL (left amplifier) + * VInVhfR (right amplifier) and VIntDClassInt - all three must + * be connected to the same voltage. + */ + REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"), +}; + +struct regulator_init_data tps61052_regulator = { + .constraints = { + .name = "vaudio-hf", + .min_uV = 4500000, + .max_uV = 4500000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers), + .consumer_supplies = tps61052_vaudio_consumers, +}; + static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { /* External displays, connector on board 2v5 power supply */ REGULATOR_SUPPLY("vaux12v5", "mcde.0"), /* SFH7741 proximity sensor */ REGULATOR_SUPPLY("vcc", "gpio-keys.0"), /* BH1780GLS ambient light sensor */ REGULATOR_SUPPLY("vcc", "2-0029"), /* lsm303dlh accelerometer */ REGULATOR_SUPPLY("vdd", "3-0018"), /* lsm303dlh magnetometer */ REGULATOR_SUPPLY("vdd", "3-001e"), /* Rohm BU21013 Touchscreen devices */ @@ -53,34 +77,211 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = { static struct regulator_consumer_supply ab8500_vintcore_consumers[] = { /* SoC core supply, no device */ REGULATOR_SUPPLY("v-intcore", NULL), /* USB Transciever */ REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"), }; static struct regulator_consumer_supply ab8500_vana_consumers[] = { /* External displays, connector on board, 1v8 power supply */ REGULATOR_SUPPLY("vsmps2", "mcde.0"), }; +/* ab8500 regulator register initialization */ +struct ab8500_regulator_reg_init +ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = { + /* + * VanaRequestCtrl = HP/LP depending on VxRequest + * VextSupply1RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00), + /* + * VextSupply2RequestCtrl = HP/LP depending on VxRequest + * VextSupply3RequestCtrl = HP/LP depending on VxRequest + * Vaux1RequestCtrl = HP/LP depending on VxRequest + * Vaux2RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00), + /* + * Vaux3RequestCtrl = HP/LP depending on VxRequest + * SwHPReq = Control through SWValid disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00), + /* + * VanaSysClkReq1HPValid = disabled + * Vaux1SysClkReq1HPValid = disabled + * Vaux2SysClkReq1HPValid = disabled + * Vaux3SysClkReq1HPValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00), + /* + * VextSupply1SysClkReq1HPValid = disabled + * VextSupply2SysClkReq1HPValid = disabled + * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40), + /* + * VanaHwHPReq1Valid = disabled + * Vaux1HwHPreq1Valid = disabled + * Vaux2HwHPReq1Valid = disabled + * Vaux3HwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00), + /* + * VextSupply1HwHPReq1Valid = disabled + * VextSupply2HwHPReq1Valid = disabled + * VextSupply3HwHPReq1Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00), + /* + * VanaHwHPReq2Valid = disabled + * Vaux1HwHPReq2Valid = disabled + * Vaux2HwHPReq2Valid = disabled + * Vaux3HwHPReq2Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00), + /* + * VextSupply1HwHPReq2Valid = disabled + * VextSupply2HwHPReq2Valid = disabled + * VextSupply3HwHPReq2Valid = HWReq2 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04), + /* + * VanaSwHPReqValid = disabled + * Vaux1SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00), + /* + * Vaux2SwHPReqValid = disabled + * Vaux3SwHPReqValid = disabled + * VextSupply1SwHPReqValid = disabled + * VextSupply2SwHPReqValid = disabled + * VextSupply3SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00), + /* + * SysClkReq2Valid1 = SysClkReq2 controlled + * SysClkReq3Valid1 = disabled + * SysClkReq4Valid1 = SysClkReq4 controlled + * SysClkReq5Valid1 = disabled + * SysClkReq6Valid1 = SysClkReq6 controlled + * SysClkReq7Valid1 = disabled + * SysClkReq8Valid1 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a), + /* + * SysClkReq2Valid2 = disabled + * SysClkReq3Valid2 = disabled + * SysClkReq4Valid2 = disabled + * SysClkReq5Valid2 = disabled + * SysClkReq6Valid2 = SysClkReq6 controlled + * SysClkReq7Valid2 = disabled + * SysClkReq8Valid2 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20), + /* + * VTVoutEna = disabled + * Vintcore12Ena = disabled + * Vintcore12Sel = 1.25 V + * Vintcore12LP = inactive (HP) + * VTVoutLP = inactive (HP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10), + /* + * VaudioEna = disabled + * VdmicEna = disabled + * Vamic1Ena = disabled + * Vamic2Ena = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00), + /* + * Vamic1_dzout = high-Z when Vamic1 is disabled + * Vamic2_dzout = high-Z when Vamic2 is disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00), + /* + * VPll = Hw controlled + * VanaRegu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02), + /* + * VrefDDREna = disabled + * VrefDDRSleepMode = inactive (no pulldown) + */ + INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00), + /* + * VextSupply1Regu = HW control + * VextSupply2Regu = HW control + * VextSupply3Regu = HW control + * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 + * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 + */ + INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a), + /* + * Vaux1Regu = force HP + * Vaux2Regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01), + /* + * Vaux3regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00), + /* + * Vsmps1 = 1.15V + */ + INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24), + /* + * Vaux1Sel = 2.5 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08), + /* + * Vaux2Sel = 2.9 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d), + /* + * Vaux3Sel = 2.91 V + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07), + /* + * VextSupply12LP = disabled (no LP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00), + /* + * Vaux1Disch = short discharge time + * Vaux2Disch = short discharge time + * Vaux3Disch = short discharge time + * Vintcore12Disch = short discharge time + * VTVoutDisch = short discharge time + * VaudioDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00), + /* + * VanaDisch = short discharge time + * VdmicPullDownEna = pulldown disabled when Vdmic is disabled + * VdmicDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00), +}; + /* AB8500 regulators */ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { /* supplies to the display/camera */ [AB8500_LDO_AUX1] = { .constraints = { .name = "V-DISPLAY", .min_uV = 2500000, .max_uV = 2900000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, /* must be on for display */ }, .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), .consumer_supplies = ab8500_vaux1_consumers, }, /* supplies to the on-board eMMC */ [AB8500_LDO_AUX2] = { .constraints = { .name = "V-eMMC1", .min_uV = 1100000, .max_uV = 3300000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 2675fae..9499215 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -5,15 +5,18 @@ * * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson * * MOP500 board specific initialization for regulators */ #ifndef __BOARD_MOP500_REGULATORS_H #define __BOARD_MOP500_REGULATORS_H #include <linux/regulator/machine.h> #include <linux/regulator/ab8500.h> +extern struct ab8500_regulator_reg_init +ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; +extern struct regulator_init_data tps61052_regulator; #endif diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 8790d984..dc8746d 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -11,70 +11,107 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/i2c.h> #include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/pl022.h> #include <linux/amba/serial.h> #include <linux/spi/spi.h> #include <linux/mfd/ab8500.h> +#include <linux/regulator/ab8500.h> #include <linux/mfd/tc3589x.h> +#include <linux/mfd/tps6105x.h> +#include <linux/mfd/ab8500/gpio.h> #include <linux/leds-lp5521.h> #include <linux/input.h> #include <linux/gpio_keys.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <plat/i2c.h> #include <plat/ste_dma40.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> #include <mach/irqs.h> #include "ste-dma40-db8500.h" #include "devices-db8500.h" #include "board-mop500.h" #include "board-mop500-regulators.h" +static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { + .gpio_base = MOP500_AB8500_GPIO(0), + .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, + /* config_reg is the initial configuration of ab8500 pins. + * The pins can be configured as GPIO or alt functions based + * on value present in GpioSel1 to GpioSel6 and AlternatFunction + * register. This is the array of 7 configuration settings. + * One has to compile time decide these settings. Below is the + * explaination of these setting + * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO + * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO + * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO + * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO + * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO + * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO + * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured + * as GPIO then this register selectes the alternate fucntions + */ + .config_reg = {0x00, 0x1E, 0x80, 0x01, + 0x7A, 0x00, 0x00}, +}; + static struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, + .regulator_reg_init = ab8500_regulator_reg_init, + .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init), .regulator = ab8500_regulators, .num_regulator = ARRAY_SIZE(ab8500_regulators), + .gpio = &ab8500_gpio_pdata, }; static struct resource ab8500_resources[] = { [0] = { .start = IRQ_DB8500_AB8500, .end = IRQ_DB8500_AB8500, .flags = IORESOURCE_IRQ } }; struct platform_device ab8500_device = { .name = "ab8500-i2c", .id = 0, .dev = { .platform_data = &ab8500_platdata, }, .num_resources = 1, .resource = ab8500_resources, }; /* + * TPS61052 + */ + +static struct tps6105x_platform_data mop500_tps61052_data = { + .mode = TPS6105X_MODE_VOLTAGE, + .regulator_data = &tps61052_regulator, +}; + +/* * TC35892 */ static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) { mop500_sdi_tc35892_init(); } static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { .gpio_base = MOP500_EGPIO(0), .setup = mop500_tc35892_init, }; @@ -126,32 +163,40 @@ static struct lp5521_led_config lp5521_sec_led[] = { .led_current = 0x2f, .max_current = 0x5f, }, }; static struct lp5521_platform_data __initdata lp5521_sec_data = { .label = "lp5521_sec", .led_config = &lp5521_sec_led[0], .num_channels = 3, .clock_mode = LP5521_CLOCK_EXT, }; -static struct i2c_board_info mop500_i2c0_devices[] = { +static struct i2c_board_info __initdata mop500_i2c0_devices[] = { { I2C_BOARD_INFO("tc3589x", 0x42), .irq = NOMADIK_GPIO_TO_IRQ(217), .platform_data = &mop500_tc35892_data, }, }; +/* I2C0 devices only available prior to HREFv60 */ +static struct i2c_board_info __initdata mop500_i2c0_old_devices[] = { + { + I2C_BOARD_INFO("tps61052", 0x33), + .platform_data = &mop500_tps61052_data, + }, +}; + static struct i2c_board_info __initdata mop500_i2c2_devices[] = { { /* lp5521 LED driver, 1st device */ I2C_BOARD_INFO("lp5521", 0x33), .platform_data = &lp5521_pri_data, }, { /* lp5521 LED driver, 2st device */ I2C_BOARD_INFO("lp5521", 0x34), .platform_data = &lp5521_sec_data, }, { @@ -396,24 +441,27 @@ static void __init mop500_init_machine(void) platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); mop500_i2c_init(); mop500_sdi_init(); mop500_spi_init(); mop500_uart_init(); platform_device_register(&ab8500_device); i2c_register_board_info(0, mop500_i2c0_devices, ARRAY_SIZE(mop500_i2c0_devices)); + if (!machine_is_hrefv60()) + i2c_register_board_info(0, mop500_i2c0_old_devices, + ARRAY_SIZE(mop500_i2c0_old_devices)); i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ .boot_params = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ .timer = &ux500_timer, .init_machine = mop500_init_machine, diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 56722f4..03a31cc 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -18,24 +18,28 @@ #define HREFV60_ACCEL_INT2_GPIO 83 #define HREFV60_MAGNET_DRDY_GPIO 32 #define HREFV60_DISP1_RST_GPIO 65 #define HREFV60_DISP2_RST_GPIO 66 /* GPIOs on the TC35892 expander */ #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) #define GPIO_SDMMC_CD MOP500_EGPIO(3) #define GPIO_PROX_SENSOR MOP500_EGPIO(7) #define GPIO_BU21013_CS MOP500_EGPIO(13) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) +#define MOP500_EGPIO_END MOP500_EGPIO(24) + +/* GPIOs on the AB8500 mixed-signals circuit */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) struct i2c_board_info; extern void mop500_sdi_init(void); extern void mop500_sdi_tc35892_init(void); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); void __init mop500_pins_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, unsigned n); diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index 7cdeb2a..97ef55f 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -26,22 +26,33 @@ #define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END #define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ + MOP500_EGPIO_NR_IRQS) /* STMPE1601 irqs */ #define STMPE_NR_INTERNAL_IRQS 9 #define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) #define STMPE_NR_GPIOS 24 #define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) #define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END #define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) -#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) +#define MOP500_STMPE1601_IRQ_END \ + MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) -#define MOP500_IRQ_END MOP500_NR_IRQS +/* AB8500 virtual gpio IRQ */ +#define AB8500_VIR_GPIO_NR_IRQS 16 + +#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \ + MOP500_STMPE1601_IRQ_END +#define MOP500_AB8500_VIR_GPIO_IRQ_END \ + (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS) + +#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END + +#define MOP500_IRQ_END MOP500_NR_IRQS #if MOP500_IRQ_END > IRQ_BOARD_END #undef IRQ_BOARD_END #define IRQ_BOARD_END MOP500_IRQ_END #endif #endif diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index e1296a7..6b86416 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c @@ -81,26 +81,25 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data) virt_irq); if (virt_irq != 0) generic_handle_irq(virt_irq); pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq); return IRQ_HANDLED; } static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) { - set_irq_chip(irq, modem_irq_chip); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); pr_debug("modem_irq: Created virtual IRQ %d\n", irq); } static int modem_irq_init(void) { int err; static struct irq_chip modem_irq_chip; struct modem_irq *mi; if (!cpu_is_u5500()) diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index eb7ffa0..96e59e3 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -305,25 +305,25 @@ unsigned int mmc_status(struct device *dev) mask = 2; return readl(VERSATILE_SYSMCI) & mask; } static struct mmci_platform_data mmc0_plat_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .status = mmc_status, .gpio_wp = -1, .gpio_cd = -1, }; -static struct resource char_lcd_resources[] = { +static struct resource chalcd_resources[] = { { .start = VERSATILE_CHAR_LCD_BASE, .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), .flags = IORESOURCE_MEM, }, }; static struct platform_device char_lcd_device = { .name = "arm-charlcd", .id = -1, .num_resources = ARRAY_SIZE(char_lcd_resources), .resource = char_lcd_resources, diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 5f4ddde..245140c 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c @@ -88,33 +88,33 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) base = sic_regbase; irq -= 64; } dctr = readb(base + VT8500_IC_DCTR + irq); dctr &= ~VT8500_EDGE; switch (flow_type) { case IRQF_TRIGGER_LOW: return -EINVAL; case IRQF_TRIGGER_HIGH: dctr |= VT8500_TRIGGER_HIGH; - irq_desc[orig_irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(orig_irq, handle_level_irq); break; case IRQF_TRIGGER_FALLING: dctr |= VT8500_TRIGGER_FALLING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; case IRQF_TRIGGER_RISING: dctr |= VT8500_TRIGGER_RISING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; } writeb(dctr, base + VT8500_IC_DCTR + irq); return 0; } static struct irq_chip vt8500_irq_chip = { .name = "vt8500", .ack = vt8500_irq_mask, .mask = vt8500_irq_mask, .unmask = vt8500_irq_unmask, @@ -127,26 +127,26 @@ void __init vt8500_init_irq(void) ic_regbase = ioremap(wmt_ic_base, SZ_64K); if (ic_regbase) { /* Enable rotating priority for IRQ */ writel((1 << 6), ic_regbase + 0x20); writel(0, ic_regbase + 0x24); for (i = 0; i < wmt_nr_irqs; i++) { /* Disable all interrupts and route them to IRQ */ writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); } } void __init wm8505_init_irq(void) { unsigned int i; ic_regbase = ioremap(wmt_ic_base, SZ_64K); @@ -158,20 +158,20 @@ void __init wm8505_init_irq(void) writel(0, ic_regbase + 0x24); writel((1 << 6), sic_regbase + 0x20); writel(0, sic_regbase + 0x24); for (i = 0; i < wmt_nr_irqs; i++) { /* Disable all interrupts and route them to IRQ */ if (i < 64) writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); else writeb(0x00, sic_regbase + VT8500_IC_DCTR + i - 64); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); } } diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 9c35010..7bf143c 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -198,17 +198,17 @@ static struct irq_chip nuc900_irq_chip = { .irq_ack = nuc900_irq_ack, .irq_mask = nuc900_irq_mask, .irq_unmask = nuc900_irq_unmask, }; void __init nuc900_init_irq(void) { int irqno; __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { - set_irq_chip(irqno, &nuc900_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc900_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index c856fa3..f0ba072 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -91,32 +91,27 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) u32 imr_val; u32 int_valid; u32 expio_irq; /* irq = gpio irq number */ desc->irq_data.chip->irq_mask(&desc->irq_data); imr_val = __raw_readw(brd_io + INTR_MASK_REG); int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; expio_irq = MXC_BOARD_IRQ_START; for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - struct irq_desc *d; if ((int_valid & 1) == 0) continue; - d = irq_desc + expio_irq; - if (unlikely(!(d->handle_irq))) - pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); - else - d->handle_irq(expio_irq, d); + generic_handle_irq(expio_irq); } desc->irq_data.chip->irq_ack(&desc->irq_data); desc->irq_data.chip->irq_unmask(&desc->irq_data); } /* * Disable an expio pin's interrupt by setting the bit in the imr. * Irq is an expio virtual irq number */ static void expio_mask_irq(struct irq_data *d) { @@ -177,26 +172,25 @@ int __init mxc_expio_init(u32 base, u32 p_irq) * Configure INT line as GPIO input */ gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq"); gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq)); /* disable the interrupt and clear the status */ __raw_writew(0, brd_io + INTR_MASK_REG); __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); __raw_writew(0, brd_io + INTR_RESET_REG); __raw_writew(0x1F, brd_io + INTR_MASK_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(p_irq, IRQF_TRIGGER_LOW); - set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); + irq_set_chained_handler(p_irq, mxc_expio_irq_handler); /* Register Lan device on the debugboard */ smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; platform_device_register(&smsc_lan9217_device); return 0; } diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index deb284b..09e2bd0 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -130,26 +130,26 @@ void __init mxc_init_irq(void __iomem *irqbase) */ __raw_writel(0, avic_base + AVIC_INTCNTL); __raw_writel(0x1f, avic_base + AVIC_NIMASK); /* disable all interrupts */ __raw_writel(0, avic_base + AVIC_INTENABLEH); __raw_writel(0, avic_base + AVIC_INTENABLEL); /* all IRQ no FIQ */ __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_avic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); #endif diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 57d5985..7a10724 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -166,38 +166,38 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) mxc_flip_edge(port, irqoffset); generic_handle_irq(gpio_irq_no_base + irqoffset); irq_stat &= ~(1 << irqoffset); } } /* MX1 and MX3 has one interrupt *per* gpio port */ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); mxc_gpio_irq_handler(port, irq_stat); } /* MX2 has one interrupt *for all* gpio ports */ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { irq_msk = __raw_readl(port[i].base + GPIO_IMR); if (!irq_msk) continue; irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk; if (irq_stat) mxc_gpio_irq_handler(&port[i], irq_stat); } } @@ -302,51 +302,53 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* save for local usage */ mxc_gpio_ports = port; gpio_table_size = cnt; printk(KERN_INFO "MXC GPIO hardware\n"); for (i = 0; i < cnt; i++) { /* disable the interrupt and clear the status */ __raw_writel(0, port[i].base + GPIO_IMR); __raw_writel(~0, port[i].base + GPIO_ISR); for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } /* register gpio chip */ port[i].chip.direction_input = mxc_gpio_direction_input; port[i].chip.direction_output = mxc_gpio_direction_output; port[i].chip.get = mxc_gpio_get; port[i].chip.set = mxc_gpio_set; port[i].chip.base = i * 32; port[i].chip.ngpio = 32; spin_lock_init(&port[i].lock); /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); if (port[i].irq_high) { /* setup handler for GPIO 16 to 31 */ - set_irq_chained_handler(port[i].irq_high, - mx3_gpio_irq_handler); - set_irq_data(port[i].irq_high, &port[i]); + irq_set_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq_high, + &port[i]); } } } if (cpu_is_mx2()) { /* setup one handler for all GPIO interrupts */ - set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); - set_irq_data(port[0].irq, port); + irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); + irq_set_handler_data(port[0].irq, port); } return 0; } diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 0c799ac..e1c6eff 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c @@ -20,41 +20,41 @@ #include <linux/irq.h> #include "irq-common.h" int imx_irq_set_priority(unsigned char irq, unsigned char prio) { struct mxc_irq_chip *chip; struct irq_chip *base; int ret; ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_priority) ret = chip->set_priority(irq, prio); } return ret; } EXPORT_SYMBOL(imx_irq_set_priority); int mxc_set_irq_fiq(unsigned int irq, unsigned int type) { struct mxc_irq_chip *chip; struct irq_chip *base; int ret; ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_irq_fiq) ret = chip->set_irq_fiq(irq, type); } return ret; } EXPORT_SYMBOL(mxc_set_irq_fiq); diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index bc3a6be..57f9395 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -158,26 +158,26 @@ void __init tzic_init_irq(void __iomem *irqbase) __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); for (i = 0; i < 4; i++) __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); /* disable all interrupts */ for (i = 0; i < 4; i++) __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); /* all IRQ no FIQ Warning :: No selection */ for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_tzic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_tzic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); #endif pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } /** diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 80643bc..f49748e 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -45,24 +45,25 @@ struct nmk_gpio_chip { unsigned int parent_irq; int secondary_parent_irq; u32 (*get_secondary_status)(unsigned int bank); void (*set_ioforce)(bool enable); spinlock_t lock; /* Keep track of configured edges */ u32 edge_rising; u32 edge_falling; u32 real_wake; u32 rwimsc; u32 fwimsc; u32 slpm; + u32 enabled; }; static struct nmk_gpio_chip * nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, unsigned offset, int gpio_mode) { @@ -309,25 +310,25 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); } nmk_gpio_glitch_slpm_init(slpm); } for (i = 0; i < num; i++) { struct nmk_gpio_chip *nmk_chip; int pin = PIN_NUM(cfgs[i]); - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); if (!nmk_chip) { ret = -EINVAL; break; } spin_lock(&nmk_chip->lock); __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, cfgs[i], sleep, glitch ? slpm : NULL); spin_unlock(&nmk_chip->lock); } if (glitch) @@ -388,25 +389,25 @@ EXPORT_SYMBOL(nmk_config_pins_sleep); * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was * configured even when in sleep and deep sleep. * * On DB8500v2 onwards, this setting loses the previous meaning and instead * indicates if wakeup detection is enabled on the pin. Note that * enable_irq_wake() will automatically enable wakeup detection. */ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) { struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); return 0; @@ -421,25 +422,25 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) * the pin is configured as an input (either explicitly or by the alternate * function). * * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is * configured as an input. Otherwise, due to the way the controller registers * work, this function will change the value output on the pin. */ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) { struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; spin_lock_irqsave(&nmk_chip->lock, flags); __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); spin_unlock_irqrestore(&nmk_chip->lock, flags); return 0; } /* Mode functions */ /** @@ -447,42 +448,42 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) * @gpio: pin number * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C * * Sets the mode of the specified pin to one of the alternate functions or * plain GPIO. */ int nmk_gpio_set_mode(int gpio, int gpio_mode) { struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; spin_lock_irqsave(&nmk_chip->lock, flags); __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); spin_unlock_irqrestore(&nmk_chip->lock, flags); return 0; } EXPORT_SYMBOL(nmk_gpio_set_mode); int nmk_gpio_get_mode(int gpio) { struct nmk_gpio_chip *nmk_chip; u32 afunc, bfunc, bit; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; bit = 1 << (gpio - nmk_chip->chip.base); afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); } EXPORT_SYMBOL(nmk_gpio_get_mode); @@ -532,47 +533,45 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, reg = readl(nmk_chip->addr + fimsc); if (enable) reg |= bitmask; else reg &= ~bitmask; writel(reg, nmk_chip->addr + fimsc); } } static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, int gpio, bool on) { -#ifdef CONFIG_ARCH_U8500 - if (cpu_is_u8500v2()) { - __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, - on ? NMK_GPIO_SLPM_WAKEUP_ENABLE - : NMK_GPIO_SLPM_WAKEUP_DISABLE); - } -#endif __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); } static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) { int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; + if (enable) + nmk_chip->enabled |= bitmask; + else + nmk_chip->enabled &= ~bitmask; + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); if (!(nmk_chip->real_wake & bitmask)) __nmk_gpio_set_wake(nmk_chip, gpio, enable); spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); return 0; @@ -581,75 +580,73 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) static void nmk_gpio_irq_mask(struct irq_data *d) { nmk_gpio_irq_maskunmask(d, false); } static void nmk_gpio_irq_unmask(struct irq_data *d) { nmk_gpio_irq_maskunmask(d, true); } static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; int gpio; gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); if (!nmk_chip) return -EINVAL; bitmask = nmk_gpio_get_bitmask(gpio); spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - if (!enabled) + if (!(nmk_chip->enabled & bitmask)) __nmk_gpio_set_wake(nmk_chip, gpio, on); if (on) nmk_chip->real_wake |= bitmask; else nmk_chip->real_wake &= ~bitmask; spin_unlock(&nmk_chip->lock); spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); return 0; } static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); - bool wake = desc->wake_depth; + bool enabled, wake = irqd_is_wakeup_set(d); int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; gpio = NOMADIK_IRQ_TO_GPIO(d->irq); nmk_chip = irq_data_get_irq_chip_data(d); bitmask = nmk_gpio_get_bitmask(gpio); if (!nmk_chip) return -EINVAL; if (type & IRQ_TYPE_LEVEL_HIGH) return -EINVAL; if (type & IRQ_TYPE_LEVEL_LOW) return -EINVAL; + enabled = nmk_chip->enabled & bitmask; + spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); if (enabled || wake) __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); nmk_chip->edge_rising &= ~bitmask; if (type & IRQ_TYPE_EDGE_RISING) nmk_chip->edge_rising |= bitmask; @@ -672,85 +669,85 @@ static struct irq_chip nmk_gpio_irq_chip = { .name = "Nomadik-GPIO", .irq_ack = nmk_gpio_irq_ack, .irq_mask = nmk_gpio_irq_mask, .irq_unmask = nmk_gpio_irq_unmask, .irq_set_type = nmk_gpio_irq_set_type, .irq_set_wake = nmk_gpio_irq_set_wake, }; static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { struct nmk_gpio_chip *nmk_chip; - struct irq_chip *host_chip = get_irq_chip(irq); + struct irq_chip *host_chip = irq_get_chip(irq); unsigned int first_irq; if (host_chip->irq_mask_ack) host_chip->irq_mask_ack(&desc->irq_data); else { host_chip->irq_mask(&desc->irq_data); if (host_chip->irq_ack) host_chip->irq_ack(&desc->irq_data); } - nmk_chip = get_irq_data(irq); + nmk_chip = irq_get_handler_data(irq); first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); while (status) { int bit = __ffs(status); generic_handle_irq(first_irq + bit); status &= ~BIT(bit); } host_chip->irq_unmask(&desc->irq_data); } static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); __nmk_gpio_irq_handler(irq, desc, status); } static void nmk_gpio_secondary_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); __nmk_gpio_irq_handler(irq, desc, status); } static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) { unsigned int first_irq; int i; first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { - set_irq_chip(i, &nmk_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); - set_irq_chip_data(i, nmk_chip); - set_irq_type(i, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(i, nmk_chip); + irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); } - set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); - set_irq_data(nmk_chip->parent_irq, nmk_chip); + irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); + irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); if (nmk_chip->secondary_parent_irq >= 0) { - set_irq_chained_handler(nmk_chip->secondary_parent_irq, + irq_set_chained_handler(nmk_chip->secondary_parent_irq, nmk_gpio_secondary_irq_handler); - set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); + irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); } return 0; } /* I/O Functions */ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) { struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); diff --git a/arch/arm/plat-omap/gpio.c b/arch/ar |