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authorThomas Zimmermann <tzimmermann@suse.de>2019-02-18 10:33:27 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-02-18 10:33:27 +0100
commit05e95ea86e3b231de493c1e6cacd8204870b6c13 (patch)
treee6dac0da4659a380bc66673d6b2acbca91261127
parentcfbcea74765d32e1a626094b41d87ac9e88680e0 (diff)
gpu: ipu-v3: Fix i.MX51 CSI control registers offset (bsc#1106929)
-rw-r--r--patches.fixes/0001-gpu-ipu-v3-Fix-i.MX51-CSI-control-registers-offset.patch39
-rw-r--r--series.conf1
2 files changed, 40 insertions, 0 deletions
diff --git a/patches.fixes/0001-gpu-ipu-v3-Fix-i.MX51-CSI-control-registers-offset.patch b/patches.fixes/0001-gpu-ipu-v3-Fix-i.MX51-CSI-control-registers-offset.patch
new file mode 100644
index 0000000000..1dd626eba6
--- /dev/null
+++ b/patches.fixes/0001-gpu-ipu-v3-Fix-i.MX51-CSI-control-registers-offset.patch
@@ -0,0 +1,39 @@
+From 2c0408dd0d8906b26fe8023889af7adf5e68b2c2 Mon Sep 17 00:00:00 2001
+From: Alexander Shiyan <shc_work@mail.ru>
+Date: Thu, 20 Dec 2018 11:06:38 +0300
+Subject: gpu: ipu-v3: Fix i.MX51 CSI control registers offset
+Git-commit: 2c0408dd0d8906b26fe8023889af7adf5e68b2c2
+Patch-mainline: v5.0-rc7
+References: bsc#1106929
+
+The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
+to the control module registers on IPUv3EX.
+This patch fixes wrong values for i.MX51 CSI0/CSI1.
+
+Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")
+
+Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/ipu-v3/ipu-common.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
+index 474b00e19697..5b7cdbfe062f 100644
+--- a/drivers/gpu/ipu-v3/ipu-common.c
++++ b/drivers/gpu/ipu-v3/ipu-common.c
+@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = {
+ .cpmem_ofs = 0x1f000000,
+ .srm_ofs = 0x1f040000,
+ .tpm_ofs = 0x1f060000,
+- .csi0_ofs = 0x1f030000,
+- .csi1_ofs = 0x1f038000,
++ .csi0_ofs = 0x1e030000,
++ .csi1_ofs = 0x1e038000,
+ .ic_ofs = 0x1e020000,
+ .disp0_ofs = 0x1e040000,
+ .disp1_ofs = 0x1e048000,
+--
+2.20.1
+
diff --git a/series.conf b/series.conf
index 94a12893fe..a816f04177 100644
--- a/series.conf
+++ b/series.conf
@@ -24258,6 +24258,7 @@
patches.arch/kvm-nvmx-unconditionally-cancel-preemption-timer-in-free_nested-cve-2019-7221
patches.fixes/0001-drm-vmwgfx-Return-error-code-from-vmw_execbuf_copy_f.patch
patches.fixes/0001-drm-vmwgfx-Fix-setting-of-dma-masks.patch
+ patches.fixes/0001-gpu-ipu-v3-Fix-i.MX51-CSI-control-registers-offset.patch
# mkp/scsi 5.0/scsi-fixes
patches.fixes/scsi-target-make-the-pi_prot_format-ConfigFS-path-re.patch