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authorMian Yousaf Kaukab <yousaf.kaukab@suse.com>2019-08-08 12:22:02 +0200
committerMian Yousaf Kaukab <yousaf.kaukab@suse.com>2019-08-08 12:22:16 +0200
commit175228747bc5fba0506f65b72aede47c1ffc726f (patch)
treefd885d94bcb9a127db63266486b94afb99059381
parent528d360fb0ee3ebb1642805b0e7f7b5f3aaddf59 (diff)
clk: rockchip: assign correct id for pclk_ddr and hclk_sd in
rk3399 (bsc#1144718,bsc#1144813).
-rw-r--r--patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch49
-rw-r--r--series.conf1
2 files changed, 50 insertions, 0 deletions
diff --git a/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch b/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
new file mode 100644
index 0000000000..e3fea783eb
--- /dev/null
+++ b/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
@@ -0,0 +1,49 @@
+From: Lin Huang <hl@rock-chips.com>
+Date: Tue, 20 Mar 2018 10:06:28 +0800
+Subject: clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
+
+Git-commit: 9dc486fdf6cc0d7f635954810ab119c5db2cbb60
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
+and these two PLL may change their frequency. If we do not
+assign right id to pclk_ddr and hclk_sd, they will alway use
+default cur register value, and may get the frequency
+exceed their signed off frequency. So assign correct Id
+for them, then we can assign frequency for them in dts.
+
+Signed-off-by: Lin Huang <hl@rock-chips.com>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/rockchip/clk-rk3399.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 3e57c6eef93d..bca10d618f0a 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ RK3399_CLKGATE_CON(9), 7, GFLAGS,
+ &rk3399_uart3_fracmux),
+
+- COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
++ COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3399_CLKGATE_CON(3), 4, GFLAGS),
+
+@@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ RK3399_CLKGATE_CON(31), 8, GFLAGS),
+
+ /* sdio & sdmmc */
+- COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
++ COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+ RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3399_CLKGATE_CON(12), 13, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
+--
+2.11.0
+
diff --git a/series.conf b/series.conf
index ebfad42021..22b533272f 100644
--- a/series.conf
+++ b/series.conf
@@ -15757,6 +15757,7 @@
patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
+ patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
patches.drivers/firmware-dmi_scan-Fix-UUID-length-safety-check
patches.drivers/thermal-imx-Fix-race-condition-in-imx_thermal_probe