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authorMichal Kubecek <mkubecek@suse.cz>2019-10-02 07:41:27 +0200
committerMichal Kubecek <mkubecek@suse.cz>2019-10-02 07:41:27 +0200
commit38ccfdfb250459d541431ddb2a25315480a6f9be (patch)
tree5000e42d76c3442e6a9bda9b9eb618209ee18012
parent035ce9b6a8a7d73a71cbd228c0e3911fc461c704 (diff)
parent075db4dccaf450f0b20a0022401430347ee4a075 (diff)
Merge branch 'users/ykaukab/SLE15-SP2/for-next' into SLE15-SP2rpm-5.3.1-2--SLE-15-SP2-Packages-Alpha4rpm-5.3.1-2
Pull PCI fixes and SP1 patches cleanup from Mian Yousaf Kaukab.
-rw-r--r--config/arm64/default10
-rw-r--r--patches.suse/0001-irqchip-gic-v3-its-fix-build-warnings.patch61
-rw-r--r--patches.suse/0001-mmc-sdhci-add-delay-after-the-last-tuning-command.patch53
-rw-r--r--patches.suse/0002-PCI-mobiveil-uniform-the-register-accessors.patch261
-rw-r--r--patches.suse/0002-mmc-sdhci-correct-the-maximum-timeout-when-enable-CM.patch53
-rw-r--r--patches.suse/0003-PCI-mobiveil-format-the-code-without-function-change.patch598
-rw-r--r--patches.suse/0004-PCI-mobiveil-correct-the-returned-error-number.patch57
-rw-r--r--patches.suse/0005-PCI-mobiveil-remove-flag-MSI_FLAG_MULTI_PCI_MSI.patch35
-rw-r--r--patches.suse/0006-PCI-mobiveil-correct-PCI-base-address-in-MEM-IO-outb.patch42
-rw-r--r--patches.suse/0007-PCI-mobiveil-replace-the-resource-list-iteration-fun.patch46
-rw-r--r--patches.suse/0008-PCI-mobiveil-use-WIN_NUM_0-explicitly-for-CFG-outbou.patch40
-rw-r--r--patches.suse/0009-PCI-mobiveil-use-the-1st-inbound-window-for-MEM-inbo.patch36
-rw-r--r--patches.suse/0010-PCI-mobiveil-correct-inbound-outbound-window-setup-r.patch198
-rw-r--r--patches.suse/0011-PCI-mobiveil-fix-the-INTx-process-error.patch63
-rw-r--r--patches.suse/0012-PCI-mobiveil-only-fix-up-the-Class-Code-field.patch52
-rw-r--r--patches.suse/0013-PCI-mobiveil-move-out-the-link-up-waiting-from-mobiv.patch65
-rw-r--r--patches.suse/0014-PCI-mobiveil-move-irq-chained-handler-setup-out-of-D.patch44
-rw-r--r--patches.suse/0015-PCI-mobiveil-initialize-Primary-Secondary-Subordinat.patch40
-rw-r--r--patches.suse/0016-dt-bindings-pci-mobiveil-change-gpio_slave-and-apb_c.patch41
-rw-r--r--patches.suse/0018-PCI-mobiveil-fix-the-checking-of-valid-device.patch50
-rw-r--r--patches.suse/0019-PCI-mobiveil-continue-to-initialize-the-host-upon-no.patch50
-rw-r--r--patches.suse/0020-PCI-mobiveil-disabled-IB-and-OB-windows-set-by-bootl.patch82
-rw-r--r--patches.suse/0023-dt-bindings-pci-Add-NXP-Layerscape-SoCs-PCIe-Gen4-co.patch100
-rw-r--r--patches.suse/0025-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch164
-rw-r--r--patches.suse/0026-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011451.patch84
-rw-r--r--patches.suse/PCI-Add-ACS-quirk-for-Amazon-Annapurna-Labs-root-por.patch65
-rw-r--r--patches.suse/PCI-Add-Amazon-s-Annapurna-Labs-vendor-ID.patch35
-rw-r--r--patches.suse/PCI-Add-quirk-to-disable-MSI-X-support-for-Amazon-s-.patch102
-rw-r--r--patches.suse/PCI-VPD-Prevent-VPD-access-for-Amazon-s-Annapurna-La.patch46
-rw-r--r--patches.suse/PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch (renamed from patches.suse/0021-PCI-mobiveil-add-Byte-and-Half-Word-width-register-a.patch)27
-rw-r--r--patches.suse/PCI-mobiveil-Add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch (renamed from patches.suse/0024-PCI-mobiveil-add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch)202
-rw-r--r--patches.suse/PCI-mobiveil-Fix-the-CPU-base-address-setup-in-inbou.patch75
-rw-r--r--patches.suse/PCI-mobiveil-Make-mobiveil_host_init-can-be-used-to-.patch (renamed from patches.suse/0022-PCI-mobiveil-make-mobiveil_host_init-can-be-used-to-.patch)62
-rw-r--r--patches.suse/PCI-mobiveil-Refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch (renamed from patches.suse/0017-PCI-mobiveil-refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch)1167
-rw-r--r--series.conf38
35 files changed, 1558 insertions, 2586 deletions
diff --git a/config/arm64/default b/config/arm64/default
index e8a0b7ec84..ae59384728 100644
--- a/config/arm64/default
+++ b/config/arm64/default
@@ -1994,7 +1994,6 @@ CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=m
CONFIG_PCIE_ROCKCHIP_EP=y
CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_MOBIVEIL=y
#
# DesignWare PCI Core Support
@@ -2014,6 +2013,15 @@ CONFIG_PCIE_ARMADA_8K=y
# CONFIG_PCIE_HISI_STB is not set
CONFIG_PCI_MESON=y
# end of DesignWare PCI Core Support
+
+#
+# Mobiveil PCIe Core Support
+#
+CONFIG_PCIE_MOBIVEIL=y
+CONFIG_PCIE_MOBIVEIL_HOST=y
+CONFIG_PCIE_MOBIVEIL_PLAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+# end of Mobiveil PCIe Core Support
# end of PCI controller drivers
#
diff --git a/patches.suse/0001-irqchip-gic-v3-its-fix-build-warnings.patch b/patches.suse/0001-irqchip-gic-v3-its-fix-build-warnings.patch
deleted file mode 100644
index d5791326f4..0000000000
--- a/patches.suse/0001-irqchip-gic-v3-its-fix-build-warnings.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From fdcd2a57f4dba25d1a0bb5c8b4f36c1f7f949137 Mon Sep 17 00:00:00 2001
-From: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
-Date: Thu, 8 Aug 2019 15:04:08 +0200
-Subject: [PATCH] irqchip/gic-v3-its: fix build warnings
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Patch-mainline: Never, Build warnings due to missing patch
-References: bsc#1144880
-
-Following warnings are fixed:
-drivers/irqchip/irq-gic-v3-its.c: In function ‘its_irq_domain_activate’:
-drivers/irqchip/irq-gic-v3-its.c:2323:11: warning: ‘return’ with a value, in function returning void
- return -EINVAL;
- ^
-drivers/irqchip/irq-gic-v3-its.c:2307:13: note: declared here
- static void its_irq_domain_activate(struct irq_domain *domain,
- ^~~~~~~~~~~~~~~~~~~~~~~
- LD drivers/net/ethernet/allwinner/built-in.o
-drivers/irqchip/irq-gic-v3-its.c: In function ‘its_vpe_irq_domain_activate’:
-drivers/irqchip/irq-gic-v3-its.c:2838:10: warning: ‘return’ with a value, in function returning void
- return 0;
- ^
-drivers/irqchip/irq-gic-v3-its.c:2830:13: note: declared here
- static void its_vpe_irq_domain_activate(struct irq_domain *domain,
-
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/irqchip/irq-gic-v3-its.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
-index fbda05bbd9ee..03ace8f3ac65 100644
---- a/drivers/irqchip/irq-gic-v3-its.c
-+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -2319,8 +2319,10 @@ static void its_irq_domain_activate(struct irq_domain *domain,
- /* Bind the LPI to the first possible CPU */
- cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
- if (cpu >= nr_cpu_ids) {
-- if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
-- return -EINVAL;
-+ if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
-+ pr_err("ITS: Can't bind LPI to non-local node CPU due to Cavium erratum 23144\n");
-+ return;
-+ }
-
- cpu = cpumask_first(cpu_online_mask);
- }
-@@ -2835,7 +2837,7 @@ static void its_vpe_irq_domain_activate(struct irq_domain *domain,
-
- /* If we use the list map, we issue VMAPP on demand... */
- if (its_list_map)
-- return 0;
-+ return;
-
- /* Map the VPE to the first possible CPU */
- vpe->col_idx = cpumask_first(cpu_online_mask);
---
-2.11.0
-
diff --git a/patches.suse/0001-mmc-sdhci-add-delay-after-the-last-tuning-command.patch b/patches.suse/0001-mmc-sdhci-add-delay-after-the-last-tuning-command.patch
deleted file mode 100644
index 594e3cda09..0000000000
--- a/patches.suse/0001-mmc-sdhci-add-delay-after-the-last-tuning-command.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From: BOUGH CHEN <haibo.chen@nxp.com>
-Date: Fri, 28 Dec 2018 08:35:49 +0000
-Subject: mmc: sdhci: add delay after the last tuning command
-
-Git-commit: 920ce03ed27541029f2322d05177457ea473973d
-Patch-mainline: Queued
-Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
-References: bsc#1123999
-
-When host set the host->tuning_delay, even the last tuning
-command need a delay, otherwise the first command after the
-tuning will meet issue.
-
-Take i.MX7D as an example, there will be the following log:
- mmc2: switch to high-speed from hs200 failed, err:-110
- mmc2: error -110 whilst initialising MMC card
-
-Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/mmc/host/sdhci.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
-index eba9bcc92ad3..283dab5fc8d4 100644
---- a/drivers/mmc/host/sdhci.c
-+++ b/drivers/mmc/host/sdhci.c
-@@ -2376,6 +2376,10 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
- return -ETIMEDOUT;
- }
-
-+ /* Spec does not require a delay between tuning cycles */
-+ if (host->tuning_delay > 0)
-+ mdelay(host->tuning_delay);
-+
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
- if (ctrl & SDHCI_CTRL_TUNED_CLK)
-@@ -2383,9 +2387,6 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
- break;
- }
-
-- /* Spec does not require a delay between tuning cycles */
-- if (host->tuning_delay > 0)
-- mdelay(host->tuning_delay);
- }
-
- pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
---
-2.11.0
-
diff --git a/patches.suse/0002-PCI-mobiveil-uniform-the-register-accessors.patch b/patches.suse/0002-PCI-mobiveil-uniform-the-register-accessors.patch
deleted file mode 100644
index 936565b828..0000000000
--- a/patches.suse/0002-PCI-mobiveil-uniform-the-register-accessors.patch
+++ /dev/null
@@ -1,261 +0,0 @@
-From d18d0dd5e43b0486cb5ba8e0f48d9307906a2389 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:08:34 +0000
-Subject: [PATCH 02/26] PCI: mobiveil: uniform the register accessors
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-It's confused that R/W some registers by csr_readl()/csr_writel(),
-while others by read_paged_register()/write_paged_register().
-Actually the low 3KB of 4KB PCIe configure space can be accessed
-directly and high 1KB is paging area. So this patch uniformed the
-register accessors to csr_readl() and csr_writel() by comparing
-the register offset with page access boundary 3KB in the accessor
-internal.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 179 +++++++++++++++++++++++++++------------
- 1 file changed, 124 insertions(+), 55 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 19541ad27fb2..6194ef10e4eb 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -47,7 +47,6 @@
- #define PAGE_SEL_SHIFT 13
- #define PAGE_SEL_MASK 0x3f
- #define PAGE_LO_MASK 0x3ff
--#define PAGE_SEL_EN 0xc00
- #define PAGE_SEL_OFFSET_SHIFT 10
-
- #define PAB_AXI_PIO_CTRL 0x0840
-@@ -117,6 +116,12 @@
- #define LINK_WAIT_MIN 90000
- #define LINK_WAIT_MAX 100000
-
-+#define PAGED_ADDR_BNDRY 0xc00
-+#define OFFSET_TO_PAGE_ADDR(off) \
-+ ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
-+#define OFFSET_TO_PAGE_IDX(off) \
-+ ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
-+
- struct mobiveil_msi { /* MSI information */
- struct mutex lock; /* protect bitmap variable */
- struct irq_domain *msi_domain;
-@@ -145,15 +150,119 @@ struct mobiveil_pcie {
- struct mobiveil_msi msi;
- };
-
--static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
-- const u32 reg)
-+/*
-+ * mobiveil_pcie_sel_page - routine to access paged register
-+ *
-+ * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
-+ * for this scheme to work extracted higher 6 bits of the offset will be
-+ * written to pg_sel field of PAB_CTRL register and rest of the lower 10
-+ * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
-+ */
-+static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
- {
-- writel_relaxed(value, pcie->csr_axi_slave_base + reg);
-+ u32 val;
-+
-+ val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
-+ val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
-+ val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
-+
-+ writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
- }
-
--static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
-+static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
- {
-- return readl_relaxed(pcie->csr_axi_slave_base + reg);
-+ if (off < PAGED_ADDR_BNDRY) {
-+ /* For directly accessed registers, clear the pg_sel field */
-+ mobiveil_pcie_sel_page(pcie, 0);
-+ return pcie->csr_axi_slave_base + off;
-+ }
-+
-+ mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
-+ return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
-+}
-+
-+static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
-+{
-+ if ((uintptr_t)addr & (size - 1)) {
-+ *val = 0;
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ switch (size) {
-+ case 4:
-+ *val = readl(addr);
-+ break;
-+ case 2:
-+ *val = readw(addr);
-+ break;
-+ case 1:
-+ *val = readb(addr);
-+ break;
-+ default:
-+ *val = 0;
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
-+{
-+ if ((uintptr_t)addr & (size - 1))
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ switch (size) {
-+ case 4:
-+ writel(val, addr);
-+ break;
-+ case 2:
-+ writew(val, addr);
-+ break;
-+ case 1:
-+ writeb(val, addr);
-+ break;
-+ default:
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
-+{
-+ void *addr;
-+ u32 val;
-+ int ret;
-+
-+ addr = mobiveil_pcie_comp_addr(pcie, off);
-+
-+ ret = mobiveil_pcie_read(addr, size, &val);
-+ if (ret)
-+ dev_err(&pcie->pdev->dev, "read CSR address failed\n");
-+
-+ return val;
-+}
-+
-+static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
-+{
-+ void *addr;
-+ int ret;
-+
-+ addr = mobiveil_pcie_comp_addr(pcie, off);
-+
-+ ret = mobiveil_pcie_write(addr, size, val);
-+ if (ret)
-+ dev_err(&pcie->pdev->dev, "write CSR address failed\n");
-+}
-+
-+static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
-+{
-+ return csr_read(pcie, off, 0x4);
-+}
-+
-+static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
-+{
-+ csr_write(pcie, val, off, 0x4);
- }
-
- static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
-@@ -349,45 +458,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
- return 0;
- }
-
--/*
-- * select_paged_register - routine to access paged register of root complex
-- *
-- * registers of RC are paged, for this scheme to work
-- * extracted higher 6 bits of the offset will be written to pg_sel
-- * field of PAB_CTRL register and rest of the lower 10 bits enabled with
-- * PAGE_SEL_EN are used as offset of the register.
-- */
--static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)
--{
-- int pab_ctrl_dw, pg_sel;
--
-- /* clear pg_sel field */
-- pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);
-- pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT));
--
-- /* set pg_sel field */
-- pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK;
-- pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT));
-- csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);
--}
--
--static void write_paged_register(struct mobiveil_pcie *pcie,
-- u32 val, u32 offset)
--{
-- u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
--
-- select_paged_register(pcie, offset);
-- csr_writel(pcie, val, off);
--}
--
--static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)
--{
-- u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
--
-- select_paged_register(pcie, offset);
-- return csr_readl(pcie, off);
--}
--
- static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
- int pci_addr, u32 type, u64 size)
- {
-@@ -404,19 +474,19 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
- pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
- csr_writel(pcie,
- pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
-- amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));
-+ amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
- amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
- amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
-
-- write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),
-- PAB_PEX_AMAP_CTRL(win_num));
-+ csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
-+ PAB_PEX_AMAP_CTRL(win_num));
-
-- write_paged_register(pcie, upper_32_bits(size64),
-- PAB_EXT_PEX_AMAP_SIZEN(win_num));
-+ csr_writel(pcie, upper_32_bits(size64),
-+ PAB_EXT_PEX_AMAP_SIZEN(win_num));
-
-- write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
-- write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
-- write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
-+ csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
-+ csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
-+ csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
- }
-
- /*
-@@ -444,8 +514,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
- csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
- lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
-
-- write_paged_register(pcie, upper_32_bits(size64),
-- PAB_EXT_AXI_AMAP_SIZE(win_num));
-+ csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
-
- /*
- * program AXI window base with appropriate value in
---
-2.11.0
-
diff --git a/patches.suse/0002-mmc-sdhci-correct-the-maximum-timeout-when-enable-CM.patch b/patches.suse/0002-mmc-sdhci-correct-the-maximum-timeout-when-enable-CM.patch
deleted file mode 100644
index 92137a88b1..0000000000
--- a/patches.suse/0002-mmc-sdhci-correct-the-maximum-timeout-when-enable-CM.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From: BOUGH CHEN <haibo.chen@nxp.com>
-Date: Mon, 7 Jan 2019 10:11:36 +0000
-Subject: mmc: sdhci: correct the maximum timeout when enable CMDQ
-
-Git-commit: ac60ee24931a2a79c95d79319087eda5ee1d4639
-Patch-mainline: Queued
-Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
-References: bsc#1123999
-
-Change to use sdhci_set_timeout() to set the maximum timeout, so that
-the host can use it's own set_timeout() callback to set the maximum
-timeout if the host has.
-
-Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/mmc/host/sdhci.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/sdhci.c
-+++ b/drivers/mmc/host/sdhci.c
-@@ -716,7 +716,7 @@ static u32 sdhci_sdma_address(struct sdh
- static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
- {
- u8 count;
-- struct mmc_data *data = cmd->data;
-+ struct mmc_data *data;
- unsigned target_timeout, current_timeout;
-
- /*
-@@ -728,6 +728,11 @@ static u8 sdhci_calc_timeout(struct sdhc
- if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
- return 0xE;
-
-+ /* Unspecified command, asume max */
-+ if (cmd == NULL)
-+ return 0xE;
-+
-+ data = cmd->data;
- /* Unspecified timeout, assume max */
- if (!data && !cmd->busy_timeout)
- return 0xE;
-@@ -3100,7 +3105,7 @@ void sdhci_cqe_enable(struct mmc_host *m
- SDHCI_BLOCK_SIZE);
-
- /* Set maximum timeout */
-- sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
-+ sdhci_set_timeout(host, NULL);
-
- host->ier = host->cqe_ier;
-
diff --git a/patches.suse/0003-PCI-mobiveil-format-the-code-without-function-change.patch b/patches.suse/0003-PCI-mobiveil-format-the-code-without-function-change.patch
deleted file mode 100644
index c94a446c40..0000000000
--- a/patches.suse/0003-PCI-mobiveil-format-the-code-without-function-change.patch
+++ /dev/null
@@ -1,598 +0,0 @@
-From 1fb52646b0c047227417173893b8d51a1bda0820 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:08:40 +0000
-Subject: [PATCH 03/26] PCI: mobiveil: format the code without function change
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Just format the code without functionality change.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 261 ++++++++++++++++++++-------------------
- 1 file changed, 137 insertions(+), 124 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 6194ef10e4eb..b48e8e9ed779 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -31,38 +31,40 @@
- * translation tables are grouped into windows, each window registers are
- * grouped into blocks of 4 or 16 registers each
- */
--#define PAB_REG_BLOCK_SIZE 16
--#define PAB_EXT_REG_BLOCK_SIZE 4
-+#define PAB_REG_BLOCK_SIZE 16
-+#define PAB_EXT_REG_BLOCK_SIZE 4
-
--#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
--#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
-+#define PAB_REG_ADDR(offset, win) \
-+ (offset + (win * PAB_REG_BLOCK_SIZE))
-+#define PAB_EXT_REG_ADDR(offset, win) \
-+ (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
-
--#define LTSSM_STATUS 0x0404
--#define LTSSM_STATUS_L0_MASK 0x3f
--#define LTSSM_STATUS_L0 0x2d
-+#define LTSSM_STATUS 0x0404
-+#define LTSSM_STATUS_L0_MASK 0x3f
-+#define LTSSM_STATUS_L0 0x2d
-
--#define PAB_CTRL 0x0808
--#define AMBA_PIO_ENABLE_SHIFT 0
--#define PEX_PIO_ENABLE_SHIFT 1
--#define PAGE_SEL_SHIFT 13
--#define PAGE_SEL_MASK 0x3f
--#define PAGE_LO_MASK 0x3ff
--#define PAGE_SEL_OFFSET_SHIFT 10
-+#define PAB_CTRL 0x0808
-+#define AMBA_PIO_ENABLE_SHIFT 0
-+#define PEX_PIO_ENABLE_SHIFT 1
-+#define PAGE_SEL_SHIFT 13
-+#define PAGE_SEL_MASK 0x3f
-+#define PAGE_LO_MASK 0x3ff
-+#define PAGE_SEL_OFFSET_SHIFT 10
-
--#define PAB_AXI_PIO_CTRL 0x0840
--#define APIO_EN_MASK 0xf
-+#define PAB_AXI_PIO_CTRL 0x0840
-+#define APIO_EN_MASK 0xf
-
--#define PAB_PEX_PIO_CTRL 0x08c0
--#define PIO_ENABLE_SHIFT 0
-+#define PAB_PEX_PIO_CTRL 0x08c0
-+#define PIO_ENABLE_SHIFT 0
-
- #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
--#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
-+#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
- #define PAB_INTP_INTX_MASK 0x01e0
- #define PAB_INTP_MSI_MASK 0x8
-
--#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
--#define WIN_ENABLE_SHIFT 0
--#define WIN_TYPE_SHIFT 1
-+#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
-+#define WIN_ENABLE_SHIFT 0
-+#define WIN_TYPE_SHIFT 1
-
- #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
-
-@@ -70,16 +72,16 @@
- #define AXI_WINDOW_ALIGN_MASK 3
-
- #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
--#define PAB_BUS_SHIFT 24
--#define PAB_DEVICE_SHIFT 19
--#define PAB_FUNCTION_SHIFT 16
-+#define PAB_BUS_SHIFT 24
-+#define PAB_DEVICE_SHIFT 19
-+#define PAB_FUNCTION_SHIFT 16
-
- #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
- #define PAB_INTP_AXI_PIO_CLASS 0x474
-
--#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
--#define AMAP_CTRL_EN_SHIFT 0
--#define AMAP_CTRL_TYPE_SHIFT 1
-+#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
-+#define AMAP_CTRL_EN_SHIFT 0
-+#define AMAP_CTRL_TYPE_SHIFT 1
-
- #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
- #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
-@@ -87,39 +89,39 @@
- #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
-
- /* starting offset of INTX bits in status register */
--#define PAB_INTX_START 5
-+#define PAB_INTX_START 5
-
- /* supported number of MSI interrupts */
--#define PCI_NUM_MSI 16
-+#define PCI_NUM_MSI 16
-
- /* MSI registers */
--#define MSI_BASE_LO_OFFSET 0x04
--#define MSI_BASE_HI_OFFSET 0x08
--#define MSI_SIZE_OFFSET 0x0c
--#define MSI_ENABLE_OFFSET 0x14
--#define MSI_STATUS_OFFSET 0x18
--#define MSI_DATA_OFFSET 0x20
--#define MSI_ADDR_L_OFFSET 0x24
--#define MSI_ADDR_H_OFFSET 0x28
-+#define MSI_BASE_LO_OFFSET 0x04
-+#define MSI_BASE_HI_OFFSET 0x08
-+#define MSI_SIZE_OFFSET 0x0c
-+#define MSI_ENABLE_OFFSET 0x14
-+#define MSI_STATUS_OFFSET 0x18
-+#define MSI_DATA_OFFSET 0x20
-+#define MSI_ADDR_L_OFFSET 0x24
-+#define MSI_ADDR_H_OFFSET 0x28
-
- /* outbound and inbound window definitions */
--#define WIN_NUM_0 0
--#define WIN_NUM_1 1
--#define CFG_WINDOW_TYPE 0
--#define IO_WINDOW_TYPE 1
--#define MEM_WINDOW_TYPE 2
--#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
--#define MAX_PIO_WINDOWS 8
-+#define WIN_NUM_0 0
-+#define WIN_NUM_1 1
-+#define CFG_WINDOW_TYPE 0
-+#define IO_WINDOW_TYPE 1
-+#define MEM_WINDOW_TYPE 2
-+#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
-+#define MAX_PIO_WINDOWS 8
-
- /* Parameters for the waiting for link up routine */
--#define LINK_WAIT_MAX_RETRIES 10
--#define LINK_WAIT_MIN 90000
--#define LINK_WAIT_MAX 100000
-+#define LINK_WAIT_MAX_RETRIES 10
-+#define LINK_WAIT_MIN 90000
-+#define LINK_WAIT_MAX 100000
-
--#define PAGED_ADDR_BNDRY 0xc00
--#define OFFSET_TO_PAGE_ADDR(off) \
-+#define PAGED_ADDR_BNDRY 0xc00
-+#define OFFSET_TO_PAGE_ADDR(off) \
- ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
--#define OFFSET_TO_PAGE_IDX(off) \
-+#define OFFSET_TO_PAGE_IDX(off) \
- ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
-
- struct mobiveil_msi { /* MSI information */
-@@ -297,14 +299,14 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
- unsigned int devfn, int where)
- {
- struct mobiveil_pcie *pcie = bus->sysdata;
-+ u32 value;
-
- if (!mobiveil_pcie_valid_device(bus, devfn))
- return NULL;
-
-- if (bus->number == pcie->root_bus_nr) {
-- /* RC config access */
-+ /* RC config access */
-+ if (bus->number == pcie->root_bus_nr)
- return pcie->csr_axi_slave_base + where;
-- }
-
- /*
- * EP config access (in Config/APIO space)
-@@ -312,10 +314,12 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
- * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
- * Relies on pci_lock serialization
- */
-- csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
-- PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
-- PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
-- PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
-+ value = bus->number << PAB_BUS_SHIFT |
-+ PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
-+ PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
-+
-+ csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
-+
- return pcie->config_axi_slave_base + where;
- }
-
-@@ -350,22 +354,22 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
-
- /* Handle INTx */
- if (intr_status & PAB_INTP_INTX_MASK) {
-- shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
-- PAB_INTX_START;
-+ shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
-+ shifted_status >>= PAB_INTX_START;
- do {
- for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
- virq = irq_find_mapping(pcie->intx_domain,
-- bit + 1);
-+ bit + 1);
- if (virq)
- generic_handle_irq(virq);
- else
-- dev_err_ratelimited(dev,
-- "unexpected IRQ, INT%d\n", bit);
-+ dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
-+ bit);
-
- /* clear interrupt */
- csr_writel(pcie,
-- shifted_status << PAB_INTX_START,
-- PAB_INTP_AMBA_MISC_STAT);
-+ shifted_status << PAB_INTX_START,
-+ PAB_INTP_AMBA_MISC_STAT);
- }
- } while ((shifted_status >> PAB_INTX_START) != 0);
- }
-@@ -375,8 +379,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
-
- /* handle MSI interrupts */
- while (msi_status & 1) {
-- msi_data = readl_relaxed(pcie->apb_csr_base
-- + MSI_DATA_OFFSET);
-+ msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
-
- /*
- * MSI_STATUS_OFFSET register gets updated to zero
-@@ -385,18 +388,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
- * two dummy reads.
- */
- msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
-- MSI_ADDR_L_OFFSET);
-+ MSI_ADDR_L_OFFSET);
- msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
-- MSI_ADDR_H_OFFSET);
-+ MSI_ADDR_H_OFFSET);
- dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
-- msi_data, msi_addr_hi, msi_addr_lo);
-+ msi_data, msi_addr_hi, msi_addr_lo);
-
- virq = irq_find_mapping(msi->dev_domain, msi_data);
- if (virq)
- generic_handle_irq(virq);
-
- msi_status = readl_relaxed(pcie->apb_csr_base +
-- MSI_STATUS_OFFSET);
-+ MSI_STATUS_OFFSET);
- }
-
- /* Clear the interrupt status */
-@@ -420,7 +423,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
-
- /* map config resource */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-- "config_axi_slave");
-+ "config_axi_slave");
- pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
- if (IS_ERR(pcie->config_axi_slave_base))
- return PTR_ERR(pcie->config_axi_slave_base);
-@@ -428,7 +431,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
-
- /* map csr resource */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-- "csr_axi_slave");
-+ "csr_axi_slave");
- pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
- if (IS_ERR(pcie->csr_axi_slave_base))
- return PTR_ERR(pcie->csr_axi_slave_base);
-@@ -459,7 +462,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
- }
-
- static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
-- int pci_addr, u32 type, u64 size)
-+ int pci_addr, u32 type, u64 size)
- {
- int pio_ctrl_val;
- int amap_ctrl_dw;
-@@ -472,19 +475,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
- }
-
- pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
-- csr_writel(pcie,
-- pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
-- amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-- amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
-- amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
-+ pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
-+ csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
-
-- csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
-- PAB_PEX_AMAP_CTRL(win_num));
-+ amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-+ amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
-+ (1 << AMAP_CTRL_EN_SHIFT) |
-+ lower_32_bits(size64);
-+ csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
-
- csr_writel(pcie, upper_32_bits(size64),
- PAB_EXT_PEX_AMAP_SIZEN(win_num));
-
- csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
-+
- csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
- csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
- }
-@@ -493,7 +497,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
- * routine to program the outbound windows
- */
- static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
-- u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
-+ u64 cpu_addr, u64 pci_addr,
-+ u32 config_io_bit, u64 size)
- {
-
- u32 value, type;
-@@ -512,7 +517,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
- type = config_io_bit;
- value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
- csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-- lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
-+ lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
-
- csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
-
-@@ -522,14 +527,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
- */
- value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
- csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
-- PAB_AXI_AMAP_AXI_WIN(win_num));
-+ PAB_AXI_AMAP_AXI_WIN(win_num));
-
- value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
-
- csr_writel(pcie, lower_32_bits(pci_addr),
-- PAB_AXI_AMAP_PEX_WIN_L(win_num));
-+ PAB_AXI_AMAP_PEX_WIN_L(win_num));
- csr_writel(pcie, upper_32_bits(pci_addr),
-- PAB_AXI_AMAP_PEX_WIN_H(win_num));
-+ PAB_AXI_AMAP_PEX_WIN_H(win_num));
-
- pcie->ob_wins_configured++;
- }
-@@ -545,7 +550,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
-
- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
- }
-+
- dev_err(&pcie->pdev->dev, "link never came up\n");
-+
- return -ETIMEDOUT;
- }
-
-@@ -558,16 +565,16 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
- msi->msi_pages_phys = (phys_addr_t)msg_addr;
-
- writel_relaxed(lower_32_bits(msg_addr),
-- pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
-+ pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
- writel_relaxed(upper_32_bits(msg_addr),
-- pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
-+ pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
- writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
- writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
- }
-
- static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- {
-- u32 value, pab_ctrl, type = 0;
-+ u32 value, pab_ctrl, type;
- int err;
- struct resource_entry *win, *tmp;
-
-@@ -582,26 +589,27 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- * Space
- */
- value = csr_readl(pcie, PCI_COMMAND);
-- csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-- PCI_COMMAND_MASTER, PCI_COMMAND);
-+ value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-+ csr_writel(pcie, value, PCI_COMMAND);
-
- /*
- * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
- * register
- */
- pab_ctrl = csr_readl(pcie, PAB_CTRL);
-- csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
-- (1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
-+ pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
-+ csr_writel(pcie, pab_ctrl, PAB_CTRL);
-
- csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
-- PAB_INTP_AMBA_MISC_ENB);
-+ PAB_INTP_AMBA_MISC_ENB);
-
- /*
- * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
- * PAB_AXI_PIO_CTRL Register
- */
- value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
-- csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
-+ value |= APIO_EN_MASK;
-+ csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
-
- /*
- * we'll program one outbound window for config reads and
-@@ -612,25 +620,25 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
-
- /* config outbound translation window */
- program_ob_windows(pcie, pcie->ob_wins_configured,
-- pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
-- resource_size(pcie->ob_io_res));
-+ pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
-+ resource_size(pcie->ob_io_res));
-
- /* memory inbound translation window */
- program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-
- /* Get the I/O and memory ranges from DT */
- resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
-- type = 0;
- if (resource_type(win->res) == IORESOURCE_MEM)
- type = MEM_WINDOW_TYPE;
-- if (resource_type(win->res) == IORESOURCE_IO)
-+ else if (resource_type(win->res) == IORESOURCE_IO)
- type = IO_WINDOW_TYPE;
-- if (type) {
-- /* configure outbound translation window */
-- program_ob_windows(pcie, pcie->ob_wins_configured,
-- win->res->start, 0, type,
-- resource_size(win->res));
-- }
-+ else
-+ continue;
-+
-+ /* configure outbound translation window */
-+ program_ob_windows(pcie, pcie->ob_wins_configured,
-+ win->res->start, 0, type,
-+ resource_size(win->res));
- }
-
- /* setup MSI hardware registers */
-@@ -650,7 +658,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
- mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
- raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
- shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-- csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
-+ shifted_val &= ~mask;
-+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
- raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
- }
-
-@@ -665,7 +674,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
- mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
- raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
- shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
-- csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
-+ shifted_val |= mask;
-+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
- raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
- }
-
-@@ -679,10 +689,11 @@ static struct irq_chip intx_irq_chip = {
-
- /* routine to setup the INTx related data */
- static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
-- irq_hw_number_t hwirq)
-+ irq_hw_number_t hwirq)
- {
- irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, domain->host_data);
-+
- return 0;
- }
-
-@@ -699,7 +710,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
-
- static struct msi_domain_info mobiveil_msi_domain_info = {
- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-- MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
-+ MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
- .chip = &mobiveil_msi_irq_chip,
- };
-
-@@ -717,7 +728,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
- }
-
- static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
-- const struct cpumask *mask, bool force)
-+ const struct cpumask *mask, bool force)
- {
- return -EINVAL;
- }
-@@ -729,7 +740,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
- };
-
- static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
-- unsigned int virq, unsigned int nr_irqs, void *args)
-+ unsigned int virq,
-+ unsigned int nr_irqs, void *args)
- {
- struct mobiveil_pcie *pcie = domain->host_data;
- struct mobiveil_msi *msi = &pcie->msi;
-@@ -749,13 +761,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
- mutex_unlock(&msi->lock);
-
- irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
-- domain->host_data, handle_level_irq,
-- NULL, NULL);
-+ domain->host_data, handle_level_irq, NULL, NULL);
- return 0;
- }
-
- static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
-- unsigned int virq, unsigned int nr_irqs)
-+ unsigned int virq,
-+ unsigned int nr_irqs)
- {
- struct irq_data *d = irq_domain_get_irq_data(domain, virq);
- struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
-@@ -763,12 +775,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
-
- mutex_lock(&msi->lock);
-
-- if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
-+ if (!test_bit(d->hwirq, msi->msi_irq_in_use))
- dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
- d->hwirq);
-- } else {
-+ else
- __clear_bit(d->hwirq, msi->msi_irq_in_use);
-- }
-
- mutex_unlock(&msi->lock);
- }
-@@ -792,12 +803,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
- }
-
- msi->msi_domain = pci_msi_create_irq_domain(fwnode,
-- &mobiveil_msi_domain_info, msi->dev_domain);
-+ &mobiveil_msi_domain_info,
-+ msi->dev_domain);
- if (!msi->msi_domain) {
- dev_err(dev, "failed to create MSI domain\n");
- irq_domain_remove(msi->dev_domain);
- return -ENOMEM;
- }
-+
- return 0;
- }
-
-@@ -808,8 +821,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
- int ret;
-
- /* setup INTx */
-- pcie->intx_domain = irq_domain_add_linear(node,
-- PCI_NUM_INTX, &intx_domain_ops, pcie);
-+ pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
-+ &intx_domain_ops, pcie);
-
- if (!pcie->intx_domain) {
- dev_err(dev, "Failed to get a INTx IRQ domain\n");
-@@ -925,10 +938,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
- static struct platform_driver mobiveil_pcie_driver = {
- .probe = mobiveil_pcie_probe,
- .driver = {
-- .name = "mobiveil-pcie",
-- .of_match_table = mobiveil_pcie_of_match,
-- .suppress_bind_attrs = true,
-- },
-+ .name = "mobiveil-pcie",
-+ .of_match_table = mobiveil_pcie_of_match,
-+ .suppress_bind_attrs = true,
-+ },
- };
-
- builtin_platform_driver(mobiveil_pcie_driver);
---
-2.11.0
-
diff --git a/patches.suse/0004-PCI-mobiveil-correct-the-returned-error-number.patch b/patches.suse/0004-PCI-mobiveil-correct-the-returned-error-number.patch
deleted file mode 100644
index c24cad6af6..0000000000
--- a/patches.suse/0004-PCI-mobiveil-correct-the-returned-error-number.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 253faf87290b55809cd2fa2a70eac4fe2e33721b Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:08:47 +0000
-Subject: [PATCH 04/26] PCI: mobiveil: correct the returned error number
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-This patch corrected the returned error number by convention,
-and removed a unnecessary error check.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index b48e8e9ed779..33615646806e 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -826,7 +826,7 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
-
- if (!pcie->intx_domain) {
- dev_err(dev, "Failed to get a INTx IRQ domain\n");
-- return -ENODEV;
-+ return -ENOMEM;
- }
-
- raw_spin_lock_init(&pcie->intx_mask_lock);
-@@ -853,11 +853,9 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
- /* allocate the PCIe port */
- bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
- if (!bridge)
-- return -ENODEV;
-+ return -ENOMEM;
-
- pcie = pci_host_bridge_priv(bridge);
-- if (!pcie)
-- return -ENOMEM;
-
- pcie->pdev = pdev;
-
-@@ -874,7 +872,7 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
- &pcie->resources, &iobase);
- if (ret) {
- dev_err(dev, "Getting bridge resources failed\n");
-- return -ENOMEM;
-+ return ret;
- }
-
- /*
---
-2.11.0
-
diff --git a/patches.suse/0005-PCI-mobiveil-remove-flag-MSI_FLAG_MULTI_PCI_MSI.patch b/patches.suse/0005-PCI-mobiveil-remove-flag-MSI_FLAG_MULTI_PCI_MSI.patch
deleted file mode 100644
index 7b3652378d..0000000000
--- a/patches.suse/0005-PCI-mobiveil-remove-flag-MSI_FLAG_MULTI_PCI_MSI.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 6796bc060461003a5deee756a20db8483d5eb48d Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:08:53 +0000
-Subject: [PATCH 05/26] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-The current code does not support multiple MSIs, so remove
-the corresponding flag from the msi_domain_info structure.
-
-Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 33615646806e..02292b0a04a3 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -710,7 +710,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
-
- static struct msi_domain_info mobiveil_msi_domain_info = {
- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-- MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
-+ MSI_FLAG_PCI_MSIX),
- .chip = &mobiveil_msi_irq_chip,
- };
-
---
-2.11.0
-
diff --git a/patches.suse/0006-PCI-mobiveil-correct-PCI-base-address-in-MEM-IO-outb.patch b/patches.suse/0006-PCI-mobiveil-correct-PCI-base-address-in-MEM-IO-outb.patch
deleted file mode 100644
index 7dd82d15e3..0000000000
--- a/patches.suse/0006-PCI-mobiveil-correct-PCI-base-address-in-MEM-IO-outb.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From ad93730e19e3b3b17fcf4d074446a8c1f2b534aa Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:00 +0000
-Subject: [PATCH 06/26] PCI: mobiveil: correct PCI base address in MEM/IO
- outbound windows
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-It should get PCI base address from the DT node property 'ranges'
-to setup MEM/IO outbound windows instead of always zero.
-
-Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
-IP driver")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 02292b0a04a3..5c0ca63ba9cf 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -637,8 +637,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
-
- /* configure outbound translation window */
- program_ob_windows(pcie, pcie->ob_wins_configured,
-- win->res->start, 0, type,
-- resource_size(win->res));
-+ win->res->start,
-+ win->res->start - win->offset,
-+ type, resource_size(win->res));
- }
-
- /* setup MSI hardware registers */
---
-2.11.0
-
diff --git a/patches.suse/0007-PCI-mobiveil-replace-the-resource-list-iteration-fun.patch b/patches.suse/0007-PCI-mobiveil-replace-the-resource-list-iteration-fun.patch
deleted file mode 100644
index fe7aab2e9f..0000000000
--- a/patches.suse/0007-PCI-mobiveil-replace-the-resource-list-iteration-fun.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 4da2904daaf9c9c3bef8dac3a366bb6fe96030f0 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:06 +0000
-Subject: [PATCH 07/26] PCI: mobiveil: replace the resource list iteration
- function
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-As it won't delete any node in this iteration, replaced
-the function resource_list_for_each_entry_safe() with
-the resource_list_for_each_entry().
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 5c0ca63ba9cf..c7802999eadf 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -576,7 +576,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- {
- u32 value, pab_ctrl, type;
- int err;
-- struct resource_entry *win, *tmp;
-+ struct resource_entry *win;
-
- err = mobiveil_bringup_link(pcie);
- if (err) {
-@@ -627,7 +627,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-
- /* Get the I/O and memory ranges from DT */
-- resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
-+ resource_list_for_each_entry(win, &pcie->resources) {
- if (resource_type(win->res) == IORESOURCE_MEM)
- type = MEM_WINDOW_TYPE;
- else if (resource_type(win->res) == IORESOURCE_IO)
---
-2.11.0
-
diff --git a/patches.suse/0008-PCI-mobiveil-use-WIN_NUM_0-explicitly-for-CFG-outbou.patch b/patches.suse/0008-PCI-mobiveil-use-WIN_NUM_0-explicitly-for-CFG-outbou.patch
deleted file mode 100644
index 9f3189482a..0000000000
--- a/patches.suse/0008-PCI-mobiveil-use-WIN_NUM_0-explicitly-for-CFG-outbou.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 0a0fff5c497b04d1c095ef9d0762fd3488f67a1f Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:12 +0000
-Subject: [PATCH 08/26] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG
- outbound window
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-As the .map_bus() use the WIN_NUM_0 for CFG transactions,
-it's better passing WIN_NUM_0 explicitly when initialize
-the CFG outbound window.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index c7802999eadf..3d1372f2167f 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -619,9 +619,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- */
-
- /* config outbound translation window */
-- program_ob_windows(pcie, pcie->ob_wins_configured,
-- pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
-- resource_size(pcie->ob_io_res));
-+ program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
-+ CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
-
- /* memory inbound translation window */
- program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
---
-2.11.0
-
diff --git a/patches.suse/0009-PCI-mobiveil-use-the-1st-inbound-window-for-MEM-inbo.patch b/patches.suse/0009-PCI-mobiveil-use-the-1st-inbound-window-for-MEM-inbo.patch
deleted file mode 100644
index 0821f63a67..0000000000
--- a/patches.suse/0009-PCI-mobiveil-use-the-1st-inbound-window-for-MEM-inbo.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From bcc82e8be586cd2f9ea2d1ba2700f35aa9a44d97 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:19 +0000
-Subject: [PATCH 09/26] PCI: mobiveil: use the 1st inbound window for MEM
- inbound transactions
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-The inbound windows have different register set with outbound windows.
-This patch change the MEM inbound window to the first one.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 3d1372f2167f..67132da187f7 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -623,7 +623,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
-
- /* memory inbound translation window */
-- program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-+ program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-
- /* Get the I/O and memory ranges from DT */
- resource_list_for_each_entry(win, &pcie->resources) {
---
-2.11.0
-
diff --git a/patches.suse/0010-PCI-mobiveil-correct-inbound-outbound-window-setup-r.patch b/patches.suse/0010-PCI-mobiveil-correct-inbound-outbound-window-setup-r.patch
deleted file mode 100644
index e7f2bde4c1..0000000000
--- a/patches.suse/0010-PCI-mobiveil-correct-inbound-outbound-window-setup-r.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From 7fd77a61f10a39fa99771896b035919db97d3357 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:25 +0000
-Subject: [PATCH 10/26] PCI: mobiveil: correct inbound/outbound window setup
- routines
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Outbound window routine:
- - Removed unused var definition and register read operations.
- - Added the upper 32-bit cpu address setup of the window.
- - Instead of blindly write, only change the fields specified.
- - Masked the lower bits of window size in case override the
- control bits.
- - Check if the passing window number is available, instead of
- the total number of the initialized windows.
-
-Inbound window routine:
- - Added parameter 'u64 cpu_addr' to specify the cpu address
- of the window instead of using 'pci_addr'.
- - Changed 'int pci_addr' to 'u64 pci_addr', and added setup
- of the upper 32-bit pci address of the window.
- - Moved the PCIe PIO master enablement to mobiveil_host_init().
- - Instead of blindly write, only change the fields specified.
- - Masked the lower bits of window size in case override the
- control bits.
- - Check if the passing window number is available, instead of
- the total number of the initialized windows.
- - And added the statistic of initialized inbound windows.
-
-Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
-Bridge IP driver")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 70 ++++++++++++++++++++++++----------------
- 1 file changed, 42 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 67132da187f7..fd121e7780da 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -65,9 +65,13 @@
- #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
- #define WIN_ENABLE_SHIFT 0
- #define WIN_TYPE_SHIFT 1
-+#define WIN_TYPE_MASK 0x3
-+#define WIN_SIZE_SHIFT 10
-+#define WIN_SIZE_MASK 0x3fffff
-
- #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
-
-+#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
- #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
- #define AXI_WINDOW_ALIGN_MASK 3
-
-@@ -82,8 +86,10 @@
- #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
- #define AMAP_CTRL_EN_SHIFT 0
- #define AMAP_CTRL_TYPE_SHIFT 1
-+#define AMAP_CTRL_TYPE_MASK 3
-
- #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
-+#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
- #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
- #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
- #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
-@@ -462,49 +468,51 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
- }
-
- static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
-- int pci_addr, u32 type, u64 size)
-+ u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
- {
-- int pio_ctrl_val;
-- int amap_ctrl_dw;
-+ u32 value;
- u64 size64 = ~(size - 1);
-
-- if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
-+ if (win_num >= pcie->ppio_wins) {
- dev_err(&pcie->pdev->dev,
- "ERROR: max inbound windows reached !\n");
- return;
- }
-
-- pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
-- pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
-- csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
--
-- amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-- amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
-- (1 << AMAP_CTRL_EN_SHIFT) |
-- lower_32_bits(size64);
-- csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
-+ value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-+ value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
-+ WIN_SIZE_MASK << WIN_SIZE_SHIFT);
-+ value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
-+ (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
-+ csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
-
- csr_writel(pcie, upper_32_bits(size64),
- PAB_EXT_PEX_AMAP_SIZEN(win_num));
-
-- csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
-+ csr_writel(pcie, lower_32_bits(cpu_addr),
-+ PAB_PEX_AMAP_AXI_WIN(win_num));
-+ csr_writel(pcie, upper_32_bits(cpu_addr),
-+ PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
-+
-+ csr_writel(pcie, lower_32_bits(pci_addr),
-+ PAB_PEX_AMAP_PEX_WIN_L(win_num));
-+ csr_writel(pcie, upper_32_bits(pci_addr),
-+ PAB_PEX_AMAP_PEX_WIN_H(win_num));
-
-- csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
-- csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
-+ pcie->ib_wins_configured++;
- }
-
- /*
- * routine to program the outbound windows
- */
- static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
-- u64 cpu_addr, u64 pci_addr,
-- u32 config_io_bit, u64 size)
-+ u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
- {
-
-- u32 value, type;
-+ u32 value;
- u64 size64 = ~(size - 1);
-
-- if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
-+ if (win_num >= pcie->apio_wins) {
- dev_err(&pcie->pdev->dev,
- "ERROR: max outbound windows reached !\n");
- return;
-@@ -514,10 +522,12 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
- * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
- * to 4 KB in PAB_AXI_AMAP_CTRL register
- */
-- type = config_io_bit;
- value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
-- csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-- lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
-+ value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
-+ WIN_SIZE_MASK << WIN_SIZE_SHIFT);
-+ value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-+ (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
-+ csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
-
- csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
-
-@@ -525,11 +535,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
- * program AXI window base with appropriate value in
- * PAB_AXI_AMAP_AXI_WIN0 register
- */
-- value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
-- csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
-+ csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
- PAB_AXI_AMAP_AXI_WIN(win_num));
--
-- value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
-+ csr_writel(pcie, upper_32_bits(cpu_addr),
-+ PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
-
- csr_writel(pcie, lower_32_bits(pci_addr),
- PAB_AXI_AMAP_PEX_WIN_L(win_num));
-@@ -611,6 +620,11 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- value |= APIO_EN_MASK;
- csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
-
-+ /* Enable PCIe PIO master */
-+ value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
-+ value |= 1 << PIO_ENABLE_SHIFT;
-+ csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
-+
- /*
- * we'll program one outbound window for config reads and
- * another default inbound window for all the upstream traffic
-@@ -623,7 +637,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
-
- /* memory inbound translation window */
-- program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-+ program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
-
- /* Get the I/O and memory ranges from DT */
- resource_list_for_each_entry(win, &pcie->resources) {
---
-2.11.0
-
diff --git a/patches.suse/0011-PCI-mobiveil-fix-the-INTx-process-error.patch b/patches.suse/0011-PCI-mobiveil-fix-the-INTx-process-error.patch
deleted file mode 100644
index ee05ca1c7c..0000000000
--- a/patches.suse/0011-PCI-mobiveil-fix-the-INTx-process-error.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 0e57c2cbf580d6461005a293adeacebf7265d8f6 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:32 +0000
-Subject: [PATCH 11/26] PCI: mobiveil: fix the INTx process error
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-In the loop block, there is not code change the loop key,
-this patch updated the loop key by re-read the INTx status
-register.
-
-This patch also change to clear the handled INTx status.
-
-Note: Need MV to test this fix.
-
-Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
-Bridge IP driver")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index fd121e7780da..597c620a6f58 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
- /* Handle INTx */
- if (intr_status & PAB_INTP_INTX_MASK) {
- shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
-+ shifted_status &= PAB_INTP_INTX_MASK;
- shifted_status >>= PAB_INTX_START;
- do {
- for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
-@@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
- dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
- bit);
-
-- /* clear interrupt */
-- csr_writel(pcie,
-- shifted_status << PAB_INTX_START,
-+ /* clear interrupt handled */
-+ csr_writel(pcie, 1 << (PAB_INTX_START + bit),
- PAB_INTP_AMBA_MISC_STAT);
- }
-- } while ((shifted_status >> PAB_INTX_START) != 0);
-+
-+ shifted_status = csr_readl(pcie,
-+ PAB_INTP_AMBA_MISC_STAT);
-+ shifted_status &= PAB_INTP_INTX_MASK;
-+ shifted_status >>= PAB_INTX_START;
-+ } while (shifted_status != 0);
- }
-
- /* read extra MSI status register */
---
-2.11.0
-
diff --git a/patches.suse/0012-PCI-mobiveil-only-fix-up-the-Class-Code-field.patch b/patches.suse/0012-PCI-mobiveil-only-fix-up-the-Class-Code-field.patch
deleted file mode 100644
index 8df9329e84..0000000000
--- a/patches.suse/0012-PCI-mobiveil-only-fix-up-the-Class-Code-field.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From bd3e63980932fe9f5dd6ddfcc609093d47023c1d Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:38 +0000
-Subject: [PATCH 12/26] PCI: mobiveil: only fix up the Class Code field
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Fix up the Class Code to PCI bridge, do not change the Revision ID.
-And move the fixup to mobiveil_host_init function.
-
-Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
-IP driver")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 597c620a6f58..818446a81041 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -660,6 +660,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- type, resource_size(win->res));
- }
-
-+ /* fixup for PCIe class register */
-+ value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
-+ value &= 0xff;
-+ value |= (PCI_CLASS_BRIDGE_PCI << 16);
-+ csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
-+
- /* setup MSI hardware registers */
- mobiveil_pcie_enable_msi(pcie);
-
-@@ -904,9 +910,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
- goto error;
- }
-
-- /* fixup for PCIe class register */
-- csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
--
- /* initialize the IRQ domains */
- ret = mobiveil_pcie_init_irq_domain(pcie);
- if (ret) {
---
-2.11.0
-
diff --git a/patches.suse/0013-PCI-mobiveil-move-out-the-link-up-waiting-from-mobiv.patch b/patches.suse/0013-PCI-mobiveil-move-out-the-link-up-waiting-from-mobiv.patch
deleted file mode 100644
index d05a49e701..0000000000
--- a/patches.suse/0013-PCI-mobiveil-move-out-the-link-up-waiting-from-mobiv.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 19380a51b8174e1551428e760bfacb115c2e7dee Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:44 +0000
-Subject: [PATCH 13/26] PCI: mobiveil: move out the link up waiting from
- mobiveil_host_init
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Host initial sequence does not depend on PCIe link up, so move it
-to the place just before the enumeration.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 15 +++++++--------
- 1 file changed, 7 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 818446a81041..b44ade7eadd3 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -589,15 +589,8 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
- static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- {
- u32 value, pab_ctrl, type;
-- int err;
- struct resource_entry *win;
-
-- err = mobiveil_bringup_link(pcie);
-- if (err) {
-- dev_info(&pcie->pdev->dev, "link bring-up failed\n");
-- return err;
-- }
--
- /*
- * program Bus Master Enable Bit in Command Register in PAB Config
- * Space
-@@ -669,7 +662,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- /* setup MSI hardware registers */
- mobiveil_pcie_enable_msi(pcie);
-
-- return err;
-+ return 0;
- }
-
- static void mobiveil_mask_intx_irq(struct irq_data *data)
-@@ -930,6 +923,12 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
- bridge->map_irq = of_irq_parse_and_map_pci;
- bridge->swizzle_irq = pci_common_swizzle;
-
-+ ret = mobiveil_bringup_link(pcie);
-+ if (ret) {
-+ dev_info(dev, "link bring-up failed\n");
-+ goto error;
-+ }
-+
- /* setup the kernel resources for the newly added PCIe root bus */
- ret = pci_scan_root_bus_bridge(bridge);
- if (ret)
---
-2.11.0
-
diff --git a/patches.suse/0014-PCI-mobiveil-move-irq-chained-handler-setup-out-of-D.patch b/patches.suse/0014-PCI-mobiveil-move-irq-chained-handler-setup-out-of-D.patch
deleted file mode 100644
index 17058dbfb8..0000000000
--- a/patches.suse/0014-PCI-mobiveil-move-irq-chained-handler-setup-out-of-D.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 6f483e98a12b759317310dbd2b9bd5a681fa30ff Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:51 +0000
-Subject: [PATCH 14/26] PCI: mobiveil: move irq chained handler setup out of DT
- parse
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Move irq_set_chained_handler_and_data() out of DT parse function.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index b44ade7eadd3..9c21ea4be278 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -467,8 +467,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
- return -ENODEV;
- }
-
-- irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
--
- return 0;
- }
-
-@@ -910,6 +908,8 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
- goto error;
- }
-
-+ irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
-+
- ret = devm_request_pci_bus_resources(dev, &pcie->resources);
- if (ret)
- goto error;
---
-2.11.0
-
diff --git a/patches.suse/0015-PCI-mobiveil-initialize-Primary-Secondary-Subordinat.patch b/patches.suse/0015-PCI-mobiveil-initialize-Primary-Secondary-Subordinat.patch
deleted file mode 100644
index 28f4723d6b..0000000000
--- a/patches.suse/0015-PCI-mobiveil-initialize-Primary-Secondary-Subordinat.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 699fe9bc3f15346f22957cbc43e775e55a99f5cb Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:09:58 +0000
-Subject: [PATCH 15/26] PCI: mobiveil: initialize Primary/Secondary/Subordinate
- bus number
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-The reset value is all zero, so set a workable value for Primary,
-Secondary and Subordinate bus numbers.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/pcie-mobiveil.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/pci/host/pcie-mobiveil.c b/drivers/pci/host/pcie-mobiveil.c
-index 9c21ea4be278..ce2954a169bb 100644
---- a/drivers/pci/host/pcie-mobiveil.c
-+++ b/drivers/pci/host/pcie-mobiveil.c
-@@ -589,6 +589,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- u32 value, pab_ctrl, type;
- struct resource_entry *win;
-
-+ /* setup bus numbers */
-+ value = csr_readl(pcie, PCI_PRIMARY_BUS);
-+ value &= 0xff000000;
-+ value |= 0x00ff0100;
-+ csr_writel(pcie, value, PCI_PRIMARY_BUS);
-+
- /*
- * program Bus Master Enable Bit in Command Register in PAB Config
- * Space
---
-2.11.0
-
diff --git a/patches.suse/0016-dt-bindings-pci-mobiveil-change-gpio_slave-and-apb_c.patch b/patches.suse/0016-dt-bindings-pci-mobiveil-change-gpio_slave-and-apb_c.patch
deleted file mode 100644
index 91dca17333..0000000000
--- a/patches.suse/0016-dt-bindings-pci-mobiveil-change-gpio_slave-and-apb_c.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 3a713694614c920c954c2ae19071e2503c5b1da4 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:04 +0000
-Subject: [PATCH 16/26] dt-bindings: pci: mobiveil: change gpio_slave and
- apb_csr to optional
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
-is not used in current code, and "apb_csr" is not used by some
-platforms.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
-index 65038aa642e5..fd4769dc3eac 100644
---- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
-+++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
-@@ -10,8 +10,10 @@ Required properties:
- interrupt source. The value must be 1.
- - compatible: Should contain "mbvl,gpex40-pcie"
- - reg: Should contain PCIe registers location and length
-+ Mandatory:
- "config_axi_slave": PCIe controller registers
- "csr_axi_slave" : Bridge config registers
-+ Optional:
- "gpio_slave" : GPIO registers to control slot power
- "apb_csr" : MSI registers
-
---
-2.11.0
-
diff --git a/patches.suse/0018-PCI-mobiveil-fix-the-checking-of-valid-device.patch b/patches.suse/0018-PCI-mobiveil-fix-the-checking-of-valid-device.patch
deleted file mode 100644
index 7fa5927926..0000000000
--- a/patches.suse/0018-PCI-mobiveil-fix-the-checking-of-valid-device.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 88a279e3fa2f61dc8f9f6ba56db4bc452d5cc3b0 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:17 +0000
-Subject: [PATCH 18/26] PCI: mobiveil: fix the checking of valid device
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Avoid to issue CFG transactions to link partner when the PCIe
-link is not up. And allow CFG transactions to all functions of
-Endpoint implemented multiple functions.
-
-Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
-Bridge IP driver")
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-
-[Yousaf]: Fix according to comments from Subrahmanya Lingappa
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-index dc5324d94466..7cc3fb56dbb9 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
- {
- struct mobiveil_pcie *pcie = bus->sysdata;
-
-+ /* If there is no link, then there is no device */
-+ if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
-+ return false;
-+
- /* Only one device down on each root port */
- if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
- return false;
-@@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
- * Do not read more than one device on the bus directly
- * attached to RC
- */
-- if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
-+ if ((bus->number == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
- return false;
-
- return true;
---
-2.11.0
-
diff --git a/patches.suse/0019-PCI-mobiveil-continue-to-initialize-the-host-upon-no.patch b/patches.suse/0019-PCI-mobiveil-continue-to-initialize-the-host-upon-no.patch
deleted file mode 100644
index bd89ad189a..0000000000
--- a/patches.suse/0019-PCI-mobiveil-continue-to-initialize-the-host-upon-no.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From b78d7f44e408246085391ec76403848f009fa07c Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:23 +0000
-Subject: [PATCH 19/26] PCI: mobiveil: continue to initialize the host upon no
- PCIe link
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
-not exit when the PCIe link is not up. And degrade the print
-level of link up info.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 1 -
- drivers/pci/host/mobiveil/pcie-mobiveil.c | 2 +-
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-index 7cc3fb56dbb9..beb823b35cee 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -596,7 +596,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
- ret = mobiveil_bringup_link(pcie);
- if (ret) {
- dev_info(dev, "link bring-up failed\n");
-- goto error;
- }
-
- /* setup the kernel resources for the newly added PCIe root bus */
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.c b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-index ee678a60825d..370658d6546d 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-@@ -222,7 +222,7 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
- }
-
-- dev_err(&pcie->pdev->dev, "link never came up\n");
-+ dev_info(&pcie->pdev->dev, "link never came up\n");
-
- return -ETIMEDOUT;
- }
---
-2.11.0
-
diff --git a/patches.suse/0020-PCI-mobiveil-disabled-IB-and-OB-windows-set-by-bootl.patch b/patches.suse/0020-PCI-mobiveil-disabled-IB-and-OB-windows-set-by-bootl.patch
deleted file mode 100644
index dc8b3a8d09..0000000000
--- a/patches.suse/0020-PCI-mobiveil-disabled-IB-and-OB-windows-set-by-bootl.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 051dd766c01e9746170e07c243907242692680b5 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:30 +0000
-Subject: [PATCH 20/26] PCI: mobiveil: disabled IB and OB windows set by
- bootloader
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Disabled all inbound and outbound windows before set up the windows
-in kernel, in case transactions match the window set by bootloader.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 7 +++++++
- drivers/pci/host/mobiveil/pcie-mobiveil.c | 18 ++++++++++++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 2 ++
- 3 files changed, 27 insertions(+)
-
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-index beb823b35cee..a42ff86e800c 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- {
- u32 value, pab_ctrl, type;
- struct resource_entry *win;
-+ int i;
-+
-+ /* Disable all inbound/outbound windows */
-+ for (i = 0; i < pcie->apio_wins; i++)
-+ mobiveil_pcie_disable_ob_win(pcie, i);
-+ for (i = 0; i < pcie->ppio_wins; i++)
-+ mobiveil_pcie_disable_ib_win(pcie, i);
-
- /* setup bus numbers */
- value = csr_readl(pcie, PCI_PRIMARY_BUS);
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.c b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-index 370658d6546d..49d471b75925 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-@@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
-
- return -ETIMEDOUT;
- }
-+
-+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
-+{
-+ u32 val;
-+
-+ val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
-+ val &= ~(1 << AMAP_CTRL_EN_SHIFT);
-+ csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
-+}
-+
-+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
-+{
-+ u32 val;
-+
-+ val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
-+ val &= ~(1 << WIN_ENABLE_SHIFT);
-+ csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
-+}
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index eb4cb61291a8..81685840b378 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
- u64 pci_addr, u32 type, u64 size);
- void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
- u64 pci_addr, u32 type, u64 size);
-+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
-+void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
- u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
- void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
-
---
-2.11.0
-
diff --git a/patches.suse/0023-dt-bindings-pci-Add-NXP-Layerscape-SoCs-PCIe-Gen4-co.patch b/patches.suse/0023-dt-bindings-pci-Add-NXP-Layerscape-SoCs-PCIe-Gen4-co.patch
deleted file mode 100644
index 5cc9d0e544..0000000000
--- a/patches.suse/0023-dt-bindings-pci-Add-NXP-Layerscape-SoCs-PCIe-Gen4-co.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 43d94668ca82c10d722e4a55b2ba2ecc8649285f Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:49 +0000
-Subject: [PATCH 23/26] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4
- controller
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- .../bindings/pci/layerscape-pci-gen4.txt | 52 ++++++++++++++++++++++
- MAINTAINERS | 8 ++++
- 2 files changed, 60 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
-
-diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
-new file mode 100644
-index 000000000000..b40fb5d15d3d
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
-@@ -0,0 +1,52 @@
-+NXP Layerscape PCIe Gen4 controller
-+
-+This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
-+the common properties defined in mobiveil-pcie.txt.
-+
-+Required properties:
-+- compatible: should contain the platform identifier such as:
-+ "fsl,lx2160a-pcie"
-+- reg: base addresses and lengths of the PCIe controller register blocks.
-+ "csr_axi_slave": Bridge config registers
-+ "config_axi_slave": PCIe controller registers
-+- interrupts: A list of interrupt outputs of the controller. Must contain an
-+ entry for each entry in the interrupt-names property.
-+- interrupt-names: It could include the following entries:
-+ "intr": The interrupt that is asserted for controller interrupts
-+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
-+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
-+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
-+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
-+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
-+ of the data transferred from/to the IP block. This can avoid the software
-+ cache flush/invalid actions, and improve the performance significantly.
-+- msi-parent : See the generic MSI binding described in
-+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-+
-+Example:
-+
-+ pcie@3400000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
-+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ dma-coherent;
-+ bus-range = <0x0 0xff>;
-+ msi-parent = <&its>;
-+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-diff --git a/MAINTAINERS b/MAINTAINERS
-index ed81cf1c6e7f..3cae0cdb3a51 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9981,6 +9981,14 @@ L: linux-arm-kernel@lists.infradead.org
- S: Maintained
- F: drivers/pci/dwc/*layerscape*
-
-+PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
-+M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-+L: linux-pci@vger.kernel.org
-+L: linux-arm-kernel@lists.viinfradead.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
-+F: drivers/pci/host/mobibeil/pci-layerscape-gen4.c
-+
- PCI DRIVER FOR IMX6
- M: Richard Zhu <hongxing.zhu@nxp.com>
- M: Lucas Stach <l.stach@pengutronix.de>
---
-2.11.0
-
diff --git a/patches.suse/0025-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch b/patches.suse/0025-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch
deleted file mode 100644
index 24a902c459..0000000000
--- a/patches.suse/0025-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch
+++ /dev/null
@@ -1,164 +0,0 @@
-From ff853c0507cb10c0ef7d3c5116805147aeddc386 Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:11:01 +0000
-Subject: [PATCH 25/26] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-PCIe configuration access to non-existent function triggered
-SERROR interrupt exception.
-
-Workaround:
-Disable error reporting on AXI bus during the Vendor ID read
-transactions in enumeration.
-
-This ERRATA is only for LX2160A Rev1.0, and it will be fixed
-in Rev2.0.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/mobiveil/pci-layerscape-gen4.c | 37 +++++++++++++++++++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 17 +++++++++++-
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 3 ++
- 3 files changed, 56 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/pci/host/mobiveil/pci-layerscape-gen4.c b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-index 174cbcac4059..d2c5dbbd5e3c 100644
---- a/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-+++ b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-@@ -22,8 +22,13 @@
-
- #include "pcie-mobiveil.h"
-
-+#define REV_1_0 (0x10)
-+
- /* LUT and PF control registers */
- #define PCIE_LUT_OFF (0x80000)
-+#define PCIE_LUT_GCR (0x28)
-+#define PCIE_LUT_GCR_RRE (0)
-+
- #define PCIE_PF_OFF (0xc0000)
- #define PCIE_PF_INT_STAT (0x18)
- #define PF_INT_STAT_PABRST (31)
-@@ -41,6 +46,7 @@ struct ls_pcie_g4 {
- struct mobiveil_pcie *pci;
- struct delayed_work dwork;
- int irq;
-+ u8 rev;
- };
-
- static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
-@@ -76,6 +82,15 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
- return header_type == PCI_HEADER_TYPE_BRIDGE;
- }
-
-+static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
-+{
-+ struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
-+
-+ pcie->rev = csr_readb(pci, PCI_REVISION_ID);
-+
-+ return 0;
-+}
-+
- static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
- {
- struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
-@@ -188,12 +203,34 @@ static void ls_pcie_g4_reset(struct work_struct *work)
- ls_pcie_g4_reinit_hw(pcie);
- }
-
-+static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ struct mobiveil_pcie *pci = bus->sysdata;
-+ struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
-+ int ret;
-+
-+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
-+ ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
-+ 0 << PCIE_LUT_GCR_RRE);
-+
-+ ret = pci_generic_config_read(bus, devfn, where, size, val);
-+
-+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
-+ ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
-+ 1 << PCIE_LUT_GCR_RRE);
-+
-+ return ret;
-+}
-+
- static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
- .interrupt_init = ls_pcie_g4_interrupt_init,
-+ .read_other_conf = ls_pcie_g4_read_other_conf,
- };
-
- static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
- .link_up = ls_pcie_g4_link_up,
-+ .host_init = ls_pcie_g4_host_init,
- };
-
- static int __init ls_pcie_g4_probe(struct platform_device *pdev)
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-index bc3c49e695fa..ba8e7a1b8a0f 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -79,9 +79,20 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
- return pcie->rp.config_axi_slave_base + where;
- }
-
-+static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ struct mobiveil_pcie *pcie = bus->sysdata;
-+ struct root_port *rp = &pcie->rp;
-+
-+ if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf)
-+ return rp->ops->read_other_conf(bus, devfn, where, size, val);
-+
-+ return pci_generic_config_read(bus, devfn, where, size, val);
-+}
- static struct pci_ops mobiveil_pcie_ops = {
- .map_bus = mobiveil_pcie_map_bus,
-- .read = pci_generic_config_read,
-+ .read = mobiveil_pcie_config_read,
- .write = pci_generic_config_write,
- };
-
-@@ -309,6 +320,10 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
- value |= (PCI_CLASS_BRIDGE_PCI << 16);
- csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
-
-+ /* Platform specific host init */
-+ if (pcie->ops->host_init)
-+ return pcie->ops->host_init(pcie);
-+
- return 0;
- }
-
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index 0ccd6cee5f8f..ab43de5e4b2b 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -145,6 +145,8 @@ struct mobiveil_msi { /* MSI information */
-
- struct mobiveil_rp_ops {
- int (*interrupt_init)(struct mobiveil_pcie *pcie);
-+ int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val);
- };
-
- struct root_port {
-@@ -160,6 +162,7 @@ struct root_port {
-
- struct mobiveil_pab_ops {
- int (*link_up)(struct mobiveil_pcie *pcie);
-+ int (*host_init)(struct mobiveil_pcie *pcie);
- };
-
- struct mobiveil_pcie {
---
-2.11.0
-
diff --git a/patches.suse/0026-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011451.patch b/patches.suse/0026-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011451.patch
deleted file mode 100644
index 34e481c1ee..0000000000
--- a/patches.suse/0026-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011451.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From e741c4607843da92b1418e87268d09785f2f431b Mon Sep 17 00:00:00 2001
-From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:11:07 +0000
-Subject: [PATCH 26/26] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
-
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
-References: fate#326572
-
-When LX2 PCIe controller is sending multiple split completions and
-ACK latency expires indicating that ACK should be send at priority.
-But because of large number of split completions and FC update DLLP,
-the controller does not give priority to ACK transmission. This
-results into ACK latency timer timeout error at the link partner and
-the pending TLPs are replayed by the link partner again.
-
-Workaround:
-1. Reduce the ACK latency timeout value to a very small value.
-2. Restrict the number of completions from the LX2 PCIe controller
- to 1, by changing the Max Read Request Size (MRRS) of link partner
- to the same value as Max Packet size (MPS).
-
-This patch implemented part 1, the part 2 can be set by kernel parameter
-'pci=pcie_bus_perf'
-
-This ERRATA is only for LX2160A Rev1.0, and it will be fixed
-in Rev2.0.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
----
- drivers/pci/host/mobiveil/pci-layerscape-gen4.c | 15 +++++++++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 4 ++++
- 2 files changed, 19 insertions(+)
-
-diff --git a/drivers/pci/host/mobiveil/pci-layerscape-gen4.c b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-index d2c5dbbd5e3c..20ce146788ca 100644
---- a/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-+++ b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-@@ -82,12 +82,27 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
- return header_type == PCI_HEADER_TYPE_BRIDGE;
- }
-
-+static void workaround_A011451(struct ls_pcie_g4 *pcie)
-+{
-+ struct mobiveil_pcie *mv_pci = pcie->pci;
-+ u32 val;
-+
-+ /* Set ACK latency timeout */
-+ val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
-+ val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
-+ val |= (4 << ACK_LAT_TO_VAL_SHIFT);
-+ csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
-+}
-+
- static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
- {
- struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
-
- pcie->rev = csr_readb(pci, PCI_REVISION_ID);
-
-+ if (pcie->rev == REV_1_0)
-+ workaround_A011451(pcie);
-+
- return 0;
- }
-
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index ab43de5e4b2b..f0e2e4ae09b5 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -85,6 +85,10 @@
- #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
- #define PAB_INTP_AXI_PIO_CLASS 0x474
-
-+#define GPEX_ACK_REPLAY_TO 0x438
-+#define ACK_LAT_TO_VAL_MASK 0x1fff
-+#define ACK_LAT_TO_VAL_SHIFT 0
-+
- #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
- #define AMAP_CTRL_EN_SHIFT 0
- #define AMAP_CTRL_TYPE_SHIFT 1
---
-2.11.0
-
diff --git a/patches.suse/PCI-Add-ACS-quirk-for-Amazon-Annapurna-Labs-root-por.patch b/patches.suse/PCI-Add-ACS-quirk-for-Amazon-Annapurna-Labs-root-por.patch
new file mode 100644
index 0000000000..9a18c3711d
--- /dev/null
+++ b/patches.suse/PCI-Add-ACS-quirk-for-Amazon-Annapurna-Labs-root-por.patch
@@ -0,0 +1,65 @@
+From: Ali Saidi <alisaidi@amazon.com>
+Date: Thu, 12 Sep 2019 16:00:40 +0300
+Subject: PCI: Add ACS quirk for Amazon Annapurna Labs root ports
+
+Git-commit: 76e67e9e0f0f2debf9df192502a759bdd0cb4dab
+Patch-mainline: v5.4-rc1
+References: bsc#1152187,bsc#1152525
+
+The Amazon's Annapurna Labs root ports don't advertise an ACS
+capability, but they don't allow peer-to-peer transactions and do
+validate bus numbers through the SMMU. Additionally, it's not possible
+for one RP to pass traffic to another RP.
+
+Signed-off-by: Ali Saidi <alisaidi@amazon.com>
+Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/pci/quirks.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 208aacf39329..e96c03b4e494 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4366,6 +4366,24 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
+ return ret;
+ }
+
++static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
++{
++ if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
++ return -ENOTTY;
++
++ /*
++ * Amazon's Annapurna Labs root ports don't include an ACS capability,
++ * but do include ACS-like functionality. The hardware doesn't support
++ * peer-to-peer transactions via the root port and each has a unique
++ * segment number.
++ *
++ * Additionally, the root ports cannot send traffic to each other.
++ */
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
++
++ return acs_flags ? 0 : 1;
++}
++
+ /*
+ * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
+ * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
+@@ -4559,6 +4577,8 @@ static const struct pci_dev_acs_enabled {
+ { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
+ { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
+ { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
++ /* Amazon Annapurna Labs */
++ { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
+ { 0 }
+ };
+
+--
+2.16.4
+
diff --git a/patches.suse/PCI-Add-Amazon-s-Annapurna-Labs-vendor-ID.patch b/patches.suse/PCI-Add-Amazon-s-Annapurna-Labs-vendor-ID.patch
new file mode 100644
index 0000000000..b8d8c7c630
--- /dev/null
+++ b/patches.suse/PCI-Add-Amazon-s-Annapurna-Labs-vendor-ID.patch
@@ -0,0 +1,35 @@
+From: Jonathan Chocron <jonnyc@amazon.com>
+Date: Thu, 12 Sep 2019 16:00:39 +0300
+Subject: PCI: Add Amazon's Annapurna Labs vendor ID
+
+Git-commit: 4a36a60c34f42f75e8b4f8cd24fcfade26111334
+Patch-mainline: v5.4-rc1
+References: bsc#1152187,bsc#1152525
+
+Add Amazon's Annapurna Labs vendor ID to pci_ids.h.
+
+Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index c842735a4f45..5ce83544f38b 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2570,6 +2570,8 @@
+
+ #define PCI_VENDOR_ID_ASMEDIA 0x1b21
+
++#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36
++
+ #define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+ #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
+--
+2.16.4
+
diff --git a/patches.suse/PCI-Add-quirk-to-disable-MSI-X-support-for-Amazon-s-.patch b/patches.suse/PCI-Add-quirk-to-disable-MSI-X-support-for-Amazon-s-.patch
new file mode 100644
index 0000000000..af1f975196
--- /dev/null
+++ b/patches.suse/PCI-Add-quirk-to-disable-MSI-X-support-for-Amazon-s-.patch
@@ -0,0 +1,102 @@
+From: Jonathan Chocron <jonnyc@amazon.com>
+Date: Thu, 12 Sep 2019 16:00:42 +0300
+Subject: PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs
+ Root Port
+
+Git-commit: 738cb37b013e5ba6abd725a22abbd8baebc95082
+Patch-mainline: v5.4-rc1
+References: bsc#1152187,bsc#1152525
+
+The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On some
+platforms it is configured to not advertise the capability at all, while
+on others it (mistakenly) does. This causes a panic during
+initialization by the pcieport driver, since it tries to configure the
+MSI-X capability. Specifically, when trying to access the MSI-X table
+a "non-existing addr" exception occurs.
+
+Example stacktrace snippet:
+
+ SError Interrupt on CPU2, code 0xbf000000 -- SError
+ CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
+ Hardware name: Annapurna Labs Alpine V3 EVP (DT)
+ pstate: 80000005 (Nzcv daif -PAN -UAO)
+ pc : __pci_enable_msix_range+0x4e4/0x608
+ lr : __pci_enable_msix_range+0x498/0x608
+ sp : ffffff80117db700
+ x29: ffffff80117db700 x28: 0000000000000001
+ x27: 0000000000000001 x26: 0000000000000000
+ x25: ffffffd3e9d8c0b0 x24: 0000000000000000
+ x23: 0000000000000000 x22: 0000000000000000
+ x21: 0000000000000001 x20: 0000000000000000
+ x19: ffffffd3e9d8c000 x18: ffffffffffffffff
+ x17: 0000000000000000 x16: 0000000000000000
+ x15: ffffff80116496c8 x14: ffffffd3e9844503
+ x13: ffffffd3e9844502 x12: 0000000000000038
+ x11: ffffffffffffff00 x10: 0000000000000040
+ x9 : ffffff801165e270 x8 : ffffff801165e268
+ x7 : 0000000000000002 x6 : 00000000000000b2
+ x5 : ffffffd3e9d8c2c0 x4 : 0000000000000000
+ x3 : 0000000000000000 x2 : 0000000000000000
+ x1 : 0000000000000000 x0 : ffffffd3e9844680
+ Kernel panic - not syncing: Asynchronous SError Interrupt
+ CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
+ Hardware name: Annapurna Labs Alpine V3 EVP (DT)
+ Call trace:
+ dump_backtrace+0x0/0x140
+ show_stack+0x14/0x20
+ dump_stack+0xa8/0xcc
+ panic+0x140/0x334
+ nmi_panic+0x6c/0x70
+ arm64_serror_panic+0x74/0x88
+ __pte_error+0x0/0x28
+ el1_error+0x84/0xf8
+ __pci_enable_msix_range+0x4e4/0x608
+ pci_alloc_irq_vectors_affinity+0xdc/0x150
+ pcie_port_device_register+0x2b8/0x4e0
+ pcie_portdrv_probe+0x34/0xf0
+
+Notice that this quirk also disables MSI (which may work, but hasn't
+been tested nor has a current use case), since currently there is no
+standard way to disable only MSI-X.
+
+Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
+---
+ drivers/pci/quirks.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index e96c03b4e494..44524d351a26 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -2925,6 +2925,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
+ quirk_msi_intx_disable_qca_bug);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
+ quirk_msi_intx_disable_qca_bug);
++
++/*
++ * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
++ * should be disabled on platforms where the device (mistakenly) advertises it.
++ *
++ * Notice that this quirk also disables MSI (which may work, but hasn't been
++ * tested), since currently there is no standard way to disable only MSI-X.
++ *
++ * The 0031 device id is reused for other non Root Port device types,
++ * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
++ */
++static void quirk_al_msi_disable(struct pci_dev *dev)
++{
++ dev->no_msi = 1;
++ pci_warn(dev, "Disabling MSI/MSI-X\n");
++}
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
++ PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
+ #endif /* CONFIG_PCI_MSI */
+
+ /*
+--
+2.16.4
+
diff --git a/patches.suse/PCI-VPD-Prevent-VPD-access-for-Amazon-s-Annapurna-La.patch b/patches.suse/PCI-VPD-Prevent-VPD-access-for-Amazon-s-Annapurna-La.patch
new file mode 100644
index 0000000000..aabcab2e57
--- /dev/null
+++ b/patches.suse/PCI-VPD-Prevent-VPD-access-for-Amazon-s-Annapurna-La.patch
@@ -0,0 +1,46 @@
+From: Jonathan Chocron <jonnyc@amazon.com>
+Date: Thu, 12 Sep 2019 16:00:41 +0300
+Subject: PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port
+
+Git-commit: a638b5de205af40bdadd867b1cb77320bbb2628e
+Patch-mainline: v5.4-rc1
+References: bsc#1152187,bsc#1152525
+
+The Amazon Annapurna Labs PCIe Root Port exposes the VPD capability,
+but there is no actual support for it.
+
+Trying to access the VPD (for example, as part of lspci -vv or when
+reading the vpd sysfs file), results in the following warning print:
+
+ pcieport 0001:00:00.0: VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update
+
+Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
+---
+ drivers/pci/vpd.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c
+index 4963c2e2bd4c..7915d10f9aa1 100644
+--- a/drivers/pci/vpd.c
++++ b/drivers/pci/vpd.c
+@@ -571,6 +571,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
+ quirk_blacklist_vpd);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
++/*
++ * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
++ * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
++ */
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
++ PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
+
+ /*
+ * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
+--
+2.16.4
+
diff --git a/patches.suse/0021-PCI-mobiveil-add-Byte-and-Half-Word-width-register-a.patch b/patches.suse/PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch
index ff0200c016..6a4bb828fd 100644
--- a/patches.suse/0021-PCI-mobiveil-add-Byte-and-Half-Word-width-register-a.patch
+++ b/patches.suse/PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch
@@ -1,29 +1,26 @@
-From 2d79eed9dabe1d9f1ceaf736d70ee9725c9794a2 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:36 +0000
-Subject: [PATCH 21/26] PCI: mobiveil: add Byte and Half-Word width register
- accessors
+Date: Tue, 13 Aug 2019 11:04:18 +0000
+Subject: PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
+Patch-mainline: Submitted, https://lkml.org/lkml/2019/8/13/483
References: fate#326572
-As there are some Byte and Half-Work width registers in PCIe
-configuration space, add Byte and Half-Word width register
-accessors.
+There are some 8-bit and 16-bit registers in PCIe configuration
+space, so add these accessors accordingly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 20 ++++++++++++++++++++
+ drivers/pci/controller/mobiveil/pcie-mobiveil.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index 81685840b378..933c2f34bc52 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
+diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+index 4f17a9837fe9..8c07f69e0330 100644
+--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+@@ -182,9 +182,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
return csr_read(pcie, off, 0x4);
}
@@ -54,5 +51,5 @@ index 81685840b378..933c2f34bc52 100644
+
#endif /* _PCIE_MOBIVEIL_H */
--
-2.11.0
+2.16.4
diff --git a/patches.suse/0024-PCI-mobiveil-add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch b/patches.suse/PCI-mobiveil-Add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch
index c13ae079d7..4968e05733 100644
--- a/patches.suse/0024-PCI-mobiveil-add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch
+++ b/patches.suse/PCI-mobiveil-Add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch
@@ -1,13 +1,11 @@
-From 7bded81e007e73cf519da680ae668540ca7a6528 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:55 +0000
-Subject: [PATCH 24/26] PCI: mobiveil: add PCIe Gen4 RC driver for NXP
- Layerscape SoCs
+Date: Tue, 13 Aug 2019 11:04:26 +0000
+Subject: PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
+Patch-mainline: Submitted, https://lkml.org/lkml/2019/8/13/484
References: fate#326572
This PCIe controller is based on the Mobiveil GPEX IP, which is
@@ -17,23 +15,23 @@ Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
- drivers/pci/host/mobiveil/Kconfig | 10 +
- drivers/pci/host/mobiveil/Makefile | 1 +
- drivers/pci/host/mobiveil/pci-layerscape-gen4.c | 254 ++++++++++++++++++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 16 +-
- 4 files changed, 279 insertions(+), 2 deletions(-)
- create mode 100644 drivers/pci/host/mobiveil/pci-layerscape-gen4.c
+ drivers/pci/controller/mobiveil/Kconfig | 10 +
+ drivers/pci/controller/mobiveil/Makefile | 1 +
+ .../pci/controller/mobiveil/pcie-layerscape-gen4.c | 274 +++++++++++++++++++++
+ drivers/pci/controller/mobiveil/pcie-mobiveil.h | 16 +-
+ 4 files changed, 299 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
-diff --git a/drivers/pci/host/mobiveil/Kconfig b/drivers/pci/host/mobiveil/Kconfig
-index 64343c07bfed..3ddb7d6163a9 100644
---- a/drivers/pci/host/mobiveil/Kconfig
-+++ b/drivers/pci/host/mobiveil/Kconfig
+diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig
+index 64343c07bfed..c823be8dab1c 100644
+--- a/drivers/pci/controller/mobiveil/Kconfig
++++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
Soft IP. It has up to 8 outbound and inbound windows
for address translation and it is a PCIe Gen4 IP.
-+config PCI_LAYERSCAPE_GEN4
-+ bool "Freescale Layerscpe PCIe Gen4 controller"
++config PCIE_LAYERSCAPE_GEN4
++ bool "Freescale Layerscape PCIe Gen4 controller"
+ depends on PCI
+ depends on OF && (ARM64 || ARCH_LAYERSCAPE)
+ depends on PCI_MSI_IRQ_DOMAIN
@@ -43,26 +41,26 @@ index 64343c07bfed..3ddb7d6163a9 100644
+ Layerscape SoCs. The PCIe controller can work in RC or
+ EP mode according to RCW[HOST_AGT_PEX] setting.
endmenu
-diff --git a/drivers/pci/host/mobiveil/Makefile b/drivers/pci/host/mobiveil/Makefile
-index 9fb6d1c6504d..ff66774ccac4 100644
---- a/drivers/pci/host/mobiveil/Makefile
-+++ b/drivers/pci/host/mobiveil/Makefile
+diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile
+index 9fb6d1c6504d..99d879de32d6 100644
+--- a/drivers/pci/controller/mobiveil/Makefile
++++ b/drivers/pci/controller/mobiveil/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
-+obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
-diff --git a/drivers/pci/host/mobiveil/pci-layerscape-gen4.c b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
++obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
+diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
new file mode 100644
-index 000000000000..174cbcac4059
+index 000000000000..1c4663a359d2
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/pci-layerscape-gen4.c
-@@ -0,0 +1,254 @@
++++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
+@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
-+ * PCIe host controller driver for NXP Layerscape SoCs
++ * PCIe Gen4 host controller driver for NXP Layerscape SoCs
+ *
-+ * Copyright 2018 NXP
++ * Copyright 2019 NXP
+ *
+ * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
+ */
@@ -83,51 +81,50 @@ index 000000000000..174cbcac4059
+#include "pcie-mobiveil.h"
+
+/* LUT and PF control registers */
-+#define PCIE_LUT_OFF (0x80000)
-+#define PCIE_PF_OFF (0xc0000)
-+#define PCIE_PF_INT_STAT (0x18)
-+#define PF_INT_STAT_PABRST (31)
++#define PCIE_LUT_OFF 0x80000
++#define PCIE_PF_OFF 0xc0000
++#define PCIE_PF_INT_STAT 0x18
++#define PF_INT_STAT_PABRST BIT(31)
+
-+#define PCIE_PF_DBG (0x7fc)
-+#define PF_DBG_LTSSM_MASK (0x3f)
-+#define PF_DBG_WE (31)
-+#define PF_DBG_PABR (27)
-+
-+#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */
++#define PCIE_PF_DBG 0x7fc
++#define PF_DBG_LTSSM_MASK 0x3f
++#define PF_DBG_LTSSM_L0 0x2d /* L0 state */
++#define PF_DBG_WE BIT(31)
++#define PF_DBG_PABR BIT(27)
+
+#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
+
+struct ls_pcie_g4 {
-+ struct mobiveil_pcie *pci;
++ struct mobiveil_pcie pci;
+ struct delayed_work dwork;
+ int irq;
+};
+
+static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
+{
-+ return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
++ return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
+static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
+ u32 off, u32 val)
+{
-+ iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
++ iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
+static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
+{
-+ return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
++ return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
+}
+
+static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
+ u32 off, u32 val)
+{
-+ iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
++ iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
+}
+
+static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
+{
-+ struct mobiveil_pcie *mv_pci = pcie->pci;
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
+ u32 header_type;
+
+ header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
@@ -144,15 +141,36 @@ index 000000000000..174cbcac4059
+ state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
+ state = state & PF_DBG_LTSSM_MASK;
+
-+ if (state == LS_PCIE_G4_LTSSM_L0)
++ if (state == PF_DBG_LTSSM_L0)
+ return 1;
+
+ return 0;
+}
+
++static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie)
++{
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
++
++ csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB);
++}
++
++static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie)
++{
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
++ u32 val;
++
++ /* Clear the interrupt status */
++ csr_writel(mv_pci, 0xffffffff, PAB_INTP_AMBA_MISC_STAT);
++
++ val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
++ PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
++ csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
++}
++
+static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
+{
-+ struct mobiveil_pcie *mv_pci = pcie->pci;
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
++ struct device *dev = &mv_pci->pdev->dev;
+ u32 val, act_stat;
+ int to = 100;
+
@@ -161,23 +179,23 @@ index 000000000000..174cbcac4059
+ usleep_range(10, 15);
+ val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
+ act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
-+ } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
++ } while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
+ if (to < 0) {
-+ dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n");
++ dev_err(dev, "Poll PABRST&PABACT timeout\n");
+ return;
+ }
+
+ /* clear PEX_RESET bit in PEX_PF0_DBG register */
+ val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
-+ val |= 1 << PF_DBG_WE;
++ val |= PF_DBG_WE;
+ ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
+
+ val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
-+ val |= 1 << PF_DBG_PABR;
++ val |= PF_DBG_PABR;
+ ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
+
+ val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
-+ val &= ~(1 << PF_DBG_WE);
++ val &= ~PF_DBG_WE;
+ ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
+
+ mobiveil_host_init(mv_pci, true);
@@ -186,21 +204,23 @@ index 000000000000..174cbcac4059
+ while (!ls_pcie_g4_link_up(mv_pci) && to--)
+ usleep_range(200, 250);
+ if (to < 0)
-+ dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n");
++ dev_err(dev, "PCIe link training timeout\n");
+}
+
-+static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id)
++static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id)
+{
+ struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;
-+ struct mobiveil_pcie *mv_pci = pcie->pci;
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
+ u32 val;
+
+ val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT);
+ if (!val)
+ return IRQ_NONE;
+
-+ if (val & PAB_INTP_RESET)
++ if (val & PAB_INTP_RESET) {
++ ls_pcie_g4_disable_interrupt(pcie);
+ schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));
++ }
+
+ csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT);
+
@@ -210,27 +230,22 @@ index 000000000000..174cbcac4059
+static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci)
+{
+ struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);
-+ u32 val;
++ struct platform_device *pdev = mv_pci->pdev;
++ struct device *dev = &pdev->dev;
+ int ret;
+
-+ pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr");
++ pcie->irq = platform_get_irq_byname(pdev, "intr");
+ if (pcie->irq < 0) {
-+ dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n");
++ dev_err(dev, "Can't get 'intr' IRQ, errno = %d\n", pcie->irq);
+ return pcie->irq;
+ }
-+ ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq,
-+ ls_pcie_g4_handler, IRQF_SHARED,
-+ mv_pci->pdev->name, pcie);
++ ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr,
++ IRQF_SHARED, pdev->name, pcie);
+ if (ret) {
-+ dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n");
++ dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret);
+ return ret;
+ }
+
-+ /* Enable interrupts */
-+ val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
-+ PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
-+ csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
-+
+ return 0;
+}
+
@@ -239,13 +254,14 @@ index 000000000000..174cbcac4059
+ struct delayed_work *dwork = container_of(work, struct delayed_work,
+ work);
+ struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);
-+ struct mobiveil_pcie *mv_pci = pcie->pci;
++ struct mobiveil_pcie *mv_pci = &pcie->pci;
+ u16 ctrl;
+
+ ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL);
+ ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
+ ls_pcie_g4_reinit_hw(pcie);
++ ls_pcie_g4_enable_interrupt(pcie);
+}
+
+static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
@@ -259,28 +275,28 @@ index 000000000000..174cbcac4059
+static int __init ls_pcie_g4_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
++ struct pci_host_bridge *bridge;
+ struct mobiveil_pcie *mv_pci;
+ struct ls_pcie_g4 *pcie;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ if (!of_parse_phandle(np, "msi-parent", 0)) {
-+ dev_err(dev, "failed to find msi-parent\n");
++ dev_err(dev, "Failed to find msi-parent\n");
+ return -EINVAL;
+ }
+
-+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
-+ if (!pcie)
++ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
++ if (!bridge)
+ return -ENOMEM;
+
-+ mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
-+ if (!mv_pci)
-+ return -ENOMEM;
++ pcie = pci_host_bridge_priv(bridge);
++ mv_pci = &pcie->pci;
+
+ mv_pci->pdev = pdev;
+ mv_pci->ops = &ls_pcie_g4_pab_ops;
+ mv_pci->rp.ops = &ls_pcie_g4_rp_ops;
-+ pcie->pci = mv_pci;
++ mv_pci->bridge = bridge;
+
+ platform_set_drvdata(pdev, pcie);
+
@@ -288,13 +304,15 @@ index 000000000000..174cbcac4059
+
+ ret = mobiveil_pcie_host_probe(mv_pci);
+ if (ret) {
-+ dev_err(dev, "fail to probe!\n");
++ dev_err(dev, "Fail to probe\n");
+ return ret;
+ }
+
+ if (!ls_pcie_g4_is_bridge(pcie))
+ return -ENODEV;
+
++ ls_pcie_g4_enable_interrupt(pcie);
++
+ return 0;
+}
+
@@ -312,11 +330,11 @@ index 000000000000..174cbcac4059
+};
+
+builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index 0f5303962e88..0ccd6cee5f8f 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -41,6 +41,8 @@
+diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+index 8c07f69e0330..1ca8cd00ae56 100644
+--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+@@ -43,6 +43,8 @@
#define PAGE_LO_MASK 0x3ff
#define PAGE_SEL_OFFSET_SHIFT 10
@@ -325,21 +343,21 @@ index 0f5303962e88..0ccd6cee5f8f 100644
#define PAB_AXI_PIO_CTRL 0x0840
#define APIO_EN_MASK 0xf
-@@ -49,8 +51,18 @@
+@@ -51,8 +53,18 @@
#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
-#define PAB_INTP_INTX_MASK 0x01e0
-#define PAB_INTP_MSI_MASK 0x8
-+#define PAB_INTP_RESET (0x1 << 1)
-+#define PAB_INTP_MSI (0x1 << 3)
-+#define PAB_INTP_INTA (0x1 << 5)
-+#define PAB_INTP_INTB (0x1 << 6)
-+#define PAB_INTP_INTC (0x1 << 7)
-+#define PAB_INTP_INTD (0x1 << 8)
-+#define PAB_INTP_PCIE_UE (0x1 << 9)
-+#define PAB_INTP_IE_PMREDI (0x1 << 29)
-+#define PAB_INTP_IE_EC (0x1 << 30)
++#define PAB_INTP_RESET BIT(1)
++#define PAB_INTP_MSI BIT(3)
++#define PAB_INTP_INTA BIT(5)
++#define PAB_INTP_INTB BIT(6)
++#define PAB_INTP_INTC BIT(7)
++#define PAB_INTP_INTD BIT(8)
++#define PAB_INTP_PCIE_UE BIT(9)
++#define PAB_INTP_IE_PMREDI BIT(29)
++#define PAB_INTP_IE_EC BIT(30)
+#define PAB_INTP_MSI_MASK PAB_INTP_MSI
+#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
+ PAB_INTP_INTC | PAB_INTP_INTD)
@@ -347,5 +365,5 @@ index 0f5303962e88..0ccd6cee5f8f 100644
#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
#define WIN_ENABLE_SHIFT 0
--
-2.11.0
+2.16.4
diff --git a/patches.suse/PCI-mobiveil-Fix-the-CPU-base-address-setup-in-inbou.patch b/patches.suse/PCI-mobiveil-Fix-the-CPU-base-address-setup-in-inbou.patch
new file mode 100644
index 0000000000..de492f6506
--- /dev/null
+++ b/patches.suse/PCI-mobiveil-Fix-the-CPU-base-address-setup-in-inbou.patch
@@ -0,0 +1,75 @@
+From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Date: Sat, 13 Jul 2019 22:11:29 +0800
+Subject: PCI: mobiveil: Fix the CPU base address setup in inbound window
+
+Git-commit: df901c85cc28b538c62f6bc20b16a8bd05fcb756
+Patch-mainline: Queued
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
+References: fate#326572
+
+Current code erroneously sets-up the CPU base address through the
+parameter 'pci_addr', which is passed to initialize the CPU (AXI) base
+address of the inbound window where the controller maps the PCI address
+space into CPU physical address space; furthermore, it also truncates it
+by programming only the lower 32-bit value into the inbound CPU address
+register.
+
+Fix both issues by introducing a new parameter 'u64 cpu_addr' to
+initialize both lower 32-bit and upper 32-bit of the CPU physical
+base address mapping PCI inbound transactions into CPU (AXI) ones.
+
+Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/pci/controller/pcie-mobiveil.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
+index 672e633601c7..a45a6447b01d 100644
+--- a/drivers/pci/controller/pcie-mobiveil.c
++++ b/drivers/pci/controller/pcie-mobiveil.c
+@@ -88,6 +88,7 @@
+ #define AMAP_CTRL_TYPE_MASK 3
+
+ #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
++#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
+ #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
+ #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
+ #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
+@@ -462,7 +463,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
+ }
+
+ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
+- u64 pci_addr, u32 type, u64 size)
++ u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
+ {
+ u32 value;
+ u64 size64 = ~(size - 1);
+@@ -482,7 +483,10 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
+ csr_writel(pcie, upper_32_bits(size64),
+ PAB_EXT_PEX_AMAP_SIZEN(win_num));
+
+- csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
++ csr_writel(pcie, lower_32_bits(cpu_addr),
++ PAB_PEX_AMAP_AXI_WIN(win_num));
++ csr_writel(pcie, upper_32_bits(cpu_addr),
++ PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
+
+ csr_writel(pcie, lower_32_bits(pci_addr),
+ PAB_PEX_AMAP_PEX_WIN_L(win_num));
+@@ -624,7 +628,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
+ CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
+
+ /* memory inbound translation window */
+- program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
++ program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
+
+ /* Get the I/O and memory ranges from DT */
+ resource_list_for_each_entry(win, &pcie->resources) {
+--
+2.16.4
+
diff --git a/patches.suse/0022-PCI-mobiveil-make-mobiveil_host_init-can-be-used-to-.patch b/patches.suse/PCI-mobiveil-Make-mobiveil_host_init-can-be-used-to-.patch
index 334db2288c..9242a5ed63 100644
--- a/patches.suse/0022-PCI-mobiveil-make-mobiveil_host_init-can-be-used-to-.patch
+++ b/patches.suse/PCI-mobiveil-Make-mobiveil_host_init-can-be-used-to-.patch
@@ -1,30 +1,28 @@
-From 12dadc46951d067f258db07bc15fc25bb570d7ea Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:42 +0000
-Subject: [PATCH 22/26] PCI: mobiveil: make mobiveil_host_init can be used to
- re-init host
+Date: Tue, 13 Aug 2019 11:04:04 +0000
+Subject: PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
+Patch-mainline: Submitted, https://lkml.org/lkml/2019/8/13/481
References: fate#326572
-Make the mobiveil_host_init function can be used to re-init
+Make the mobiveil_host_init() function can be used to re-init
host controller's PAB and GPEX CSR register block, as NXP
integrated Mobiveil IP has to reset and then re-init the PAB
-and GPEX CSR registers upon Hot-reset.
+and GPEX CSR registers upon hot-reset.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 41 +++++++++++++-------------
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 3 +-
- 2 files changed, 23 insertions(+), 21 deletions(-)
+ .../pci/controller/mobiveil/pcie-mobiveil-host.c | 43 +++++++++++-----------
+ drivers/pci/controller/mobiveil/pcie-mobiveil.h | 3 +-
+ 2 files changed, 24 insertions(+), 22 deletions(-)
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-index a42ff86e800c..bc3c49e695fa 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -217,7 +217,7 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
+diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+index 995487c4f760..775754522363 100644
+--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+@@ -215,16 +215,21 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
}
@@ -33,9 +31,6 @@ index a42ff86e800c..bc3c49e695fa 100644
{
u32 value, pab_ctrl, type;
struct resource_entry *win;
-@@ -229,11 +229,16 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
- for (i = 0; i < pcie->ppio_wins; i++)
- mobiveil_pcie_disable_ib_win(pcie, i);
- /* setup bus numbers */
- value = csr_readl(pcie, PCI_PRIMARY_BUS);
@@ -55,7 +50,7 @@ index a42ff86e800c..bc3c49e695fa 100644
/*
* program Bus Master Enable Bit in Command Register in PAB Config
-@@ -279,7 +284,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
+@@ -270,7 +275,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
/* Get the I/O and memory ranges from DT */
@@ -64,7 +59,7 @@ index a42ff86e800c..bc3c49e695fa 100644
if (resource_type(win->res) == IORESOURCE_MEM) {
type = MEM_WINDOW_TYPE;
} else if (resource_type(win->res) == IORESOURCE_IO) {
-@@ -550,8 +555,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
+@@ -541,8 +546,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
resource_size_t iobase;
int ret;
@@ -73,7 +68,7 @@ index a42ff86e800c..bc3c49e695fa 100644
ret = mobiveil_pcie_parse_dt(pcie);
if (ret) {
dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
-@@ -565,34 +568,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
+@@ -551,34 +554,35 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
/* parse the host bridge base addresses from the device tree file */
ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
@@ -116,7 +111,14 @@ index a42ff86e800c..bc3c49e695fa 100644
bridge->dev.parent = dev;
bridge->sysdata = pcie;
bridge->busnr = pcie->rp.root_bus_nr;
-@@ -608,7 +612,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
+@@ -589,13 +593,13 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
+ ret = mobiveil_bringup_link(pcie);
+ if (ret) {
+ dev_info(dev, "link bring-up failed\n");
+- goto error;
++ return ret;
+ }
+
/* setup the kernel resources for the newly added PCIe root bus */
ret = pci_scan_root_bus_bridge(bridge);
if (ret)
@@ -125,7 +127,7 @@ index a42ff86e800c..bc3c49e695fa 100644
bus = bridge->bus;
-@@ -618,7 +622,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
+@@ -605,7 +609,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
pci_bus_add_devices(bus);
return 0;
@@ -133,11 +135,11 @@ index a42ff86e800c..bc3c49e695fa 100644
- pci_free_resource_list(&pcie->resources);
- return ret;
}
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-index 933c2f34bc52..0f5303962e88 100644
---- a/drivers/pci/host/mobiveil/pcie-mobiveil.h
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -152,7 +152,7 @@ struct mobiveil_pab_ops {
+diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+index 4825e30030cd..4f17a9837fe9 100644
+--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+@@ -153,7 +153,7 @@ struct mobiveil_pab_ops {
struct mobiveil_pcie {
struct platform_device *pdev;
@@ -146,7 +148,7 @@ index 933c2f34bc52..0f5303962e88 100644
void __iomem *csr_axi_slave_base; /* PAB registers base */
phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
void __iomem *apb_csr_base; /* MSI register base */
-@@ -165,6 +165,7 @@ struct mobiveil_pcie {
+@@ -167,6 +167,7 @@ struct mobiveil_pcie {
};
int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
@@ -155,5 +157,5 @@ index 933c2f34bc52..0f5303962e88 100644
int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
--
-2.11.0
+2.16.4
diff --git a/patches.suse/0017-PCI-mobiveil-refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch b/patches.suse/PCI-mobiveil-Refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch
index 5cb44eafa9..f3963f41e0 100644
--- a/patches.suse/0017-PCI-mobiveil-refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch
+++ b/patches.suse/PCI-mobiveil-Refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch
@@ -1,61 +1,68 @@
-From f168cc364bc09247ceeb469f3a3d7f9a5352cb5a Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Date: Tue, 29 Jan 2019 08:10:11 +0000
-Subject: [PATCH 17/26] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP
- driver
+Date: Tue, 13 Aug 2019 11:03:57 +0000
+Subject: PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver
-Patch-mainline: Submitted, https://patchwork.kernel.org/cover/10785657/
+Patch-mainline: Submitted, https://lkml.org/lkml/2019/8/13/480
References: fate#326572
-As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
-make platforms which integrated the Mobiveil PCIe IP more easy
-to add their drivers, this patch moved the Mobiveil driver to
-a new directory 'drivers/pci/host/mobiveil' and refactored
-it according to the abstraction of RC&EP (EP driver will be added
-later).
+Refactor the Mobiveil PCIe Host Bridge IP driver to make
+it easier to add support for both RC and EP mode driver.
+This patch moved the Mobiveil driver to an new directory
+'drivers/pci/controller/mobiveil' and refactor it according
+to the RC and EP abstraction.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
- MAINTAINERS | 2 +-
- drivers/pci/host/Kconfig | 11 +-
- drivers/pci/host/Makefile | 2 +-
- drivers/pci/host/mobiveil/Kconfig | 24 +
- drivers/pci/host/mobiveil/Makefile | 4 +
- drivers/pci/host/mobiveil/pcie-mobiveil-host.c | 614 +++++++++++++++++++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil-plat.c | 54 +++
- drivers/pci/host/mobiveil/pcie-mobiveil.c | 228 +++++++++
- drivers/pci/host/mobiveil/pcie-mobiveil.h | 187 ++++++++
- 9 files changed, 1114 insertions(+), 12 deletions(-)
- create mode 100644 drivers/pci/host/mobiveil/Kconfig
- create mode 100644 drivers/pci/host/mobiveil/Makefile
- create mode 100644 drivers/pci/host/mobiveil/pcie-mobiveil-host.c
- create mode 100644 drivers/pci/host/mobiveil/pcie-mobiveil-plat.c
- create mode 100644 drivers/pci/host/mobiveil/pcie-mobiveil.c
- create mode 100644 drivers/pci/host/mobiveil/pcie-mobiveil.h
+ MAINTAINERS | 2
+ arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2
+ drivers/pci/controller/Kconfig | 11
+ drivers/pci/controller/Makefile | 2
+ drivers/pci/controller/mobiveil/Kconfig | 24
+ drivers/pci/controller/mobiveil/Makefile | 4
+ drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 611 ++++++++++++
+ drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c | 59 +
+ drivers/pci/controller/mobiveil/pcie-mobiveil.c | 227 ++++
+ drivers/pci/controller/mobiveil/pcie-mobiveil.h | 189 +++
+ drivers/pci/controller/pcie-mobiveil.c | 964 -------------------
+ 11 files changed, 1118 insertions(+), 977 deletions(-)
+ create mode 100644 drivers/pci/controller/mobiveil/Kconfig
+ create mode 100644 drivers/pci/controller/mobiveil/Makefile
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h
+ delete mode 100644 drivers/pci/controller/pcie-mobiveil.c
-diff --git a/MAINTAINERS b/MAINTAINERS
-index 00fcfa67069f..ed81cf1c6e7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -10002,7 +10002,7 @@ M: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+@@ -12341,7 +12341,7 @@ M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
L: linux-pci@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
-F: drivers/pci/controller/pcie-mobiveil.c
-+F: drivers/pci/host/mobiveil/pcie-mobiveil*
++F: drivers/pci/controller/mobiveil/pcie-mobiveil*
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
- M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
-index dfefe4212647..b5f904dbcc2d 100644
---- a/drivers/pci/host/Kconfig
-+++ b/drivers/pci/host/Kconfig
-@@ -180,16 +180,6 @@ config PCIE_ROCKCHIP
- There is 1 internal PCIe port available to support GEN2 with
- 4 slots.
+ M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
+--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+@@ -7,7 +7,7 @@
+ #include "tegra186-p3310.dtsi"
+
+ / {
+- model = "NVIDIA Jetson TX2 Developer Kit";
++ model = "NVIDIA Jetson TX2 Developer Kit dtb:next-20190925+sram-fix-2";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+ aconnect {
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -241,16 +241,6 @@ config PCIE_MEDIATEK
+ Say Y here if you want to enable PCIe controller support on
+ MediaTek SoCs.
-config PCIE_MOBIVEIL
- bool "Mobiveil AXI PCIe controller"
@@ -67,34 +74,32 @@ index dfefe4212647..b5f904dbcc2d 100644
- Soft IP. It has up to 8 outbound and inbound windows
- for address translation and it is a PCIe Gen4 IP.
-
- config VMD
- depends on PCI_MSI && X86_64 && SRCU
- tristate "Intel Volume Management Device Driver"
-@@ -206,4 +196,5 @@ config VMD
- To compile this driver as a module, choose M here: the
+ config PCIE_TANGO_SMP8759
+ bool "Tango SMP8759 PCIe controller (DANGEROUS)"
+ depends on ARCH_TANGO && PCI_MSI && OF
+@@ -282,4 +272,5 @@ config VMD
module will be called vmd.
-+source "drivers/pci/host/mobiveil/Kconfig"
+ source "drivers/pci/controller/dwc/Kconfig"
++source "drivers/pci/controller/mobiveil/Kconfig"
endmenu
-diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
-index 7c14e80b14b6..f433c16d1940 100644
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -18,8 +18,8 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
- obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
- obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
- obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -26,11 +26,11 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rock
+ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
+ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
+ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
-obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
+ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
+ # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+ obj-y += dwc/
+obj-y += mobiveil/
+
# The following drivers are for devices that use the generic ACPI
- # pci_root.c driver but don't support standard ECAM config access.
-diff --git a/drivers/pci/host/mobiveil/Kconfig b/drivers/pci/host/mobiveil/Kconfig
-new file mode 100644
-index 000000000000..64343c07bfed
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/Kconfig
++++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0
+
@@ -120,27 +125,23 @@ index 000000000000..64343c07bfed
+ for address translation and it is a PCIe Gen4 IP.
+
+endmenu
-diff --git a/drivers/pci/host/mobiveil/Makefile b/drivers/pci/host/mobiveil/Makefile
-new file mode 100644
-index 000000000000..9fb6d1c6504d
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/Makefile
++++ b/drivers/pci/controller/mobiveil/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
+obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
+obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-host.c b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-new file mode 100644
-index 000000000000..dc5324d94466
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-host.c
-@@ -0,0 +1,614 @@
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Mobiveil PCIe Host controller
+ *
+ * Copyright (c) 2018 Mobiveil Inc.
++ * Copyright 2019 NXP
++ *
+ * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+ * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
+ */
@@ -175,7 +176,7 @@ index 000000000000..dc5324d94466
+ * Do not read more than one device on the bus directly
+ * attached to RC
+ */
-+ if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
++ if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
+ return false;
+
+ return true;
@@ -186,7 +187,7 @@ index 000000000000..dc5324d94466
+ * root port or endpoint
+ */
+static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
-+ unsigned int devfn, int where)
++ unsigned int devfn, int where)
+{
+ struct mobiveil_pcie *pcie = bus->sysdata;
+ u32 value;
@@ -672,7 +673,7 @@ index 000000000000..dc5324d94466
+{
+ struct pci_bus *bus;
+ struct pci_bus *child;
-+ struct pci_host_bridge *bridge;
++ struct pci_host_bridge *bridge = pcie->bridge;
+ struct device *dev = &pcie->pdev->dev;
+ resource_size_t iobase;
+ int ret;
@@ -685,11 +686,6 @@ index 000000000000..dc5324d94466
+ return ret;
+ }
+
-+ /* allocate the PCIe port */
-+ bridge = devm_pci_alloc_host_bridge(dev, 0);
-+ if (!bridge)
-+ return -ENOMEM;
-+
+ /* parse the host bridge base addresses from the device tree file */
+ ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
+ &pcie->resources, &iobase);
@@ -750,17 +746,16 @@ index 000000000000..dc5324d94466
+ pci_free_resource_list(&pcie->resources);
+ return ret;
+}
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil-plat.c b/drivers/pci/host/mobiveil/pcie-mobiveil-plat.c
-new file mode 100644
-index 000000000000..216c62f35568
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil-plat.c
-@@ -0,0 +1,54 @@
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c
+@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Mobiveil PCIe Host controller
+ *
+ * Copyright (c) 2018 Mobiveil Inc.
++ * Copyright 2019 NXP
++ *
+ * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+ * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
+ */
@@ -778,12 +773,15 @@ index 000000000000..216c62f35568
+static int mobiveil_pcie_probe(struct platform_device *pdev)
+{
+ struct mobiveil_pcie *pcie;
++ struct pci_host_bridge *bridge;
+ struct device *dev = &pdev->dev;
+
-+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
-+ if (!pcie)
++ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
++ if (!bridge)
+ return -ENOMEM;
+
++ pcie = pci_host_bridge_priv(bridge);
++
+ pcie->pdev = pdev;
+
+ return mobiveil_pcie_host_probe(pcie);
@@ -810,17 +808,16 @@ index 000000000000..216c62f35568
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
+MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.c b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-new file mode 100644
-index 000000000000..ee678a60825d
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.c
-@@ -0,0 +1,228 @@
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Mobiveil PCIe Host controller
+ *
+ * Copyright (c) 2018 Mobiveil Inc.
++ * Copyright 2019 NXP
++ *
+ * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+ * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
+ */
@@ -960,10 +957,9 @@ index 000000000000..ee678a60825d
+ }
+
+ value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
-+ value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
-+ WIN_SIZE_MASK << WIN_SIZE_SHIFT);
-+ value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
-+ (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
++ value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
++ value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
++ (lower_32_bits(size64) & WIN_SIZE_MASK);
+ csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
+
+ csr_writel(pcie, upper_32_bits(size64),
@@ -988,7 +984,6 @@ index 000000000000..ee678a60825d
+void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
+ u64 pci_addr, u32 type, u64 size)
+{
-+
+ u32 value;
+ u64 size64 = ~(size - 1);
+
@@ -1003,10 +998,9 @@ index 000000000000..ee678a60825d
+ * to 4 KB in PAB_AXI_AMAP_CTRL register
+ */
+ value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
-+ value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
-+ WIN_SIZE_MASK << WIN_SIZE_SHIFT);
++ value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
+ value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
-+ (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
++ (lower_32_bits(size64) & WIN_SIZE_MASK);
+ csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
+
+ csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
@@ -1044,17 +1038,16 @@ index 000000000000..ee678a60825d
+
+ return -ETIMEDOUT;
+}
-diff --git a/drivers/pci/host/mobiveil/pcie-mobiveil.h b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-new file mode 100644
-index 000000000000..eb4cb61291a8
--- /dev/null
-+++ b/drivers/pci/host/mobiveil/pcie-mobiveil.h
-@@ -0,0 +1,187 @@
++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PCIe host controller driver for Mobiveil PCIe Host controller
+ *
+ * Copyright (c) 2018 Mobiveil Inc.
++ * Copyright 2019 NXP
++ *
+ * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+ * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
+ */
@@ -1108,8 +1101,7 @@ index 000000000000..eb4cb61291a8
+#define WIN_ENABLE_SHIFT 0
+#define WIN_TYPE_SHIFT 1
+#define WIN_TYPE_MASK 0x3
-+#define WIN_SIZE_SHIFT 10
-+#define WIN_SIZE_MASK 0x3fffff
++#define WIN_SIZE_MASK 0xfffffc00
+
+#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
+
@@ -1214,6 +1206,7 @@ index 000000000000..eb4cb61291a8
+ u32 ib_wins_configured; /* configured inbound windows */
+ const struct mobiveil_pab_ops *ops;
+ struct root_port rp;
++ struct pci_host_bridge *bridge;
+};
+
+int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
@@ -1237,6 +1230,970 @@ index 000000000000..eb4cb61291a8
+}
+
+#endif /* _PCIE_MOBIVEIL_H */
---
-2.11.0
-
+--- a/drivers/pci/controller/pcie-mobiveil.c
++++ /dev/null
+@@ -1,964 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/*
+- * PCIe host controller driver for Mobiveil PCIe Host controller
+- *
+- * Copyright (c) 2018 Mobiveil Inc.
+- * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
+- */
+-
+-#include <linux/delay.h>
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+-#include <linux/irq.h>
+-#include <linux/irqchip/chained_irq.h>
+-#include <linux/irqdomain.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/msi.h>
+-#include <linux/of_address.h>
+-#include <linux/of_irq.h>
+-#include <linux/of_platform.h>
+-#include <linux/of_pci.h>
+-#include <linux/pci.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-
+-#include "../pci.h"
+-
+-/* register offsets and bit positions */
+-
+-/*
+- * translation tables are grouped into windows, each window registers are
+- * grouped into blocks of 4 or 16 registers each
+- */
+-#define PAB_REG_BLOCK_SIZE 16
+-#define PAB_EXT_REG_BLOCK_SIZE 4
+-
+-#define PAB_REG_ADDR(offset, win) \
+- (offset + (win * PAB_REG_BLOCK_SIZE))
+-#define PAB_EXT_REG_ADDR(offset, win) \
+- (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
+-
+-#define LTSSM_STATUS 0x0404
+-#define LTSSM_STATUS_L0_MASK 0x3f
+-#define LTSSM_STATUS_L0 0x2d
+-
+-#define PAB_CTRL 0x0808
+-#define AMBA_PIO_ENABLE_SHIFT 0
+-#define PEX_PIO_ENABLE_SHIFT 1
+-#define PAGE_SEL_SHIFT 13
+-#define PAGE_SEL_MASK 0x3f
+-#define PAGE_LO_MASK 0x3ff
+-#define PAGE_SEL_OFFSET_SHIFT 10
+-
+-#define PAB_AXI_PIO_CTRL 0x0840
+-#define APIO_EN_MASK 0xf
+-
+-#define PAB_PEX_PIO_CTRL 0x08c0
+-#define PIO_ENABLE_SHIFT 0
+-
+-#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
+-#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
+-#define PAB_INTP_INTX_MASK 0x01e0
+-#define PAB_INTP_MSI_MASK 0x8
+-
+-#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
+-#define WIN_ENABLE_SHIFT 0
+-#define WIN_TYPE_SHIFT 1
+-#define WIN_TYPE_MASK 0x3
+-#define WIN_SIZE_MASK 0xfffffc00
+-
+-#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
+-
+-#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
+-#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
+-#define AXI_WINDOW_ALIGN_MASK 3
+-
+-#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
+-#define PAB_BUS_SHIFT 24
+-#define PAB_DEVICE_SHIFT 19
+-#define PAB_FUNCTION_SHIFT 16
+-
+-#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
+-#define PAB_INTP_AXI_PIO_CLASS 0x474
+-
+-#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
+-#define AMAP_CTRL_EN_SHIFT 0
+-#define AMAP_CTRL_TYPE_SHIFT 1
+-#define AMAP_CTRL_TYPE_MASK 3
+-
+-#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
+-#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
+-#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
+-#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
+-#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
+-
+-/* starting offset of INTX bits in status register */
+-#define PAB_INTX_START 5
+-
+-/* supported number of MSI interrupts */
+-#define PCI_NUM_MSI 16
+-
+-/* MSI registers */
+-#define MSI_BASE_LO_OFFSET 0x04
+-#define MSI_BASE_HI_OFFSET 0x08
+-#define MSI_SIZE_OFFSET 0x0c
+-#define MSI_ENABLE_OFFSET 0x14
+-#define MSI_STATUS_OFFSET 0x18
+-#define MSI_DATA_OFFSET 0x20
+-#define MSI_ADDR_L_OFFSET 0x24
+-#define MSI_ADDR_H_OFFSET 0x28
+-
+-/* outbound and inbound window definitions */
+-#define WIN_NUM_0 0
+-#define WIN_NUM_1 1
+-#define CFG_WINDOW_TYPE 0
+-#define IO_WINDOW_TYPE 1
+-#define MEM_WINDOW_TYPE 2
+-#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
+-#define MAX_PIO_WINDOWS 8
+-
+-/* Parameters for the waiting for link up routine */
+-#define LINK_WAIT_MAX_RETRIES 10
+-#define LINK_WAIT_MIN 90000
+-#define LINK_WAIT_MAX 100000
+-
+-#define PAGED_ADDR_BNDRY 0xc00
+-#define OFFSET_TO_PAGE_ADDR(off) \
+- ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
+-#define OFFSET_TO_PAGE_IDX(off) \
+- ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
+-
+-struct mobiveil_msi { /* MSI information */
+- struct mutex lock; /* protect bitmap variable */
+- struct irq_domain *msi_domain;
+- struct irq_domain *dev_domain;
+- phys_addr_t msi_pages_phys;
+- int num_of_vectors;
+- DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
+-};
+-
+-struct mobiveil_pcie {
+- struct platform_device *pdev;
+- struct list_head resources;
+- void __iomem *config_axi_slave_base; /* endpoint config base */
+- void __iomem *csr_axi_slave_base; /* root port config base */
+- void __iomem *apb_csr_base; /* MSI register base */
+- phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
+- struct irq_domain *intx_domain;
+- raw_spinlock_t intx_mask_lock;
+- int irq;
+- int apio_wins;
+- int ppio_wins;
+- int ob_wins_configured; /* configured outbound windows */
+- int ib_wins_configured; /* configured inbound windows */
+- struct resource *ob_io_res;
+- char root_bus_nr;
+- struct mobiveil_msi msi;
+-};
+-
+-/*
+- * mobiveil_pcie_sel_page - routine to access paged register
+- *
+- * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
+- * for this scheme to work extracted higher 6 bits of the offset will be
+- * written to pg_sel field of PAB_CTRL register and rest of the lower 10
+- * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
+- */
+-static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
+-{
+- u32 val;
+-
+- val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
+- val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
+- val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
+-
+- writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
+-}
+-
+-static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
+-{
+- if (off < PAGED_ADDR_BNDRY) {
+- /* For directly accessed registers, clear the pg_sel field */
+- mobiveil_pcie_sel_page(pcie, 0);
+- return pcie->csr_axi_slave_base + off;
+- }
+-
+- mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
+- return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
+-}
+-
+-static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
+-{
+- if ((uintptr_t)addr & (size - 1)) {
+- *val = 0;
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- }
+-
+- switch (size) {
+- case 4:
+- *val = readl(addr);
+- break;
+- case 2:
+- *val = readw(addr);
+- break;
+- case 1:
+- *val = readb(addr);
+- break;
+- default:
+- *val = 0;
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- }
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
+-{
+- if ((uintptr_t)addr & (size - 1))
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+- switch (size) {
+- case 4:
+- writel(val, addr);
+- break;
+- case 2:
+- writew(val, addr);
+- break;
+- case 1:
+- writeb(val, addr);
+- break;
+- default:
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- }
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
+-{
+- void *addr;
+- u32 val;
+- int ret;
+-
+- addr = mobiveil_pcie_comp_addr(pcie, off);
+-
+- ret = mobiveil_pcie_read(addr, size, &val);
+- if (ret)
+- dev_err(&pcie->pdev->dev, "read CSR address failed\n");
+-
+- return val;
+-}
+-
+-static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
+-{
+- void *addr;
+- int ret;
+-
+- addr = mobiveil_pcie_comp_addr(pcie, off);
+-
+- ret = mobiveil_pcie_write(addr, size, val);
+- if (ret)
+- dev_err(&pcie->pdev->dev, "write CSR address failed\n");
+-}
+-
+-static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
+-{
+- return csr_read(pcie, off, 0x4);
+-}
+-
+-static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
+-{
+- csr_write(pcie, val, off, 0x4);
+-}
+-
+-static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
+-{
+- return (csr_readl(pcie, LTSSM_STATUS) &
+- LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
+-}
+-
+-static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
+-{
+- struct mobiveil_pcie *pcie = bus->sysdata;
+-
+- /* Only one device down on each root port */
+- if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
+- return false;
+-
+- /*
+- * Do not read more than one device on the bus directly
+- * attached to RC
+- */
+- if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))
+- return false;
+-
+- return true;
+-}
+-
+-/*
+- * mobiveil_pcie_map_bus - routine to get the configuration base of either
+- * root port or endpoint
+- */
+-static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
+- unsigned int devfn, int where)
+-{
+- struct mobiveil_pcie *pcie = bus->sysdata;
+- u32 value;
+-
+- if (!mobiveil_pcie_valid_device(bus, devfn))
+- return NULL;
+-
+- /* RC config access */
+- if (bus->number == pcie->root_bus_nr)
+- return pcie->csr_axi_slave_base + where;
+-
+- /*
+- * EP config access (in Config/APIO space)
+- * Program PEX Address base (31..16 bits) with appropriate value
+- * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
+- * Relies on pci_lock serialization
+- */
+- value = bus->number << PAB_BUS_SHIFT |
+- PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
+- PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
+-
+- csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
+-
+- return pcie->config_axi_slave_base + where;
+-}
+-
+-static struct pci_ops mobiveil_pcie_ops = {
+- .map_bus = mobiveil_pcie_map_bus,
+- .read = pci_generic_config_read,
+- .write = pci_generic_config_write,
+-};
+-
+-static void mobiveil_pcie_isr(struct irq_desc *desc)
+-{
+- struct irq_chip *chip = irq_desc_get_chip(desc);
+- struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
+- struct device *dev = &pcie->pdev->dev;
+- struct mobiveil_msi *msi = &pcie->msi;
+- u32 msi_data, msi_addr_lo, msi_addr_hi;
+- u32 intr_status, msi_status;
+- unsigned long shifted_status;
+- u32 bit, virq, val, mask;
+-
+- /*
+- * The core provides a single interrupt for both INTx/MSI messages.
+- * So we'll read both INTx and MSI status
+- */
+-
+- chained_irq_enter(chip, desc);
+-
+- /* read INTx status */
+- val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
+- mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
+- intr_status = val & mask;
+-
+- /* Handle INTx */
+- if (intr_status & PAB_INTP_INTX_MASK) {
+- shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
+- shifted_status &= PAB_INTP_INTX_MASK;
+- shifted_status >>= PAB_INTX_START;
+- do {
+- for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
+- virq = irq_find_mapping(pcie->intx_domain,
+- bit + 1);
+- if (virq)
+- generic_handle_irq(virq);
+- else
+- dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
+- bit);
+-
+- /* clear interrupt handled */
+- csr_writel(pcie, 1 << (PAB_INTX_START + bit),
+- PAB_INTP_AMBA_MISC_STAT);
+- }
+-
+- shifted_status = csr_readl(pcie,
+- PAB_INTP_AMBA_MISC_STAT);
+- shifted_status &= PAB_INTP_INTX_MASK;
+- shifted_status >>= PAB_INTX_START;
+- } while (shifted_status != 0);
+- }
+-
+- /* read extra MSI status register */
+- msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
+-
+- /* handle MSI interrupts */
+- while (msi_status & 1) {
+- msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
+-
+- /*
+- * MSI_STATUS_OFFSET register gets updated to zero
+- * once we pop not only the MSI data but also address
+- * from MSI hardware FIFO. So keeping these following
+- * two dummy reads.
+- */
+- msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
+- MSI_ADDR_L_OFFSET);
+- msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
+- MSI_ADDR_H_OFFSET);
+- dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
+- msi_data, msi_addr_hi, msi_addr_lo);
+-
+- virq = irq_find_mapping(msi->dev_domain, msi_data);
+- if (virq)
+- generic_handle_irq(virq);
+-
+- msi_status = readl_relaxed(pcie->apb_csr_base +
+- MSI_STATUS_OFFSET);
+- }
+-
+- /* Clear the interrupt status */
+- csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
+- chained_irq_exit(chip, desc);
+-}
+-
+-static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
+-{
+- struct device *dev = &pcie->pdev->dev;
+- struct platform_device *pdev = pcie->pdev;
+- struct device_node *node = dev->of_node;
+- struct resource *res;
+-
+- /* map config resource */
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+- "config_axi_slave");
+- pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
+- if (IS_ERR(pcie->config_axi_slave_base))
+- return PTR_ERR(pcie->config_axi_slave_base);
+- pcie->ob_io_res = res;
+-
+- /* map csr resource */
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+- "csr_axi_slave");
+- pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
+- if (IS_ERR(pcie->csr_axi_slave_base))
+- return PTR_ERR(pcie->csr_axi_slave_base);
+- pcie->pcie_reg_base = res->start;
+-
+- /* map MSI config resource */
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
+- pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
+- if (IS_ERR(pcie->apb_csr_base))
+- return PTR_ERR(pcie->apb_csr_base);
+-
+- /* read the number of windows requested */
+- if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
+- pcie->apio_wins = MAX_PIO_WINDOWS;
+-
+- if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
+- pcie->ppio_wins = MAX_PIO_WINDOWS;
+-
+- pcie->irq = platform_get_irq(pdev, 0);
+- if (pcie->irq <= 0) {
+- dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
+- return -ENODEV;
+- }
+-
+- return 0;
+-}
+-
+-static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
+- u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
+-{
+- u32 value;
+- u64 size64 = ~(size - 1);
+-
+- if (win_num >= pcie->ppio_wins) {
+- dev_err(&pcie->pdev->dev,
+- "ERROR: max inbound windows reached !\n");
+- return;
+- }
+-
+- value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
+- value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
+- value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
+- (lower_32_bits(size64) & WIN_SIZE_MASK);
+- csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
+-
+- csr_writel(pcie, upper_32_bits(size64),
+- PAB_EXT_PEX_AMAP_SIZEN(win_num));
+-
+- csr_writel(pcie, lower_32_bits(cpu_addr),
+- PAB_PEX_AMAP_AXI_WIN(win_num));
+- csr_writel(pcie, upper_32_bits(cpu_addr),
+- PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
+-
+- csr_writel(pcie, lower_32_bits(pci_addr),
+- PAB_PEX_AMAP_PEX_WIN_L(win_num));
+- csr_writel(pcie, upper_32_bits(pci_addr),
+- PAB_PEX_AMAP_PEX_WIN_H(win_num));
+-
+- pcie->ib_wins_configured++;
+-}
+-
+-/*
+- * routine to program the outbound windows
+- */
+-static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
+- u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
+-{
+- u32 value;
+- u64 size64 = ~(size - 1);
+-
+- if (win_num >= pcie->apio_wins) {
+- dev_err(&pcie->pdev->dev,
+- "ERROR: max outbound windows reached !\n");
+- return;
+- }
+-
+- /*
+- * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
+- * to 4 KB in PAB_AXI_AMAP_CTRL register
+- */
+- value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
+- value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
+- value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
+- (lower_32_bits(size64) & WIN_SIZE_MASK);
+- csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
+-
+- csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
+-
+- /*
+- * program AXI window base with appropriate value in
+- * PAB_AXI_AMAP_AXI_WIN0 register
+- */
+- csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
+- PAB_AXI_AMAP_AXI_WIN(win_num));
+- csr_writel(pcie, upper_32_bits(cpu_addr),
+- PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
+-
+- csr_writel(pcie, lower_32_bits(pci_addr),
+- PAB_AXI_AMAP_PEX_WIN_L(win_num));
+- csr_writel(pcie, upper_32_bits(pci_addr),
+- PAB_AXI_AMAP_PEX_WIN_H(win_num));
+-
+- pcie->ob_wins_configured++;
+-}
+-
+-static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
+-{
+- int retries;
+-
+- /* check if the link is up or not */
+- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+- if (mobiveil_pcie_link_up(pcie))
+- return 0;
+-
+- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+- }
+-
+- dev_err(&pcie->pdev->dev, "link never came up\n");
+-
+- return -ETIMEDOUT;
+-}
+-
+-static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
+-{
+- phys_addr_t msg_addr = pcie->pcie_reg_base;
+- struct mobiveil_msi *msi = &pcie->msi;
+-
+- pcie->msi.num_of_vectors = PCI_NUM_MSI;
+- msi->msi_pages_phys = (phys_addr_t)msg_addr;
+-
+- writel_relaxed(lower_32_bits(msg_addr),
+- pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
+- writel_relaxed(upper_32_bits(msg_addr),
+- pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
+- writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
+- writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
+-}
+-
+-static int mobiveil_host_init(struct mobiveil_pcie *pcie)
+-{
+- u32 value, pab_ctrl, type;
+- struct resource_entry *win;
+-
+- /* setup bus numbers */
+- value = csr_readl(pcie, PCI_PRIMARY_BUS);
+- value &= 0xff000000;
+- value |= 0x00ff0100;
+- csr_writel(pcie, value, PCI_PRIMARY_BUS);
+-
+- /*
+- * program Bus Master Enable Bit in Command Register in PAB Config
+- * Space
+- */
+- value = csr_readl(pcie, PCI_COMMAND);
+- value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+- csr_writel(pcie, value, PCI_COMMAND);
+-
+- /*
+- * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
+- * register
+- */
+- pab_ctrl = csr_readl(pcie, PAB_CTRL);
+- pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
+- csr_writel(pcie, pab_ctrl, PAB_CTRL);
+-
+- csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
+- PAB_INTP_AMBA_MISC_ENB);
+-
+- /*
+- * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
+- * PAB_AXI_PIO_CTRL Register
+- */
+- value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
+- value |= APIO_EN_MASK;
+- csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
+-
+- /* Enable PCIe PIO master */
+- value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
+- value |= 1 << PIO_ENABLE_SHIFT;
+- csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
+-
+- /*
+- * we'll program one outbound window for config reads and
+- * another default inbound window for all the upstream traffic
+- * rest of the outbound windows will be configured according to
+- * the "ranges" field defined in device tree
+- */
+-
+- /* config outbound translation window */
+- program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
+- CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
+-
+- /* memory inbound translation window */
+- program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
+-
+- /* Get the I/O and memory ranges from DT */
+- resource_list_for_each_entry(win, &pcie->resources) {
+- if (resource_type(win->res) == IORESOURCE_MEM)
+- type = MEM_WINDOW_TYPE;
+- else if (resource_type(win->res) == IORESOURCE_IO)
+- type = IO_WINDOW_TYPE;
+- else
+- continue;
+-
+- /* configure outbound translation window */
+- program_ob_windows(pcie, pcie->ob_wins_configured,
+- win->res->start,
+- win->res->start - win->offset,
+- type, resource_size(win->res));
+- }
+-
+- /* fixup for PCIe class register */
+- value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
+- value &= 0xff;
+- value |= (PCI_CLASS_BRIDGE_PCI << 16);
+- csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+-
+- /* setup MSI hardware registers */
+- mobiveil_pcie_enable_msi(pcie);
+-
+- return 0;
+-}
+-
+-static void mobiveil_mask_intx_irq(struct irq_data *data)
+-{
+- struct irq_desc *desc = irq_to_desc(data->irq);
+- struct mobiveil_pcie *pcie;
+- unsigned long flags;
+- u32 mask, shifted_val;
+-
+- pcie = irq_desc_get_chip_data(desc);
+- mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
+- raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
+- shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
+- shifted_val &= ~mask;
+- csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
+- raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
+-}
+-
+-static void mobiveil_unmask_intx_irq(struct irq_data *data)
+-{
+- struct irq_desc *desc = irq_to_desc(data->irq);
+- struct mobiveil_pcie *pcie;
+- unsigned long flags;
+- u32 shifted_val, mask;
+-
+- pcie = irq_desc_get_chip_data(desc);
+- mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
+- raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
+- shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
+- shifted_val |= mask;
+- csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
+- raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
+-}
+-
+-static struct irq_chip intx_irq_chip = {
+- .name = "mobiveil_pcie:intx",
+- .irq_enable = mobiveil_unmask_intx_irq,
+- .irq_disable = mobiveil_mask_intx_irq,
+- .irq_mask = mobiveil_mask_intx_irq,
+- .irq_unmask = mobiveil_unmask_intx_irq,
+-};
+-
+-/* routine to setup the INTx related data */
+-static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+- irq_hw_number_t hwirq)
+-{
+- irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
+- irq_set_chip_data(irq, domain->host_data);
+-
+- return 0;
+-}
+-
+-/* INTx domain operations structure */
+-static const struct irq_domain_ops intx_domain_ops = {
+- .map = mobiveil_pcie_intx_map,
+-};
+-
+-static struct irq_chip mobiveil_msi_irq_chip = {
+- .name = "Mobiveil PCIe MSI",
+- .irq_mask = pci_msi_mask_irq,
+- .irq_unmask = pci_msi_unmask_irq,
+-};
+-
+-static struct msi_domain_info mobiveil_msi_domain_info = {
+- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+- MSI_FLAG_PCI_MSIX),
+- .chip = &mobiveil_msi_irq_chip,
+-};
+-
+-static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+-{
+- struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
+- phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
+-
+- msg->address_lo = lower_32_bits(addr);
+- msg->address_hi = upper_32_bits(addr);
+- msg->data = data->hwirq;
+-
+- dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
+- (int)data->hwirq, msg->address_hi, msg->address_lo);
+-}
+-
+-static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
+- const struct cpumask *mask, bool force)
+-{
+- return -EINVAL;
+-}
+-
+-static struct irq_chip mobiveil_msi_bottom_irq_chip = {
+- .name = "Mobiveil MSI",
+- .irq_compose_msi_msg = mobiveil_compose_msi_msg,
+- .irq_set_affinity = mobiveil_msi_set_affinity,
+-};
+-
+-static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
+- unsigned int virq,
+- unsigned int nr_irqs, void *args)
+-{
+- struct mobiveil_pcie *pcie = domain->host_data;
+- struct mobiveil_msi *msi = &pcie->msi;
+- unsigned long bit;
+-
+- WARN_ON(nr_irqs != 1);
+- mutex_lock(&msi->lock);
+-
+- bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
+- if (bit >= msi->num_of_vectors) {
+- mutex_unlock(&msi->lock);
+- return -ENOSPC;
+- }
+-
+- set_bit(bit, msi->msi_irq_in_use);
+-
+- mutex_unlock(&msi->lock);
+-
+- irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
+- domain->host_data, handle_level_irq, NULL, NULL);
+- return 0;
+-}
+-
+-static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
+- unsigned int virq,
+- unsigned int nr_irqs)
+-{
+- struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+- struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
+- struct mobiveil_msi *msi = &pcie->msi;
+-
+- mutex_lock(&msi->lock);
+-
+- if (!test_bit(d->hwirq, msi->msi_irq_in_use))
+- dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
+- d->hwirq);
+- else
+- __clear_bit(d->hwirq, msi->msi_irq_in_use);
+-
+- mutex_unlock(&msi->lock);
+-}
+-static const struct irq_domain_ops msi_domain_ops = {
+- .alloc = mobiveil_irq_msi_domain_alloc,
+- .free = mobiveil_irq_msi_domain_free,
+-};
+-
+-static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
+-{
+- struct device *dev = &pcie->pdev->dev;
+- struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
+- struct mobiveil_msi *msi = &pcie->msi;
+-
+- mutex_init(&pcie->msi.lock);
+- msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
+- &msi_domain_ops, pcie);
+- if (!msi->dev_domain) {
+- dev_err(dev, "failed to create IRQ domain\n");
+- return -ENOMEM;
+- }
+-
+- msi->msi_domain = pci_msi_create_irq_domain(fwnode,
+- &mobiveil_msi_domain_info,
+- msi->dev_domain);
+- if (!msi->msi_domain) {
+- dev_err(dev, "failed to create MSI domain\n");
+- irq_domain_remove(msi->dev_domain);
+- return -ENOMEM;
+- }
+-
+- return 0;
+-}
+-
+-static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
+-{
+- struct device *dev = &pcie->pdev->dev;
+- struct device_node *node = dev->of_node;
+- int ret;
+-
+- /* setup INTx */
+- pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
+- &intx_domain_ops, pcie);
+-
+- if (!pcie->intx_domain) {
+- dev_err(dev, "Failed to get a INTx IRQ domain\n");
+- return -ENOMEM;
+- }
+-
+- raw_spin_lock_init(&pcie->intx_mask_lock);
+-
+- /* setup MSI */
+- ret = mobiveil_allocate_msi_domains(pcie);
+- if (ret)
+- return ret;
+-
+- return 0;
+-}
+-
+-static int mobiveil_pcie_probe(struct platform_device *pdev)
+-{
+- struct mobiveil_pcie *pcie;
+- struct pci_bus *bus;
+- struct pci_bus *child;
+- struct pci_host_bridge *bridge;
+- struct device *dev = &pdev->dev;
+- resource_size_t iobase;
+- int ret;
+-
+- /* allocate the PCIe port */
+- bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
+- if (!bridge)
+- return -ENOMEM;
+-
+- pcie = pci_host_bridge_priv(bridge);
+-
+- pcie->pdev = pdev;
+-
+- ret = mobiveil_pcie_parse_dt(pcie);
+- if (ret) {
+- dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
+- return ret;
+- }
+-
+- INIT_LIST_HEAD(&pcie->resources);
+-
+- /* parse the host bridge base addresses from the device tree file */
+- ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
+- &pcie->resources, &iobase);
+- if (ret) {
+- dev_err(dev, "Getting bridge resources failed\n");
+- return ret;
+- }
+-
+- /*
+- * configure all inbound and outbound windows and prepare the RC for
+- * config access
+- */
+- ret = mobiveil_host_init(pcie);
+- if (ret) {
+- dev_err(dev, "Failed to initialize host\n");
+- goto error;
+- }
+-
+- /* initialize the IRQ domains */
+- ret = mobiveil_pcie_init_irq_domain(pcie);
+- if (ret) {
+- dev_err(dev, "Failed creating IRQ Domain\n");
+- goto error;
+- }
+-
+- irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
+-
+- ret = devm_request_pci_bus_resources(dev, &pcie->resources);
+- if (ret)
+- goto error;
+-
+- /* Initialize bridge */
+- list_splice_init(&pcie->resources, &bridge->windows);
+- bridge->dev.parent = dev;
+- bridge->sysdata = pcie;
+- bridge->busnr = pcie->root_bus_nr;
+- bridge->ops = &mobiveil_pcie_ops;
+- bridge->map_irq = of_irq_parse_and_map_pci;
+- bridge->swizzle_irq = pci_common_swizzle;
+-
+- ret = mobiveil_bringup_link(pcie);
+- if (ret) {
+- dev_info(dev, "link bring-up failed\n");
+- goto error;
+- }
+-
+- /* setup the kernel resources for the newly added PCIe root bus */
+- ret = pci_scan_root_bus_bridge(bridge);
+- if (ret)
+- goto error;
+-
+- bus = bridge->bus;
+-
+- pci_assign_unassigned_bus_resources(bus);
+- list_for_each_entry(child, &bus->children, node)
+- pcie_bus_configure_settings(child);
+- pci_bus_add_devices(bus);
+-
+- return 0;
+-error:
+- pci_free_resource_list(&pcie->resources);
+- return ret;
+-}
+-
+-static const struct of_device_id mobiveil_pcie_of_match[] = {
+- {.compatible = "mbvl,gpex40-pcie",},
+- {},
+-};
+-
+-MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
+-
+-static struct platform_driver mobiveil_pcie_driver = {
+- .probe = mobiveil_pcie_probe,
+- .driver = {
+- .name = "mobiveil-pcie",
+- .of_match_table = mobiveil_pcie_of_match,
+- .suppress_bind_attrs = true,
+- },
+-};
+-
+-builtin_platform_driver(mobiveil_pcie_driver);
+-
+-MODULE_LICENSE("GPL v2");
+-MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
+-MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
diff --git a/series.conf b/series.conf
index 0bf708ca35..69d10e30fd 100644
--- a/series.conf
+++ b/series.conf
@@ -208,6 +208,10 @@
patches.suse/scsi-cxlflash-Mark-expected-switch-fall-throughs.patch
patches.suse/scsi-scsi_dh_rdac-zero-cdb-in-send_mode_select.patch
patches.suse/livepatch-nullify-obj-mod-in-klp_module_coming-s-error-path.patch
+ patches.suse/PCI-Add-Amazon-s-Annapurna-Labs-vendor-ID.patch
+ patches.suse/PCI-Add-ACS-quirk-for-Amazon-Annapurna-Labs-root-por.patch
+ patches.suse/PCI-VPD-Prevent-VPD-access-for-Amazon-s-Annapurna-La.patch
+ patches.suse/PCI-Add-quirk-to-disable-MSI-X-support-for-Amazon-s-.patch
patches.suse/0001-video-backlight-Drop-default-m-for-LCD-BACKLIGHT_CLA.patch
patches.suse/0004-drm-amdgpu-Fix-KFD-related-kernel-oops-on-Hawaii.patch
@@ -460,6 +464,12 @@
########################################################
# Other drivers
########################################################
+ #NXP lx2160 PCIe controller driver v8
+ patches.suse/PCI-mobiveil-Fix-the-CPU-base-address-setup-in-inbou.patch
+ patches.suse/PCI-mobiveil-Refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch
+ patches.suse/PCI-mobiveil-Make-mobiveil_host_init-can-be-used-to-.patch
+ patches.suse/PCI-mobiveil-Add-8-bit-and-16-bit-CSR-register-acces.patch
+ patches.suse/PCI-mobiveil-Add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch
########################################################
# Debugging
@@ -729,33 +739,5 @@
+yousaf.kaukab patches.suse/0001-PCI-Vulcan-AHCI-PCI-bar-fix-for-Broadcom-Vulcan-earl.patch
+yousaf.kaukab patches.suse/0001-ahci-thunderx2-stop-engine-fix-update.patch
+yousaf.kaukab patches.suse/0001-ahci-thunderx2-update-stop-engine-errata-delay-value.patch
-+yousaf.kaukab patches.suse/0001-mmc-sdhci-add-delay-after-the-last-tuning-command.patch
-+yousaf.kaukab patches.suse/0002-PCI-mobiveil-uniform-the-register-accessors.patch
-+yousaf.kaukab patches.suse/0002-mmc-sdhci-correct-the-maximum-timeout-when-enable-CM.patch
-+yousaf.kaukab patches.suse/0003-PCI-mobiveil-format-the-code-without-function-change.patch
-+yousaf.kaukab patches.suse/0004-PCI-mobiveil-correct-the-returned-error-number.patch
-+yousaf.kaukab patches.suse/0005-PCI-mobiveil-remove-flag-MSI_FLAG_MULTI_PCI_MSI.patch
-+yousaf.kaukab patches.suse/0006-PCI-mobiveil-correct-PCI-base-address-in-MEM-IO-outb.patch
-+yousaf.kaukab patches.suse/0007-PCI-mobiveil-replace-the-resource-list-iteration-fun.patch
-+yousaf.kaukab patches.suse/0008-PCI-mobiveil-use-WIN_NUM_0-explicitly-for-CFG-outbou.patch
-+yousaf.kaukab patches.suse/0009-PCI-mobiveil-use-the-1st-inbound-window-for-MEM-inbo.patch
-+yousaf.kaukab patches.suse/0010-PCI-mobiveil-correct-inbound-outbound-window-setup-r.patch
-+yousaf.kaukab patches.suse/0011-PCI-mobiveil-fix-the-INTx-process-error.patch
-+yousaf.kaukab patches.suse/0012-PCI-mobiveil-only-fix-up-the-Class-Code-field.patch
-+yousaf.kaukab patches.suse/0013-PCI-mobiveil-move-out-the-link-up-waiting-from-mobiv.patch
+yousaf.kaukab patches.suse/0013-ahci-thunderx2-Fix-for-errata-that-affects-stop-engi.patch
-+yousaf.kaukab patches.suse/0014-PCI-mobiveil-move-irq-chained-handler-setup-out-of-D.patch
-+yousaf.kaukab patches.suse/0015-PCI-mobiveil-initialize-Primary-Secondary-Subordinat.patch
-+yousaf.kaukab patches.suse/0016-dt-bindings-pci-mobiveil-change-gpio_slave-and-apb_c.patch
-+yousaf.kaukab patches.suse/0017-PCI-mobiveil-refactor-Mobiveil-PCIe-Host-Bridge-IP-d.patch
-+yousaf.kaukab patches.suse/0018-PCI-mobiveil-fix-the-checking-of-valid-device.patch
-+yousaf.kaukab patches.suse/0019-PCI-mobiveil-continue-to-initialize-the-host-upon-no.patch
-+yousaf.kaukab patches.suse/0020-PCI-mobiveil-disabled-IB-and-OB-windows-set-by-bootl.patch
-+yousaf.kaukab patches.suse/0021-PCI-mobiveil-add-Byte-and-Half-Word-width-register-a.patch
-+yousaf.kaukab patches.suse/0022-PCI-mobiveil-make-mobiveil_host_init-can-be-used-to-.patch
-+yousaf.kaukab patches.suse/0023-dt-bindings-pci-Add-NXP-Layerscape-SoCs-PCIe-Gen4-co.patch
-+yousaf.kaukab patches.suse/0024-PCI-mobiveil-add-PCIe-Gen4-RC-driver-for-NXP-Layersc.patch
-+yousaf.kaukab patches.suse/0025-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch
-+yousaf.kaukab patches.suse/0026-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011451.patch
-+yousaf.kaukab patches.suse/0001-irqchip-gic-v3-its-fix-build-warnings.patch
+yousaf.kaukab patches.suse/0008-kabi-arm64-reserve-space-in-cpu_hwcaps-and-cpu_hwcap.patch