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authorMian Yousaf Kaukab <yousaf.kaukab@suse.com>2019-08-08 12:22:02 +0200
committerMian Yousaf Kaukab <yousaf.kaukab@suse.com>2019-08-08 12:22:15 +0200
commit528d360fb0ee3ebb1642805b0e7f7b5f3aaddf59 (patch)
treedcc1e4fbb317349b081b1c42876739c40b3bbb13
parentfed12a173a71da39bde62da34a7bfad21b33f784 (diff)
clk: rockchip: Add 1.6GHz PLL rate for rk3399
(bsc#1144718,bsc#1144813).
-rw-r--r--patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch35
-rw-r--r--series.conf1
2 files changed, 36 insertions, 0 deletions
diff --git a/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch b/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
new file mode 100644
index 0000000000..96ba76d585
--- /dev/null
+++ b/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
@@ -0,0 +1,35 @@
+From: Derek Basehore <dbasehore@chromium.org>
+Date: Tue, 13 Mar 2018 13:37:19 -0700
+Subject: clk: rockchip: Add 1.6GHz PLL rate for rk3399
+
+Git-commit: 4ee3fd4abeca30d530fe67972f1964f7454259d6
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+We need this rate to generate 100, 200, and 228.57MHz from the same
+PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
+an external display.
+
+Signed-off-by: Derek Basehore <dbasehore@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/rockchip/clk-rk3399.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 6847120b61cd..3e57c6eef93d 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
+ RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
+--
+2.11.0
+
diff --git a/series.conf b/series.conf
index 0922f564ab..ebfad42021 100644
--- a/series.conf
+++ b/series.conf
@@ -15755,6 +15755,7 @@
patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi
patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning
patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
+ patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
patches.drivers/firmware-dmi_scan-Fix-UUID-length-safety-check