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authorNicolas Saenz Julienne <nsaenzjulienne@suse.de>2019-08-02 15:54:33 +0200
committerNicolas Saenz Julienne <nsaenzjulienne@suse.de>2019-08-08 11:39:12 +0200
commit5566a8dcba0352719ad35c0b926642c15344dcd8 (patch)
tree294040bd11faccb6f5a519b373af276f9f2a939c
parentc4d66a184fdcf5c4fdb5f2fb1d7064b013faa22a (diff)
clk: bcm2835: remove pllb (jsc#SLE-7294).
-rw-r--r--patches.drivers/clk-bcm2835-remove-pllb.patch57
-rw-r--r--series.conf1
2 files changed, 58 insertions, 0 deletions
diff --git a/patches.drivers/clk-bcm2835-remove-pllb.patch b/patches.drivers/clk-bcm2835-remove-pllb.patch
new file mode 100644
index 0000000000..89fb673a95
--- /dev/null
+++ b/patches.drivers/clk-bcm2835-remove-pllb.patch
@@ -0,0 +1,57 @@
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Wed, 12 Jun 2019 20:24:53 +0200
+Subject: clk: bcm2835: remove pllb
+Git-commit: 2256d89333bd17b8b56b42734a7e1046d52f7fc3
+Patch-mainline: v5.3-rc1
+References: jsc#SLE-7294
+
+Raspberry Pi's firmware controls this pll, we should use the firmware
+interface to access it.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Acked-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 28 ++++------------------------
+ 1 file changed, 4 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index 770bb01f523e..867ae3c20041 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1651,30 +1651,10 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
+ .fixed_divider = 1,
+ .flags = CLK_SET_RATE_PARENT),
+
+- /* PLLB is used for the ARM's clock. */
+- [BCM2835_PLLB] = REGISTER_PLL(
+- .name = "pllb",
+- .cm_ctrl_reg = CM_PLLB,
+- .a2w_ctrl_reg = A2W_PLLB_CTRL,
+- .frac_reg = A2W_PLLB_FRAC,
+- .ana_reg_base = A2W_PLLB_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKB,
+-
+- .ana = &bcm2835_ana_default,
+-
+- .min_rate = 600000000u,
+- .max_rate = 3000000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE),
+- [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
+- .name = "pllb_arm",
+- .source_pll = "pllb",
+- .cm_reg = CM_PLLB,
+- .a2w_reg = A2W_PLLB_ARM,
+- .load_mask = CM_PLLB_LOADARM,
+- .hold_mask = CM_PLLB_HOLDARM,
+- .fixed_divider = 1,
+- .flags = CLK_SET_RATE_PARENT),
++ /*
++ * PLLB is used for the ARM's clock. Controlled by firmware, see
++ * clk-raspberrypi.c.
++ */
+
+ /*
+ * PLLC is the core PLL, used to drive the core VPU clock.
+
diff --git a/series.conf b/series.conf
index e2c1a17504..29e0e621b8 100644
--- a/series.conf
+++ b/series.conf
@@ -23159,6 +23159,7 @@
patches.drivers/dmaengine-hsu-Revert-set-HSU_CH_MTSR-to-memory-width.patch
patches.drivers/0008-dmaengine-rcar-dmac-Reject-zero-length-slave-DMA-req.patch
patches.drivers/clk-qcom-Fix-Wunused-const-variable.patch
+ patches.drivers/clk-bcm2835-remove-pllb.patch
patches.drivers/clk-tegra210-fix-PLLU-and-PLLU_OUT1.patch
patches.drivers/clk-rockchip-Don-t-yell-about-bad-mmc-phases-when-ge.patch
patches.fixes/floppy-fix-div-by-zero-in-setup_format_params.patch