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authorTakashi Iwai <tiwai@suse.de>2019-07-16 14:46:35 +0200
committerTakashi Iwai <tiwai@suse.de>2019-07-16 14:47:08 +0200
commit91e6df2549f750ac971e830c3c940e60679bf8ca (patch)
treece00dcbfcf1328e8f79a032bf34dd1bcee3f2977
parent36965fe1a1b8ed8b563bc470f536c7d935cc2989 (diff)
crypto: talitos - Align SEC1 accesses to 32 bits boundaries
(bsc#1051510).
-rw-r--r--patches.fixes/crypto-talitos-Align-SEC1-accesses-to-32-bits-bounda.patch44
-rw-r--r--series.conf1
2 files changed, 45 insertions, 0 deletions
diff --git a/patches.fixes/crypto-talitos-Align-SEC1-accesses-to-32-bits-bounda.patch b/patches.fixes/crypto-talitos-Align-SEC1-accesses-to-32-bits-bounda.patch
new file mode 100644
index 0000000000..d0609ce42f
--- /dev/null
+++ b/patches.fixes/crypto-talitos-Align-SEC1-accesses-to-32-bits-bounda.patch
@@ -0,0 +1,44 @@
+From c9cca7034b34a2d82e9a03b757de2485c294851c Mon Sep 17 00:00:00 2001
+From: Christophe Leroy <christophe.leroy@c-s.fr>
+Date: Tue, 21 May 2019 13:34:18 +0000
+Subject: [PATCH] crypto: talitos - Align SEC1 accesses to 32 bits boundaries.
+Git-commit: c9cca7034b34a2d82e9a03b757de2485c294851c
+Patch-mainline: v5.3-rc1
+References: bsc#1051510
+
+The MPC885 reference manual states:
+
+SEC Lite-initiated 8xx writes can occur only on 32-bit-word boundaries, but
+reads can occur on any byte boundary. Writing back a header read from a
+non-32-bit-word boundary will yield unpredictable results.
+
+In order to ensure that, cra_alignmask is set to 3 for SEC1.
+
+Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
+Fixes: 9c4a79653b35 ("crypto: talitos - Freescale integrated security engine (SEC) driver")
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/crypto/talitos.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
+index 7c8a3a717b91..750b0159e654 100644
+--- a/drivers/crypto/talitos.c
++++ b/drivers/crypto/talitos.c
+@@ -3327,7 +3327,10 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
+ alg->cra_priority = t_alg->algt.priority;
+ else
+ alg->cra_priority = TALITOS_CRA_PRIORITY;
+- alg->cra_alignmask = 0;
++ if (has_ftr_sec1(priv))
++ alg->cra_alignmask = 3;
++ else
++ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct talitos_ctx);
+ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
+
+--
+2.16.4
+
diff --git a/series.conf b/series.conf
index cbf681411c..b97d294748 100644
--- a/series.conf
+++ b/series.conf
@@ -22821,6 +22821,7 @@
patches.fixes/crypto-talitos-check-data-blocksize-in-ablkcipher.patch
patches.fixes/crypto-talitos-HMAC-SNOOP-NO-AFEU-mode-requires-SW-i.patch
patches.fixes/crypto-talitos-properly-handle-split-ICV.patch
+ patches.fixes/crypto-talitos-Align-SEC1-accesses-to-32-bits-bounda.patch
patches.fixes/lib-scatterlist-Fix-mapping-iterator-when-sg-offset-.patch
patches.drivers/pwm-stm32-Use-3-cells-of_xlate.patch
patches.drivers/gpio-omap-fix-lack-of-irqstatus_raw0-for-OMAP4.patch