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authorTakashi Iwai <tiwai@suse.de>2019-08-08 13:57:04 +0200
committerTakashi Iwai <tiwai@suse.de>2019-08-08 13:57:04 +0200
commita8ba4907b6602527212a927b33d3ab45e5a66528 (patch)
tree4ae34cb337f7da3c473420443d547dc718ce91a6
parent28f2b24bbd24cf3f19143eb51c88764ecea608d5 (diff)
parent33134210f3bc36f7c7453db4e8fee1743dc7420b (diff)
Merge branch 'users/ykaukab/SLE15/test' into SLE15
Pull rockchip fixes from Mian Yousaf Kaukab
-rw-r--r--patches.drivers/0001-clk-add-clk_bulk_get-accessories.patch415
-rw-r--r--patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch35
-rw-r--r--patches.drivers/0002-clk-Export-clk_bulk_prepare.patch36
-rw-r--r--patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch49
-rw-r--r--patches.drivers/0003-clk-bulk-silently-error-out-on-EPROBE_DEFER.patch38
-rw-r--r--patches.drivers/0003-soc-rockchip-power-domain-use-clk_bulk-APIs.patch218
-rw-r--r--patches.drivers/0004-soc-rockchip-power-domain-Add-a-sanity-check-on-pd-n.patch52
-rw-r--r--patches.drivers/0005-soc-rockchip-power-domain-Use-of_clk_get_parent_coun.patch48
-rw-r--r--patches.drivers/0007-PM-devfreq-rk3399_dmc-remove-wait-for-dcf-irq-event.patch126
-rw-r--r--patches.drivers/0008-PM-devfreq-rk3399_dmc-do-not-print-error-when-get-su.patch48
-rw-r--r--patches.drivers/0009-PM-devfreq-rk3399_dmc-fix-spelling-mistakes.patch64
-rw-r--r--patches.drivers/0010-PM-devfreq-rk3399_dmc-remove-unneeded-semicolon.patch34
-rw-r--r--patches.drivers/0011-PM-devfreq-rockchip-dfi-Move-GRF-definitions-to-a-co.patch110
-rw-r--r--patches.drivers/0012-PM-devfreq-rk3399_dmc-Pass-ODT-and-auto-power-down-p.patch178
-rw-r--r--series.conf14
15 files changed, 1465 insertions, 0 deletions
diff --git a/patches.drivers/0001-clk-add-clk_bulk_get-accessories.patch b/patches.drivers/0001-clk-add-clk_bulk_get-accessories.patch
new file mode 100644
index 0000000000..eee51d7bba
--- /dev/null
+++ b/patches.drivers/0001-clk-add-clk_bulk_get-accessories.patch
@@ -0,0 +1,415 @@
+From: Dong Aisheng <aisheng.dong@nxp.com>
+Date: Fri, 19 May 2017 21:49:04 +0800
+Subject: clk: add clk_bulk_get accessories
+
+Git-commit: 266e4e9d9150e98141b85c7400f8aa3cd57a7f9b
+Patch-mainline: v4.13-rc1
+References: bsc#1144813
+
+These helper function allows drivers to get several clk consumers in
+one operation. If any of the clk cannot be acquired then any clks
+that were got will be put before returning to the caller.
+
+This can relieve the driver owners' life who needs to handle many clocks,
+as well as each clock error reporting.
+
+Cc: Michael Turquette <mturquette@baylibre.com>
+Cc: Stephen Boyd <sboyd@codeaurora.org>
+Cc: Russell King <linux@arm.linux.org.uk>
+Cc: Geert Uytterhoeven <geert@linux-m68k.org>
+Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
+Cc: Viresh Kumar <viresh.kumar@linaro.org>
+Cc: Mark Brown <broonie@kernel.org>
+Cc: Shawn Guo <shawnguo@kernel.org>
+Cc: Fabio Estevam <fabio.estevam@nxp.com>
+Cc: Sascha Hauer <kernel@pengutronix.de>
+Cc: Anson Huang <anson.huang@nxp.com>
+Cc: Robin Gong <yibin.gong@nxp.com>
+Cc: Bai Ping <ping.bai@nxp.com>
+Cc: Leonard Crestez <leonard.crestez@nxp.com>
+Cc: Octavian Purdila <octavian.purdila@nxp.com>
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/Makefile | 2 +-
+ drivers/clk/clk-bulk.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/clk.h | 111 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 269 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/clk/clk-bulk.c
+
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index c19983afcb81..ed1e99f19ec3 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -1,5 +1,5 @@
+ # common clock types
+-obj-$(CONFIG_HAVE_CLK) += clk-devres.o
++obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o
+ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
+ obj-$(CONFIG_COMMON_CLK) += clk.o
+ obj-$(CONFIG_COMMON_CLK) += clk-divider.o
+diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
+new file mode 100644
+index 000000000000..c834f5abfc49
+--- /dev/null
++++ b/drivers/clk/clk-bulk.c
+@@ -0,0 +1,157 @@
++/*
++ * Copyright 2017 NXP
++ *
++ * Dong Aisheng <aisheng.dong@nxp.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/export.h>
++
++void clk_bulk_put(int num_clks, struct clk_bulk_data *clks)
++{
++ while (--num_clks >= 0) {
++ clk_put(clks[num_clks].clk);
++ clks[num_clks].clk = NULL;
++ }
++}
++EXPORT_SYMBOL_GPL(clk_bulk_put);
++
++int __must_check clk_bulk_get(struct device *dev, int num_clks,
++ struct clk_bulk_data *clks)
++{
++ int ret;
++ int i;
++
++ for (i = 0; i < num_clks; i++)
++ clks[i].clk = NULL;
++
++ for (i = 0; i < num_clks; i++) {
++ clks[i].clk = clk_get(dev, clks[i].id);
++ if (IS_ERR(clks[i].clk)) {
++ ret = PTR_ERR(clks[i].clk);
++ dev_err(dev, "Failed to get clk '%s': %d\n",
++ clks[i].id, ret);
++ clks[i].clk = NULL;
++ goto err;
++ }
++ }
++
++ return 0;
++
++err:
++ clk_bulk_put(i, clks);
++
++ return ret;
++}
++EXPORT_SYMBOL(clk_bulk_get);
++
++#ifdef CONFIG_HAVE_CLK_PREPARE
++
++/**
++ * clk_bulk_unprepare - undo preparation of a set of clock sources
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table being unprepared
++ *
++ * clk_bulk_unprepare may sleep, which differentiates it from clk_bulk_disable.
++ * Returns 0 on success, -EERROR otherwise.
++ */
++void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks)
++{
++ while (--num_clks >= 0)
++ clk_unprepare(clks[num_clks].clk);
++}
++EXPORT_SYMBOL_GPL(clk_bulk_unprepare);
++
++/**
++ * clk_bulk_prepare - prepare a set of clocks
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table being prepared
++ *
++ * clk_bulk_prepare may sleep, which differentiates it from clk_bulk_enable.
++ * Returns 0 on success, -EERROR otherwise.
++ */
++int __must_check clk_bulk_prepare(int num_clks,
++ const struct clk_bulk_data *clks)
++{
++ int ret;
++ int i;
++
++ for (i = 0; i < num_clks; i++) {
++ ret = clk_prepare(clks[i].clk);
++ if (ret) {
++ pr_err("Failed to prepare clk '%s': %d\n",
++ clks[i].id, ret);
++ goto err;
++ }
++ }
++
++ return 0;
++
++err:
++ clk_bulk_unprepare(i, clks);
++
++ return ret;
++}
++
++#endif /* CONFIG_HAVE_CLK_PREPARE */
++
++/**
++ * clk_bulk_disable - gate a set of clocks
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table being gated
++ *
++ * clk_bulk_disable must not sleep, which differentiates it from
++ * clk_bulk_unprepare. clk_bulk_disable must be called before
++ * clk_bulk_unprepare.
++ */
++void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks)
++{
++
++ while (--num_clks >= 0)
++ clk_disable(clks[num_clks].clk);
++}
++EXPORT_SYMBOL_GPL(clk_bulk_disable);
++
++/**
++ * clk_bulk_enable - ungate a set of clocks
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table being ungated
++ *
++ * clk_bulk_enable must not sleep
++ * Returns 0 on success, -EERROR otherwise.
++ */
++int __must_check clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks)
++{
++ int ret;
++ int i;
++
++ for (i = 0; i < num_clks; i++) {
++ ret = clk_enable(clks[i].clk);
++ if (ret) {
++ pr_err("Failed to enable clk '%s': %d\n",
++ clks[i].id, ret);
++ goto err;
++ }
++ }
++
++ return 0;
++
++err:
++ clk_bulk_disable(i, clks);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(clk_bulk_enable);
+diff --git a/include/linux/clk.h b/include/linux/clk.h
+index 024cd07870d0..72b0cfce9165 100644
+--- a/include/linux/clk.h
++++ b/include/linux/clk.h
+@@ -77,6 +77,21 @@ struct clk_notifier_data {
+ unsigned long new_rate;
+ };
+
++/**
++ * struct clk_bulk_data - Data used for bulk clk operations.
++ *
++ * @id: clock consumer ID
++ * @clk: struct clk * to store the associated clock
++ *
++ * The CLK APIs provide a series of clk_bulk_() API calls as
++ * a convenience to consumers which require multiple clks. This
++ * structure is used to manage data for these calls.
++ */
++struct clk_bulk_data {
++ const char *id;
++ struct clk *clk;
++};
++
+ #ifdef CONFIG_COMMON_CLK
+
+ /**
+@@ -185,12 +200,20 @@ static inline bool clk_is_match(const struct clk *p, const struct clk *q)
+ */
+ #ifdef CONFIG_HAVE_CLK_PREPARE
+ int clk_prepare(struct clk *clk);
++int __must_check clk_bulk_prepare(int num_clks,
++ const struct clk_bulk_data *clks);
+ #else
+ static inline int clk_prepare(struct clk *clk)
+ {
+ might_sleep();
+ return 0;
+ }
++
++static inline int clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
++{
++ might_sleep();
++ return 0;
++}
+ #endif
+
+ /**
+@@ -204,11 +227,16 @@ static inline int clk_prepare(struct clk *clk)
+ */
+ #ifdef CONFIG_HAVE_CLK_PREPARE
+ void clk_unprepare(struct clk *clk);
++void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
+ #else
+ static inline void clk_unprepare(struct clk *clk)
+ {
+ might_sleep();
+ }
++static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks)
++{
++ might_sleep();
++}
+ #endif
+
+ #ifdef CONFIG_HAVE_CLK
+@@ -230,6 +258,29 @@ static inline void clk_unprepare(struct clk *clk)
+ struct clk *clk_get(struct device *dev, const char *id);
+
+ /**
++ * clk_bulk_get - lookup and obtain a number of references to clock producer.
++ * @dev: device for clock "consumer"
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table of consumer
++ *
++ * This helper function allows drivers to get several clk consumers in one
++ * operation. If any of the clk cannot be acquired then any clks
++ * that were obtained will be freed before returning to the caller.
++ *
++ * Returns 0 if all clocks specified in clk_bulk_data table are obtained
++ * successfully, or valid IS_ERR() condition containing errno.
++ * The implementation uses @dev and @clk_bulk_data.id to determine the
++ * clock consumer, and thereby the clock producer.
++ * The clock returned is stored in each @clk_bulk_data.clk field.
++ *
++ * Drivers must assume that the clock source is not enabled.
++ *
++ * clk_bulk_get should not be called from within interrupt context.
++ */
++int __must_check clk_bulk_get(struct device *dev, int num_clks,
++ struct clk_bulk_data *clks);
++
++/**
+ * devm_clk_get - lookup and obtain a managed reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: clock consumer ID
+@@ -279,6 +330,18 @@ struct clk *devm_get_clk_from_child(struct device *dev,
+ int clk_enable(struct clk *clk);
+
+ /**
++ * clk_bulk_enable - inform the system when the set of clks should be running.
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table of consumer
++ *
++ * May be called from atomic contexts.
++ *
++ * Returns success (0) or negative errno.
++ */
++int __must_check clk_bulk_enable(int num_clks,
++ const struct clk_bulk_data *clks);
++
++/**
+ * clk_disable - inform the system when the clock source is no longer required.
+ * @clk: clock source
+ *
+@@ -295,6 +358,24 @@ int clk_enable(struct clk *clk);
+ void clk_disable(struct clk *clk);
+
+ /**
++ * clk_bulk_disable - inform the system when the set of clks is no
++ * longer required.
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table of consumer
++ *
++ * Inform the system that a set of clks is no longer required by
++ * a driver and may be shut down.
++ *
++ * May be called from atomic contexts.
++ *
++ * Implementation detail: if the set of clks is shared between
++ * multiple drivers, clk_bulk_enable() calls must be balanced by the
++ * same number of clk_bulk_disable() calls for the clock source to be
++ * disabled.
++ */
++void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks);
++
++/**
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
+ * This is only valid once the clock source has been enabled.
+ * @clk: clock source
+@@ -314,6 +395,19 @@ unsigned long clk_get_rate(struct clk *clk);
+ void clk_put(struct clk *clk);
+
+ /**
++ * clk_bulk_put - "free" the clock source
++ * @num_clks: the number of clk_bulk_data
++ * @clks: the clk_bulk_data table of consumer
++ *
++ * Note: drivers must ensure that all clk_bulk_enable calls made on this
++ * clock source are balanced by clk_bulk_disable calls prior to calling
++ * this function.
++ *
++ * clk_bulk_put should not be called from within interrupt context.
++ */
++void clk_bulk_put(int num_clks, struct clk_bulk_data *clks);
++
++/**
+ * devm_clk_put - "free" a managed clock source
+ * @dev: device used to acquire the clock
+ * @clk: clock source acquired with devm_clk_get()
+@@ -445,6 +539,12 @@ static inline struct clk *clk_get(struct device *dev, const char *id)
+ return NULL;
+ }
+
++static inline int clk_bulk_get(struct device *dev, int num_clks,
++ struct clk_bulk_data *clks)
++{
++ return 0;
++}
++
+ static inline struct clk *devm_clk_get(struct device *dev, const char *id)
+ {
+ return NULL;
+@@ -458,6 +558,8 @@ static inline struct clk *devm_get_clk_from_child(struct device *dev,
+
+ static inline void clk_put(struct clk *clk) {}
+
++static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {}
++
+ static inline void devm_clk_put(struct device *dev, struct clk *clk) {}
+
+ static inline int clk_enable(struct clk *clk)
+@@ -465,8 +567,17 @@ static inline int clk_enable(struct clk *clk)
+ return 0;
+ }
+
++static inline int clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
++{
++ return 0;
++}
++
+ static inline void clk_disable(struct clk *clk) {}
+
++
++static inline void clk_bulk_disable(int num_clks,
++ struct clk_bulk_data *clks) {}
++
+ static inline unsigned long clk_get_rate(struct clk *clk)
+ {
+ return 0;
+--
+2.11.0
+
diff --git a/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch b/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
new file mode 100644
index 0000000000..96ba76d585
--- /dev/null
+++ b/patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
@@ -0,0 +1,35 @@
+From: Derek Basehore <dbasehore@chromium.org>
+Date: Tue, 13 Mar 2018 13:37:19 -0700
+Subject: clk: rockchip: Add 1.6GHz PLL rate for rk3399
+
+Git-commit: 4ee3fd4abeca30d530fe67972f1964f7454259d6
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+We need this rate to generate 100, 200, and 228.57MHz from the same
+PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
+an external display.
+
+Signed-off-by: Derek Basehore <dbasehore@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/rockchip/clk-rk3399.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 6847120b61cd..3e57c6eef93d 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
+ RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
+--
+2.11.0
+
diff --git a/patches.drivers/0002-clk-Export-clk_bulk_prepare.patch b/patches.drivers/0002-clk-Export-clk_bulk_prepare.patch
new file mode 100644
index 0000000000..97f2d880a8
--- /dev/null
+++ b/patches.drivers/0002-clk-Export-clk_bulk_prepare.patch
@@ -0,0 +1,36 @@
+From: Bjorn Andersson <bjorn.andersson@linaro.org>
+Date: Fri, 22 Sep 2017 22:00:29 -0700
+Subject: clk: Export clk_bulk_prepare()
+
+Git-commit: 9792bf5ad5e30b207274ccbb459a89eab6033b46
+Patch-mainline: v4.14-rc4
+References: bsc#1144813
+
+Allow clk_bulk_prepare() to be referenced by kernel modules by adding
+the missing EXPORT_SYMBOL_GPL().
+
+Fixes: 266e4e9d9150 ("clk: add clk_bulk_get accessories")
+Reported-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/clk-bulk.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
+index c834f5abfc49..4c10456f8a32 100644
+--- a/drivers/clk/clk-bulk.c
++++ b/drivers/clk/clk-bulk.c
+@@ -105,6 +105,7 @@ int __must_check clk_bulk_prepare(int num_clks,
+
+ return ret;
+ }
++EXPORT_SYMBOL_GPL(clk_bulk_prepare);
+
+ #endif /* CONFIG_HAVE_CLK_PREPARE */
+
+--
+2.11.0
+
diff --git a/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch b/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
new file mode 100644
index 0000000000..e3fea783eb
--- /dev/null
+++ b/patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
@@ -0,0 +1,49 @@
+From: Lin Huang <hl@rock-chips.com>
+Date: Tue, 20 Mar 2018 10:06:28 +0800
+Subject: clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
+
+Git-commit: 9dc486fdf6cc0d7f635954810ab119c5db2cbb60
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
+and these two PLL may change their frequency. If we do not
+assign right id to pclk_ddr and hclk_sd, they will alway use
+default cur register value, and may get the frequency
+exceed their signed off frequency. So assign correct Id
+for them, then we can assign frequency for them in dts.
+
+Signed-off-by: Lin Huang <hl@rock-chips.com>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/rockchip/clk-rk3399.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
+index 3e57c6eef93d..bca10d618f0a 100644
+--- a/drivers/clk/rockchip/clk-rk3399.c
++++ b/drivers/clk/rockchip/clk-rk3399.c
+@@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ RK3399_CLKGATE_CON(9), 7, GFLAGS,
+ &rk3399_uart3_fracmux),
+
+- COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
++ COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3399_CLKGATE_CON(3), 4, GFLAGS),
+
+@@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
+ RK3399_CLKGATE_CON(31), 8, GFLAGS),
+
+ /* sdio & sdmmc */
+- COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
++ COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+ RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3399_CLKGATE_CON(12), 13, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
+--
+2.11.0
+
diff --git a/patches.drivers/0003-clk-bulk-silently-error-out-on-EPROBE_DEFER.patch b/patches.drivers/0003-clk-bulk-silently-error-out-on-EPROBE_DEFER.patch
new file mode 100644
index 0000000000..e10f3e2a2a
--- /dev/null
+++ b/patches.drivers/0003-clk-bulk-silently-error-out-on-EPROBE_DEFER.patch
@@ -0,0 +1,38 @@
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 9 Apr 2018 16:13:03 +0200
+Subject: clk: bulk: silently error out on EPROBE_DEFER
+
+Git-commit: 329470f2d5447f76088250d7b7fbc1f9b175ccfc
+Patch-mainline: v4.18-rc1
+References: bsc#1144718,bsc#1144813
+
+In clk_bulk_get(), if we fail to get the clock due to probe deferal, we
+shouldn't print an error message. Just be silent in this case.
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/clk/clk-bulk.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
+index 4c10456f8a32..6904ed6da504 100644
+--- a/drivers/clk/clk-bulk.c
++++ b/drivers/clk/clk-bulk.c
+@@ -42,8 +42,9 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
+ clks[i].clk = clk_get(dev, clks[i].id);
+ if (IS_ERR(clks[i].clk)) {
+ ret = PTR_ERR(clks[i].clk);
+- dev_err(dev, "Failed to get clk '%s': %d\n",
+- clks[i].id, ret);
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "Failed to get clk '%s': %d\n",
++ clks[i].id, ret);
+ clks[i].clk = NULL;
+ goto err;
+ }
+--
+2.11.0
+
diff --git a/patches.drivers/0003-soc-rockchip-power-domain-use-clk_bulk-APIs.patch b/patches.drivers/0003-soc-rockchip-power-domain-use-clk_bulk-APIs.patch
new file mode 100644
index 0000000000..aea936cd10
--- /dev/null
+++ b/patches.drivers/0003-soc-rockchip-power-domain-use-clk_bulk-APIs.patch
@@ -0,0 +1,218 @@
+From: Jeffy Chen <jeffy.chen@rock-chips.com>
+Date: Wed, 28 Feb 2018 20:41:43 +0800
+Subject: soc: rockchip: power-domain: use clk_bulk APIs
+
+Git-commit: d909072d0521a84e67fbe5cce602d7befffabf7e
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+Use clk_bulk APIs, and also add error handling for clk enable.
+
+Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/soc/rockchip/pm_domains.c | 90 ++++++++++++++++++---------------------
+ 1 file changed, 42 insertions(+), 48 deletions(-)
+
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index 5c342167b9db..ad96ddeaeb78 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -67,7 +67,7 @@ struct rockchip_pm_domain {
+ struct regmap **qos_regmap;
+ u32 *qos_save_regs[MAX_QOS_REGS_NUM];
+ int num_clks;
+- struct clk *clks[];
++ struct clk_bulk_data *clks;
+ };
+
+ struct rockchip_pmu {
+@@ -274,13 +274,18 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
+
+ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
+ {
+- int i;
++ struct rockchip_pmu *pmu = pd->pmu;
++ int ret;
+
+- mutex_lock(&pd->pmu->mutex);
++ mutex_lock(&pmu->mutex);
+
+ if (rockchip_pmu_domain_is_on(pd) != power_on) {
+- for (i = 0; i < pd->num_clks; i++)
+- clk_enable(pd->clks[i]);
++ ret = clk_bulk_enable(pd->num_clks, pd->clks);
++ if (ret < 0) {
++ dev_err(pmu->dev, "failed to enable clocks\n");
++ mutex_unlock(&pmu->mutex);
++ return ret;
++ }
+
+ if (!power_on) {
+ rockchip_pmu_save_qos(pd);
+@@ -298,11 +303,10 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
+ rockchip_pmu_restore_qos(pd);
+ }
+
+- for (i = pd->num_clks - 1; i >= 0; i--)
+- clk_disable(pd->clks[i]);
++ clk_bulk_disable(pd->num_clks, pd->clks);
+ }
+
+- mutex_unlock(&pd->pmu->mutex);
++ mutex_unlock(&pmu->mutex);
+ return 0;
+ }
+
+@@ -364,8 +368,6 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ const struct rockchip_domain_info *pd_info;
+ struct rockchip_pm_domain *pd;
+ struct device_node *qos_node;
+- struct clk *clk;
+- int clk_cnt;
+ int i, j;
+ u32 id;
+ int error;
+@@ -391,41 +393,36 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ return -EINVAL;
+ }
+
+- clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+- pd = devm_kzalloc(pmu->dev,
+- sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
+- GFP_KERNEL);
++ pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->info = pd_info;
+ pd->pmu = pmu;
+
+- for (i = 0; i < clk_cnt; i++) {
+- clk = of_clk_get(node, i);
+- if (IS_ERR(clk)) {
+- error = PTR_ERR(clk);
++ pd->num_clks = of_count_phandle_with_args(node, "clocks",
++ "#clock-cells");
++
++ pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, sizeof(*pd->clks),
++ GFP_KERNEL);
++ if (!pd->clks)
++ return -ENOMEM;
++
++ for (i = 0; i < pd->num_clks; i++) {
++ pd->clks[i].clk = of_clk_get(node, i);
++ if (IS_ERR(pd->clks[i].clk)) {
++ error = PTR_ERR(pd->clks[i].clk);
+ dev_err(pmu->dev,
+ "%s: failed to get clk at index %d: %d\n",
+ node->name, i, error);
+- goto err_out;
+- }
+-
+- error = clk_prepare(clk);
+- if (error) {
+- dev_err(pmu->dev,
+- "%s: failed to prepare clk %pC (index %d): %d\n",
+- node->name, clk, i, error);
+- clk_put(clk);
+- goto err_out;
++ return error;
+ }
+-
+- pd->clks[pd->num_clks++] = clk;
+-
+- dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
+- clk, node->name);
+ }
+
++ error = clk_bulk_prepare(pd->num_clks, pd->clks);
++ if (error)
++ goto err_put_clocks;
++
+ pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
+ NULL);
+
+@@ -435,7 +432,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ GFP_KERNEL);
+ if (!pd->qos_regmap) {
+ error = -ENOMEM;
+- goto err_out;
++ goto err_unprepare_clocks;
+ }
+
+ for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
+@@ -445,7 +442,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ GFP_KERNEL);
+ if (!pd->qos_save_regs[j]) {
+ error = -ENOMEM;
+- goto err_out;
++ goto err_unprepare_clocks;
+ }
+ }
+
+@@ -453,13 +450,13 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ qos_node = of_parse_phandle(node, "pm_qos", j);
+ if (!qos_node) {
+ error = -ENODEV;
+- goto err_out;
++ goto err_unprepare_clocks;
+ }
+ pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
+ if (IS_ERR(pd->qos_regmap[j])) {
+ error = -ENODEV;
+ of_node_put(qos_node);
+- goto err_out;
++ goto err_unprepare_clocks;
+ }
+ of_node_put(qos_node);
+ }
+@@ -470,7 +467,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ dev_err(pmu->dev,
+ "failed to power on domain '%s': %d\n",
+ node->name, error);
+- goto err_out;
++ goto err_unprepare_clocks;
+ }
+
+ pd->genpd.name = node->name;
+@@ -486,17 +483,16 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ pmu->genpd_data.domains[id] = &pd->genpd;
+ return 0;
+
+-err_out:
+- while (--i >= 0) {
+- clk_unprepare(pd->clks[i]);
+- clk_put(pd->clks[i]);
+- }
++err_unprepare_clocks:
++ clk_bulk_unprepare(pd->num_clks, pd->clks);
++err_put_clocks:
++ clk_bulk_put(pd->num_clks, pd->clks);
+ return error;
+ }
+
+ static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
+ {
+- int i, ret;
++ int ret;
+
+ /*
+ * We're in the error cleanup already, so we only complain,
+@@ -507,10 +503,8 @@ static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
+ dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
+ pd->genpd.name, ret);
+
+- for (i = 0; i < pd->num_clks; i++) {
+- clk_unprepare(pd->clks[i]);
+- clk_put(pd->clks[i]);
+- }
++ clk_bulk_unprepare(pd->num_clks, pd->clks);
++ clk_bulk_put(pd->num_clks, pd->clks);
+
+ /* protect the zeroing of pm->num_clks */
+ mutex_lock(&pd->pmu->mutex);
+--
+2.11.0
+
diff --git a/patches.drivers/0004-soc-rockchip-power-domain-Add-a-sanity-check-on-pd-n.patch b/patches.drivers/0004-soc-rockchip-power-domain-Add-a-sanity-check-on-pd-n.patch
new file mode 100644
index 0000000000..705389b784
--- /dev/null
+++ b/patches.drivers/0004-soc-rockchip-power-domain-Add-a-sanity-check-on-pd-n.patch
@@ -0,0 +1,52 @@
+From: Jeffy Chen <jeffy.chen@rock-chips.com>
+Date: Mon, 5 Mar 2018 17:17:22 +0800
+Subject: soc: rockchip: power-domain: Add a sanity check on pd->num_clks
+
+Git-commit: b1271993aa3855bda5073c6061a095fd6e6febc6
+Patch-mainline: v4.17-rc1
+References: bsc#1144718,bsc#1144813
+
+The of_count_phandle_with_args() can fail and return error(for example,
+rk3399 pd_vio doesn't have clocks). That would break the pd probe.
+
+Add a sanity check on pd->num_clks to avoid that.
+
+Fixes: 65084121d59d ("soc: rockchip: power-domain: use clk_bulk APIs")
+Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
+Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/soc/rockchip/pm_domains.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index ad96ddeaeb78..53efc386b1ad 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -402,11 +402,16 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+
+ pd->num_clks = of_count_phandle_with_args(node, "clocks",
+ "#clock-cells");
+-
+- pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, sizeof(*pd->clks),
+- GFP_KERNEL);
+- if (!pd->clks)
+- return -ENOMEM;
++ if (pd->num_clks > 0) {
++ pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
++ sizeof(*pd->clks), GFP_KERNEL);
++ if (!pd->clks)
++ return -ENOMEM;
++ } else {
++ dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
++ node->name, pd->num_clks);
++ pd->num_clks = 0;
++ }
+
+ for (i = 0; i < pd->num_clks; i++) {
+ pd->clks[i].clk = of_clk_get(node, i);
+--
+2.11.0
+
diff --git a/patches.drivers/0005-soc-rockchip-power-domain-Use-of_clk_get_parent_coun.patch b/patches.drivers/0005-soc-rockchip-power-domain-Use-of_clk_get_parent_coun.patch
new file mode 100644
index 0000000000..0145ef3e87
--- /dev/null
+++ b/patches.drivers/0005-soc-rockchip-power-domain-Use-of_clk_get_parent_coun.patch
@@ -0,0 +1,48 @@
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 18 Apr 2018 16:50:03 +0200
+Subject: soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of
+ open coding
+
+Git-commit: 54d52ad940bb50284c85adcf481413fb3b82925a
+Patch-mainline: v4.18-rc1
+References: bsc#1144718,bsc#1144813
+
+As of_clk_get_parent_count() returns zero on failure, while
+of_count_phandle_with_args() might return a negative error code, this
+also fixes the issue of possibly using a negative number in the
+allocation below.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/soc/rockchip/pm_domains.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index 53efc386b1ad..13913d40c821 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -14,6 +14,7 @@
+ #include <linux/pm_clock.h>
+ #include <linux/pm_domain.h>
+ #include <linux/of_address.h>
++#include <linux/clk-provider.h>
+ #include <linux/of_platform.h>
+ #include <linux/clk.h>
+ #include <linux/regmap.h>
+@@ -400,8 +401,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ pd->info = pd_info;
+ pd->pmu = pmu;
+
+- pd->num_clks = of_count_phandle_with_args(node, "clocks",
+- "#clock-cells");
++ pd->num_clks = of_clk_get_parent_count(node);
+ if (pd->num_clks > 0) {
+ pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
+ sizeof(*pd->clks), GFP_KERNEL);
+--
+2.11.0
+
diff --git a/patches.drivers/0007-PM-devfreq-rk3399_dmc-remove-wait-for-dcf-irq-event.patch b/patches.drivers/0007-PM-devfreq-rk3399_dmc-remove-wait-for-dcf-irq-event.patch
new file mode 100644
index 0000000000..a2e2ba9265
--- /dev/null
+++ b/patches.drivers/0007-PM-devfreq-rk3399_dmc-remove-wait-for-dcf-irq-event.patch
@@ -0,0 +1,126 @@
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Wed, 9 May 2018 14:57:45 +0200
+Subject: PM / devfreq: rk3399_dmc: remove wait for dcf irq event.
+
+Git-commit: 90dd72e1290dd86c4b6e5c421fcd13e60e625782
+Patch-mainline: v4.19-rc1
+References: bsc#1144718,bsc#1144813
+
+We have already wait dcf done in ATF, so don't need wait dcf irq
+in kernel, besides, clear dcf irq in kernel will import competiton
+between kernel and ATF, only handle dcf irq in ATF is a better way.
+
+Signed-off-by: Lin Huang <hl@rock-chips.com>
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/rk3399_dmc.c | 53 +-------------------------------------------
+ 1 file changed, 1 insertion(+), 52 deletions(-)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index 5dfbfa3cc878..44a379657cd5 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -68,15 +68,6 @@ struct rk3399_dmcfreq {
+ struct devfreq_event_dev *edev;
+ struct mutex lock;
+ struct dram_timing timing;
+-
+- /*
+- * DDR Converser of Frequency (DCF) is used to implement DDR frequency
+- * conversion without the participation of CPU, we will implement and
+- * control it in arm trust firmware.
+- */
+- wait_queue_head_t wait_dcf_queue;
+- int irq;
+- int wait_dcf_flag;
+ struct regulator *vdd_center;
+ unsigned long rate, target_rate;
+ unsigned long volt, target_volt;
+@@ -117,7 +108,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+ goto out;
+ }
+ }
+- dmcfreq->wait_dcf_flag = 1;
+
+ err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
+ if (err) {
+@@ -129,14 +119,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+ }
+
+ /*
+- * Wait until bcf irq happen, it means freq scaling finish in
+- * arm trust firmware, use 100ms as timeout time.
+- */
+- if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
+- !dmcfreq->wait_dcf_flag, HZ / 10))
+- dev_warn(dev, "Timeout waiting for dcf interrupt\n");
+-
+- /*
+ * Check the dpll rate,
+ * There only two result we will get,
+ * 1. Ddr frequency scaling fail, we still get the old rate.
+@@ -241,22 +223,6 @@ static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
+ static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
+ rk3399_dmcfreq_resume);
+
+-static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
+-{
+- struct rk3399_dmcfreq *dmcfreq = dev_id;
+- struct arm_smccc_res res;
+-
+- dmcfreq->wait_dcf_flag = 0;
+- wake_up(&dmcfreq->wait_dcf_queue);
+-
+- /* Clear the DCF interrupt */
+- arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+- ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
+- 0, 0, 0, 0, &res);
+-
+- return IRQ_HANDLED;
+-}
+-
+ static int of_get_ddr_timings(struct dram_timing *timing,
+ struct device_node *np)
+ {
+@@ -330,16 +296,10 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct rk3399_dmcfreq *data;
+- int ret, irq, index, size;
++ int ret, index, size;
+ uint32_t *timing;
+ struct dev_pm_opp *opp;
+
+- irq = platform_get_irq(pdev, 0);
+- if (irq < 0) {
+- dev_err(&pdev->dev,
+- "Cannot get the dmc interrupt resource: %d\n", irq);
+- return irq;
+- }
+ data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+@@ -358,17 +318,6 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+ return PTR_ERR(data->dmc_clk);
+ };
+
+- data->irq = irq;
+- ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
+- dev_name(dev), data);
+- if (ret) {
+- dev_err(dev, "Failed to request dmc irq: %d\n", ret);
+- return ret;
+- }
+-
+- init_waitqueue_head(&data->wait_dcf_queue);
+- data->wait_dcf_flag = 0;
+-
+ data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
+ if (IS_ERR(data->edev))
+ return -EPROBE_DEFER;
+--
+2.11.0
+
diff --git a/patches.drivers/0008-PM-devfreq-rk3399_dmc-do-not-print-error-when-get-su.patch b/patches.drivers/0008-PM-devfreq-rk3399_dmc-do-not-print-error-when-get-su.patch
new file mode 100644
index 0000000000..d7da930186
--- /dev/null
+++ b/patches.drivers/0008-PM-devfreq-rk3399_dmc-do-not-print-error-when-get-su.patch
@@ -0,0 +1,48 @@
+From: Lin Huang <hl@rock-chips.com>
+Date: Wed, 9 May 2018 14:57:47 +0200
+Subject: PM / devfreq: rk3399_dmc: do not print error when get supply and clk
+ defer.
+
+Git-commit: 49edc52312c34c981722833b0d9344c2aa83892d
+Patch-mainline: v4.19-rc1
+References: bsc#1144718,bsc#1144813
+
+We just return -EPROBE_DEFER error code to caller and do not
+print error message when try to get center logic regulator
+and DMC clock defer.
+
+Signed-off-by: Lin Huang <hl@rock-chips.com>
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/rk3399_dmc.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index 44a379657cd5..5bfca028eaaf 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -308,12 +308,18 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+
+ data->vdd_center = devm_regulator_get(dev, "center");
+ if (IS_ERR(data->vdd_center)) {
++ if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++
+ dev_err(dev, "Cannot get the regulator \"center\"\n");
+ return PTR_ERR(data->vdd_center);
+ }
+
+ data->dmc_clk = devm_clk_get(dev, "dmc_clk");
+ if (IS_ERR(data->dmc_clk)) {
++ if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++
+ dev_err(dev, "Cannot get the clk dmc_clk\n");
+ return PTR_ERR(data->dmc_clk);
+ };
+--
+2.11.0
+
diff --git a/patches.drivers/0009-PM-devfreq-rk3399_dmc-fix-spelling-mistakes.patch b/patches.drivers/0009-PM-devfreq-rk3399_dmc-fix-spelling-mistakes.patch
new file mode 100644
index 0000000000..0f7d843400
--- /dev/null
+++ b/patches.drivers/0009-PM-devfreq-rk3399_dmc-fix-spelling-mistakes.patch
@@ -0,0 +1,64 @@
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Wed, 9 May 2018 14:57:48 +0200
+Subject: PM / devfreq: rk3399_dmc: fix spelling mistakes.
+
+Git-commit: dfa7d764caf00b12da276ea473d7f1fd7fd40200
+Patch-mainline: v4.19-rc1
+References: bsc#1144718,bsc#1144813
+
+Fix some spelling mistakes in error and debug messages.
+
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/rk3399_dmc.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index 5bfca028eaaf..d5c03e5abe13 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -103,7 +103,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+ err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+ target_volt);
+ if (err) {
+- dev_err(dev, "Cannot to set voltage %lu uV\n",
++ dev_err(dev, "Cannot set voltage %lu uV\n",
+ target_volt);
+ goto out;
+ }
+@@ -111,8 +111,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+
+ err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
+ if (err) {
+- dev_err(dev, "Cannot to set frequency %lu (%d)\n",
+- target_rate, err);
++ dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
++ err);
+ regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+ dmcfreq->volt);
+ goto out;
+@@ -128,8 +128,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+
+ /* If get the incorrect rate, set voltage to old value. */
+ if (dmcfreq->rate != target_rate) {
+- dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
+- Current frequency %lu\n", target_rate, dmcfreq->rate);
++ dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
++ target_rate, dmcfreq->rate);
+ regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+ dmcfreq->volt);
+ goto out;
+@@ -137,7 +137,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+ err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+ target_volt);
+ if (err)
+- dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
++ dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
+
+ dmcfreq->rate = target_rate;
+ dmcfreq->volt = target_volt;
+--
+2.11.0
+
diff --git a/patches.drivers/0010-PM-devfreq-rk3399_dmc-remove-unneeded-semicolon.patch b/patches.drivers/0010-PM-devfreq-rk3399_dmc-remove-unneeded-semicolon.patch
new file mode 100644
index 0000000000..e9ef68395f
--- /dev/null
+++ b/patches.drivers/0010-PM-devfreq-rk3399_dmc-remove-unneeded-semicolon.patch
@@ -0,0 +1,34 @@
+From: Yangtao Li <tiny.windzz@gmail.com>
+Date: Sat, 16 Feb 2019 10:18:24 -0500
+Subject: PM / devfreq: rk3399_dmc: remove unneeded semicolon
+
+Git-commit: e2794d74f1ec6d31e662b147d55041bd00277278
+Patch-mainline: v5.2-rc1
+References: bsc#1144718,bsc#1144813
+
+The semicolon is unneeded, so remove it.
+
+Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
+Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/rk3399_dmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index e795ad2b3f6b..a228dad2bee4 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -322,7 +322,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+
+ dev_err(dev, "Cannot get the clk dmc_clk\n");
+ return PTR_ERR(data->dmc_clk);
+- };
++ }
+
+ data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
+ if (IS_ERR(data->edev))
+--
+2.11.0
+
diff --git a/patches.drivers/0011-PM-devfreq-rockchip-dfi-Move-GRF-definitions-to-a-co.patch b/patches.drivers/0011-PM-devfreq-rockchip-dfi-Move-GRF-definitions-to-a-co.patch
new file mode 100644
index 0000000000..c572d93e6e
--- /dev/null
+++ b/patches.drivers/0011-PM-devfreq-rockchip-dfi-Move-GRF-definitions-to-a-co.patch
@@ -0,0 +1,110 @@
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Thu, 21 Mar 2019 19:14:36 -0400
+Subject: PM / devfreq: rockchip-dfi: Move GRF definitions to a common place.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Git-commit: adfe3b76608ffe547af5a74415f15499b798f32a
+Patch-mainline: v5.2-rc1
+References: bsc#1144718,bsc#1144813
+
+Some rk3399 GRF (Generic Register Files) definitions can be used for
+different drivers. Move these definitions to a common include so we
+don't need to duplicate these definitions.
+
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Gaël PORTAY <gael.portay@collabora.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 23 +++++++----------------
+ include/soc/rockchip/rk3399_grf.h | 21 +++++++++++++++++++++
+ 2 files changed, 28 insertions(+), 16 deletions(-)
+ create mode 100644 include/soc/rockchip/rk3399_grf.h
+
+diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
+index fcbf76ebf55d..a436ec4901bb 100644
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -26,6 +26,8 @@
+ #include <linux/list.h>
+ #include <linux/of.h>
+
++#include <soc/rockchip/rk3399_grf.h>
++
+ #define RK3399_DMC_NUM_CH 2
+
+ /* DDRMON_CTRL */
+@@ -43,18 +45,6 @@
+ #define DDRMON_CH1_COUNT_NUM 0x3c
+ #define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+
+-/* pmu grf */
+-#define PMUGRF_OS_REG2 0x308
+-#define DDRTYPE_SHIFT 13
+-#define DDRTYPE_MASK 7
+-
+-enum {
+- DDR3 = 3,
+- LPDDR3 = 6,
+- LPDDR4 = 7,
+- UNUSED = 0xFF
+-};
+-
+ struct dmc_usage {
+ u32 access;
+ u32 total;
+@@ -83,16 +73,17 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+ u32 ddr_type;
+
+ /* get ddr type */
+- regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
+- ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
++ regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
++ ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
++ RK3399_PMUGRF_DDRTYPE_MASK;
+
+ /* clear DDRMON_CTRL setting */
+ writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+
+ /* set ddr type to dfi */
+- if (ddr_type == LPDDR3)
++ if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
+ writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+- else if (ddr_type == LPDDR4)
++ else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+
+ /* enable count, use software mode */
+diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
+new file mode 100644
+index 000000000000..3eebabcb2812
+--- /dev/null
++++ b/include/soc/rockchip/rk3399_grf.h
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions
++ *
++ * Copyright (c) 2018, Collabora Ltd.
++ * Author: Enric Balletbo i Serra <enric.balletbo@collabora.com>
++ */
++
++#ifndef __SOC_RK3399_GRF_H
++#define __SOC_RK3399_GRF_H
++
++/* PMU GRF Registers */
++#define RK3399_PMUGRF_OS_REG2 0x308
++#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
++#define RK3399_PMUGRF_DDRTYPE_MASK 7
++#define RK3399_PMUGRF_DDRTYPE_DDR3 3
++#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
++#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
++#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
++
++#endif
+--
+2.11.0
+
diff --git a/patches.drivers/0012-PM-devfreq-rk3399_dmc-Pass-ODT-and-auto-power-down-p.patch b/patches.drivers/0012-PM-devfreq-rk3399_dmc-Pass-ODT-and-auto-power-down-p.patch
new file mode 100644
index 0000000000..7c22d14dbb
--- /dev/null
+++ b/patches.drivers/0012-PM-devfreq-rk3399_dmc-Pass-ODT-and-auto-power-down-p.patch
@@ -0,0 +1,178 @@
+From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Date: Thu, 21 Mar 2019 19:14:38 -0400
+Subject: PM / devfreq: rk3399_dmc: Pass ODT and auto power down parameters to
+ TF-A.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Git-commit: 9173c5ceb035aab28171cd74dfddf27f47213b99
+Patch-mainline: v5.2-rc1
+References: bsc#1144718,bsc#1144813
+
+Trusted Firmware-A (TF-A) for rk3399 implements a SiP call to get the
+on-die termination (ODT) and auto power down parameters from kernel,
+this patch adds the functionality to do this. Also, if DDR clock
+frequency is lower than the on-die termination (ODT) disable frequency
+this driver should disable the DDR ODT.
+
+Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Gaël PORTAY <gael.portay@collabora.com>
+Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
+Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
+---
+ drivers/devfreq/rk3399_dmc.c | 71 ++++++++++++++++++++++++++++++++++++-
+ include/soc/rockchip/rockchip_sip.h | 1 +
+ 2 files changed, 71 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
+index a228dad2bee4..567c034d0301 100644
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -18,14 +18,17 @@
+ #include <linux/devfreq.h>
+ #include <linux/devfreq-event.h>
+ #include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_opp.h>
++#include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/rwsem.h>
+ #include <linux/suspend.h>
+
++#include <soc/rockchip/rk3399_grf.h>
+ #include <soc/rockchip/rockchip_sip.h>
+
+ struct dram_timing {
+@@ -69,8 +72,11 @@ struct rk3399_dmcfreq {
+ struct mutex lock;
+ struct dram_timing timing;
+ struct regulator *vdd_center;
++ struct regmap *regmap_pmu;
+ unsigned long rate, target_rate;
+ unsigned long volt, target_volt;
++ unsigned int odt_dis_freq;
++ int odt_pd_arg0, odt_pd_arg1;
+ };
+
+ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+@@ -80,6 +86,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+ struct dev_pm_opp *opp;
+ unsigned long old_clk_rate = dmcfreq->rate;
+ unsigned long target_volt, target_rate;
++ struct arm_smccc_res res;
++ bool odt_enable = false;
+ int err;
+
+ opp = devfreq_recommended_opp(dev, freq, flags);
+@@ -95,6 +103,19 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+
+ mutex_lock(&dmcfreq->lock);
+
++ if (target_rate >= dmcfreq->odt_dis_freq)
++ odt_enable = true;
++
++ /*
++ * This makes a SMC call to the TF-A to set the DDR PD (power-down)
++ * timings and to enable or disable the ODT (on-die termination)
++ * resistors.
++ */
++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
++ dmcfreq->odt_pd_arg1,
++ ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
++ odt_enable, 0, 0, 0, &res);
++
+ /*
+ * If frequency scaling from low to high, adjust voltage first.
+ * If frequency scaling from high to low, adjust frequency first.
+@@ -294,11 +315,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+ {
+ struct arm_smccc_res res;
+ struct device *dev = &pdev->dev;
+- struct device_node *np = pdev->dev.of_node;
++ struct device_node *np = pdev->dev.of_node, *node;
+ struct rk3399_dmcfreq *data;
+ int ret, index, size;
+ uint32_t *timing;
+ struct dev_pm_opp *opp;
++ u32 ddr_type;
++ u32 val;
+
+ data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
+ if (!data)
+@@ -354,11 +377,57 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+ }
+ }
+
++ node = of_parse_phandle(np, "rockchip,pmu", 0);
++ if (node) {
++ data->regmap_pmu = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_pmu))
++ return PTR_ERR(data->regmap_pmu);
++ }
++
++ regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
++ ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
++ RK3399_PMUGRF_DDRTYPE_MASK;
++
++ switch (ddr_type) {
++ case RK3399_PMUGRF_DDRTYPE_DDR3:
++ data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
++ break;
++ case RK3399_PMUGRF_DDRTYPE_LPDDR3:
++ data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
++ break;
++ case RK3399_PMUGRF_DDRTYPE_LPDDR4:
++ data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
++ break;
++ default:
++ return -EINVAL;
++ };
++
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+ ROCKCHIP_SIP_CONFIG_DRAM_INIT,
+ 0, 0, 0, 0, &res);
+
+ /*
++ * In TF-A there is a platform SIP call to set the PD (power-down)
++ * timings and to enable or disable the ODT (on-die termination).
++ * This call needs three arguments as follows:
++ *
++ * arg0:
++ * bit[0-7] : sr_idle
++ * bit[8-15] : sr_mc_gate_idle
++ * bit[16-31] : standby idle
++ * arg1:
++ * bit[0-11] : pd_idle
++ * bit[16-27] : srpd_lite_idle
++ * arg2:
++ * bit[0] : odt enable
++ */
++ data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
++ ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
++ ((data->timing.standby_idle & 0xffff) << 16);
++ data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
++ ((data->timing.srpd_lite_idle & 0xfff) << 16);
++
++ /*
+ * We add a devfreq driver to our parent since it has a device tree node
+ * with operating points.
+ */
+diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
+index 7e28092c4d3d..ad9482c56797 100644
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -23,5 +23,6 @@
+ #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05
+ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
++#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
+
+ #endif
+--
+2.11.0
+
diff --git a/series.conf b/series.conf
index 7dfaf6c53b..4b71651883 100644
--- a/series.conf
+++ b/series.conf
@@ -2915,6 +2915,7 @@
patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789-
patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-0
patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent-
+ patches.drivers/0001-clk-add-clk_bulk_get-accessories.patch
patches.drivers/clk-at91-fix-clk-generated-compilation
patches.drivers/0023-clk-rockchip-add-dt-binding-header-for-rk3128.patch
patches.drivers/0024-clk-rockchip-add-ids-for-rk3399-testclks-used-for-ca.patch
@@ -7487,6 +7488,7 @@
patches.drivers/nvme-pci-Use-PCI-bus-address-for-data-queues-in-CMB.patch
patches.fixes/xfs-always-swap-the-cow-forks-when-swapping-extents.patch
patches.fixes/xfs-handle-racy-AIO-in-xfs_reflink_end_cow.patch
+ patches.drivers/0002-clk-Export-clk_bulk_prepare.patch
patches.drivers/0003-hwmon-xgene-Fix-up-error-handling-path-mixup-in-xgen.patch
patches.drivers/0001-mmc-core-add-driver-strength-selection-when-selectin.patch
patches.drivers/mmc-sdhci-xenon-Fix-clock-resource-by-adding-an-opti
@@ -15331,6 +15333,8 @@
patches.fixes/udf-Provide-saner-default-for-invalid-uid-gid.patch
patches.drivers/dt-bindings-arm-document-soc-compatible-value-for-armadillo-800-eva.patch
patches.drivers/soc-qcom-wcnss_ctrl-Fix-increment-in-NV-upload
+ patches.drivers/0003-soc-rockchip-power-domain-use-clk_bulk-APIs.patch
+ patches.drivers/0004-soc-rockchip-power-domain-Add-a-sanity-check-on-pd-n.patch
patches.suse/0202-dm-crypt-limit-the-number-of-allocated-pages.patch
patches.suse/0203-dm-remove-unused-macro-DM_MOD_NAME_SIZE.patch
patches.suse/0204-dm-integrity-fail-early-if-required-HMAC-key-is-not-.patch
@@ -15752,7 +15756,9 @@
patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi
patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning
patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
+ patches.drivers/0001-clk-rockchip-Add-1.6GHz-PLL-rate-for-rk3399.patch
patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
+ patches.drivers/0002-clk-rockchip-assign-correct-id-for-pclk_ddr-and-hclk.patch
patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
patches.drivers/firmware-dmi_scan-Fix-UUID-length-safety-check
patches.drivers/thermal-imx-Fix-race-condition-in-imx_thermal_probe
@@ -17244,7 +17250,9 @@
patches.drivers/0001-md-fix-two-problems-with-setting-the-re-add-device-s.patch
patches.fixes/md-fix-NULL-dereference-of-mddev-pers-in-remove_and_.patch
patches.fixes/md-raid1-add-error-handling-of-read-error-from-FailF.patch
+ patches.drivers/0005-soc-rockchip-power-domain-Use-of_clk_get_parent_coun.patch
patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency
+ patches.drivers/0003-clk-bulk-silently-error-out-on-EPROBE_DEFER.patch
patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent
patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND
patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
@@ -18365,6 +18373,9 @@
patches.drivers/leds-max8997-use-mode-when-calling-max8997_led_set_m
patches.drivers/ACPI-PM-save-NVS-memory-for-ASUS-1025C-laptop
patches.drivers/dt-bindings-clock-add-rk3399-ddr3-standard-speed-bins.patch
+ patches.drivers/0007-PM-devfreq-rk3399_dmc-remove-wait-for-dcf-irq-event.patch
+ patches.drivers/0008-PM-devfreq-rk3399_dmc-do-not-print-error-when-get-su.patch
+ patches.drivers/0009-PM-devfreq-rk3399_dmc-fix-spelling-mistakes.patch
patches.arch/PM-devfreq-rk3399_dmc-Fix-duplicated-opp-table-on-re.patch
patches.drivers/0007-cpufreq-CPPC-Add-cpuinfo_cur_freq-support-for-CPPC.patch
patches.drivers/ACPI-scan-Initialize-status-to-ACPI_STA_DEFAULT.patch
@@ -22324,6 +22335,9 @@
patches.drivers/cpufreq-pmac32-fix-possible-object-reference-leak.patch
patches.drivers/cpufreq-ppc_cbe-fix-possible-object-reference-leak.patch
patches.drivers/PM-core-Propagate-dev-power.wakeup_path-when-no-call.patch
+ patches.drivers/0010-PM-devfreq-rk3399_dmc-remove-unneeded-semicolon.patch
+ patches.drivers/0011-PM-devfreq-rockchip-dfi-Move-GRF-definitions-to-a-co.patch
+ patches.drivers/0012-PM-devfreq-rk3399_dmc-Pass-ODT-and-auto-power-down-p.patch
patches.fixes/ACPI-property-fix-handling-of-data_nodes-in-acpi_get.patch
patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
patches.arch/x86-mce-handle-varying-mca-bank-counts.patch