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authorThomas Zimmermann <tzimmermann@suse.de>2019-06-11 09:07:47 +0200
committerThomas Zimmermann <tzimmermann@suse.de>2019-06-11 09:07:47 +0200
commit44184d30169fb424e28a9f008e21806897d59d9b (patch)
tree01aa77b99d6cba42969db4d364f52a2c184e40ea
parent943a224f27ca6d9462d68670542e8b03629d5de4 (diff)
drm/i915/gvt: refine ggtt range validation (bsc#1113722)
-rw-r--r--patches.drm/0002-drm-i915-gvt-refine-ggtt-range-validation.patch58
-rw-r--r--series.conf1
2 files changed, 59 insertions, 0 deletions
diff --git a/patches.drm/0002-drm-i915-gvt-refine-ggtt-range-validation.patch b/patches.drm/0002-drm-i915-gvt-refine-ggtt-range-validation.patch
new file mode 100644
index 0000000000..05c71328dd
--- /dev/null
+++ b/patches.drm/0002-drm-i915-gvt-refine-ggtt-range-validation.patch
@@ -0,0 +1,58 @@
+From 5e0b3f3b27731f660612249b74b520f1bce6c198 Mon Sep 17 00:00:00 2001
+From: Xiong Zhang <xiong.y.zhang@intel.com>
+Date: Mon, 27 May 2019 13:45:50 +0800
+Subject: drm/i915/gvt: refine ggtt range validation
+Git-commit: 5e0b3f3b27731f660612249b74b520f1bce6c198
+Patch-mainline: v5.2-rc4
+References: bsc#1113722
+
+The vgpu ggtt range should be in vgpu aperture or hidden range. This
+patch enforce begin and end address check and guarantee both of them are
+in the valid range.
+
+For size=0, it will regress to vgpu_gmadr_is_valid(), will refine
+this usage in a later fix.
+
+Fixes: 2707e4446688 ("drm/i915/gvt: vGPU graphics memory virtualization")
+Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
+Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/gvt/gtt.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
+index f3a75bb9ec27..d767c45a57e2 100644
+--- a/drivers/gpu/drm/i915/gvt/gtt.c
++++ b/drivers/gpu/drm/i915/gvt/gtt.c
+@@ -53,13 +53,19 @@ static int preallocated_oos_pages = 8192;
+ */
+ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
+ {
+- if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
+- && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
+- gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
+- addr, size);
+- return false;
+- }
+- return true;
++ if (size == 0)
++ return vgpu_gmadr_is_valid(vgpu, addr);
++
++ if (vgpu_gmadr_is_aperture(vgpu, addr) &&
++ vgpu_gmadr_is_aperture(vgpu, addr + size - 1))
++ return true;
++ else if (vgpu_gmadr_is_hidden(vgpu, addr) &&
++ vgpu_gmadr_is_hidden(vgpu, addr + size - 1))
++ return true;
++
++ gvt_dbg_mm("Invalid ggtt range at 0x%llx, size: 0x%x\n",
++ addr, size);
++ return false;
+ }
+
+ /* translate a guest gmadr to host gmadr */
+--
+2.21.0
+
diff --git a/series.conf b/series.conf
index 166d263cab..029b774773 100644
--- a/series.conf
+++ b/series.conf
@@ -22300,6 +22300,7 @@
patches.suse/memcg-make-it-work-on-sparse-non-0-node-systems.patch
patches.suse/kernel-signal.c-trace_signal_deliver-when-signal_gro.patch
patches.arch/powerpc-perf-Fix-MMCRA-corruption-by-bhrb_filter.patch
+ patches.drm/0002-drm-i915-gvt-refine-ggtt-range-validation.patch
# dhowells/linux-fs keys-uefi
patches.suse/0001-KEYS-Allow-unrestricted-boot-time-addition-of-keys-t.patch