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authorTakashi Iwai <tiwai@suse.de>2019-02-21 09:09:54 +0100
committerTakashi Iwai <tiwai@suse.de>2019-02-21 09:09:59 +0100
commit9dc0ac830b4d411f7c21960da5adc29f70b9db91 (patch)
tree7b53ff1c29cd262237aa8618a94a0cffec3610e1
parent8bd676dc31cd37ceed01aece5e4e97bb0a1b0268 (diff)
drm/bridge: tc358767: fix single lane configuration
(bsc#1051510).
-rw-r--r--patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch60
-rw-r--r--series.conf1
2 files changed, 61 insertions, 0 deletions
diff --git a/patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch b/patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch
new file mode 100644
index 0000000000..ef53175565
--- /dev/null
+++ b/patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch
@@ -0,0 +1,60 @@
+From 4d9d54a730434cc068dd3515ba6116697196f77b Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Thu, 3 Jan 2019 13:59:50 +0200
+Subject: [PATCH] drm/bridge: tc358767: fix single lane configuration
+Git-commit: 4d9d54a730434cc068dd3515ba6116697196f77b
+Patch-mainline: v5.0-rc2
+References: bsc#1051510
+
+PHY_2LANE bit is always set in DP_PHY_CTRL, breaking 1 lane use.
+
+Set PHY_2LANE only when 2 lanes are used.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-4-tomi.valkeinen@ti.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/bridge/tc358767.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
+index 5f0a666db2fd..fee53422c31f 100644
+--- a/drivers/gpu/drm/bridge/tc358767.c
++++ b/drivers/gpu/drm/bridge/tc358767.c
+@@ -543,6 +543,7 @@ static int tc_aux_link_setup(struct tc_data *tc)
+ unsigned long rate;
+ u32 value;
+ int ret;
++ u32 dp_phy_ctrl;
+
+ rate = clk_get_rate(tc->refclk);
+ switch (rate) {
+@@ -567,7 +568,10 @@ static int tc_aux_link_setup(struct tc_data *tc)
+ value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
+ tc_write(SYS_PLLPARAM, value);
+
+- tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN);
++ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
++ if (tc->link.base.num_lanes == 2)
++ dp_phy_ctrl |= PHY_2LANE;
++ tc_write(DP_PHY_CTRL, dp_phy_ctrl);
+
+ /*
+ * Initially PLLs are in bypass. Force PLL parameter update,
+@@ -860,7 +864,9 @@ static int tc_main_link_setup(struct tc_data *tc)
+ tc_write(SYS_PLLPARAM, value);
+
+ /* Setup Main Link */
+- dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN | PHY_M0_EN;
++ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
++ if (tc->link.base.num_lanes == 2)
++ dp_phy_ctrl |= PHY_2LANE;
+ tc_write(DP_PHY_CTRL, dp_phy_ctrl);
+ msleep(100);
+
+--
+2.16.4
+
diff --git a/series.conf b/series.conf
index 41f1cdf30c..75af55e4c1 100644
--- a/series.conf
+++ b/series.conf
@@ -20239,6 +20239,7 @@
patches.drivers/ALSA-hda-realtek-Add-unplug-function-into-unplug-sta.patch
patches.drivers/ALSA-hda-realtek-Disable-headset-Mic-VREF-for-headse.patch
patches.drm/drm-bridge-tc358767-add-defines-for-DP1_SRCCTRL-PHY_.patch
+ patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch
patches.drivers/ACPI-power-Skip-duplicate-power-resource-references-.patch
patches.arch/x86-modpost-replace-last-remnants-of-retpoline-with-config_retpoline.patch
patches.fixes/rbd-don-t-return-0-on-unmap-if-rbd_dev_flag_removing-is-set.patch