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authorTakashi Iwai <tiwai@suse.de>2019-02-21 09:09:54 +0100
committerTakashi Iwai <tiwai@suse.de>2019-02-21 09:10:02 +0100
commitf50a2104283924b0744911adee0a7d6b8270e2a4 (patch)
treef2a3b3f8cd1e01d5b1e73b61799b9de60b6c9b0f
parent9dc0ac830b4d411f7c21960da5adc29f70b9db91 (diff)
drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value
(bsc#1051510).
-rw-r--r--patches.drm/drm-bridge-tc358767-fix-initial-DP0-1_SRCCTRL-value.patch55
-rw-r--r--series.conf1
2 files changed, 56 insertions, 0 deletions
diff --git a/patches.drm/drm-bridge-tc358767-fix-initial-DP0-1_SRCCTRL-value.patch b/patches.drm/drm-bridge-tc358767-fix-initial-DP0-1_SRCCTRL-value.patch
new file mode 100644
index 0000000000..877218abd1
--- /dev/null
+++ b/patches.drm/drm-bridge-tc358767-fix-initial-DP0-1_SRCCTRL-value.patch
@@ -0,0 +1,55 @@
+From 9a63bd6fe1b5590ffa42ae2ed22ee21363293e31 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Thu, 3 Jan 2019 13:59:51 +0200
+Subject: [PATCH] drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value
+Git-commit: 9a63bd6fe1b5590ffa42ae2ed22ee21363293e31
+Patch-mainline: v5.0-rc2
+References: bsc#1051510
+
+Initially DP0_SRCCTRL is set to a static value which includes
+DP0_SRCCTRL_LANES_2 and DP0_SRCCTRL_BW27, even when only 1 lane of
+1.62Gbps speed is used. DP1_SRCCTRL is configured to a magic number.
+
+This patch changes the configuration as follows:
+
+Configure DP0_SRCCTRL by using tc_srcctrl() which provides the correct
+value.
+
+DP1_SRCCTRL needs two bits to be set to the same value as DP0_SRCCTRL:
+SSCG and BW27. All other bits can be zero.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-5-tomi.valkeinen@ti.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/bridge/tc358767.c | 11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
+index fee53422c31f..ab299f4debfa 100644
+--- a/drivers/gpu/drm/bridge/tc358767.c
++++ b/drivers/gpu/drm/bridge/tc358767.c
+@@ -836,12 +836,11 @@ static int tc_main_link_setup(struct tc_data *tc)
+ if (!tc->mode)
+ return -EINVAL;
+
+- /* from excel file - DP0_SrcCtrl */
+- tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
+- DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
+- DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
+- /* from excel file - DP1_SrcCtrl */
+- tc_write(DP1_SRCCTRL, 0x00003083);
++ tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
++ /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
++ tc_write(DP1_SRCCTRL,
++ (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
++ ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
+
+ rate = clk_get_rate(tc->refclk);
+ switch (rate) {
+--
+2.16.4
+
diff --git a/series.conf b/series.conf
index 75af55e4c1..b04c5cbb42 100644
--- a/series.conf
+++ b/series.conf
@@ -20240,6 +20240,7 @@
patches.drivers/ALSA-hda-realtek-Disable-headset-Mic-VREF-for-headse.patch
patches.drm/drm-bridge-tc358767-add-defines-for-DP1_SRCCTRL-PHY_.patch
patches.drm/drm-bridge-tc358767-fix-single-lane-configuration.patch
+ patches.drm/drm-bridge-tc358767-fix-initial-DP0-1_SRCCTRL-value.patch
patches.drivers/ACPI-power-Skip-duplicate-power-resource-references-.patch
patches.arch/x86-modpost-replace-last-remnants-of-retpoline-with-config_retpoline.patch
patches.fixes/rbd-don-t-return-0-on-unmap-if-rbd_dev_flag_removing-is-set.patch