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authorTakashi Iwai <tiwai@suse.de>2019-05-24 20:37:03 +0200
committerTakashi Iwai <tiwai@suse.de>2019-05-24 20:37:03 +0200
commit7358223589a24e13b0898003b38d3dc29f13396c (patch)
tree9ef33f4861d6d699d53c9d52f405374164b206cb
parent70d4924acc7d5d05d66016efa5239e659c4e0c65 (diff)
drm/i915/gvt: do not let TRTTE and 0x4dfc write passthrough
to hardware (bsc#1051510).
-rw-r--r--patches.drm/drm-i915-gvt-do-not-let-TRTTE-and-0x4dfc-write-passt.patch64
-rw-r--r--series.conf1
2 files changed, 65 insertions, 0 deletions
diff --git a/patches.drm/drm-i915-gvt-do-not-let-TRTTE-and-0x4dfc-write-passt.patch b/patches.drm/drm-i915-gvt-do-not-let-TRTTE-and-0x4dfc-write-passt.patch
new file mode 100644
index 0000000000..c9e2e8cf08
--- /dev/null
+++ b/patches.drm/drm-i915-gvt-do-not-let-TRTTE-and-0x4dfc-write-passt.patch
@@ -0,0 +1,64 @@
+From e175a2520c7788a323ae93f04013b8fdaa552c69 Mon Sep 17 00:00:00 2001
+From: Yan Zhao <yan.y.zhao@intel.com>
+Date: Tue, 7 May 2019 22:16:44 -0400
+Subject: [PATCH] drm/i915/gvt: do not let TRTTE and 0x4dfc write passthrough to hardware
+Git-commit: e175a2520c7788a323ae93f04013b8fdaa552c69
+Patch-mainline: v5.2-rc2
+References: bsc#1051510
+
+the vGPU write on TRTTE and 0x4dfc is now write to vreg first. their
+values all be restored hardware when context switching.
+
+Fixes: e39c5add3221 ("drm/i915/gvt: vGPU MMIO virtualization")
+Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
+Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/gvt/handlers.c | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
+index 90673fca792f..e09bd6e0cc4d 100644
+--- a/drivers/gpu/drm/i915/gvt/handlers.c
++++ b/drivers/gpu/drm/i915/gvt/handlers.c
+@@ -1364,7 +1364,6 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
+ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
+ void *p_data, unsigned int bytes)
+ {
+- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ u32 trtte = *(u32 *)p_data;
+
+ if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
+@@ -1373,11 +1372,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
+ return -EINVAL;
+ }
+ write_vreg(vgpu, offset, p_data, bytes);
+- /* TRTTE is not per-context */
+-
+- mmio_hw_access_pre(dev_priv);
+- I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
+- mmio_hw_access_post(dev_priv);
+
+ return 0;
+ }
+@@ -1385,15 +1379,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
+ static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
+ void *p_data, unsigned int bytes)
+ {
+- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+- u32 val = *(u32 *)p_data;
+-
+- if (val & 1) {
+- /* unblock hw logic */
+- mmio_hw_access_pre(dev_priv);
+- I915_WRITE(_MMIO(offset), val);
+- mmio_hw_access_post(dev_priv);
+- }
+ write_vreg(vgpu, offset, p_data, bytes);
+ return 0;
+ }
+--
+2.16.4
+
diff --git a/series.conf b/series.conf
index 0f8d44f36a..50481ef042 100644
--- a/series.conf
+++ b/series.conf
@@ -22137,6 +22137,7 @@
patches.fixes/crypto-vmx-CTR-always-increment-IV-as-quadword.patch
patches.drm/drm-vmwgfx-Don-t-send-drm-sysfs-hotplug-events-on-in.patch
patches.drm/drm-vmwgfx-integer-underflow-in-vmw_cmd_dx_set_shade.patch
+ patches.drm/drm-i915-gvt-do-not-let-TRTTE-and-0x4dfc-write-passt.patch
patches.drivers/platform-x86-pmc_atom-Add-Lex-3I380D-industrial-PC-t.patch
patches.drivers/platform-x86-pmc_atom-Add-several-Beckhoff-Automatio.patch