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authorKernel Build Daemon <kbuild@suse.de>2019-06-19 07:05:27 +0200
committerKernel Build Daemon <kbuild@suse.de>2019-06-19 07:05:27 +0200
commita8bd41833e27d5a64377b6cf3caf68bf069676c0 (patch)
tree81ffd310bf2e3f9d8dafe6a69480e8b01d825e73
parentf5fe85e6b73d6394f07f5f239cd0b84f2b1e7098 (diff)
parentdb190917572ade92733ed13e42e9712247236ff2 (diff)
Merge branch 'SLE15' into SLE15-AZURESLE15-AZURE
-rw-r--r--blacklist.conf1
-rw-r--r--patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch40
-rw-r--r--patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch57
-rw-r--r--patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch65
-rw-r--r--patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch103
-rw-r--r--patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch72
-rw-r--r--patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch42
-rw-r--r--patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch94
-rw-r--r--patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch70
-rw-r--r--patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch60
-rw-r--r--patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch141
-rw-r--r--patches.drivers/ras-cec-fix-binary-search-function.patch90
-rw-r--r--patches.fixes/SMB3-Fix-endian-warning.patch40
-rw-r--r--series.conf12
14 files changed, 887 insertions, 0 deletions
diff --git a/blacklist.conf b/blacklist.conf
index 5ff842e246..6ca90c0e98 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -1253,3 +1253,4 @@ b616b9dbc5f613d64224b2e430211211812eadd0 # reverting drm/nouveau kconfig change
a25d8c327bb41742dbd59f8c545f59f3b9c39983 # md/raid5: reverting the above
9421e45f5ff3d558cf8b75a8cc0824530caf3453 # uio: reverted by the below
3d27c4de8d4fb2d4099ff324671792aa2578c6f9 # uio: reverting the above
+9d8d0294e78a164d407133dea05caf4b84247d6a # documentation only
diff --git a/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch b/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch
new file mode 100644
index 0000000000..6b9f1eb7d7
--- /dev/null
+++ b/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch
@@ -0,0 +1,40 @@
+From: Jim Mattson <jmattson@google.com>
+Date: Wed, 27 Mar 2019 13:15:37 -0700
+Subject: kvm: x86: Include CPUID leaf 0x8000001e in kvm's supported CPUID
+Git-commit: 382409b4c43e5b44ae4a869ff793d3cf01d12004
+Patch-mainline: v5.2-rc2
+References: bsc#1114279
+
+Kvm now supports extended CPUID functions through 0x8000001f. CPUID
+leaf 0x8000001e is AMD's Processor Topology Information leaf. This
+contains similar information to CPUID leaf 0xb (Intel's Extended
+Topology Enumeration leaf), and should be included in the output of
+KVM_GET_SUPPORTED_CPUID, even though userspace is likely to override
+some of this information based upon the configuration of the
+particular VM.
+
+Cc: Brijesh Singh <brijesh.singh@amd.com>
+Cc: Borislav Petkov <bp@suse.de>
+Fixes: 8765d75329a38 ("KVM: X86: Extend CPUID range to include new leaf")
+Signed-off-by: Jim Mattson <jmattson@google.com>
+Reviewed-by: Marc Orr <marcorr@google.com>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ arch/x86/kvm/cpuid.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
+index 3c96ce8fbb96..e18a9f9f65b5 100644
+--- a/arch/x86/kvm/cpuid.c
++++ b/arch/x86/kvm/cpuid.c
+@@ -702,6 +702,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ entry->ecx = entry->edx = 0;
+ break;
+ case 0x8000001a:
++ case 0x8000001e:
+ break;
+ /*Add support for Centaur's CPUID instruction*/
+ case 0xC0000000:
+
diff --git a/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch b/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch
new file mode 100644
index 0000000000..96647bad22
--- /dev/null
+++ b/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch
@@ -0,0 +1,57 @@
+From: Jim Mattson <jmattson@google.com>
+Date: Wed, 27 Mar 2019 13:15:36 -0700
+Subject: kvm: x86: Include multiple indices with CPUID leaf 0x8000001d
+Git-commit: 32a243df82c8dc04ccba7fc6c6564ae9261cb738
+Patch-mainline: v5.2-rc2
+References: bsc#1114279
+
+Per the APM, "CPUID Fn8000_001D_E[D,C,B,A]X reports cache topology
+information for the cache enumerated by the value passed to the
+instruction in ECX, referred to as Cache n in the following
+description. To gather information for all cache levels, software must
+repeatedly execute CPUID with 8000_001Dh in EAX and ECX set to
+increasing values beginning with 0 until a value of 00h is returned in
+the field CacheType (EAX[4:0]) indicating no more cache descriptions
+are available for this processor."
+
+The termination condition is the same as leaf 4, so we can reuse that
+code block for leaf 0x8000001d.
+
+Fixes: 8765d75329a38 ("KVM: X86: Extend CPUID range to include new leaf")
+Cc: Brijesh Singh <brijesh.singh@amd.com>
+Cc: Borislav Petkov <bp@suse.de>
+Signed-off-by: Jim Mattson <jmattson@google.com>
+Reviewed-by: Marc Orr <marcorr@google.com>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ arch/x86/kvm/cpuid.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
+index 80a642a0143d..3c96ce8fbb96 100644
+--- a/arch/x86/kvm/cpuid.c
++++ b/arch/x86/kvm/cpuid.c
+@@ -456,8 +456,9 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ }
+ break;
+ }
+- /* function 4 has additional index. */
+- case 4: {
++ /* functions 4 and 0x8000001d have additional index. */
++ case 4:
++ case 0x8000001d: {
+ int i, cache_type;
+
+ entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+@@ -702,8 +703,6 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ break;
+ case 0x8000001a:
+ break;
+- case 0x8000001d:
+- break;
+ /*Add support for Centaur's CPUID instruction*/
+ case 0xC0000000:
+ /*Just support up to 0xC0000004 now*/
+
diff --git a/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch b/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch
new file mode 100644
index 0000000000..41cd328937
--- /dev/null
+++ b/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch
@@ -0,0 +1,65 @@
+From: Frank van der Linden <fllinden@amazon.com>
+Date: Wed, 22 May 2019 22:17:45 +0000
+Subject: x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor
+Git-commit: 2ac44ab608705948564791ce1d15d43ba81a1e38
+Patch-mainline: v5.2-rc3
+References: bsc#1114279
+
+For F17h AMD CPUs, the CPB capability ('Core Performance Boost') is forcibly set,
+because some versions of that chip incorrectly report that they do not have it.
+
+However, a hypervisor may filter out the CPB capability, for good
+reasons. For example, KVM currently does not emulate setting the CPB
+bit in MSR_K7_HWCR, and unchecked MSR access errors will be thrown
+when trying to set it as a guest:
+
+ unchecked MSR access error: WRMSR to 0xc0010015 (tried to write 0x0000000001000011) at rIP: 0xffffffff890638f4 (native_write_msr+0x4/0x20)
+
+ Call Trace:
+ boost_set_msr+0x50/0x80 [acpi_cpufreq]
+ cpuhp_invoke_callback+0x86/0x560
+ sort_range+0x20/0x20
+ cpuhp_thread_fun+0xb0/0x110
+ smpboot_thread_fn+0xef/0x160
+ kthread+0x113/0x130
+ kthread_create_worker_on_cpu+0x70/0x70
+ ret_from_fork+0x35/0x40
+
+To avoid this issue, don't forcibly set the CPB capability for a CPU
+when running under a hypervisor.
+
+Signed-off-by: Frank van der Linden <fllinden@amazon.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+Cc: Andy Lutomirski <luto@kernel.org>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: bp@alien8.de
+Cc: jiaxun.yang@flygoat.com
+Fixes: 0237199186e7 ("x86/CPU/AMD: Set the CPB bit unconditionally on F17h")
+Link: http://lkml.kernel.org/r/20190522221745.GA15789@dev-dsk-fllinden-2c-c1893d73.us-west-2.amazon.com
+[ Minor edits to the changelog. ]
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+---
+ arch/x86/kernel/cpu/amd.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+index 80a405c2048a..8d4e50428b68 100644
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -824,8 +824,11 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
+ {
+ set_cpu_cap(c, X86_FEATURE_ZEN);
+
+- /* Fix erratum 1076: CPB feature bit not being set in CPUID. */
+- if (!cpu_has(c, X86_FEATURE_CPB))
++ /*
++ * Fix erratum 1076: CPB feature bit not being set in CPUID.
++ * Always set it, except when running under a hypervisor.
++ */
++ if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
+ set_cpu_cap(c, X86_FEATURE_CPB);
+ }
+
+
diff --git a/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch b/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
new file mode 100644
index 0000000000..ed550385fe
--- /dev/null
+++ b/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
@@ -0,0 +1,103 @@
+From: Tony Luck <tony.luck@intel.com>
+Date: Tue, 12 Mar 2019 10:09:38 -0700
+Subject: x86/mce: Fix machine_check_poll() tests for error types
+Git-commit: f19501aa07f18268ab14f458b51c1c6b7f72a134
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+There has been a lurking "TBD" in the machine check poll routine ever
+since it was first split out from the machine check handler. The
+potential issue is that the poll routine may have just begun a read from
+the STATUS register in a machine check bank when the hardware logs an
+error in that bank and signals a machine check.
+
+That race used to be pretty small back when machine checks were
+broadcast, but the addition of local machine check means that the poll
+code could continue running and clear the error from the bank before the
+local machine check handler on another CPU gets around to reading it.
+
+Fix the code to be sure to only process errors that need to be processed
+in the poll code, leaving other logged errors alone for the machine
+check handler to find and process.
+
+ [ bp: Massage a bit and flip the "== 0" check to the usual !(..) test. ]
+
+Fixes: b79109c3bbcf ("x86, mce: separate correct machine check poller and fatal exception handler")
+Fixes: ed7290d0ee8f ("x86, mce: implement new status bits")
+Reported-by: Ashok Raj <ashok.raj@intel.com>
+Signed-off-by: Tony Luck <tony.luck@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: x86-ml <x86@kernel.org>
+Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
+Link: https://lkml.kernel.org/r/20190312170938.GA23035@agluck-desk
+---
+ arch/x86/kernel/cpu/mcheck/mce.c | 44 +++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 37 insertions(+), 7 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
+index b7fb541a4873..e558ca77cfe8 100644
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -712,19 +712,49 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
+
+ barrier();
+ m.status = mce_rdmsrl(msr_ops.status(i));
++
++ /* If this entry is not valid, ignore it */
+ if (!(m.status & MCI_STATUS_VAL))
+ continue;
+
+ /*
+- * Uncorrected or signalled events are handled by the exception
+- * handler when it is enabled, so don't process those here.
+- *
+- * TBD do the same check for MCI_STATUS_EN here?
++ * If we are logging everything (at CPU online) or this
++ * is a corrected error, then we must log it.
+ */
+- if (!(flags & MCP_UC) &&
+- (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
+- continue;
++ if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
++ goto log_it;
++
++ /*
++ * Newer Intel systems that support software error
++ * recovery need to make additional checks. Other
++ * CPUs should skip over uncorrected errors, but log
++ * everything else.
++ */
++ if (!mca_cfg.ser) {
++ if (m.status & MCI_STATUS_UC)
++ continue;
++ goto log_it;
++ }
++
++ /* Log "not enabled" (speculative) errors */
++ if (!(m.status & MCI_STATUS_EN))
++ goto log_it;
++
++ /*
++ * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
++ * UC == 1 && PCC == 0 && S == 0
++ */
++ if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
++ goto log_it;
++
++ /*
++ * Skip anything else. Presumption is that our read of this
++ * bank is racing with a machine check. Leave the log alone
++ * for do_machine_check() to deal with it.
++ */
++ continue;
+
++log_it:
+ error_seen = true;
+
+ mce_read_aux(&m, i);
+
diff --git a/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch b/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch
new file mode 100644
index 0000000000..feaa22f1ea
--- /dev/null
+++ b/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch
@@ -0,0 +1,72 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Thu, 13 Jun 2019 15:49:02 +0200
+Subject: x86/microcode, cpuhotplug: Add a microcode loader CPU hotplug callback
+Git-commit: 78f4e932f7760d965fb1569025d1576ab77557c5
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+Adric Blake reported the following warning during suspend-resume:
+
+ Enabling non-boot CPUs ...
+ x86: Booting SMP configuration:
+ smpboot: Booting Node 0 Processor 1 APIC 0x2
+ unchecked MSR access error: WRMSR to 0x10f (tried to write 0x0000000000000000) \
+ at rIP: 0xffffffff8d267924 (native_write_msr+0x4/0x20)
+ Call Trace:
+ intel_set_tfa
+ intel_pmu_cpu_starting
+ ? x86_pmu_dead_cpu
+ x86_pmu_starting_cpu
+ cpuhp_invoke_callback
+ ? _raw_spin_lock_irqsave
+ notify_cpu_starting
+ start_secondary
+ secondary_startup_64
+ microcode: sig=0x806ea, pf=0x80, revision=0x96
+ microcode: updated to revision 0xb4, date = 2019-04-01
+ CPU1 is up
+
+The MSR in question is MSR_TFA_RTM_FORCE_ABORT and that MSR is emulated
+by microcode. The log above shows that the microcode loader callback
+happens after the PMU restoration, leading to the conjecture that
+because the microcode hasn't been updated yet, that MSR is not present
+yet, leading to the #GP.
+
+Add a microcode loader-specific hotplug vector which comes before
+the PERF vectors and thus executes earlier and makes sure the MSR is
+present.
+
+Fixes: 400816f60c54 ("perf/x86/intel: Implement support for TSX Force Abort")
+Reported-by: Adric Blake <promarbler14@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: <stable@vger.kernel.org>
+Cc: x86@kernel.org
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=203637
+---
+ arch/x86/kernel/cpu/microcode/core.c | 2 +-
+ include/linux/cpuhotplug.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/x86/kernel/cpu/microcode/core.c
++++ b/arch/x86/kernel/cpu/microcode/core.c
+@@ -853,7 +853,7 @@ int __init microcode_init(void)
+ goto out_ucode_group;
+
+ register_syscore_ops(&mc_syscore_ops);
+- cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
++ cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:online",
+ mc_cpu_online, mc_cpu_down_prep);
+
+ pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION);
+--- a/include/linux/cpuhotplug.h
++++ b/include/linux/cpuhotplug.h
+@@ -84,6 +84,7 @@ enum cpuhp_state {
+ CPUHP_AP_IRQ_ARMADA_XP_STARTING,
+ CPUHP_AP_IRQ_BCM2836_STARTING,
+ CPUHP_AP_ARM_MVEBU_COHERENCY,
++ CPUHP_AP_MICROCODE_LOADER,
+ CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
+ CPUHP_AP_PERF_X86_STARTING,
+ CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
diff --git a/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch b/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch
new file mode 100644
index 0000000000..09f5dbadd8
--- /dev/null
+++ b/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch
@@ -0,0 +1,42 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Thu, 4 Apr 2019 22:14:07 +0200
+Subject: x86/microcode: Fix the ancient deprecated microcode loading method
+Git-commit: 24613a04ad1c0588c10f4b5403ca60a73d164051
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+Commit
+
+ 2613f36ed965 ("x86/microcode: Attempt late loading only when new microcode is present")
+
+added the new define UCODE_NEW to denote that an update should happen
+only when newer microcode (than installed on the system) has been found.
+
+But it missed adjusting that for the old /dev/cpu/microcode loading
+interface. Fix it.
+
+Fixes: 2613f36ed965 ("x86/microcode: Attempt late loading only when new microcode is present")
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Jann Horn <jannh@google.com>
+Link: https://lkml.kernel.org/r/20190405133010.24249-3-bp@alien8.de
+---
+ arch/x86/kernel/cpu/microcode/core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
+index 5260185cbf7b..8a4a7823451a 100644
+--- a/arch/x86/kernel/cpu/microcode/core.c
++++ b/arch/x86/kernel/cpu/microcode/core.c
+@@ -418,8 +418,9 @@ static int do_microcode_update(const void __user *buf, size_t size)
+ if (ustate == UCODE_ERROR) {
+ error = -1;
+ break;
+- } else if (ustate == UCODE_OK)
++ } else if (ustate == UCODE_NEW) {
+ apply_microcode_on_target(cpu);
++ }
+ }
+
+ return error;
+
diff --git a/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch b/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch
new file mode 100644
index 0000000000..71866ad228
--- /dev/null
+++ b/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch
@@ -0,0 +1,94 @@
+From: Gary Hook <Gary.Hook@amd.com>
+Date: Mon, 29 Apr 2019 22:22:58 +0000
+Subject: x86/mm/mem_encrypt: Disable all instrumentation for early SME setup
+Git-commit: b51ce3744f115850166f3d6c292b9c8cb849ad4f
+Patch-mainline: v5.1
+References: bsc#1114279
+
+Enablement of AMD's Secure Memory Encryption feature is determined very
+early after start_kernel() is entered. Part of this procedure involves
+scanning the command line for the parameter 'mem_encrypt'.
+
+To determine intended state, the function sme_enable() uses library
+functions cmdline_find_option() and strncmp(). Their use occurs early
+enough such that it cannot be assumed that any instrumentation subsystem
+is initialized.
+
+For example, making calls to a KASAN-instrumented function before KASAN
+is set up will result in the use of uninitialized memory and a boot
+failure.
+
+When AMD's SME support is enabled, conditionally disable instrumentation
+of these dependent functions in lib/string.c and arch/x86/lib/cmdline.c.
+
+ [ bp: Get rid of intermediary nostackp var and cleanup whitespace. ]
+
+Fixes: aca20d546214 ("x86/mm: Add support to make use of Secure Memory Encryption")
+Reported-by: Li RongQing <lirongqing@baidu.com>
+Signed-off-by: Gary R Hook <gary.hook@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Cc: Boris Brezillon <bbrezillon@kernel.org>
+Cc: Coly Li <colyli@suse.de>
+Cc: "dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Kees Cook <keescook@chromium.org>
+Cc: Kent Overstreet <kent.overstreet@gmail.com>
+Cc: "luto@kernel.org" <luto@kernel.org>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Matthew Wilcox <willy@infradead.org>
+Cc: "mingo@redhat.com" <mingo@redhat.com>
+Cc: "peterz@infradead.org" <peterz@infradead.org>
+Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: x86-ml <x86@kernel.org>
+Link: https://lkml.kernel.org/r/155657657552.7116.18363762932464011367.stgit@sosrh3.amd.com
+---
+ arch/x86/lib/Makefile | 12 ++++++++++++
+ lib/Makefile | 11 +++++++++++
+ 2 files changed, 23 insertions(+)
+
+--- a/arch/x86/lib/Makefile
++++ b/arch/x86/lib/Makefile
+@@ -5,6 +5,18 @@
+ # Produces uninteresting flaky coverage.
+ KCOV_INSTRUMENT_delay.o := n
+
++# Early boot use of cmdline; don't instrument it
++ifdef CONFIG_AMD_MEM_ENCRYPT
++KCOV_INSTRUMENT_cmdline.o := n
++KASAN_SANITIZE_cmdline.o := n
++
++ifdef CONFIG_FUNCTION_TRACER
++CFLAGS_REMOVE_cmdline.o = -pg
++endif
++
++CFLAGS_cmdline.o := $(call cc-option, -fno-stack-protector)
++endif
++
+ inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk
+ inat_tables_maps = $(srctree)/arch/x86/lib/x86-opcode-map.txt
+ quiet_cmd_inat_tables = GEN $@
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -16,6 +16,17 @@ KCOV_INSTRUMENT_list_debug.o := n
+ KCOV_INSTRUMENT_debugobjects.o := n
+ KCOV_INSTRUMENT_dynamic_debug.o := n
+
++# Early boot use of cmdline, don't instrument it
++ifdef CONFIG_AMD_MEM_ENCRYPT
++KASAN_SANITIZE_string.o := n
++
++ifdef CONFIG_FUNCTION_TRACER
++CFLAGS_REMOVE_string.o = -pg
++endif
++
++CFLAGS_string.o := $(call cc-option, -fno-stack-protector)
++endif
++
+ lib-y := ctype.o string.o vsprintf.o cmdline.o \
+ rbtree.o radix-tree.o dump_stack.o timerqueue.o\
+ idr.o int_sqrt.o extable.o \
diff --git a/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch b/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch
new file mode 100644
index 0000000000..1d23f6a244
--- /dev/null
+++ b/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch
@@ -0,0 +1,70 @@
+From: Andy Lutomirski <luto@kernel.org>
+Date: Tue, 14 May 2019 13:24:39 -0700
+Subject: x86/speculation/mds: Revert CPU buffer clear on double fault exit
+Git-commit: 88640e1dcd089879530a49a8d212d1814678dfe7
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+The double fault ESPFIX path doesn't return to user mode at all --
+it returns back to the kernel by simulating a #GP fault.
+prepare_exit_to_usermode() will run on the way out of
+general_protection before running user code.
+
+Signed-off-by: Andy Lutomirski <luto@kernel.org>
+Cc: Borislav Petkov <bp@suse.de>
+Cc: Frederic Weisbecker <frederic@kernel.org>
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: Jon Masters <jcm@redhat.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: stable@vger.kernel.org
+Fixes: 04dcbdb80578 ("x86/speculation/mds: Clear CPU buffers on exit to user")
+Link: http://lkml.kernel.org/r/ac97612445c0a44ee10374f6ea79c222fe22a5c4.1557865329.git.luto@kernel.org
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ Documentation/x86/mds.rst | 7 -------
+ arch/x86/kernel/traps.c | 8 --------
+ 2 files changed, 15 deletions(-)
+
+--- a/arch/x86/kernel/traps.c
++++ b/arch/x86/kernel/traps.c
+@@ -59,7 +59,6 @@
+ #include <asm/alternative.h>
+ #include <asm/fpu/xstate.h>
+ #include <asm/trace/mpx.h>
+-#include <asm/nospec-branch.h>
+ #include <asm/mpx.h>
+ #include <asm/vm86.h>
+
+@@ -394,13 +393,6 @@ dotraplinkage void do_double_fault(struc
+ regs->ip = (unsigned long)general_protection;
+ regs->sp = (unsigned long)&gpregs->orig_ax;
+
+- /*
+- * This situation can be triggered by userspace via
+- * modify_ldt(2) and the return does not take the regular
+- * user space exit, so a CPU buffer clear is required when
+- * MDS mitigation is enabled.
+- */
+- mds_user_clear_cpu_buffers();
+ return;
+ }
+ #endif
+--- a/Documentation/x86/mds.rst
++++ b/Documentation/x86/mds.rst
+@@ -157,13 +157,6 @@ Mitigation points
+ mitigated on the return from do_nmi() to provide almost complete
+ coverage.
+
+- - Double fault (#DF):
+-
+- A double fault is usually fatal, but the ESPFIX workaround, which can
+- be triggered from user space through modify_ldt(2) is a recoverable
+- double fault. #DF uses the paranoid exit path, so explicit mitigation
+- in the double fault handler is required.
+-
+ - Machine Check Exception (#MC):
+
+ Another corner case is a #MC which hits between the CPU buffer clear
diff --git a/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch b/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch
new file mode 100644
index 0000000000..947777dc21
--- /dev/null
+++ b/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch
@@ -0,0 +1,60 @@
+From: Robert Richter <rrichter@marvell.com>
+Date: Tue, 14 May 2019 10:49:09 +0000
+Subject: EDAC/mc: Fix edac_mc_find() in case no device is found
+Git-commit: 29a0c843973bc385918158c6976e4dbe891df969
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+The function should return NULL in case no device is found, but it
+always returns the last checked mc device from the list even if the
+index did not match. Fix that.
+
+I did some analysis why this did not raise any issues for about 3 years
+and the reason is that edac_mc_find() is mostly used to search for
+existing devices. Thus, the bug is not triggered.
+
+ [ bp: Drop the if (mci->mc_idx > idx) test in favor of readability. ]
+
+Fixes: c73e8833bec5 ("EDAC, mc: Fix locking around mc_devices list")
+Signed-off-by: Robert Richter <rrichter@marvell.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
+Cc: James Morse <james.morse@arm.com>
+Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
+Link: https://lkml.kernel.org/r/20190514104838.15065-1-rrichter@marvell.com
+---
+ drivers/edac/edac_mc.c | 12 ++++--------
+ 1 file changed, 4 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
+index 13594ffadcb3..64922c8fa7e3 100644
+--- a/drivers/edac/edac_mc.c
++++ b/drivers/edac/edac_mc.c
+@@ -679,22 +679,18 @@ static int del_mc_from_global_list(struct mem_ctl_info *mci)
+
+ struct mem_ctl_info *edac_mc_find(int idx)
+ {
+- struct mem_ctl_info *mci = NULL;
++ struct mem_ctl_info *mci;
+ struct list_head *item;
+
+ mutex_lock(&mem_ctls_mutex);
+
+ list_for_each(item, &mc_devices) {
+ mci = list_entry(item, struct mem_ctl_info, link);
+-
+- if (mci->mc_idx >= idx) {
+- if (mci->mc_idx == idx) {
+- goto unlock;
+- }
+- break;
+- }
++ if (mci->mc_idx == idx)
++ goto unlock;
+ }
+
++ mci = NULL;
+ unlock:
+ mutex_unlock(&mem_ctls_mutex);
+ return mci;
+
diff --git a/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch b/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch
new file mode 100644
index 0000000000..dcfec72517
--- /dev/null
+++ b/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch
@@ -0,0 +1,141 @@
+From: Cong Wang <xiyou.wangcong@gmail.com>
+Date: Tue, 16 Apr 2019 14:33:51 -0700
+Subject: RAS/CEC: Convert the timer callback to a workqueue
+Git-commit: 0ade0b6240c4853cf9725924c46c10f4251639d7
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+cec_timer_fn() is a timer callback which reads ce_arr.array[] and
+updates its decay values. However, it runs in interrupt context and the
+mutex protection the CEC uses for that array, is inadequate. Convert the
+used timer to a workqueue to keep the tasks the CEC performs preemptible
+and thus low-prio.
+
+ [ bp: Rewrite commit message.
+ s/timer/decay/gi to make it agnostic as to what facility is used. ]
+
+Fixes: 011d82611172 ("RAS: Add a Corrected Errors Collector")
+Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: <stable@vger.kernel.org>
+Link: https://lkml.kernel.org/r/20190416213351.28999-2-xiyou.wangcong@gmail.com
+---
+ drivers/ras/cec.c | 50 +++++++++++++++++++++++---------------------------
+ 1 file changed, 23 insertions(+), 27 deletions(-)
+
+--- a/drivers/ras/cec.c
++++ b/drivers/ras/cec.c
+@@ -1,6 +1,7 @@
+ #include <linux/mm.h>
+ #include <linux/gfp.h>
+ #include <linux/kernel.h>
++#include <linux/workqueue.h>
+
+ #include <asm/mce.h>
+
+@@ -122,16 +123,12 @@ static u64 dfs_pfn;
+ /* Amount of errors after which we offline */
+ static unsigned int count_threshold = COUNT_MASK;
+
+-/*
+- * The timer "decays" element count each timer_interval which is 24hrs by
+- * default.
+- */
+-
+-#define CEC_TIMER_DEFAULT_INTERVAL 24 * 60 * 60 /* 24 hrs */
+-#define CEC_TIMER_MIN_INTERVAL 1 * 60 * 60 /* 1h */
+-#define CEC_TIMER_MAX_INTERVAL 30 * 24 * 60 * 60 /* one month */
+-static struct timer_list cec_timer;
+-static u64 timer_interval = CEC_TIMER_DEFAULT_INTERVAL;
++/* Each element "decays" each decay_interval which is 24hrs by default. */
++#define CEC_DECAY_DEFAULT_INTERVAL 24 * 60 * 60 /* 24 hrs */
++#define CEC_DECAY_MIN_INTERVAL 1 * 60 * 60 /* 1h */
++#define CEC_DECAY_MAX_INTERVAL 30 * 24 * 60 * 60 /* one month */
++static struct delayed_work cec_work;
++static u64 decay_interval = CEC_DECAY_DEFAULT_INTERVAL;
+
+ /*
+ * Decrement decay value. We're using DECAY_BITS bits to denote decay of an
+@@ -159,22 +156,21 @@ static void do_spring_cleaning(struct ce
+ /*
+ * @interval in seconds
+ */
+-static void cec_mod_timer(struct timer_list *t, unsigned long interval)
++static void cec_mod_work(unsigned long interval)
+ {
+ unsigned long iv;
+
+- iv = interval * HZ + jiffies;
+-
+- mod_timer(t, round_jiffies(iv));
++ iv = interval * HZ;
++ mod_delayed_work(system_wq, &cec_work, round_jiffies(iv));
+ }
+
+-static void cec_timer_fn(unsigned long data)
++static void cec_work_fn(struct work_struct *work)
+ {
+- struct ce_array *ca = (struct ce_array *)data;
+-
+- do_spring_cleaning(ca);
++ mutex_lock(&ce_mutex);
++ do_spring_cleaning(&ce_arr);
++ mutex_unlock(&ce_mutex);
+
+- cec_mod_timer(&cec_timer, timer_interval);
++ cec_mod_work(decay_interval);
+ }
+
+ /*
+@@ -381,15 +377,15 @@ static int decay_interval_set(void *data
+ {
+ *(u64 *)data = val;
+
+- if (val < CEC_TIMER_MIN_INTERVAL)
++ if (val < CEC_DECAY_MIN_INTERVAL)
+ return -EINVAL;
+
+- if (val > CEC_TIMER_MAX_INTERVAL)
++ if (val > CEC_DECAY_MAX_INTERVAL)
+ return -EINVAL;
+
+- timer_interval = val;
++ decay_interval = val;
+
+- cec_mod_timer(&cec_timer, timer_interval);
++ cec_mod_work(decay_interval);
+ return 0;
+ }
+ DEFINE_DEBUGFS_ATTRIBUTE(decay_interval_ops, u64_get, decay_interval_set, "%lld\n");
+@@ -433,7 +429,7 @@ static int array_dump(struct seq_file *m
+
+ seq_printf(m, "Flags: 0x%x\n", ca->flags);
+
+- seq_printf(m, "Timer interval: %lld seconds\n", timer_interval);
++ seq_printf(m, "Decay interval: %lld seconds\n", decay_interval);
+ seq_printf(m, "Decays: %lld\n", ca->decays_done);
+
+ seq_printf(m, "Action threshold: %d\n", count_threshold);
+@@ -479,7 +475,7 @@ static int __init create_debugfs_nodes(v
+ }
+
+ decay = debugfs_create_file("decay_interval", S_IRUSR | S_IWUSR, d,
+- &timer_interval, &decay_interval_ops);
++ &decay_interval, &decay_interval_ops);
+ if (!decay) {
+ pr_warn("Error creating decay_interval debugfs node!\n");
+ goto err;
+@@ -515,8 +511,8 @@ void __init cec_init(void)
+ if (create_debugfs_nodes())
+ return;
+
+- setup_timer(&cec_timer, cec_timer_fn, (unsigned long)&ce_arr);
+- cec_mod_timer(&cec_timer, CEC_TIMER_DEFAULT_INTERVAL);
++ INIT_DELAYED_WORK(&cec_work, cec_work_fn);
++ schedule_delayed_work(&cec_work, CEC_DECAY_DEFAULT_INTERVAL);
+
+ pr_info("Correctable Errors collector initialized.\n");
+ }
diff --git a/patches.drivers/ras-cec-fix-binary-search-function.patch b/patches.drivers/ras-cec-fix-binary-search-function.patch
new file mode 100644
index 0000000000..ea4580d069
--- /dev/null
+++ b/patches.drivers/ras-cec-fix-binary-search-function.patch
@@ -0,0 +1,90 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Sat, 20 Apr 2019 13:27:51 +0200
+Subject: RAS/CEC: Fix binary search function
+Git-commit: f3c74b38a55aefe1004200d15a83f109b510068c
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+Switch to using Donald Knuth's binary search algorithm (The Art of
+Computer Programming, vol. 3, section 6.2.1). This should've been done
+from the very beginning but the author must've been smoking something
+very potent at the time.
+
+The problem with the current one was that it would return the wrong
+element index in certain situations:
+
+ https://lkml.kernel.org/r/CAM_iQpVd02zkVJ846cj-Fg1yUNuz6tY5q1Vpj4LrXmE06dPYYg@mail.gmail.com
+
+and the noodling code after the loop was fishy at best.
+
+So switch to using Knuth's binary search. The final result is much
+cleaner and straightforward.
+
+Fixes: 011d82611172 ("RAS: Add a Corrected Errors Collector")
+Reported-by: Cong Wang <xiyou.wangcong@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: <stable@vger.kernel.org>
+---
+ drivers/ras/cec.c | 34 ++++++++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
+index 88e4f3ff0cb8..dbfe3e61d2c2 100644
+--- a/drivers/ras/cec.c
++++ b/drivers/ras/cec.c
+@@ -183,32 +183,38 @@ static void cec_timer_fn(struct timer_list *unused)
+ */
+ static int __find_elem(struct ce_array *ca, u64 pfn, unsigned int *to)
+ {
++ int min = 0, max = ca->n - 1;
+ u64 this_pfn;
+- int min = 0, max = ca->n;
+
+- while (min < max) {
+- int tmp = (max + min) >> 1;
++ while (min <= max) {
++ int i = (min + max) >> 1;
+
+- this_pfn = PFN(ca->array[tmp]);
++ this_pfn = PFN(ca->array[i]);
+
+ if (this_pfn < pfn)
+- min = tmp + 1;
++ min = i + 1;
+ else if (this_pfn > pfn)
+- max = tmp;
+- else {
+- min = tmp;
+- break;
++ max = i - 1;
++ else if (this_pfn == pfn) {
++ if (to)
++ *to = i;
++
++ return i;
+ }
+ }
+
++ /*
++ * When the loop terminates without finding @pfn, min has the index of
++ * the element slot where the new @pfn should be inserted. The loop
++ * terminates when min > max, which means the min index points to the
++ * bigger element while the max index to the smaller element, in-between
++ * which the new @pfn belongs to.
++ *
++ * For more details, see exercise 1, Section 6.2.1 in TAOCP, vol. 3.
++ */
+ if (to)
+ *to = min;
+
+- this_pfn = PFN(ca->array[min]);
+-
+- if (this_pfn == pfn)
+- return min;
+-
+ return -ENOKEY;
+ }
+
+
diff --git a/patches.fixes/SMB3-Fix-endian-warning.patch b/patches.fixes/SMB3-Fix-endian-warning.patch
new file mode 100644
index 0000000000..23ad8ba478
--- /dev/null
+++ b/patches.fixes/SMB3-Fix-endian-warning.patch
@@ -0,0 +1,40 @@
+From: Steve French <smfrench@gmail.com>
+Date: Tue, 19 Sep 2017 11:43:47 -0500
+Subject: [PATCH] SMB3: Fix endian warning
+References: bsc#1137884
+Patch-mainline: v4.14-rc2
+Git-commit: 590d08d3da45e9fed423b08ab38d71886c07abc8
+
+Multi-dialect negotiate patch had a minor endian error.
+
+Signed-off-by: Steve French <smfrench@gmail.com>
+Reviewed-by: Ronnie Sahlberg <lsahlber@redhat.com>
+Cc: Stable <stable@vger.kernel.org> # 4.13+
+Acked-by: Aurelien Aptel <aaptel@suse.com>
+
+---
+ fs/cifs/smb2pdu.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
+index b0eaebe627e9..b4c58a1db1ae 100644
+--- a/fs/cifs/smb2pdu.c
++++ b/fs/cifs/smb2pdu.c
+@@ -570,10 +570,11 @@ SMB2_negotiate(const unsigned int xid, struct cifs_ses *ses)
+ /* ops set to 3.0 by default for default so update */
+ ses->server->ops = &smb21_operations;
+ }
+- } else if (rsp->DialectRevision != ses->server->vals->protocol_id) {
++ } else if (le16_to_cpu(rsp->DialectRevision) !=
++ ses->server->vals->protocol_id) {
+ /* if requested single dialect ensure returned dialect matched */
+ cifs_dbg(VFS, "Illegal 0x%x dialect returned: not requested\n",
+- cpu_to_le16(rsp->DialectRevision));
++ le16_to_cpu(rsp->DialectRevision));
+ return -EIO;
+ }
+
+--
+2.16.4
+
+
diff --git a/series.conf b/series.conf
index c21e988b50..9ae45bfd13 100644
--- a/series.conf
+++ b/series.conf
@@ -7087,6 +7087,7 @@
patches.suse/0041-libceph-don-t-allow-bidirectional-swap-of-pg-upmap-items.patch
patches.suse/0042-ceph-avoid-panic-in-create_session_open_msg-if-utsname-returns-null.patch
patches.fixes/0001-Fix-SMB3.1.1-guest-authentication-to-Samba.patch
+ patches.fixes/SMB3-Fix-endian-warning.patch
patches.fixes/0001-SMB3-Warn-user-if-trying-to-sign-connection-that-aut.patch
patches.fixes/0001-cifs-release-cifs-root_cred-after-exit_cifs.patch
patches.fixes/0001-cifs-release-auth_key.response-for-reconnect.patch
@@ -22252,13 +22253,16 @@
patches.drivers/ALSA-hda-realtek-Apply-the-fixup-for-ASUS-Q325UAR.patch
patches.arch/KVM-PPC-Book3S-Protect-memslots-while-validating-use.patch
patches.fixes/ufs-fix-braino-in-ufs_get_inode_gid-for-solaris-UFS-.patch
+ patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch
patches.arch/cpu-speculation-add-mitigations-cmdline-option.patch
patches.arch/x86-speculation-support-mitigations-cmdline-option.patch
patches.arch/powerpc-speculation-support-mitigations-cmdline-option.patch
patches.arch/s390-speculation-support-mitigations-cmdline-option.patch
+ patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch
patches.fixes/ACPI-button-reinitialize-button-state-upon-resume.patch
patches.drivers/PM-core-Propagate-dev-power.wakeup_path-when-no-call.patch
patches.fixes/ACPI-property-fix-handling-of-data_nodes-in-acpi_get.patch
+ patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
patches.arch/x86-mce-handle-varying-mca-bank-counts.patch
patches.drivers/hwmon-f71805f-Use-request_muxed_region-for-Super-IO-.patch
patches.drivers/hwmon-pc87427-Use-request_muxed_region-for-Super-IO-.patch
@@ -22555,7 +22559,9 @@
patches.drm/drm-bridge-adv7511-Fix-low-refresh-rate-selection.patch
patches.drivers/thermal-cpu_cooling-Actually-trace-CPU-load-in-therm.patch
patches.suse/objtool-fix-function-fallthrough-detection.patch
+ patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch
patches.fixes/configfs-fix-possible-use-after-free-in-configfs_reg.patch
+ patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch
patches.drivers/media-atmel-atmel-isc-fix-INIT_WORK-misplacement.patch
patches.drivers/media-omap_vout-potential-buffer-overflow-in-vidioc_.patch
patches.drivers/media-davinci-vpbe-array-underflow-in-vpbe_enum_outp.patch
@@ -22592,6 +22598,8 @@
patches.drivers/platform-x86-pmc_atom-Add-several-Beckhoff-Automatio.patch
patches.fixes/blk-mq-fix-hang-caused-by-freeze-unfreeze-sequence.patch
patches.fixes/ext4-wait-for-outstanding-dio-during-truncate-in-noj.patch
+ patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch
+ patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch
patches.drivers/gpio-fix-gpio-adp5588-build-errors.patch
patches.fixes/0001-docs-Fix-conf.py-for-Sphinx-2.0.patch
patches.drivers/ALSA-hda-realtek-Set-default-power-save-node-to-0.patch
@@ -22630,6 +22638,7 @@
patches.arch/KVM-PPC-Book3S-HV-XIVE-Do-not-clear-IRQ-data-of-pass.patch
patches.arch/powerpc-perf-Fix-MMCRA-corruption-by-bhrb_filter.patch
patches.fixes/efi-x86-Add-missing-error-handling-to-old_memmap-1-1.patch
+ patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch
patches.fixes/fuse-fallocate-fix-return-with-locked-inode.patch
patches.drivers/hwmon-core-add-thermal-sensors-only-if-dev-of_node-i.patch
patches.drivers/hwmon-pmbus-core-Treat-parameters-as-paged-if-on-mul.patch
@@ -22654,6 +22663,9 @@
patches.drm/drm-i915-perf-fix-whitelist-on-Gen10.patch
patches.drivers/usb-dwc2-Fix-DMA-cache-alignment-issues.patch
patches.drivers/platform-x86-mlx-platform-Fix-parent-device-in-i2c-m.patch
+ patches.drivers/ras-cec-fix-binary-search-function.patch
+ patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch
+ patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch
patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch
patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch
patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch