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authorBorislav Petkov <bp@suse.de>2019-06-15 09:33:51 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 09:33:51 +0200
commit0a372f48fe0adc0458f70f3b59fd4b69c5d0bb6b (patch)
treea6f77f62ec860063bcae961d4d5f3cbda8998a72
parent317d610acee4aa50bd7c90615e5966e596d3d6bc (diff)
x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on
Dhyana (fate#327735).
-rw-r--r--patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch47
-rw-r--r--series.conf1
2 files changed, 48 insertions, 0 deletions
diff --git a/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch b/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
new file mode 100644
index 0000000000..e176cb8ba0
--- /dev/null
+++ b/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
@@ -0,0 +1,47 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:32 +0800
+Subject: x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana
+Git-commit: 0b13bec787dccca96f8c431da732657ae01baf9a
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU uses no delay in smp_quirk_init_udelay(), and does
+HLT on idle just like AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: bp@alien8.de
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/87000fa82e273f5967c908448414228faf61e077.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/smpboot.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
+index f02ecaf97904..5369d7fac797 100644
+--- a/arch/x86/kernel/smpboot.c
++++ b/arch/x86/kernel/smpboot.c
+@@ -676,6 +676,7 @@ static void __init smp_quirk_init_udelay(void)
+
+ /* if modern processor, use no delay */
+ if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
++ ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
+ ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
+ init_udelay = 0;
+ return;
+@@ -1592,7 +1593,8 @@ static inline void mwait_play_dead(void)
+ void *mwait_ptr;
+ int i;
+
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+ return;
+ if (!this_cpu_has(X86_FEATURE_MWAIT))
+ return;
+
diff --git a/series.conf b/series.conf
index d7bff01ce9..50673d79d7 100644
--- a/series.conf
+++ b/series.conf
@@ -19533,6 +19533,7 @@
patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
+ patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch