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authorBorislav Petkov <bp@suse.de>2019-06-15 10:30:02 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 10:30:02 +0200
commit732e9eb15604cf6da453793eace2821557712d17 (patch)
tree1a94e1bf1dc781e47275d22cd72c99e733035728
parent9641595a3477f3163b3b33af5ec7388f36e34a59 (diff)
x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and
northbridge (fate#327735).
-rw-r--r--patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch163
-rw-r--r--series.conf1
2 files changed, 164 insertions, 0 deletions
diff --git a/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch b/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
new file mode 100644
index 0000000000..d97786d7a7
--- /dev/null
+++ b/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
@@ -0,0 +1,163 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Tue, 25 Sep 2018 22:46:11 +0800
+Subject: x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge
+Git-commit: c6babb5806b77c6ca7078c3487bb0a29704a4e38
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Hygon's PCI vendor ID is 0x1d94, and there are PCI devices
+0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform.
+Add Hygon Dhyana support to the PCI and northbridge subsystems by using
+the code path of AMD family 17h.
+
+ [ bp: Massage commit message, sort local vars into reverse xmas tree
+ order and move the amd_northbridges.num check up. ]
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: helgaas@kernel.org
+Cc: linux-pci@vger.kernel.org
+Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cn
+---
+ arch/x86/kernel/amd_nb.c | 45 +++++++++++++++++++++++++++++++++++++--------
+ arch/x86/pci/amd_bus.c | 6 ++++--
+ include/linux/pci_ids.h | 2 ++
+ 3 files changed, 43 insertions(+), 10 deletions(-)
+
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -55,6 +55,21 @@ static const struct pci_device_id amd_nb
+ {}
+ };
+
++static const struct pci_device_id hygon_root_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
++ {}
++};
++
++const struct pci_device_id hygon_nb_misc_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
++ {}
++};
++
++static const struct pci_device_id hygon_nb_link_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
++ {}
++};
++
+ const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
+ { 0x00, 0x18, 0x20 },
+ { 0xff, 0x00, 0x20 },
+@@ -188,15 +203,24 @@ EXPORT_SYMBOL_GPL(amd_df_indirect_read);
+
+ int amd_cache_northbridges(void)
+ {
+- u16 i = 0;
+- struct amd_northbridge *nb;
++ const struct pci_device_id *misc_ids = amd_nb_misc_ids;
++ const struct pci_device_id *link_ids = amd_nb_link_ids;
++ const struct pci_device_id *root_ids = amd_root_ids;
+ struct pci_dev *root, *misc, *link;
++ struct amd_northbridge *nb;
++ u16 i = 0;
+
+ if (amd_northbridges.num)
+ return 0;
+
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
++ root_ids = hygon_root_ids;
++ misc_ids = hygon_nb_misc_ids;
++ link_ids = hygon_nb_link_ids;
++ }
++
+ misc = NULL;
+- while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
++ while ((misc = next_northbridge(misc, misc_ids)) != NULL)
+ i++;
+
+ if (!i)
+@@ -212,11 +236,11 @@ int amd_cache_northbridges(void)
+ link = misc = root = NULL;
+ for (i = 0; i != amd_northbridges.num; i++) {
+ node_to_amd_nb(i)->root = root =
+- next_northbridge(root, amd_root_ids);
++ next_northbridge(root, root_ids);
+ node_to_amd_nb(i)->misc = misc =
+- next_northbridge(misc, amd_nb_misc_ids);
++ next_northbridge(misc, misc_ids);
+ node_to_amd_nb(i)->link = link =
+- next_northbridge(link, amd_nb_link_ids);
++ next_northbridge(link, link_ids);
+ }
+
+ if (amd_gart_present())
+@@ -255,6 +279,7 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges
+ */
+ bool __init early_is_amd_nb(u32 device)
+ {
++ const struct pci_device_id *misc_ids = amd_nb_misc_ids;
+ const struct pci_device_id *id;
+ u32 vendor = device & 0xffff;
+
+@@ -262,8 +287,11 @@ bool __init early_is_amd_nb(u32 device)
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return false;
+
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
++ misc_ids = hygon_nb_misc_ids;
++
+ device >>= 16;
+- for (id = amd_nb_misc_ids; id->vendor; id++)
++ for (id = misc_ids; id->vendor; id++)
+ if (vendor == id->vendor && device == id->device)
+ return true;
+ return false;
+@@ -275,7 +303,8 @@ struct resource *amd_get_mmconfig_range(
+ u64 base, msr;
+ unsigned int segn_busn_bits;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return NULL;
+
+ /* assume all cpus from fam10h have mmconfig */
+--- a/arch/x86/pci/amd_bus.c
++++ b/arch/x86/pci/amd_bus.c
+@@ -92,7 +92,8 @@ static int __init early_root_info_init(v
+ vendor = id & 0xffff;
+ device = (id>>16) & 0xffff;
+
+- if (vendor != PCI_VENDOR_ID_AMD)
++ if (vendor != PCI_VENDOR_ID_AMD &&
++ vendor != PCI_VENDOR_ID_HYGON)
+ continue;
+
+ if (hb_probes[i].device == device) {
+@@ -389,7 +390,8 @@ static int __init pci_io_ecs_init(void)
+
+ static int __init amd_postcore_init(void)
+ {
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return 0;
+
+ early_root_info_init();
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2542,6 +2542,8 @@
+ #define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+ #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
++#define PCI_VENDOR_ID_HYGON 0x1d94
++
+ #define PCI_VENDOR_ID_TEKRAM 0x1de1
+ #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
+
diff --git a/series.conf b/series.conf
index 8d7eac7c3f..511d50d698 100644
--- a/series.conf
+++ b/series.conf
@@ -19537,6 +19537,7 @@
patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch
patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch
+ patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch