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authorBorislav Petkov <bp@suse.de>2019-06-15 12:02:07 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 12:02:07 +0200
commit950ac7830495599ed8268d8dbc0edaaf5472dfc5 (patch)
tree8ef1f08df7016c9558c723cae67f73a41849b490
parent67e2d3fb95948e81089165961e1d0dc54381c313 (diff)
- x86/bugs: Add Hygon Dhyana to the respective mitigation
machinery (fate#327735). - Refresh patches.arch/x86-speculation-consolidate-cpu-whitelists.patch. - Refresh patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch.
-rw-r--r--patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch60
-rw-r--r--patches.arch/x86-speculation-consolidate-cpu-whitelists.patch25
-rw-r--r--patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch14
-rw-r--r--series.conf1
4 files changed, 84 insertions, 16 deletions
diff --git a/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch b/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
new file mode 100644
index 0000000000..ffe46a05c0
--- /dev/null
+++ b/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
@@ -0,0 +1,60 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:35:50 +0800
+Subject: x86/bugs: Add Hygon Dhyana to the respective mitigation machinery
+Git-commit: 1a576b23d63794f39a247fb31056eecccbf9a287
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has the same speculative execution as AMD family
+17h, so share AMD spectre mitigation code with Hygon Dhyana.
+
+Also Hygon Dhyana is not affected by meltdown, so add exception for it.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/0861d39c8a103fc0deca15bafbc85d403666d9ef.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/bugs.c | 4 +++-
+ arch/x86/kernel/cpu/common.c | 1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
+index 40bdaea97fe7..b810cc239375 100644
+--- a/arch/x86/kernel/cpu/bugs.c
++++ b/arch/x86/kernel/cpu/bugs.c
+@@ -312,6 +312,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
+ }
+
+ if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
+ pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
+ return SPECTRE_V2_CMD_AUTO;
+@@ -371,7 +372,8 @@ static void __init spectre_v2_select_mitigation(void)
+ return;
+
+ retpoline_auto:
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+ retpoline_amd:
+ if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
+ pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
+diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
+index 658c85d16a9b..d14c879ba7ba 100644
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -963,6 +963,7 @@ static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
+
+ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
+ { X86_VENDOR_AMD },
++ { X86_VENDOR_HYGON },
+ {}
+ };
+
+
diff --git a/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch b/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
index 9662a8077a..1e9e4005cf 100644
--- a/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
+++ b/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
@@ -20,12 +20,12 @@ Reviewed-by: Jon Masters <jcm@redhat.com>
Tested-by: Jon Masters <jcm@redhat.com>
Acked-by: Borislav Petkov <bp@suse.de>
---
- arch/x86/kernel/cpu/common.c | 103 ++++++++++++++++++++++---------------------
- 1 file changed, 55 insertions(+), 48 deletions(-)
+ arch/x86/kernel/cpu/common.c | 109 +++++++++++++++++++++++--------------------
+ 1 file changed, 59 insertions(+), 50 deletions(-)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
-@@ -898,60 +898,68 @@ static void identify_cpu_without_cpuid(s
+@@ -898,61 +898,71 @@ static void identify_cpu_without_cpuid(s
#endif
}
@@ -39,8 +39,6 @@ Acked-by: Borislav Petkov <bp@suse.de>
- { X86_VENDOR_INTEL, 5 },
- { X86_VENDOR_NSC, 5 },
- { X86_VENDOR_ANY, 4 },
-- {}
--};
+#define NO_SPECULATION BIT(0)
+#define NO_MELTDOWN BIT(1)
+#define NO_SSB BIT(2)
@@ -55,6 +53,9 @@ Acked-by: Borislav Petkov <bp@suse.de>
+#define VULNWL_AMD(family, whitelist) \
+ VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
+
++#define VULNWL_HYGON(family, whitelist) \
++ VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
++
+static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
+ VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
@@ -85,14 +86,18 @@ Acked-by: Borislav Petkov <bp@suse.de>
+ VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF),
-
--static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
-- { X86_VENDOR_AMD },
+ /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
+ VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
++ VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
{}
};
+-static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
+- { X86_VENDOR_AMD },
+- { X86_VENDOR_HYGON },
+- {}
+-};
+-
-/* Only list CPUs which speculate but are non susceptible to SSB */
-static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
@@ -138,7 +143,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
return;
setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
-@@ -960,15 +968,14 @@ static void __init cpu_set_bug_bits(stru
+@@ -961,15 +971,14 @@ static void __init cpu_set_bug_bits(stru
if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
@@ -156,7 +161,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
return;
/* Rogue Data Cache Load? No! */
-@@ -977,7 +984,7 @@ static void __init cpu_set_bug_bits(stru
+@@ -978,7 +987,7 @@ static void __init cpu_set_bug_bits(stru
setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
diff --git a/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch b/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
index 736111e827..fdc98d038f 100644
--- a/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
+++ b/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
@@ -56,8 +56,8 @@ Acked-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/msr-index.h | 5 +++++
- arch/x86/kernel/cpu/common.c | 25 ++++++++++++++++---------
- 3 files changed, 23 insertions(+), 9 deletions(-)
+ arch/x86/kernel/cpu/common.c | 28 ++++++++++++++++++----------
+ 3 files changed, 25 insertions(+), 10 deletions(-)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -99,7 +99,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
#define VULNWL(_vendor, _family, _model, _whitelist) \
{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
-@@ -918,6 +919,7 @@ static const __initconst struct x86_cpu_
+@@ -921,6 +922,7 @@ static const __initconst struct x86_cpu_
VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
@@ -107,7 +107,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION),
VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION),
VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION),
-@@ -934,17 +936,19 @@ static const __initconst struct x86_cpu_
+@@ -937,17 +939,20 @@ static const __initconst struct x86_cpu_
VULNWL_INTEL(CORE_YONAH, NO_SSB),
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF),
@@ -129,14 +129,16 @@ Acked-by: Borislav Petkov <bp@suse.de>
+ VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+ VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+ VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
-
++
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
- VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
+- VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
+ VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
++ VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
{}
};
-@@ -975,6 +979,9 @@ static void __init cpu_set_bug_bits(stru
+@@ -978,6 +983,9 @@ static void __init cpu_set_bug_bits(stru
if (ia32_cap & ARCH_CAP_IBRS_ALL)
setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
diff --git a/series.conf b/series.conf
index f0279fb706..f29be53b57 100644
--- a/series.conf
+++ b/series.conf
@@ -19539,6 +19539,7 @@
patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch
patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
patches.arch/x86-apic-add-hygon-dhyana-support.patch
+ patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch