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authorBorislav Petkov <bp@suse.de>2019-05-19 00:22:27 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 12:02:31 +0200
commit956d7756eb4dcf362585df20f40be8ca30c3277e (patch)
treeb5f9e963152519d7119fe4e7a7f320c5f60682ce
parent950ac7830495599ed8268d8dbc0edaaf5472dfc5 (diff)
x86/mce: Don't disable MCA banks when offlining a CPU on AMD
-rw-r--r--patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch53
-rw-r--r--series.conf1
2 files changed, 54 insertions, 0 deletions
diff --git a/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch b/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
new file mode 100644
index 0000000000..a127df8082
--- /dev/null
+++ b/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
@@ -0,0 +1,53 @@
+From: Yazen Ghannam <yazen.ghannam@amd.com>
+Date: Tue, 13 Jun 2017 18:28:34 +0200
+Subject: x86/mce: Don't disable MCA banks when offlining a CPU on AMD
+Git-commit: ec33838244c8535b23b8d24b167996fd1318bb68
+Patch-mainline: v4.13-rc1
+References: fate#327735
+
+AMD systems have non-core, shared MCA banks within a die. These banks
+are controlled by a master CPU per die. If this CPU is offlined then all
+the shared banks are disabled in addition to the CPU's core banks.
+
+Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
+between SMT thread siblings. If a CPU is offlined then all its sibling's
+MCA banks are also disabled.
+
+Extend the existing vendor check to AMD too.
+
+Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
+[ Fix up comment. ]
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Link: http://lkml.kernel.org/r/20170613162835.30750-8-bp@alien8.de
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+---
+ arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
+index 5cfbaeb6529a..3c54c2b9efc2 100644
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -1912,12 +1912,13 @@ static void mce_disable_error_reporting(void)
+ static void vendor_disable_error_reporting(void)
+ {
+ /*
+- * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
++ * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
+ * Disabling them for just a single offlined CPU is bad, since it will
+ * inhibit reporting for all shared resources on the socket like the
+ * last level cache (LLC), the integrated memory controller (iMC), etc.
+ */
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ return;
+
+ mce_disable_error_reporting();
+
diff --git a/series.conf b/series.conf
index f29be53b57..2417437096 100644
--- a/series.conf
+++ b/series.conf
@@ -1227,6 +1227,7 @@
patches.fixes/cpu-hotplug-Remove-unused-check_for_tasks-function.patch
patches.arch/powerpc-Only-obtain-cpu_hotplug_lock-if-called-by-rt.patch
patches.drivers/0001-ACPI-APEI-Handle-GSIV-and-GPIO-notification-types.patch
+ patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
patches.fixes/xen-mce-dont-issue-error-message.patch
patches.fixes/0001-RAS-CEC-Check-the-correct-variable-in-the-debugfs-er.patch
patches.drivers/0001-usb-typec-Don-t-prevent-using-constant-typec_mode_de.patch