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authorTakashi Iwai <tiwai@suse.de>2019-06-15 18:03:15 +0200
committerTakashi Iwai <tiwai@suse.de>2019-06-15 18:03:15 +0200
commit9f439026d193a38d3e1bfc04bf339c27c2f312d9 (patch)
tree8359fed078b5e1213dcb4f79cd0a080524c41725
parentd586254a8b25b6a3d5a75da5d3d9e7e3c089553a (diff)
parent26d3159a79867c5855fb3cd3c4dbf3c6b93aaf21 (diff)
Merge branch 'users/bpetkov/SLE15/for-next' into SLE15
Pull Hygon Dhyana support from Borislav Petkov
-rw-r--r--config/x86_64/default1
-rw-r--r--patches.arch/acpi-add-hygon-dhyana-support.patch48
-rw-r--r--patches.arch/cpufreq-add-hygon-dhyana-support.patch91
-rw-r--r--patches.arch/edac-amd64-add-hygon-dhyana-support.patch92
-rw-r--r--patches.arch/perf-tools-add-hygon-dhyana-support.patch39
-rw-r--r--patches.arch/tools-cpupower-add-hygon-dhyana-support.patch115
-rw-r--r--patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch38
-rw-r--r--patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch57
-rw-r--r--patches.arch/x86-apic-add-hygon-dhyana-support.patch62
-rw-r--r--patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch60
-rw-r--r--patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch502
-rw-r--r--patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch131
-rw-r--r--patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch55
-rw-r--r--patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch133
-rw-r--r--patches.arch/x86-kvm-add-hygon-dhyana-support-to-kvm.patch83
-rw-r--r--patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch111
-rw-r--r--patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch53
-rw-r--r--patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch163
-rw-r--r--patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch47
-rw-r--r--patches.arch/x86-speculation-consolidate-cpu-whitelists.patch25
-rw-r--r--patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch14
-rw-r--r--patches.arch/x86-xen-add-hygon-dhyana-support-to-xen.patch78
-rw-r--r--patches.drivers/cpufreq-amd-ignore-the-check-for-procfeedback-in-st-cz.patch52
-rw-r--r--series.conf26
24 files changed, 2057 insertions, 19 deletions
diff --git a/config/x86_64/default b/config/x86_64/default
index d1e645f531..4adf1dc15e 100644
--- a/config/x86_64/default
+++ b/config/x86_64/default
@@ -508,6 +508,7 @@ CONFIG_X86_DEBUGCTLMSR=y
# CONFIG_PROCESSOR_SELECT is not set
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_HYGON=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
diff --git a/patches.arch/acpi-add-hygon-dhyana-support.patch b/patches.arch/acpi-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..63485b51f6
--- /dev/null
+++ b/patches.arch/acpi-add-hygon-dhyana-support.patch
@@ -0,0 +1,48 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:37:05 +0800
+Subject: ACPI: Add Hygon Dhyana support
+Git-commit: 7377ed4bd56e6cc1ddbb63f03626fc5b92d3d6fe
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has NONSTOP TSC feature, so enable the ACPI driver
+support to it.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Cc: rjw@rjwysocki.net
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: lenb@kernel.org
+Cc: rafael@kernel.org
+Cc: linux-acpi@vger.kernel.org
+Link: https://lkml.kernel.org/r/cce6ee26f4e2ebbab493433264d89d7cea661284.1537533369.git.puwen@hygon.cn
+---
+ drivers/acpi/acpi_pad.c | 1 +
+ drivers/acpi/processor_idle.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/acpi/acpi_pad.c
++++ b/drivers/acpi/acpi_pad.c
+@@ -70,6 +70,7 @@ static void power_saving_mwait_init(void
+
+ #if defined(CONFIG_X86)
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_INTEL:
+ /*
+--- a/drivers/acpi/processor_idle.c
++++ b/drivers/acpi/processor_idle.c
+@@ -203,6 +203,7 @@ static void lapic_timer_state_broadcast(
+ static void tsc_check_state(int state)
+ {
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_INTEL:
+ /*
diff --git a/patches.arch/cpufreq-add-hygon-dhyana-support.patch b/patches.arch/cpufreq-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..664f59219f
--- /dev/null
+++ b/patches.arch/cpufreq-add-hygon-dhyana-support.patch
@@ -0,0 +1,91 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:37:38 +0800
+Subject: cpufreq: Add Hygon Dhyana support
+Git-commit: cc9690cfc7a36873b219d569049e10f073dd22e4
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU supports ACPI P-States, and there is SMBus device
+(PCI device ID 0x790b) on the Hygon platform. Add Hygon Dhyana support
+to the cpufreq driver by using the code path of AMD family 17h.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Cc: rjw@rjwysocki.net
+Cc: viresh.kumar@linaro.org
+Cc: bp@alien8.de
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: rafael@kernel.org
+Cc: linux-pm@vger.kernel.org
+Link: https://lkml.kernel.org/r/4db6f0f8537a93c172430c446a0297a6ab1c3c2d.1537533369.git.puwen@hygon.cn
+---
+ drivers/cpufreq/acpi-cpufreq.c | 5 +++++
+ drivers/cpufreq/amd_freq_sensitivity.c | 9 +++++++--
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
+index b61f4ec43e06..d62fd374d5c7 100644
+--- a/drivers/cpufreq/acpi-cpufreq.c
++++ b/drivers/cpufreq/acpi-cpufreq.c
+@@ -61,6 +61,7 @@ enum {
+
+ #define INTEL_MSR_RANGE (0xffff)
+ #define AMD_MSR_RANGE (0x7)
++#define HYGON_MSR_RANGE (0x7)
+
+ #define MSR_K7_HWCR_CPB_DIS (1ULL << 25)
+
+@@ -95,6 +96,7 @@ static bool boost_state(unsigned int cpu)
+ rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
+ msr = lo | ((u64)hi << 32);
+ return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
+ msr = lo | ((u64)hi << 32);
+@@ -113,6 +115,7 @@ static int boost_set_msr(bool enable)
+ msr_addr = MSR_IA32_MISC_ENABLE;
+ msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
+ break;
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ msr_addr = MSR_K7_HWCR;
+ msr_mask = MSR_K7_HWCR_CPB_DIS;
+@@ -225,6 +228,8 @@ static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr)
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ msr &= AMD_MSR_RANGE;
++ else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
++ msr &= HYGON_MSR_RANGE;
+ else
+ msr &= INTEL_MSR_RANGE;
+
+diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_freq_sensitivity.c
+index be926d9a66e5..4ac7c3cf34be 100644
+--- a/drivers/cpufreq/amd_freq_sensitivity.c
++++ b/drivers/cpufreq/amd_freq_sensitivity.c
+@@ -111,11 +111,16 @@ static int __init amd_freq_sensitivity_init(void)
+ {
+ u64 val;
+ struct pci_dev *pcidev;
++ unsigned int pci_vendor;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ pci_vendor = PCI_VENDOR_ID_AMD;
++ else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
++ pci_vendor = PCI_VENDOR_ID_HYGON;
++ else
+ return -ENODEV;
+
+- pcidev = pci_get_device(PCI_VENDOR_ID_AMD,
++ pcidev = pci_get_device(pci_vendor,
+ PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
+
+ if (!pcidev) {
+
diff --git a/patches.arch/edac-amd64-add-hygon-dhyana-support.patch b/patches.arch/edac-amd64-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..71a84f2531
--- /dev/null
+++ b/patches.arch/edac-amd64-add-hygon-dhyana-support.patch
@@ -0,0 +1,92 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Thu, 27 Sep 2018 16:31:28 +0200
+Subject: EDAC, amd64: Add Hygon Dhyana support
+Git-commit: c4a3e94641449362ee970f521a2cdb0e8cd08690
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Add support for Hygon Dhyana CPU to EDAC.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: mchehab@kernel.org
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: thomas.lendacky@amd.com
+Cc: linux-edac@vger.kernel.org
+Link: https://lkml.kernel.org/r/9d71061301177822bc55b3bfd44f91057458d886.1537533369.git.puwen@hygon.cn
+---
+ drivers/edac/amd64_edac.c | 10 +++++++++-
+ drivers/edac/mce_amd.c | 4 +++-
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/edac/amd64_edac.c
++++ b/drivers/edac/amd64_edac.c
+@@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64
+
+ scrubval = scrubrates[i].scrubval;
+
+- if (pvt->fam == 0x17) {
++ if (pvt->fam == 0x17 || pvt->fam == 0x18) {
+ __f17h_set_scrubval(pvt, scrubval);
+ } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
+ f15h_select_dct(pvt, 0);
+@@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl
+ break;
+
+ case 0x17:
++ case 0x18:
+ amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
+ if (scrubval & BIT(0)) {
+ amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
+@@ -1044,6 +1045,7 @@ static void determine_memory_type(struct
+ goto ddr3;
+
+ case 0x17:
++ case 0x18:
+ if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
+ pvt->dram_type = MEM_LRDDR4;
+ else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
+@@ -3189,8 +3191,13 @@ static struct amd64_family_type *per_fam
+ break;
+
+ case 0x17:
++ /* fall through */
++ case 0x18:
+ fam_type = &family_types[F17_CPUS];
+ pvt->ops = &family_types[F17_CPUS].ops;
++
++ if (pvt->fam == 0x18)
++ family_types[F17_CPUS].ctl_name = "F18h";
+ break;
+
+ default:
+@@ -3429,6 +3436,7 @@ static const struct x86_cpu_id amd64_cpu
+ { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
++ { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { }
+ };
+ MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
+--- a/drivers/edac/mce_amd.c
++++ b/drivers/edac/mce_amd.c
+@@ -1063,7 +1063,8 @@ static int __init mce_amd_init(void)
+ {
+ struct cpuinfo_x86 *c = &boot_cpu_data;
+
+- if (c->x86_vendor != X86_VENDOR_AMD)
++ if (c->x86_vendor != X86_VENDOR_AMD &&
++ c->x86_vendor != X86_VENDOR_HYGON)
+ return -ENODEV;
+
+ fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
+@@ -1117,6 +1118,7 @@ static int __init mce_amd_init(void)
+ break;
+
+ case 0x17:
++ case 0x18:
+ xec_mask = 0x3f;
+ if (!boot_cpu_has(X86_FEATURE_SMCA)) {
+ printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
diff --git a/patches.arch/perf-tools-add-hygon-dhyana-support.patch b/patches.arch/perf-tools-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..7234edbfe0
--- /dev/null
+++ b/patches.arch/perf-tools-add-hygon-dhyana-support.patch
@@ -0,0 +1,39 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Mon, 12 Nov 2018 15:40:51 +0800
+Subject: perf tools: Add Hygon Dhyana support
+Git-commit: 4787eff3fa88f62fede6ed7afa06477ae6bf984d
+Patch-mainline: v5.0-rc1
+References: fate#327735
+
+The tool perf is useful for the performance analysis on the Hygon Dhyana
+platform. But right now there is no Hygon support for it to analyze the
+KVM guest os data. So add Hygon Dhyana support to it by checking vendor
+string to share the code path of AMD.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Acked-by: Borislav Petkov <bp@suse.de>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Jiri Olsa <jolsa@kernel.org>
+Cc: Namhyung Kim <namhyung@kernel.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Link: http://lkml.kernel.org/r/1542008451-31735-1-git-send-email-puwen@hygon.cn
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+---
+ tools/perf/arch/x86/util/kvm-stat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/perf/arch/x86/util/kvm-stat.c b/tools/perf/arch/x86/util/kvm-stat.c
+index b32409a0e546..081353d7b095 100644
+--- a/tools/perf/arch/x86/util/kvm-stat.c
++++ b/tools/perf/arch/x86/util/kvm-stat.c
+@@ -156,7 +156,7 @@ int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid)
+ if (strstr(cpuid, "Intel")) {
+ kvm->exit_reasons = vmx_exit_reasons;
+ kvm->exit_reasons_isa = "VMX";
+- } else if (strstr(cpuid, "AMD")) {
++ } else if (strstr(cpuid, "AMD") || strstr(cpuid, "Hygon")) {
+ kvm->exit_reasons = svm_exit_reasons;
+ kvm->exit_reasons_isa = "SVM";
+ } else
+
diff --git a/patches.arch/tools-cpupower-add-hygon-dhyana-support.patch b/patches.arch/tools-cpupower-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..2509caa3f4
--- /dev/null
+++ b/patches.arch/tools-cpupower-add-hygon-dhyana-support.patch
@@ -0,0 +1,115 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Thu, 4 Oct 2018 09:21:43 +0800
+Subject: tools/cpupower: Add Hygon Dhyana support
+Git-commit: 995d5f64b62f20f05b8e0972f07ec4d6c23333c9
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The tool cpupower is useful to get CPU frequency information and monitor
+power stats on the Hygon Dhyana platform. So add Hygon Dhyana support to
+it by checking vendor and family to share the code path of AMD family
+17h.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Shuah Khan (Samsung OSG) <shuah@kernel.org>
+CC: Prarit Bhargava <prarit@redhat.com>
+CC: Shuah Khan <shuah@kernel.org>
+CC: Thomas Gleixner <tglx@linutronix.de>
+CC: Thomas Renninger <trenn@suse.com>
+CC: linux-pm@vger.kernel.org
+Link: http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
+---
+ tools/power/cpupower/utils/cpufreq-info.c | 6 ++++--
+ tools/power/cpupower/utils/helpers/amd.c | 1 -
+ tools/power/cpupower/utils/helpers/cpuid.c | 8 +++++---
+ tools/power/cpupower/utils/helpers/helpers.h | 2 +-
+ tools/power/cpupower/utils/idle_monitor/mperf_monitor.c | 3 ++-
+ 5 files changed, 12 insertions(+), 8 deletions(-)
+
+--- a/tools/power/cpupower/utils/cpufreq-info.c
++++ b/tools/power/cpupower/utils/cpufreq-info.c
+@@ -172,6 +172,7 @@ static int get_boost_mode(unsigned int c
+ unsigned long pstates[MAX_HW_PSTATES] = {0,};
+
+ if (cpupower_cpu_info.vendor != X86_VENDOR_AMD &&
++ cpupower_cpu_info.vendor != X86_VENDOR_HYGON &&
+ cpupower_cpu_info.vendor != X86_VENDOR_INTEL)
+ return 0;
+
+@@ -192,8 +193,9 @@ static int get_boost_mode(unsigned int c
+ printf(_(" Supported: %s\n"), support ? _("yes") : _("no"));
+ printf(_(" Active: %s\n"), active ? _("yes") : _("no"));
+
+- if (cpupower_cpu_info.vendor == X86_VENDOR_AMD &&
+- cpupower_cpu_info.family >= 0x10) {
++ if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD &&
++ cpupower_cpu_info.family >= 0x10) ||
++ cpupower_cpu_info.vendor == X86_VENDOR_HYGON) {
+ ret = decode_pstates(cpu, cpupower_cpu_info.family, b_states,
+ pstates, &pstate_no);
+ if (ret)
+--- a/tools/power/cpupower/utils/helpers/amd.c
++++ b/tools/power/cpupower/utils/helpers/amd.c
+@@ -47,7 +47,6 @@ static int get_cof(int family, union msr
+ int fid, did;
+
+ did = get_did(family, pstate);
+-
+ t = 0x10;
+ fid = pstate.bits.fid;
+ if (family == 0x11)
+--- a/tools/power/cpupower/utils/helpers/cpuid.c
++++ b/tools/power/cpupower/utils/helpers/cpuid.c
+@@ -7,7 +7,7 @@
+ #include "helpers/helpers.h"
+
+ static const char *cpu_vendor_table[X86_VENDOR_MAX] = {
+- "Unknown", "GenuineIntel", "AuthenticAMD",
++ "Unknown", "GenuineIntel", "AuthenticAMD", "HygonGenuine",
+ };
+
+ #if defined(__i386__) || defined(__x86_64__)
+@@ -108,6 +108,7 @@ out:
+ fclose(fp);
+ /* Get some useful CPU capabilities from cpuid */
+ if (cpu_info->vendor != X86_VENDOR_AMD &&
++ cpu_info->vendor != X86_VENDOR_HYGON &&
+ cpu_info->vendor != X86_VENDOR_INTEL)
+ return ret;
+
+@@ -123,8 +124,9 @@ out:
+ if (cpuid_level >= 6 && (cpuid_ecx(6) & 0x1))
+ cpu_info->caps |= CPUPOWER_CAP_APERF;
+
+- /* AMD Boost state enable/disable register */
+- if (cpu_info->vendor == X86_VENDOR_AMD) {
++ /* AMD or Hygon Boost state enable/disable register */
++ if (cpu_info->vendor == X86_VENDOR_AMD ||
++ cpu_info->vendor == X86_VENDOR_HYGON) {
+ if (ext_cpuid_level >= 0x80000007 &&
+ (cpuid_edx(0x80000007) & (1 << 9)))
+ cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
+--- a/tools/power/cpupower/utils/helpers/helpers.h
++++ b/tools/power/cpupower/utils/helpers/helpers.h
+@@ -60,7 +60,7 @@ extern int be_verbose;
+
+ /* cpuid and cpuinfo helpers **************************/
+ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
+- X86_VENDOR_AMD, X86_VENDOR_MAX};
++ X86_VENDOR_AMD, X86_VENDOR_HYGON, X86_VENDOR_MAX};
+
+ #define CPUPOWER_CAP_INV_TSC 0x00000001
+ #define CPUPOWER_CAP_APERF 0x00000002
+--- a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c
++++ b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c
+@@ -240,7 +240,8 @@ static int init_maxfreq_mode(void)
+ if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_INV_TSC))
+ goto use_sysfs;
+
+- if (cpupower_cpu_info.vendor == X86_VENDOR_AMD) {
++ if (cpupower_cpu_info.vendor == X86_VENDOR_AMD ||
++ cpupower_cpu_info.vendor == X86_VENDOR_HYGON) {
+ /* MSR_AMD_HWCR tells us whether TSC runs at P0/mperf
+ * freq.
+ * A test whether hwcr is accessable/available would be:
diff --git a/patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch b/patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch
new file mode 100644
index 0000000000..8fb352f8b7
--- /dev/null
+++ b/patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch
@@ -0,0 +1,38 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:35:01 +0800
+Subject: x86/alternative: Init ideal_nops for Hygon Dhyana
+Git-commit: c3fecca457c1aa1c1a2f81bfe68393af244a263e
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The ideal_nops for Hygon Dhyana CPU should be p6_nops.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/79e76c3173716984fe5fdd4a8e2c798bf4193205.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/alternative.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
+index b9d5e7c9ef43..184e9a06b0ff 100644
+--- a/arch/x86/kernel/alternative.c
++++ b/arch/x86/kernel/alternative.c
+@@ -222,6 +222,10 @@ void __init arch_init_ideal_nops(void)
+ }
+ break;
+
++ case X86_VENDOR_HYGON:
++ ideal_nops = p6_nops;
++ return;
++
+ case X86_VENDOR_AMD:
+ if (boot_cpu_data.x86 > 0xf) {
+ ideal_nops = p6_nops;
+
diff --git a/patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch b/patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch
new file mode 100644
index 0000000000..da871463ab
--- /dev/null
+++ b/patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch
@@ -0,0 +1,57 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Tue, 25 Sep 2018 22:45:01 +0800
+Subject: x86/amd_nb: Check vendor in AMD-only functions
+Git-commit: b7a5cb4f220e78490735b2b984ad29b7d8e612a9
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Exit early in functions which are meant to run on AMD only but which get
+run on different vendor (VMs, etc).
+
+ [ bp: rewrite commit message. ]
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: bhelgaas@google.com
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: helgaas@kernel.org
+Link: https://lkml.kernel.org/r/487d8078708baedaf63eb00a82251e228b58f1c2.1537885177.git.puwen@hygon.cn
+---
+ arch/x86/include/asm/amd_nb.h | 3 +++
+ arch/x86/kernel/amd_nb.c | 4 ++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
+index fddb6d26239f..1ae4e5791afa 100644
+--- a/arch/x86/include/asm/amd_nb.h
++++ b/arch/x86/include/asm/amd_nb.h
+@@ -103,6 +103,9 @@ static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
+
+ static inline bool amd_gart_present(void)
+ {
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ return false;
++
+ /* GART present only on Fam15h, upto model 0fh */
+ if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
+ (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index b481b95bd8f6..b51c6b183a35 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -264,6 +264,10 @@ bool __init early_is_amd_nb(u32 device)
+ const struct pci_device_id *id;
+ u32 vendor = device & 0xffff;
+
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
++ return false;
++
+ device >>= 16;
+ for (id = amd_nb_misc_ids; id->vendor; id++)
+ if (vendor == id->vendor && device == id->device)
+
diff --git a/patches.arch/x86-apic-add-hygon-dhyana-support.patch b/patches.arch/x86-apic-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..2941f5619c
--- /dev/null
+++ b/patches.arch/x86-apic-add-hygon-dhyana-support.patch
@@ -0,0 +1,62 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:35:28 +0800
+Subject: x86/apic: Add Hygon Dhyana support
+Git-commit: da33dfef404174b0b452f4d2a9a9e00801794f3a
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Add Hygon Dhyana support to the APIC subsystem. When running in 32 bit
+mode, bigsmp should be enabled if there are more than 8 cores online.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/7a557265a8c7c9e842fe60f9d8e064458801aef3.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/apic/apic.c | 7 +++++++
+ arch/x86/kernel/apic/probe_32.c | 1 +
+ 2 files changed, 8 insertions(+)
+
+diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
+index 84132eddb5a8..ab731ab09f06 100644
+--- a/arch/x86/kernel/apic/apic.c
++++ b/arch/x86/kernel/apic/apic.c
+@@ -224,6 +224,11 @@ static int modern_apic(void)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+ boot_cpu_data.x86 >= 0xf)
+ return 1;
++
++ /* Hygon systems use modern APIC */
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
++ return 1;
++
+ return lapic_get_version() >= 0x14;
+ }
+
+@@ -1912,6 +1917,8 @@ static int __init detect_init_APIC(void)
+ (boot_cpu_data.x86 >= 15))
+ break;
+ goto no_apic;
++ case X86_VENDOR_HYGON:
++ break;
+ case X86_VENDOR_INTEL:
+ if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
+ (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
+diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
+index 02e8acb134f8..47ff2976c292 100644
+--- a/arch/x86/kernel/apic/probe_32.c
++++ b/arch/x86/kernel/apic/probe_32.c
+@@ -185,6 +185,7 @@ void __init default_setup_apic_routing(void)
+ break;
+ }
+ /* If P4 and above fall through */
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ def_to_bigsmp = 1;
+ }
+
diff --git a/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch b/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
new file mode 100644
index 0000000000..ffe46a05c0
--- /dev/null
+++ b/patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
@@ -0,0 +1,60 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:35:50 +0800
+Subject: x86/bugs: Add Hygon Dhyana to the respective mitigation machinery
+Git-commit: 1a576b23d63794f39a247fb31056eecccbf9a287
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has the same speculative execution as AMD family
+17h, so share AMD spectre mitigation code with Hygon Dhyana.
+
+Also Hygon Dhyana is not affected by meltdown, so add exception for it.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/0861d39c8a103fc0deca15bafbc85d403666d9ef.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/bugs.c | 4 +++-
+ arch/x86/kernel/cpu/common.c | 1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
+index 40bdaea97fe7..b810cc239375 100644
+--- a/arch/x86/kernel/cpu/bugs.c
++++ b/arch/x86/kernel/cpu/bugs.c
+@@ -312,6 +312,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
+ }
+
+ if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
+ pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
+ return SPECTRE_V2_CMD_AUTO;
+@@ -371,7 +372,8 @@ static void __init spectre_v2_select_mitigation(void)
+ return;
+
+ retpoline_auto:
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+ retpoline_amd:
+ if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
+ pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
+diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
+index 658c85d16a9b..d14c879ba7ba 100644
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -963,6 +963,7 @@ static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
+
+ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
+ { X86_VENDOR_AMD },
++ { X86_VENDOR_HYGON },
+ {}
+ };
+
+
diff --git a/patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch b/patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
new file mode 100644
index 0000000000..5083e2476b
--- /dev/null
+++ b/patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
@@ -0,0 +1,502 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:33:12 +0800
+Subject: x86/cpu: Create Hygon Dhyana architecture support file
+Git-commit: c9661c1e80b609cd038db7c908e061f0535804ef
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Add x86 architecture support for a new processor: Hygon Dhyana Family
+18h. Carve out initialization code needed by Dhyana into a separate
+compilation unit.
+
+To identify Hygon Dhyana CPU, add a new vendor type X86_VENDOR_HYGON.
+
+Since Dhyana uses AMD functionality to a large degree, select
+CPU_SUP_AMD which provides that functionality.
+
+ [ bp: drop explicit license statement as it has an SPDX tag already. ]
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/1a882065223bacbde5726f3beaa70cebd8dcd814.1537533369.git.puwen@hygon.cn
+---
+ MAINTAINERS | 6
+ arch/x86/Kconfig.cpu | 14 +
+ arch/x86/include/asm/processor.h | 3
+ arch/x86/kernel/cpu/Makefile | 1
+ arch/x86/kernel/cpu/hygon.c | 404 +++++++++++++++++++++++++++++++++++++++
+ 5 files changed, 427 insertions(+), 1 deletion(-)
+
+--- a/arch/x86/include/asm/processor.h
++++ b/arch/x86/include/asm/processor.h
+@@ -157,7 +157,8 @@ enum cpuid_regs_idx {
+ #define X86_VENDOR_CENTAUR 5
+ #define X86_VENDOR_TRANSMETA 7
+ #define X86_VENDOR_NSC 8
+-#define X86_VENDOR_NUM 9
++#define X86_VENDOR_HYGON 9
++#define X86_VENDOR_NUM 10
+
+ #define X86_VENDOR_UNKNOWN 0xff
+
+--- a/arch/x86/Kconfig.cpu
++++ b/arch/x86/Kconfig.cpu
+@@ -438,6 +438,20 @@ config CPU_SUP_AMD
+
+ If unsure, say N.
+
++config CPU_SUP_HYGON
++ default y
++ bool "Support Hygon processors" if PROCESSOR_SELECT
++ select CPU_SUP_AMD
++ help
++ This enables detection, tunings and quirks for Hygon processors
++
++ You need this enabled if you want your kernel to run on an
++ Hygon CPU. Disabling this option on other types of CPUs
++ makes the kernel a tiny bit smaller. Disabling it on an Hygon
++ CPU might render the kernel unbootable.
++
++ If unsure, say N.
++
+ config CPU_SUP_CENTAUR
+ default y
+ bool "Support Centaur processors" if PROCESSOR_SELECT
+--- /dev/null
++++ b/arch/x86/kernel/cpu/hygon.c
+@@ -0,0 +1,404 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Hygon Processor Support for Linux
++ *
++ * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
++ *
++ * Author: Pu Wen <puwen@hygon.cn>
++ */
++#include <linux/io.h>
++
++#include <asm/cpu.h>
++#include <asm/smp.h>
++#include <asm/spec-ctrl.h>
++#include <asm/delay.h>
++#ifdef CONFIG_X86_64
++# include <asm/set_memory.h>
++#endif
++
++#include "cpu.h"
++
++/*
++ * nodes_per_socket: Stores the number of nodes per socket.
++ * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
++ */
++static u32 nodes_per_socket = 1;
++
++#ifdef CONFIG_NUMA
++/*
++ * To workaround broken NUMA config. Read the comment in
++ * srat_detect_node().
++ */
++static int nearby_node(int apicid)
++{
++ int i, node;
++
++ for (i = apicid - 1; i >= 0; i--) {
++ node = __apicid_to_node[i];
++ if (node != NUMA_NO_NODE && node_online(node))
++ return node;
++ }
++ for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
++ node = __apicid_to_node[i];
++ if (node != NUMA_NO_NODE && node_online(node))
++ return node;
++ }
++ return first_node(node_online_map); /* Shouldn't happen */
++}
++#endif
++
++static void hygon_get_topology_early(struct cpuinfo_x86 *c)
++{
++ if (cpu_has(c, X86_FEATURE_TOPOEXT))
++ smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
++}
++
++/*
++ * Fixup core topology information for
++ * (1) Hygon multi-node processors
++ * Assumption: Number of cores in each internal node is the same.
++ * (2) Hygon processors supporting compute units
++ */
++static void hygon_get_topology(struct cpuinfo_x86 *c)
++{
++ u8 node_id;
++ int cpu = smp_processor_id();
++
++ /* get information required for multi-node processors */
++ if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
++ int err;
++ u32 eax, ebx, ecx, edx;
++
++ cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
++
++ node_id = ecx & 0xff;
++
++ c->cpu_core_id = ebx & 0xff;
++
++ if (smp_num_siblings > 1)
++ c->x86_max_cores /= smp_num_siblings;
++
++ /*
++ * In case leaf B is available, use it to derive
++ * topology information.
++ */
++ err = detect_extended_topology(c);
++ if (!err)
++ c->x86_coreid_bits = get_count_order(c->x86_max_cores);
++
++ } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
++ u64 value;
++
++ rdmsrl(MSR_FAM10H_NODE_ID, value);
++ node_id = value & 7;
++
++ per_cpu(cpu_llc_id, cpu) = node_id;
++ } else
++ return;
++
++ if (nodes_per_socket > 1)
++ set_cpu_cap(c, X86_FEATURE_AMD_DCM);
++}
++
++/*
++ * On Hygon setup the lower bits of the APIC id distinguish the cores.
++ * Assumes number of cores is a power of two.
++ */
++static void hygon_detect_cmp(struct cpuinfo_x86 *c)
++{
++ unsigned int bits;
++ int cpu = smp_processor_id();
++
++ bits = c->x86_coreid_bits;
++ /* Low order bits define the core id (index of core in socket) */
++ c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
++ /* Convert the initial APIC ID into the socket ID */
++ c->phys_proc_id = c->initial_apicid >> bits;
++ /* use socket ID also for last level cache */
++ per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
++}
++
++static void srat_detect_node(struct cpuinfo_x86 *c)
++{
++#ifdef CONFIG_NUMA
++ int cpu = smp_processor_id();
++ int node;
++ unsigned int apicid = c->apicid;
++
++ node = numa_cpu_node(cpu);
++ if (node == NUMA_NO_NODE)
++ node = per_cpu(cpu_llc_id, cpu);
++
++ /*
++ * On multi-fabric platform (e.g. Numascale NumaChip) a
++ * platform-specific handler needs to be called to fixup some
++ * IDs of the CPU.
++ */
++ if (x86_cpuinit.fixup_cpu_id)
++ x86_cpuinit.fixup_cpu_id(c, node);
++
++ if (!node_online(node)) {
++ /*
++ * Two possibilities here:
++ *
++ * - The CPU is missing memory and no node was created. In
++ * that case try picking one from a nearby CPU.
++ *
++ * - The APIC IDs differ from the HyperTransport node IDs.
++ * Assume they are all increased by a constant offset, but
++ * in the same order as the HT nodeids. If that doesn't
++ * result in a usable node fall back to the path for the
++ * previous case.
++ *
++ * This workaround operates directly on the mapping between
++ * APIC ID and NUMA node, assuming certain relationship
++ * between APIC ID, HT node ID and NUMA topology. As going
++ * through CPU mapping may alter the outcome, directly
++ * access __apicid_to_node[].
++ */
++ int ht_nodeid = c->initial_apicid;
++
++ if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
++ node = __apicid_to_node[ht_nodeid];
++ /* Pick a nearby node */
++ if (!node_online(node))
++ node = nearby_node(apicid);
++ }
++ numa_set_node(cpu, node);
++#endif
++}
++
++static void early_init_hygon_mc(struct cpuinfo_x86 *c)
++{
++#ifdef CONFIG_SMP
++ unsigned int bits, ecx;
++
++ /* Multi core CPU? */
++ if (c->extended_cpuid_level < 0x80000008)
++ return;
++
++ ecx = cpuid_ecx(0x80000008);
++
++ c->x86_max_cores = (ecx & 0xff) + 1;
++
++ /* CPU telling us the core id bits shift? */
++ bits = (ecx >> 12) & 0xF;
++
++ /* Otherwise recompute */
++ if (bits == 0) {
++ while ((1 << bits) < c->x86_max_cores)
++ bits++;
++ }
++
++ c->x86_coreid_bits = bits;
++#endif
++}
++
++static void bsp_init_hygon(struct cpuinfo_x86 *c)
++{
++#ifdef CONFIG_X86_64
++ unsigned long long tseg;
++
++ /*
++ * Split up direct mapping around the TSEG SMM area.
++ * Don't do it for gbpages because there seems very little
++ * benefit in doing so.
++ */
++ if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
++ unsigned long pfn = tseg >> PAGE_SHIFT;
++
++ pr_debug("tseg: %010llx\n", tseg);
++ if (pfn_range_is_mapped(pfn, pfn + 1))
++ set_memory_4k((unsigned long)__va(tseg), 1);
++ }
++#endif
++
++ if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
++ u64 val;
++
++ rdmsrl(MSR_K7_HWCR, val);
++ if (!(val & BIT(24)))
++ pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
++ }
++
++ if (cpu_has(c, X86_FEATURE_MWAITX))
++ use_mwaitx_delay();
++
++ if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
++ u32 ecx;
++
++ ecx = cpuid_ecx(0x8000001e);
++ nodes_per_socket = ((ecx >> 8) & 7) + 1;
++ } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
++ u64 value;
++
++ rdmsrl(MSR_FAM10H_NODE_ID, value);
++ nodes_per_socket = ((value >> 3) & 7) + 1;
++ }
++
++ if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
++ !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
++ /*
++ * Try to cache the base value so further operations can
++ * avoid RMW. If that faults, do not enable SSBD.
++ */
++ if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
++ setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
++ setup_force_cpu_cap(X86_FEATURE_SSBD);
++ x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
++ }
++ }
++}
++
++static void early_init_hygon(struct cpuinfo_x86 *c)
++{
++ u32 dummy;
++
++ early_init_hygon_mc(c);
++
++ set_cpu_cap(c, X86_FEATURE_K8);
++
++ rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
++
++ /*
++ * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
++ * with P/T states and does not stop in deep C-states
++ */
++ if (c->x86_power & (1 << 8)) {
++ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
++ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
++ }
++
++ /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
++ if (c->x86_power & BIT(12))
++ set_cpu_cap(c, X86_FEATURE_ACC_POWER);
++
++#ifdef CONFIG_X86_64
++ set_cpu_cap(c, X86_FEATURE_SYSCALL32);
++#endif
++
++#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
++ /*
++ * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
++ * can safely set X86_FEATURE_EXTD_APICID unconditionally.
++ */
++ if (boot_cpu_has(X86_FEATURE_APIC))
++ set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
++#endif
++
++ /*
++ * This is only needed to tell the kernel whether to use VMCALL
++ * and VMMCALL. VMMCALL is never executed except under virt, so
++ * we can set it unconditionally.
++ */
++ set_cpu_cap(c, X86_FEATURE_VMMCALL);
++
++ hygon_get_topology_early(c);
++}
++
++static void init_hygon(struct cpuinfo_x86 *c)
++{
++ early_init_hygon(c);
++
++ /*
++ * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
++ * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
++ */
++ clear_cpu_cap(c, 0*32+31);
++
++ set_cpu_cap(c, X86_FEATURE_REP_GOOD);
++
++ /* get apicid instead of initial apic id from cpuid */
++ c->apicid = hard_smp_processor_id();
++
++ set_cpu_cap(c, X86_FEATURE_ZEN);
++ set_cpu_cap(c, X86_FEATURE_CPB);
++
++ cpu_detect_cache_sizes(c);
++
++ hygon_detect_cmp(c);
++ hygon_get_topology(c);
++ srat_detect_node(c);
++
++ if (cpu_has(c, X86_FEATURE_XMM2)) {
++ unsigned long long val;
++ int ret;
++
++ /*
++ * A serializing LFENCE has less overhead than MFENCE, so
++ * use it for execution serialization. On families which
++ * don't have that MSR, LFENCE is already serializing.
++ * msr_set_bit() uses the safe accessors, too, even if the MSR
++ * is not present.
++ */
++ msr_set_bit(MSR_F10H_DECFG,
++ MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
++
++ /*
++ * Verify that the MSR write was successful (could be running
++ * under a hypervisor) and only then assume that LFENCE is
++ * serializing.
++ */
++ ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
++ if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
++ /* A serializing LFENCE stops RDTSC speculation */
++ set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
++ } else {
++ /* MFENCE stops RDTSC speculation */
++ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
++ }
++ }
++
++ /*
++ * Hygon processors have APIC timer running in deep C states.
++ */
++ set_cpu_cap(c, X86_FEATURE_ARAT);
++
++ /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
++ if (!cpu_has(c, X86_FEATURE_XENPV))
++ set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
++}
++
++static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
++{
++ u32 ebx, eax, ecx, edx;
++ u16 mask = 0xfff;
++
++ if (c->extended_cpuid_level < 0x80000006)
++ return;
++
++ cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
++
++ tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
++ tlb_lli_4k[ENTRIES] = ebx & mask;
++
++ /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
++ if (!((eax >> 16) & mask))
++ tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
++ else
++ tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
++
++ /* a 4M entry uses two 2M entries */
++ tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
++
++ /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
++ if (!(eax & mask)) {
++ cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
++ tlb_lli_2m[ENTRIES] = eax & 0xff;
++ } else
++ tlb_lli_2m[ENTRIES] = eax & mask;
++
++ tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
++}
++
++static const struct cpu_dev hygon_cpu_dev = {
++ .c_vendor = "Hygon",
++ .c_ident = { "HygonGenuine" },
++ .c_early_init = early_init_hygon,
++ .c_detect_tlb = cpu_detect_tlb_hygon,
++ .c_bsp_init = bsp_init_hygon,
++ .c_init = init_hygon,
++ .c_x86_vendor = X86_VENDOR_HYGON,
++};
++
++cpu_dev_register(hygon_cpu_dev);
+--- a/arch/x86/kernel/cpu/Makefile
++++ b/arch/x86/kernel/cpu/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_X86_FEATURE_NAMES) += capfl
+
+ obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
+ obj-$(CONFIG_CPU_SUP_AMD) += amd.o
++obj-$(CONFIG_CPU_SUP_HYGON) += hygon.o
+ obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
+ obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
+ obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -6166,6 +6166,12 @@ W: https://linuxtv.org
+ S: Supported
+ F: drivers/media/platform/sti/hva
+
++HYGON PROCESSOR SUPPORT
++M: Pu Wen <puwen@hygon.cn>
++L: linux-kernel@vger.kernel.org
++S: Maintained
++F: arch/x86/kernel/cpu/hygon.c
++
+ Hyper-V CORE AND DRIVERS
+ M: "K. Y. Srinivasan" <kys@microsoft.com>
+ M: Haiyang Zhang <haiyangz@microsoft.com>
diff --git a/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch b/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
new file mode 100644
index 0000000000..eb60e4264f
--- /dev/null
+++ b/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
@@ -0,0 +1,131 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:33:44 +0800
+Subject: x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
+Git-commit: d4f7423efdd1419b17524d090ff9ff4024bcf09b
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has a topology extensions bit in CPUID. With
+this bit, the kernel can get the cache information. So add support in
+cpuid4_cache_lookup_regs() to get the correct cache size.
+
+The Hygon Dhyana CPU also discovers num_cache_leaves via CPUID leaf
+0x8000001d, so add support to it in find_num_cache_leaves().
+
+Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
+functions to initialize Dhyana cache info. Setup cache cpumap in the
+same way as AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: bp@alien8.de
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/2a686b2ac0e2f5a1f2f5f101124d9dd44f949731.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/cpu.h | 2 ++
+ arch/x86/kernel/cpu/hygon.c | 3 +++
+ arch/x86/kernel/cpu/intel_cacheinfo.c | 31 +++++++++++++++++++++++++++++--
+ 3 files changed, 34 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/cpu.h
++++ b/arch/x86/kernel/cpu/cpu.h
+@@ -50,5 +50,7 @@ extern void x86_spec_ctrl_setup_ap(void)
+ extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
+ extern int detect_extended_topology(struct cpuinfo_x86 *c);
+ extern int detect_ht_early(struct cpuinfo_x86 *c);
++extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
++void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
+
+ #endif /* ARCH_X86_CPU_H */
+--- a/arch/x86/kernel/cpu/hygon.c
++++ b/arch/x86/kernel/cpu/hygon.c
+@@ -86,6 +86,7 @@ static void hygon_get_topology(struct cp
+ if (!err)
+ c->x86_coreid_bits = get_count_order(c->x86_max_cores);
+
++ cacheinfo_hygon_init_llc_id(c, cpu, node_id);
+ } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
+ u64 value;
+
+@@ -320,6 +321,8 @@ static void init_hygon(struct cpuinfo_x8
+ hygon_get_topology(c);
+ srat_detect_node(c);
+
++ init_hygon_cacheinfo(c);
++
+ if (cpu_has(c, X86_FEATURE_XMM2)) {
+ unsigned long long val;
+ int ret;
+--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
+@@ -395,6 +395,22 @@ static void amd_l3_disable_index(struct
+ }
+ }
+
++void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
++{
++ /*
++ * We may have multiple LLCs if L3 caches exist, so check if we
++ * have an L3 cache by looking at the L3 cache CPUID leaf.
++ */
++ if (!cpuid_edx(0x80000006))
++ return;
++
++ /*
++ * LLC is at the core complex level.
++ * Core complex ID is ApicId[3] for these processors.
++ */
++ per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
++}
++
+ /*
+ * disable a L3 cache index by using a disable-slot
+ *
+@@ -599,6 +615,10 @@ cpuid4_cache_lookup_regs(int index, stru
+ else
+ amd_cpuid4(index, &eax, &ebx, &ecx);
+ amd_init_l3_cache(this_leaf, index);
++ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
++ cpuid_count(0x8000001d, index, &eax.full,
++ &ebx.full, &ecx.full, &edx);
++ amd_init_l3_cache(this_leaf, index);
+ } else {
+ cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
+ }
+@@ -622,7 +642,8 @@ static int find_num_cache_leaves(struct
+ union _cpuid4_leaf_eax cache_eax;
+ int i = -1;
+
+- if (c->x86_vendor == X86_VENDOR_AMD)
++ if (c->x86_vendor == X86_VENDOR_AMD ||
++ c->x86_vendor == X86_VENDOR_HYGON)
+ op = 0x8000001d;
+ else
+ op = 4;
+@@ -649,6 +670,11 @@ void init_amd_cacheinfo(struct cpuinfo_x
+ }
+ }
+
++void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
++{
++ num_cache_leaves = find_num_cache_leaves(c);
++}
++
+ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+ {
+ /* Cache sizes */
+@@ -871,7 +897,8 @@ static void __cache_cpumap_setup(unsigne
+ int index_msb, i;
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+
+- if (c->x86_vendor == X86_VENDOR_AMD) {
++ if (c->x86_vendor == X86_VENDOR_AMD ||
++ c->x86_vendor == X86_VENDOR_HYGON) {
+ if (__cache_amd_cpumap_setup(cpu, index, base))
+ return;
+ }
diff --git a/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch b/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
new file mode 100644
index 0000000000..eda9ef26e6
--- /dev/null
+++ b/patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
@@ -0,0 +1,55 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:16 +0800
+Subject: x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
+Git-commit: 39dc6f154dac134e4612827cb5283934c1862cb8
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has a special MSR way to force WB for memory >4GB,
+and support TOP_MEM2. Therefore, it is necessary to add Hygon Dhyana
+support in amd_special_default_mtrr().
+
+The number of variable MTRRs for Hygon is 2 as AMD's.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/8246f81648d014601de3812ade40e85d9c50d9b3.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
+ arch/x86/kernel/cpu/mtrr/main.c | 2 +-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
+index 765afd599039..3668c5df90c6 100644
+--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
++++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
+@@ -831,7 +831,8 @@ int __init amd_special_default_mtrr(void)
+ {
+ u32 l, h;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return 0;
+ if (boot_cpu_data.x86 < 0xf)
+ return 0;
+diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
+index 9a19c800fe40..507039c20128 100644
+--- a/arch/x86/kernel/cpu/mtrr/main.c
++++ b/arch/x86/kernel/cpu/mtrr/main.c
+@@ -127,7 +127,7 @@ static void __init set_num_var_ranges(void)
+
+ if (use_intel())
+ rdmsr(MSR_MTRRcap, config, dummy);
+- else if (is_cpu(AMD))
++ else if (is_cpu(AMD) || is_cpu(HYGON))
+ config = 2;
+ else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
+ config = 8;
+
diff --git a/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch b/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
new file mode 100644
index 0000000000..3015ea2ff2
--- /dev/null
+++ b/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
@@ -0,0 +1,133 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:47 +0800
+Subject: x86/events: Add Hygon Dhyana support to PMU infrastructure
+Git-commit: 6d0ef316b9f8ea03fa867debda70b2f11a0b9736
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
+Family 17h one. To support it, call amd_pmu_init() to share the AMD PMU
+initialization flow, and change the PMU name to "HYGON".
+
+The Hygon Dhyana CPU supports both legacy and extension PMC MSRs (perf
+counter registers and event selection registers), so add Hygon Dhyana
+support in the similar way as AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/events/amd/core.c | 4 ++++
+ arch/x86/events/amd/uncore.c | 20 +++++++++++++-------
+ arch/x86/events/core.c | 4 ++++
+ arch/x86/kernel/cpu/perfctr-watchdog.c | 2 ++
+ 4 files changed, 23 insertions(+), 7 deletions(-)
+
+diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
+index c84584bb9402..7d2d7c801dba 100644
+--- a/arch/x86/events/amd/core.c
++++ b/arch/x86/events/amd/core.c
+@@ -669,6 +669,10 @@ static int __init amd_core_pmu_init(void)
+ * We fallback to using default amd_get_event_constraints.
+ */
+ break;
++ case 0x18:
++ pr_cont("Fam18h ");
++ /* Using default amd_get_event_constraints. */
++ break;
+ default:
+ pr_err("core perfctr but no constraints; unknown hardware!\n");
+ return -ENODEV;
+diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
+index 981ba5e8241b..c7d745bc4136 100644
+--- a/arch/x86/events/amd/uncore.c
++++ b/arch/x86/events/amd/uncore.c
+@@ -507,17 +507,19 @@ static int __init amd_uncore_init(void)
+ {
+ int ret = -ENODEV;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return -ENODEV;
+
+ if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
+ return -ENODEV;
+
+- if (boot_cpu_data.x86 == 0x17) {
++ if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+ /*
+- * For F17h, the Northbridge counters are repurposed as Data
+- * Fabric counters. Also, L3 counters are supported too. The PMUs
+- * are exported based on family as either L2 or L3 and NB or DF.
++ * For F17h or F18h, the Northbridge counters are
++ * repurposed as Data Fabric counters. Also, L3
++ * counters are supported too. The PMUs are exported
++ * based on family as either L2 or L3 and NB or DF.
+ */
+ num_counters_nb = NUM_COUNTERS_NB;
+ num_counters_llc = NUM_COUNTERS_L3;
+@@ -547,7 +549,9 @@ static int __init amd_uncore_init(void)
+ if (ret)
+ goto fail_nb;
+
+- pr_info("AMD NB counters detected\n");
++ pr_info("%s NB counters detected\n",
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
++ "HYGON" : "AMD");
+ ret = 0;
+ }
+
+@@ -561,7 +565,9 @@ static int __init amd_uncore_init(void)
+ if (ret)
+ goto fail_llc;
+
+- pr_info("AMD LLC counters detected\n");
++ pr_info("%s LLC counters detected\n",
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
++ "HYGON" : "AMD");
+ ret = 0;
+ }
+
+diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
+index dfb2f7c0d019..9c562f5fbde0 100644
+--- a/arch/x86/events/core.c
++++ b/arch/x86/events/core.c
+@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void)
+ case X86_VENDOR_AMD:
+ err = amd_pmu_init();
+ break;
++ case X86_VENDOR_HYGON:
++ err = amd_pmu_init();
++ x86_pmu.name = "HYGON";
++ break;
+ default:
+ err = -ENOTSUPP;
+ }
+diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
+index d389083330c5..9556930cd8c1 100644
+--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
++++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
+@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
+ {
+ /* returns the bit offset of the performance counter register */
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ if (msr >= MSR_F15H_PERF_CTR)
+ return (msr - MSR_F15H_PERF_CTR) >> 1;
+@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
+ {
+ /* returns the bit offset of the event selection register */
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ if (msr >= MSR_F15H_PERF_CTL)
+ return (msr - MSR_F15H_PERF_CTL) >> 1;
+
diff --git a/patches.arch/x86-kvm-add-hygon-dhyana-support-to-kvm.patch b/patches.arch/x86-kvm-add-hygon-dhyana-support-to-kvm.patch
new file mode 100644
index 0000000000..e5d2085c8f
--- /dev/null
+++ b/patches.arch/x86-kvm-add-hygon-dhyana-support-to-kvm.patch
@@ -0,0 +1,83 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:36:31 +0800
+Subject: x86/kvm: Add Hygon Dhyana support to KVM
+Git-commit: b8f4abb652146ddde04ab6e2a80e8cde27ff4470
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
+So enable the KVM infrastructure support to it.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: pbonzini@redhat.com
+Cc: rkrcmar@redhat.com
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: kvm@vger.kernel.org
+Link: https://lkml.kernel.org/r/654dd12876149fba9561698eaf9fc15d030301f8.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/include/asm/kvm_emulate.h | 4 ++++
+ arch/x86/include/asm/virtext.h | 5 +++--
+ arch/x86/kvm/emulate.c | 11 ++++++++++-
+ 3 files changed, 17 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
+index 0f82cd91cd3c..93c4bf598fb0 100644
+--- a/arch/x86/include/asm/kvm_emulate.h
++++ b/arch/x86/include/asm/kvm_emulate.h
+@@ -364,6 +364,10 @@ struct x86_emulate_ctxt {
+ #define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574
+ #define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273
+
++#define X86EMUL_CPUID_VENDOR_HygonGenuine_ebx 0x6f677948
++#define X86EMUL_CPUID_VENDOR_HygonGenuine_ecx 0x656e6975
++#define X86EMUL_CPUID_VENDOR_HygonGenuine_edx 0x6e65476e
++
+ #define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547
+ #define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e
+ #define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69
+diff --git a/arch/x86/include/asm/virtext.h b/arch/x86/include/asm/virtext.h
+index 0116b2ee9e64..e05e0d309244 100644
+--- a/arch/x86/include/asm/virtext.h
++++ b/arch/x86/include/asm/virtext.h
+@@ -83,9 +83,10 @@ static inline void cpu_emergency_vmxoff(void)
+ */
+ static inline int cpu_has_svm(const char **msg)
+ {
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) {
+ if (msg)
+- *msg = "not amd";
++ *msg = "not amd or hygon";
+ return 0;
+ }
+
+diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
+index 106482da6388..34edf198708f 100644
+--- a/arch/x86/kvm/emulate.c
++++ b/arch/x86/kvm/emulate.c
+@@ -2711,7 +2711,16 @@ static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
+ edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
+ return true;
+
+- /* default: (not Intel, not AMD), apply Intel's stricter rules... */
++ /* Hygon ("HygonGenuine") */
++ if (ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx &&
++ ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx &&
++ edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx)
++ return true;
++
++ /*
++ * default: (not Intel, not AMD, not Hygon), apply Intel's
++ * stricter rules...
++ */
+ return false;
+ }
+
+
diff --git a/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch b/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
new file mode 100644
index 0000000000..479ebdd24c
--- /dev/null
+++ b/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
@@ -0,0 +1,111 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:36:04 +0800
+Subject: x86/mce: Add Hygon Dhyana support to the MCA infrastructure
+Git-commit: ac78bd72355d0da64c073c12927264d4ff19b886
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The machine check architecture for Hygon Dhyana CPU is similar to the
+AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
+code path of AMD family 17h.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: tony.luck@intel.com
+Cc: thomas.lendacky@amd.com
+Cc: linux-edac@vger.kernel.org
+Link: https://lkml.kernel.org/r/87d8a4f16bdea0bfe0c0cf2e4a8d2c2a99b1055c.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/include/asm/mce.h | 2 ++
+ arch/x86/kernel/cpu/mcheck/mce-severity.c | 3 ++-
+ arch/x86/kernel/cpu/mcheck/mce.c | 18 ++++++++++++++----
+ 3 files changed, 18 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/include/asm/mce.h
++++ b/arch/x86/include/asm/mce.h
+@@ -269,6 +269,8 @@ static inline void mce_amd_feature_init(
+ static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
+ #endif
+
++static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
++
+ int mce_available(struct cpuinfo_x86 *c);
+ bool mce_is_memory_error(struct mce *m);
+
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -507,9 +507,9 @@ static int mce_usable_address(struct mce
+
+ bool mce_is_memory_error(struct mce *m)
+ {
+- if (m->cpuvendor == X86_VENDOR_AMD) {
++ if (m->cpuvendor == X86_VENDOR_AMD ||
++ m->cpuvendor == X86_VENDOR_HYGON) {
+ return amd_mce_is_memory_error(m);
+-
+ } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+ /*
+ * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
+@@ -538,6 +538,9 @@ static bool mce_is_correctable(struct mc
+ if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+ return false;
+
++ if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
++ return false;
++
+ if (m->status & MCI_STATUS_UC)
+ return false;
+
+@@ -1698,7 +1701,7 @@ static int __mcheck_cpu_ancient_init(str
+ */
+ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
+ {
+- if (c->x86_vendor == X86_VENDOR_AMD) {
++ if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
+ mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
+ mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
+ mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
+@@ -1725,6 +1728,11 @@ static void __mcheck_cpu_init_vendor(str
+ break;
+ }
+
++ case X86_VENDOR_HYGON:
++ mce_hygon_feature_init(c);
++ break;
++
++
+ default:
+ break;
+ }
+@@ -1947,12 +1955,14 @@ static void mce_disable_error_reporting(
+ static void vendor_disable_error_reporting(void)
+ {
+ /*
+- * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
++ * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
++ * are socket-wide.
+ * Disabling them for just a single offlined CPU is bad, since it will
+ * inhibit reporting for all shared resources on the socket like the
+ * last level cache (LLC), the integrated memory controller (iMC), etc.
+ */
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ return;
+
+--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
++++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
+@@ -328,7 +328,8 @@ int (*mce_severity)(struct mce *m, int t
+
+ void __init mcheck_vendor_init_severity(void)
+ {
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+ mce_severity = mce_severity_amd;
+ }
+
diff --git a/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch b/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
new file mode 100644
index 0000000000..a127df8082
--- /dev/null
+++ b/patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
@@ -0,0 +1,53 @@
+From: Yazen Ghannam <yazen.ghannam@amd.com>
+Date: Tue, 13 Jun 2017 18:28:34 +0200
+Subject: x86/mce: Don't disable MCA banks when offlining a CPU on AMD
+Git-commit: ec33838244c8535b23b8d24b167996fd1318bb68
+Patch-mainline: v4.13-rc1
+References: fate#327735
+
+AMD systems have non-core, shared MCA banks within a die. These banks
+are controlled by a master CPU per die. If this CPU is offlined then all
+the shared banks are disabled in addition to the CPU's core banks.
+
+Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
+between SMT thread siblings. If a CPU is offlined then all its sibling's
+MCA banks are also disabled.
+
+Extend the existing vendor check to AMD too.
+
+Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
+[ Fix up comment. ]
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Link: http://lkml.kernel.org/r/20170613162835.30750-8-bp@alien8.de
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+---
+ arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
+index 5cfbaeb6529a..3c54c2b9efc2 100644
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -1912,12 +1912,13 @@ static void mce_disable_error_reporting(void)
+ static void vendor_disable_error_reporting(void)
+ {
+ /*
+- * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
++ * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
+ * Disabling them for just a single offlined CPU is bad, since it will
+ * inhibit reporting for all shared resources on the socket like the
+ * last level cache (LLC), the integrated memory controller (iMC), etc.
+ */
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ return;
+
+ mce_disable_error_reporting();
+
diff --git a/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch b/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
new file mode 100644
index 0000000000..d97786d7a7
--- /dev/null
+++ b/patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
@@ -0,0 +1,163 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Tue, 25 Sep 2018 22:46:11 +0800
+Subject: x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge
+Git-commit: c6babb5806b77c6ca7078c3487bb0a29704a4e38
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Hygon's PCI vendor ID is 0x1d94, and there are PCI devices
+0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform.
+Add Hygon Dhyana support to the PCI and northbridge subsystems by using
+the code path of AMD family 17h.
+
+ [ bp: Massage commit message, sort local vars into reverse xmas tree
+ order and move the amd_northbridges.num check up. ]
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: helgaas@kernel.org
+Cc: linux-pci@vger.kernel.org
+Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cn
+---
+ arch/x86/kernel/amd_nb.c | 45 +++++++++++++++++++++++++++++++++++++--------
+ arch/x86/pci/amd_bus.c | 6 ++++--
+ include/linux/pci_ids.h | 2 ++
+ 3 files changed, 43 insertions(+), 10 deletions(-)
+
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -55,6 +55,21 @@ static const struct pci_device_id amd_nb
+ {}
+ };
+
++static const struct pci_device_id hygon_root_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
++ {}
++};
++
++const struct pci_device_id hygon_nb_misc_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
++ {}
++};
++
++static const struct pci_device_id hygon_nb_link_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
++ {}
++};
++
+ const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
+ { 0x00, 0x18, 0x20 },
+ { 0xff, 0x00, 0x20 },
+@@ -188,15 +203,24 @@ EXPORT_SYMBOL_GPL(amd_df_indirect_read);
+
+ int amd_cache_northbridges(void)
+ {
+- u16 i = 0;
+- struct amd_northbridge *nb;
++ const struct pci_device_id *misc_ids = amd_nb_misc_ids;
++ const struct pci_device_id *link_ids = amd_nb_link_ids;
++ const struct pci_device_id *root_ids = amd_root_ids;
+ struct pci_dev *root, *misc, *link;
++ struct amd_northbridge *nb;
++ u16 i = 0;
+
+ if (amd_northbridges.num)
+ return 0;
+
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
++ root_ids = hygon_root_ids;
++ misc_ids = hygon_nb_misc_ids;
++ link_ids = hygon_nb_link_ids;
++ }
++
+ misc = NULL;
+- while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
++ while ((misc = next_northbridge(misc, misc_ids)) != NULL)
+ i++;
+
+ if (!i)
+@@ -212,11 +236,11 @@ int amd_cache_northbridges(void)
+ link = misc = root = NULL;
+ for (i = 0; i != amd_northbridges.num; i++) {
+ node_to_amd_nb(i)->root = root =
+- next_northbridge(root, amd_root_ids);
++ next_northbridge(root, root_ids);
+ node_to_amd_nb(i)->misc = misc =
+- next_northbridge(misc, amd_nb_misc_ids);
++ next_northbridge(misc, misc_ids);
+ node_to_amd_nb(i)->link = link =
+- next_northbridge(link, amd_nb_link_ids);
++ next_northbridge(link, link_ids);
+ }
+
+ if (amd_gart_present())
+@@ -255,6 +279,7 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges
+ */
+ bool __init early_is_amd_nb(u32 device)
+ {
++ const struct pci_device_id *misc_ids = amd_nb_misc_ids;
+ const struct pci_device_id *id;
+ u32 vendor = device & 0xffff;
+
+@@ -262,8 +287,11 @@ bool __init early_is_amd_nb(u32 device)
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return false;
+
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
++ misc_ids = hygon_nb_misc_ids;
++
+ device >>= 16;
+- for (id = amd_nb_misc_ids; id->vendor; id++)
++ for (id = misc_ids; id->vendor; id++)
+ if (vendor == id->vendor && device == id->device)
+ return true;
+ return false;
+@@ -275,7 +303,8 @@ struct resource *amd_get_mmconfig_range(
+ u64 base, msr;
+ unsigned int segn_busn_bits;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return NULL;
+
+ /* assume all cpus from fam10h have mmconfig */
+--- a/arch/x86/pci/amd_bus.c
++++ b/arch/x86/pci/amd_bus.c
+@@ -92,7 +92,8 @@ static int __init early_root_info_init(v
+ vendor = id & 0xffff;
+ device = (id>>16) & 0xffff;
+
+- if (vendor != PCI_VENDOR_ID_AMD)
++ if (vendor != PCI_VENDOR_ID_AMD &&
++ vendor != PCI_VENDOR_ID_HYGON)
+ continue;
+
+ if (hb_probes[i].device == device) {
+@@ -389,7 +390,8 @@ static int __init pci_io_ecs_init(void)
+
+ static int __init amd_postcore_init(void)
+ {
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return 0;
+
+ early_root_info_init();
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2542,6 +2542,8 @@
+ #define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+ #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
++#define PCI_VENDOR_ID_HYGON 0x1d94
++
+ #define PCI_VENDOR_ID_TEKRAM 0x1de1
+ #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
+
diff --git a/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch b/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
new file mode 100644
index 0000000000..e176cb8ba0
--- /dev/null
+++ b/patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
@@ -0,0 +1,47 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:32 +0800
+Subject: x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana
+Git-commit: 0b13bec787dccca96f8c431da732657ae01baf9a
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU uses no delay in smp_quirk_init_udelay(), and does
+HLT on idle just like AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: bp@alien8.de
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/87000fa82e273f5967c908448414228faf61e077.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/smpboot.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
+index f02ecaf97904..5369d7fac797 100644
+--- a/arch/x86/kernel/smpboot.c
++++ b/arch/x86/kernel/smpboot.c
+@@ -676,6 +676,7 @@ static void __init smp_quirk_init_udelay(void)
+
+ /* if modern processor, use no delay */
+ if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
++ ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
+ ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
+ init_udelay = 0;
+ return;
+@@ -1592,7 +1593,8 @@ static inline void mwait_play_dead(void)
+ void *mwait_ptr;
+ int i;
+
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+ return;
+ if (!this_cpu_has(X86_FEATURE_MWAIT))
+ return;
+
diff --git a/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch b/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
index 9662a8077a..1e9e4005cf 100644
--- a/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
+++ b/patches.arch/x86-speculation-consolidate-cpu-whitelists.patch
@@ -20,12 +20,12 @@ Reviewed-by: Jon Masters <jcm@redhat.com>
Tested-by: Jon Masters <jcm@redhat.com>
Acked-by: Borislav Petkov <bp@suse.de>
---
- arch/x86/kernel/cpu/common.c | 103 ++++++++++++++++++++++---------------------
- 1 file changed, 55 insertions(+), 48 deletions(-)
+ arch/x86/kernel/cpu/common.c | 109 +++++++++++++++++++++++--------------------
+ 1 file changed, 59 insertions(+), 50 deletions(-)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
-@@ -898,60 +898,68 @@ static void identify_cpu_without_cpuid(s
+@@ -898,61 +898,71 @@ static void identify_cpu_without_cpuid(s
#endif
}
@@ -39,8 +39,6 @@ Acked-by: Borislav Petkov <bp@suse.de>
- { X86_VENDOR_INTEL, 5 },
- { X86_VENDOR_NSC, 5 },
- { X86_VENDOR_ANY, 4 },
-- {}
--};
+#define NO_SPECULATION BIT(0)
+#define NO_MELTDOWN BIT(1)
+#define NO_SSB BIT(2)
@@ -55,6 +53,9 @@ Acked-by: Borislav Petkov <bp@suse.de>
+#define VULNWL_AMD(family, whitelist) \
+ VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
+
++#define VULNWL_HYGON(family, whitelist) \
++ VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
++
+static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
+ VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
@@ -85,14 +86,18 @@ Acked-by: Borislav Petkov <bp@suse.de>
+ VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF),
-
--static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
-- { X86_VENDOR_AMD },
+ /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
+ VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
++ VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
{}
};
+-static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
+- { X86_VENDOR_AMD },
+- { X86_VENDOR_HYGON },
+- {}
+-};
+-
-/* Only list CPUs which speculate but are non susceptible to SSB */
-static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
@@ -138,7 +143,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
return;
setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
-@@ -960,15 +968,14 @@ static void __init cpu_set_bug_bits(stru
+@@ -961,15 +971,14 @@ static void __init cpu_set_bug_bits(stru
if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
@@ -156,7 +161,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
return;
/* Rogue Data Cache Load? No! */
-@@ -977,7 +984,7 @@ static void __init cpu_set_bug_bits(stru
+@@ -978,7 +987,7 @@ static void __init cpu_set_bug_bits(stru
setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
diff --git a/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch b/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
index 736111e827..fdc98d038f 100644
--- a/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
+++ b/patches.arch/x86-speculation-mds-add-basic-bug-infrastructure-for-mds.patch
@@ -56,8 +56,8 @@ Acked-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/msr-index.h | 5 +++++
- arch/x86/kernel/cpu/common.c | 25 ++++++++++++++++---------
- 3 files changed, 23 insertions(+), 9 deletions(-)
+ arch/x86/kernel/cpu/common.c | 28 ++++++++++++++++++----------
+ 3 files changed, 25 insertions(+), 10 deletions(-)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -99,7 +99,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
#define VULNWL(_vendor, _family, _model, _whitelist) \
{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
-@@ -918,6 +919,7 @@ static const __initconst struct x86_cpu_
+@@ -921,6 +922,7 @@ static const __initconst struct x86_cpu_
VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
@@ -107,7 +107,7 @@ Acked-by: Borislav Petkov <bp@suse.de>
VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION),
VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION),
VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION),
-@@ -934,17 +936,19 @@ static const __initconst struct x86_cpu_
+@@ -937,17 +939,20 @@ static const __initconst struct x86_cpu_
VULNWL_INTEL(CORE_YONAH, NO_SSB),
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF),
@@ -129,14 +129,16 @@ Acked-by: Borislav Petkov <bp@suse.de>
+ VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+ VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
+ VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
-
++
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
- VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
+- VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF),
+ VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
++ VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
{}
};
-@@ -975,6 +979,9 @@ static void __init cpu_set_bug_bits(stru
+@@ -978,6 +983,9 @@ static void __init cpu_set_bug_bits(stru
if (ia32_cap & ARCH_CAP_IBRS_ALL)
setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
diff --git a/patches.arch/x86-xen-add-hygon-dhyana-support-to-xen.patch b/patches.arch/x86-xen-add-hygon-dhyana-support-to-xen.patch
new file mode 100644
index 0000000000..773d267acf
--- /dev/null
+++ b/patches.arch/x86-xen-add-hygon-dhyana-support-to-xen.patch
@@ -0,0 +1,78 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:36:46 +0800
+Subject: x86/xen: Add Hygon Dhyana support to Xen
+Git-commit: 4044240365e85ef7ae43a6dc454669b57853124c
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+To make Xen work on the Hygon platform, reuse AMD's Xen support code
+path for Hygon Dhyana CPU.
+
+There are six core performance events counters per thread, so there are
+six MSRs for these counters. Also there are four legacy PMC MSRs, they
+are aliases of the counters.
+
+In this version, use the legacy and safe version of MSR access. Tested
+successfully with VPMU enabled in Xen on Hygon platform by testing with
+perf.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
+Cc: jgross@suse.com
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Cc: xen-devel@lists.xenproject.org
+Link: https://lkml.kernel.org/r/311bf41f08f24550aa6c5da3f1e03a68d3b89dac.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/xen/pmu.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
+index 7d00d4ad44d4..9403854cde31 100644
+--- a/arch/x86/xen/pmu.c
++++ b/arch/x86/xen/pmu.c
+@@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
+ k7_counters_mirrored = 0;
+ break;
+ }
++ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
++ amd_num_counters = F10H_NUM_COUNTERS;
++ amd_counters_base = MSR_K7_PERFCTR0;
++ amd_ctrls_base = MSR_K7_EVNTSEL0;
++ amd_msr_step = 1;
++ k7_counters_mirrored = 0;
+ } else {
+ uint32_t eax, ebx, ecx, edx;
+
+@@ -285,7 +291,7 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
+
+ bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
+ {
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
+ if (is_amd_pmu_msr(msr)) {
+ if (!xen_amd_pmu_emulate(msr, val, 1))
+ *val = native_read_msr_safe(msr, err);
+@@ -308,7 +314,7 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
+ {
+ uint64_t val = ((uint64_t)high << 32) | low;
+
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
+ if (is_amd_pmu_msr(msr)) {
+ if (!xen_amd_pmu_emulate(msr, &val, 0))
+ *err = native_write_msr_safe(msr, low, high);
+@@ -379,7 +385,7 @@ static unsigned long long xen_intel_read_pmc(int counter)
+
+ unsigned long long xen_read_pmc(int counter)
+ {
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ return xen_amd_read_pmc(counter);
+ else
+ return xen_intel_read_pmc(counter);
+
diff --git a/patches.drivers/cpufreq-amd-ignore-the-check-for-procfeedback-in-st-cz.patch b/patches.drivers/cpufreq-amd-ignore-the-check-for-procfeedback-in-st-cz.patch
new file mode 100644
index 0000000000..57f06dc96c
--- /dev/null
+++ b/patches.drivers/cpufreq-amd-ignore-the-check-for-procfeedback-in-st-cz.patch
@@ -0,0 +1,52 @@
+From: Akshu Agrawal <Akshu.Agrawal@amd.com>
+Date: Thu, 18 Jan 2018 15:51:30 +0530
+Subject: cpufreq: AMD: Ignore the check for ProcFeedback in ST/CZ
+Git-commit: 59a3b3a8db16621574cbac69f6f1eddb9c60e821
+Patch-mainline: v4.16-rc1
+References: fate#327735
+
+In ST/CZ CPUID 8000_0007_EDX[11, ProcFeedbackInterface] is 0,
+but the mechanism is still available and can be used.
+
+Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ drivers/cpufreq/amd_freq_sensitivity.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_freq_sensitivity.c
+index 042023bbbf62..be926d9a66e5 100644
+--- a/drivers/cpufreq/amd_freq_sensitivity.c
++++ b/drivers/cpufreq/amd_freq_sensitivity.c
+@@ -14,6 +14,7 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/types.h>
++#include <linux/pci.h>
+ #include <linux/percpu-defs.h>
+ #include <linux/init.h>
+ #include <linux/mod_devicetable.h>
+@@ -109,12 +110,18 @@ static unsigned int amd_powersave_bias_target(struct cpufreq_policy *policy,
+ static int __init amd_freq_sensitivity_init(void)
+ {
+ u64 val;
++ struct pci_dev *pcidev;
+
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+ return -ENODEV;
+
+- if (!static_cpu_has(X86_FEATURE_PROC_FEEDBACK))
+- return -ENODEV;
++ pcidev = pci_get_device(PCI_VENDOR_ID_AMD,
++ PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
++
++ if (!pcidev) {
++ if (!static_cpu_has(X86_FEATURE_PROC_FEEDBACK))
++ return -ENODEV;
++ }
+
+ if (rdmsrl_safe(MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &val))
+ return -ENODEV;
+
diff --git a/series.conf b/series.conf
index dd80a2dba4..755d66e271 100644
--- a/series.conf
+++ b/series.conf
@@ -1227,6 +1227,7 @@
patches.fixes/cpu-hotplug-Remove-unused-check_for_tasks-function.patch
patches.arch/powerpc-Only-obtain-cpu_hotplug_lock-if-called-by-rt.patch
patches.drivers/0001-ACPI-APEI-Handle-GSIV-and-GPIO-notification-types.patch
+ patches.arch/x86-mce-don-t-disable-mca-banks-when-offlining-a-cpu-on-amd.patch
patches.fixes/xen-mce-dont-issue-error-message.patch
patches.fixes/0001-RAS-CEC-Check-the-correct-variable-in-the-debugfs-er.patch
patches.drivers/0001-usb-typec-Don-t-prevent-using-constant-typec_mode_de.patch
@@ -13531,6 +13532,7 @@
patches.fixes/gcc-plugins-add-include-required-by-gcc-release-8.patch
patches.fixes/gcc-plugins-use-dynamic-initializers.patch
patches.fixes/nfsd4-permit-layoutget-of-executable-only-files.patch
+ patches.drivers/cpufreq-amd-ignore-the-check-for-procfeedback-in-st-cz.patch
patches.arch/x86-pm-make-apm-idle-driver-initialize-polling-state
patches.drivers/ACPI-sbshc-remove-raw-pointer-from-printk-message
patches.drivers/ACPI-bus-Do-not-call-_STA-on-battery-devices-with-un
@@ -19530,6 +19532,22 @@
patches.suse/sched-numa-remove-unused-code-from-update_numa_stats.patch
patches.suse/sched-numa-remove-unused-nr_running-field.patch
patches.arch/x86-corruption-check-fix-panic-in-memory_corruption_check-when-boot-option-without-value-is-provided
+ patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
+ patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
+ patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
+ patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
+ patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
+ patches.arch/x86-alternative-init-ideal_nops-for-hygon-dhyana.patch
+ patches.arch/x86-amd_nb-check-vendor-in-amd-only-functions.patch
+ patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
+ patches.arch/x86-apic-add-hygon-dhyana-support.patch
+ patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
+ patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
+ patches.arch/x86-kvm-add-hygon-dhyana-support-to-kvm.patch
+ patches.arch/x86-xen-add-hygon-dhyana-support-to-xen.patch
+ patches.arch/acpi-add-hygon-dhyana-support.patch
+ patches.arch/cpufreq-add-hygon-dhyana-support.patch
+ patches.arch/tools-cpupower-add-hygon-dhyana-support.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch
@@ -19670,6 +19688,7 @@
patches.fixes/libnvdimm-label-fix-sparse-warning.patch
patches.drivers/acpi-nfit-fix-address-range-scrub-completion-tracking.patch
patches.drivers/edac-raise-the-maximum-number-of-memory-controllers.patch
+ patches.arch/edac-amd64-add-hygon-dhyana-support.patch
patches.drivers/edac-i7core-sb-skx-edac-fix-uncorrected-error-counting.patch
patches.drivers/edac-skx_edac-fix-logical-channel-intermediate-decoding.patch
patches.drivers/edac-thunderx-fix-memory-leak-in-thunderx_l2c_threaded_isr.patch
@@ -20617,6 +20636,7 @@
patches.drivers/efi-Permit-multiple-entries-in-persistent-memreserve.patch
patches.drivers/efi-Reduce-the-amount-of-memblock-reservations-for-p.patch
patches.fixes/tools-lib-lockdep-Rename-trywlock-into-trywrlock.patch
+ patches.arch/perf-tools-add-hygon-dhyana-support.patch
patches.arch/x86-vdso-remove-obsolete-fake-section-table-reservation.patch
patches.arch/x86-mm-drop-usage-of-_flush_tlb_all-in-kernel_physical_mapping_init.patch
patches.arch/powerpc-xmon-Fix-invocation-inside-lock-region.patch
@@ -22449,9 +22469,6 @@
patches.suse/0005-MODSIGN-Allow-the-db-UEFI-variable-to-be-suppressed.patch
patches.suse/0006-modsign-Use-secondary-trust-keyring-for-module-signi.patch
- # git://git.infradead.org/nvme.git nvme-5.2
- patches.fixes/nvme-multipath-avoid-crash-on-invalid-subsystem-cntl.patch
-
# out-of-tree patches
patches.suse/nvme-multipath-round-robin-I-O-policy.patch
patches.suse/cifs-fix-set-info.patch
@@ -22472,6 +22489,9 @@
# end of sorted patches
########################################################
+ # git://git.infradead.org/nvme.git nvme-5.2
+ patches.fixes/nvme-multipath-avoid-crash-on-invalid-subsystem-cntl.patch
+
########################################################
#
# packaging-specific patches (tweaks for autobuild,