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authorBorislav Petkov <bp@suse.de>2019-06-15 17:30:21 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 17:30:21 +0200
commita764bc79f8c81051c95ab48399ee0b7a5204b066 (patch)
tree1ddc198aec9d6e6b07f04132b8afac4de4f4cf64
parent85f4332322f386ddfea1b511b34eb1fa4794e220 (diff)
EDAC, amd64: Add Hygon Dhyana support (fate#327735).
-rw-r--r--patches.arch/edac-amd64-add-hygon-dhyana-support.patch92
-rw-r--r--series.conf1
2 files changed, 93 insertions, 0 deletions
diff --git a/patches.arch/edac-amd64-add-hygon-dhyana-support.patch b/patches.arch/edac-amd64-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..71a84f2531
--- /dev/null
+++ b/patches.arch/edac-amd64-add-hygon-dhyana-support.patch
@@ -0,0 +1,92 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Thu, 27 Sep 2018 16:31:28 +0200
+Subject: EDAC, amd64: Add Hygon Dhyana support
+Git-commit: c4a3e94641449362ee970f521a2cdb0e8cd08690
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+Add support for Hygon Dhyana CPU to EDAC.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: mchehab@kernel.org
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: thomas.lendacky@amd.com
+Cc: linux-edac@vger.kernel.org
+Link: https://lkml.kernel.org/r/9d71061301177822bc55b3bfd44f91057458d886.1537533369.git.puwen@hygon.cn
+---
+ drivers/edac/amd64_edac.c | 10 +++++++++-
+ drivers/edac/mce_amd.c | 4 +++-
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/edac/amd64_edac.c
++++ b/drivers/edac/amd64_edac.c
+@@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64
+
+ scrubval = scrubrates[i].scrubval;
+
+- if (pvt->fam == 0x17) {
++ if (pvt->fam == 0x17 || pvt->fam == 0x18) {
+ __f17h_set_scrubval(pvt, scrubval);
+ } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
+ f15h_select_dct(pvt, 0);
+@@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl
+ break;
+
+ case 0x17:
++ case 0x18:
+ amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
+ if (scrubval & BIT(0)) {
+ amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
+@@ -1044,6 +1045,7 @@ static void determine_memory_type(struct
+ goto ddr3;
+
+ case 0x17:
++ case 0x18:
+ if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
+ pvt->dram_type = MEM_LRDDR4;
+ else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
+@@ -3189,8 +3191,13 @@ static struct amd64_family_type *per_fam
+ break;
+
+ case 0x17:
++ /* fall through */
++ case 0x18:
+ fam_type = &family_types[F17_CPUS];
+ pvt->ops = &family_types[F17_CPUS].ops;
++
++ if (pvt->fam == 0x18)
++ family_types[F17_CPUS].ctl_name = "F18h";
+ break;
+
+ default:
+@@ -3429,6 +3436,7 @@ static const struct x86_cpu_id amd64_cpu
+ { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
++ { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
+ { }
+ };
+ MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
+--- a/drivers/edac/mce_amd.c
++++ b/drivers/edac/mce_amd.c
+@@ -1063,7 +1063,8 @@ static int __init mce_amd_init(void)
+ {
+ struct cpuinfo_x86 *c = &boot_cpu_data;
+
+- if (c->x86_vendor != X86_VENDOR_AMD)
++ if (c->x86_vendor != X86_VENDOR_AMD &&
++ c->x86_vendor != X86_VENDOR_HYGON)
+ return -ENODEV;
+
+ fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
+@@ -1117,6 +1118,7 @@ static int __init mce_amd_init(void)
+ break;
+
+ case 0x17:
++ case 0x18:
+ xec_mask = 0x3f;
+ if (!boot_cpu_has(X86_FEATURE_SMCA)) {
+ printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
diff --git a/series.conf b/series.conf
index 464263a96c..3fc970f854 100644
--- a/series.conf
+++ b/series.conf
@@ -19687,6 +19687,7 @@
patches.fixes/libnvdimm-label-fix-sparse-warning.patch
patches.drivers/acpi-nfit-fix-address-range-scrub-completion-tracking.patch
patches.drivers/edac-raise-the-maximum-number-of-memory-controllers.patch
+ patches.arch/edac-amd64-add-hygon-dhyana-support.patch
patches.drivers/edac-i7core-sb-skx-edac-fix-uncorrected-error-counting.patch
patches.drivers/edac-skx_edac-fix-logical-channel-intermediate-decoding.patch
patches.drivers/edac-thunderx-fix-memory-leak-in-thunderx_l2c_threaded_isr.patch