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authorBorislav Petkov <bp@suse.de>2019-06-14 22:36:52 +0200
committerBorislav Petkov <bp@suse.de>2019-06-14 22:36:52 +0200
commitd0d2f7168d4ea2ca279f37b6ff59758847c4152d (patch)
treee4d940bf680e76b933b01501baa2d48a11272485
parent5cfd89f93fef9a5a618ee2b5f05219876efa1807 (diff)
x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
-rw-r--r--patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch131
-rw-r--r--series.conf1
2 files changed, 132 insertions, 0 deletions
diff --git a/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch b/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
new file mode 100644
index 0000000000..eb60e4264f
--- /dev/null
+++ b/patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
@@ -0,0 +1,131 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:33:44 +0800
+Subject: x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
+Git-commit: d4f7423efdd1419b17524d090ff9ff4024bcf09b
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The Hygon Dhyana CPU has a topology extensions bit in CPUID. With
+this bit, the kernel can get the cache information. So add support in
+cpuid4_cache_lookup_regs() to get the correct cache size.
+
+The Hygon Dhyana CPU also discovers num_cache_leaves via CPUID leaf
+0x8000001d, so add support to it in find_num_cache_leaves().
+
+Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
+functions to initialize Dhyana cache info. Setup cache cpumap in the
+same way as AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: bp@alien8.de
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/2a686b2ac0e2f5a1f2f5f101124d9dd44f949731.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/kernel/cpu/cpu.h | 2 ++
+ arch/x86/kernel/cpu/hygon.c | 3 +++
+ arch/x86/kernel/cpu/intel_cacheinfo.c | 31 +++++++++++++++++++++++++++++--
+ 3 files changed, 34 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/cpu.h
++++ b/arch/x86/kernel/cpu/cpu.h
+@@ -50,5 +50,7 @@ extern void x86_spec_ctrl_setup_ap(void)
+ extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
+ extern int detect_extended_topology(struct cpuinfo_x86 *c);
+ extern int detect_ht_early(struct cpuinfo_x86 *c);
++extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
++void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
+
+ #endif /* ARCH_X86_CPU_H */
+--- a/arch/x86/kernel/cpu/hygon.c
++++ b/arch/x86/kernel/cpu/hygon.c
+@@ -86,6 +86,7 @@ static void hygon_get_topology(struct cp
+ if (!err)
+ c->x86_coreid_bits = get_count_order(c->x86_max_cores);
+
++ cacheinfo_hygon_init_llc_id(c, cpu, node_id);
+ } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
+ u64 value;
+
+@@ -320,6 +321,8 @@ static void init_hygon(struct cpuinfo_x8
+ hygon_get_topology(c);
+ srat_detect_node(c);
+
++ init_hygon_cacheinfo(c);
++
+ if (cpu_has(c, X86_FEATURE_XMM2)) {
+ unsigned long long val;
+ int ret;
+--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
++++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
+@@ -395,6 +395,22 @@ static void amd_l3_disable_index(struct
+ }
+ }
+
++void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
++{
++ /*
++ * We may have multiple LLCs if L3 caches exist, so check if we
++ * have an L3 cache by looking at the L3 cache CPUID leaf.
++ */
++ if (!cpuid_edx(0x80000006))
++ return;
++
++ /*
++ * LLC is at the core complex level.
++ * Core complex ID is ApicId[3] for these processors.
++ */
++ per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
++}
++
+ /*
+ * disable a L3 cache index by using a disable-slot
+ *
+@@ -599,6 +615,10 @@ cpuid4_cache_lookup_regs(int index, stru
+ else
+ amd_cpuid4(index, &eax, &ebx, &ecx);
+ amd_init_l3_cache(this_leaf, index);
++ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
++ cpuid_count(0x8000001d, index, &eax.full,
++ &ebx.full, &ecx.full, &edx);
++ amd_init_l3_cache(this_leaf, index);
+ } else {
+ cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
+ }
+@@ -622,7 +642,8 @@ static int find_num_cache_leaves(struct
+ union _cpuid4_leaf_eax cache_eax;
+ int i = -1;
+
+- if (c->x86_vendor == X86_VENDOR_AMD)
++ if (c->x86_vendor == X86_VENDOR_AMD ||
++ c->x86_vendor == X86_VENDOR_HYGON)
+ op = 0x8000001d;
+ else
+ op = 4;
+@@ -649,6 +670,11 @@ void init_amd_cacheinfo(struct cpuinfo_x
+ }
+ }
+
++void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
++{
++ num_cache_leaves = find_num_cache_leaves(c);
++}
++
+ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
+ {
+ /* Cache sizes */
+@@ -871,7 +897,8 @@ static void __cache_cpumap_setup(unsigne
+ int index_msb, i;
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+
+- if (c->x86_vendor == X86_VENDOR_AMD) {
++ if (c->x86_vendor == X86_VENDOR_AMD ||
++ c->x86_vendor == X86_VENDOR_HYGON) {
+ if (__cache_amd_cpumap_setup(cpu, index, base))
+ return;
+ }
diff --git a/series.conf b/series.conf
index 140d96d2e2..ab3652285c 100644
--- a/series.conf
+++ b/series.conf
@@ -19531,6 +19531,7 @@
patches.suse/sched-numa-remove-unused-nr_running-field.patch
patches.arch/x86-corruption-check-fix-panic-in-memory_corruption_check-when-boot-option-without-value-is-provided
patches.arch/x86-cpu-create-hygon-dhyana-architecture-support-file.patch
+ patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch