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authorBorislav Petkov <bp@suse.de>2019-06-15 09:42:57 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 09:42:57 +0200
commite0edbf292f64e0fb14411ca257d897f0fc7d6bfa (patch)
treecab812c8f947e1e5e7ee32c127780cab8329f044
parent0a372f48fe0adc0458f70f3b59fd4b69c5d0bb6b (diff)
x86/events: Add Hygon Dhyana support to PMU infrastructure
-rw-r--r--patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch133
-rw-r--r--series.conf1
2 files changed, 134 insertions, 0 deletions
diff --git a/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch b/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
new file mode 100644
index 0000000000..3015ea2ff2
--- /dev/null
+++ b/patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
@@ -0,0 +1,133 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:34:47 +0800
+Subject: x86/events: Add Hygon Dhyana support to PMU infrastructure
+Git-commit: 6d0ef316b9f8ea03fa867debda70b2f11a0b9736
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
+Family 17h one. To support it, call amd_pmu_init() to share the AMD PMU
+initialization flow, and change the PMU name to "HYGON".
+
+The Hygon Dhyana CPU supports both legacy and extension PMC MSRs (perf
+counter registers and event selection registers), so add Hygon Dhyana
+support in the similar way as AMD does.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: x86@kernel.org
+Cc: thomas.lendacky@amd.com
+Link: https://lkml.kernel.org/r/9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/events/amd/core.c | 4 ++++
+ arch/x86/events/amd/uncore.c | 20 +++++++++++++-------
+ arch/x86/events/core.c | 4 ++++
+ arch/x86/kernel/cpu/perfctr-watchdog.c | 2 ++
+ 4 files changed, 23 insertions(+), 7 deletions(-)
+
+diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
+index c84584bb9402..7d2d7c801dba 100644
+--- a/arch/x86/events/amd/core.c
++++ b/arch/x86/events/amd/core.c
+@@ -669,6 +669,10 @@ static int __init amd_core_pmu_init(void)
+ * We fallback to using default amd_get_event_constraints.
+ */
+ break;
++ case 0x18:
++ pr_cont("Fam18h ");
++ /* Using default amd_get_event_constraints. */
++ break;
+ default:
+ pr_err("core perfctr but no constraints; unknown hardware!\n");
+ return -ENODEV;
+diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
+index 981ba5e8241b..c7d745bc4136 100644
+--- a/arch/x86/events/amd/uncore.c
++++ b/arch/x86/events/amd/uncore.c
+@@ -507,17 +507,19 @@ static int __init amd_uncore_init(void)
+ {
+ int ret = -ENODEV;
+
+- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
++ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return -ENODEV;
+
+ if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
+ return -ENODEV;
+
+- if (boot_cpu_data.x86 == 0x17) {
++ if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+ /*
+- * For F17h, the Northbridge counters are repurposed as Data
+- * Fabric counters. Also, L3 counters are supported too. The PMUs
+- * are exported based on family as either L2 or L3 and NB or DF.
++ * For F17h or F18h, the Northbridge counters are
++ * repurposed as Data Fabric counters. Also, L3
++ * counters are supported too. The PMUs are exported
++ * based on family as either L2 or L3 and NB or DF.
+ */
+ num_counters_nb = NUM_COUNTERS_NB;
+ num_counters_llc = NUM_COUNTERS_L3;
+@@ -547,7 +549,9 @@ static int __init amd_uncore_init(void)
+ if (ret)
+ goto fail_nb;
+
+- pr_info("AMD NB counters detected\n");
++ pr_info("%s NB counters detected\n",
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
++ "HYGON" : "AMD");
+ ret = 0;
+ }
+
+@@ -561,7 +565,9 @@ static int __init amd_uncore_init(void)
+ if (ret)
+ goto fail_llc;
+
+- pr_info("AMD LLC counters detected\n");
++ pr_info("%s LLC counters detected\n",
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
++ "HYGON" : "AMD");
+ ret = 0;
+ }
+
+diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
+index dfb2f7c0d019..9c562f5fbde0 100644
+--- a/arch/x86/events/core.c
++++ b/arch/x86/events/core.c
+@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void)
+ case X86_VENDOR_AMD:
+ err = amd_pmu_init();
+ break;
++ case X86_VENDOR_HYGON:
++ err = amd_pmu_init();
++ x86_pmu.name = "HYGON";
++ break;
+ default:
+ err = -ENOTSUPP;
+ }
+diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
+index d389083330c5..9556930cd8c1 100644
+--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
++++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
+@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
+ {
+ /* returns the bit offset of the performance counter register */
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ if (msr >= MSR_F15H_PERF_CTR)
+ return (msr - MSR_F15H_PERF_CTR) >> 1;
+@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
+ {
+ /* returns the bit offset of the event selection register */
+ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_HYGON:
+ case X86_VENDOR_AMD:
+ if (msr >= MSR_F15H_PERF_CTL)
+ return (msr - MSR_F15H_PERF_CTL) >> 1;
+
diff --git a/series.conf b/series.conf
index 50673d79d7..6ca0d478aa 100644
--- a/series.conf
+++ b/series.conf
@@ -19534,6 +19534,7 @@
patches.arch/x86-cpu-get-cache-info-and-setup-cache-cpumap-for-hygon-dhyana.patch
patches.arch/x86-cpu-mtrr-support-top_mem2-and-get-mtrr-number.patch
patches.arch/x86-smpboot-do-not-use-bsp-init-delay-and-mwait-to-idle-on-dhyana.patch
+ patches.arch/x86-events-add-hygon-dhyana-support-to-pmu-infrastructure.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch