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authorBorislav Petkov <bp@suse.de>2019-06-15 13:05:52 +0200
committerBorislav Petkov <bp@suse.de>2019-06-15 13:05:52 +0200
commite8b6320d5533d21d312c4adc2dddaf1feb016f86 (patch)
tree9794fd84629d6f0d25086e7e9800141acd08a8e8
parent956d7756eb4dcf362585df20f40be8ca30c3277e (diff)
x86/mce: Add Hygon Dhyana support to the MCA infrastructure
-rw-r--r--patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch111
-rw-r--r--series.conf1
2 files changed, 112 insertions, 0 deletions
diff --git a/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch b/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
new file mode 100644
index 0000000000..479ebdd24c
--- /dev/null
+++ b/patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
@@ -0,0 +1,111 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sun, 23 Sep 2018 17:36:04 +0800
+Subject: x86/mce: Add Hygon Dhyana support to the MCA infrastructure
+Git-commit: ac78bd72355d0da64c073c12927264d4ff19b886
+Patch-mainline: v4.20-rc1
+References: fate#327735
+
+The machine check architecture for Hygon Dhyana CPU is similar to the
+AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
+code path of AMD family 17h.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Cc: tglx@linutronix.de
+Cc: mingo@redhat.com
+Cc: hpa@zytor.com
+Cc: tony.luck@intel.com
+Cc: thomas.lendacky@amd.com
+Cc: linux-edac@vger.kernel.org
+Link: https://lkml.kernel.org/r/87d8a4f16bdea0bfe0c0cf2e4a8d2c2a99b1055c.1537533369.git.puwen@hygon.cn
+---
+ arch/x86/include/asm/mce.h | 2 ++
+ arch/x86/kernel/cpu/mcheck/mce-severity.c | 3 ++-
+ arch/x86/kernel/cpu/mcheck/mce.c | 18 ++++++++++++++----
+ 3 files changed, 18 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/include/asm/mce.h
++++ b/arch/x86/include/asm/mce.h
+@@ -269,6 +269,8 @@ static inline void mce_amd_feature_init(
+ static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
+ #endif
+
++static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
++
+ int mce_available(struct cpuinfo_x86 *c);
+ bool mce_is_memory_error(struct mce *m);
+
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -507,9 +507,9 @@ static int mce_usable_address(struct mce
+
+ bool mce_is_memory_error(struct mce *m)
+ {
+- if (m->cpuvendor == X86_VENDOR_AMD) {
++ if (m->cpuvendor == X86_VENDOR_AMD ||
++ m->cpuvendor == X86_VENDOR_HYGON) {
+ return amd_mce_is_memory_error(m);
+-
+ } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+ /*
+ * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
+@@ -538,6 +538,9 @@ static bool mce_is_correctable(struct mc
+ if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
+ return false;
+
++ if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
++ return false;
++
+ if (m->status & MCI_STATUS_UC)
+ return false;
+
+@@ -1698,7 +1701,7 @@ static int __mcheck_cpu_ancient_init(str
+ */
+ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
+ {
+- if (c->x86_vendor == X86_VENDOR_AMD) {
++ if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
+ mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
+ mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
+ mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
+@@ -1725,6 +1728,11 @@ static void __mcheck_cpu_init_vendor(str
+ break;
+ }
+
++ case X86_VENDOR_HYGON:
++ mce_hygon_feature_init(c);
++ break;
++
++
+ default:
+ break;
+ }
+@@ -1947,12 +1955,14 @@ static void mce_disable_error_reporting(
+ static void vendor_disable_error_reporting(void)
+ {
+ /*
+- * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
++ * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
++ * are socket-wide.
+ * Disabling them for just a single offlined CPU is bad, since it will
+ * inhibit reporting for all shared resources on the socket like the
+ * last level cache (LLC), the integrated memory controller (iMC), etc.
+ */
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ return;
+
+--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
++++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
+@@ -328,7 +328,8 @@ int (*mce_severity)(struct mce *m, int t
+
+ void __init mcheck_vendor_init_severity(void)
+ {
+- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
++ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
++ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+ mce_severity = mce_severity_amd;
+ }
+
diff --git a/series.conf b/series.conf
index 2417437096..8b69bd7d31 100644
--- a/series.conf
+++ b/series.conf
@@ -19541,6 +19541,7 @@
patches.arch/x86-pci-x86-amd_nb-add-hygon-dhyana-support-to-pci-and-northbridge.patch
patches.arch/x86-apic-add-hygon-dhyana-support.patch
patches.arch/x86-bugs-add-hygon-dhyana-to-the-respective-mitigation-machinery.patch
+ patches.arch/x86-mce-add-hygon-dhyana-support-to-the-mca-infrastructure.patch
patches.fixes/0001-x86-xen-Fix-boot-loader-version-reported-for-PVH-gue.patch
patches.arch/x86-kexec-correct-kexec_backup_src_end-off-by-one-error.patch
patches.fixes/resource-include-resource-end-in-walk_-interfaces.patch