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authorThomas Zimmermann <tzimmermann@suse.de>2019-01-18 12:52:13 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-01-18 17:08:04 +0100
commit1b233d0e54cbf3ac7d45b4175933a1c4010702f3 (patch)
treecb119466b32ce67ce600e08b70d1951cbf204f60
parent0570bd2d15b48c3dd6e42839ab7825a363f6a10a (diff)
drm/i915/icl: Fix DDI/TC port clk_off bits (bsc#1113956)
-rw-r--r--patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch89
-rw-r--r--series.conf1
2 files changed, 90 insertions, 0 deletions
diff --git a/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch b/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
new file mode 100644
index 0000000000..fab0813271
--- /dev/null
+++ b/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
@@ -0,0 +1,89 @@
+From bb1c7edc6d4d5cc6917814d858d47b22d2e93cde Mon Sep 17 00:00:00 2001
+From: Mahesh Kumar <mahesh1.kumar@intel.com>
+Date: Mon, 15 Oct 2018 19:37:52 -0700
+Subject: drm/i915/icl: Fix DDI/TC port clk_off bits
+Git-commit: bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
+from offset 12 & TC4 is at offset 21.
+Create a function to choose correct clk-off bit.
+
+v2: Add fixes tag (Lucas)
+
+Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
+Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
+Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181016023752.9285-1-lucas.demarchi@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_reg.h | 3 +++
+ drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
+ 2 files changed, 21 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -9313,6 +9313,9 @@ enum skl_power_gate {
+ #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
+ #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
+ (port) + 10))
++#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
++#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
++ 21 : (tc_port) + 12))
+ #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port) * 2)
+ #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -2535,6 +2535,21 @@ uint32_t ddi_signal_levels(struct intel_
+ return DDI_BUF_TRANS_SELECT(level);
+ }
+
++static inline
++uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
++ enum port port)
++{
++ if (intel_port_is_combophy(dev_priv, port)) {
++ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
++ } else if (intel_port_is_tc(dev_priv, port)) {
++ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
++
++ return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
++ }
++
++ return 0;
++}
++
+ void icl_map_plls_to_ports(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct drm_atomic_state *old_state)
+@@ -2558,7 +2573,7 @@ void icl_map_plls_to_ports(struct drm_cr
+ mutex_lock(&dev_priv->dpll_lock);
+
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+- WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
++ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+
+ if (intel_port_is_combophy(dev_priv, port)) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+@@ -2567,7 +2582,7 @@ void icl_map_plls_to_ports(struct drm_cr
+ POSTING_READ(DPCLKA_CFGCR0_ICL);
+ }
+
+- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
++ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ mutex_unlock(&dev_priv->dpll_lock);
+@@ -2595,7 +2610,7 @@ void icl_unmap_plls_to_ports(struct drm_
+ mutex_lock(&dev_priv->dpll_lock);
+ I915_WRITE(DPCLKA_CFGCR0_ICL,
+ I915_READ(DPCLKA_CFGCR0_ICL) |
+- DPCLKA_CFGCR0_DDI_CLK_OFF(port));
++ icl_dpclka_cfgcr0_clk_off(dev_priv, port));
+ mutex_unlock(&dev_priv->dpll_lock);
+ }
+ }
diff --git a/series.conf b/series.conf
index b7c31fb625..04b1eff39d 100644
--- a/series.conf
+++ b/series.conf
@@ -42095,6 +42095,7 @@
patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch
patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch
patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch
+ patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch
patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch
patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch