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authorPetr Tesarik <ptesarik@suse.cz>2019-01-17 16:50:12 +0100
committerPetr Tesarik <ptesarik@suse.cz>2019-01-17 16:50:12 +0100
commit71f53af014151674fce09ea55d7093edcb88dacc (patch)
tree63caf9a1b9ab11cf0199777cdff1f8a46e122b70
parentb28185031310f96e96453e51348e9ecd03684e27 (diff)
parent40c6068cc2808fd1d5a3820aac4ad08c77d6cced (diff)
Merge branch 'users/tzimmermann/SLE15-SP1/for-next' into SLE15-SP1
Pull DRM fixes from Thomas Zimmermann
-rw-r--r--blacklist.conf74
-rw-r--r--patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch151
-rw-r--r--patches.drm/0003-drm-i915-Record-GT-workarounds-in-a-list.patch793
-rw-r--r--patches.drm/0004-drm-i915-Introduce-per-engine-workarounds.patch474
-rw-r--r--patches.drm/0005-drm-nouveau-kms-nv50-also-flush-fb-writes-when-rewin.patch77
-rw-r--r--patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch67
-rw-r--r--patches.drm/0044-drm-msm-disp-dpu-Use-proper-define-for-drm_encoder_i.patch111
-rw-r--r--patches.drm/0045-drm-msm-gpu-fix-parameters-in-function-msm_gpu_crash.patch55
-rw-r--r--patches.drm/0046-drm-msm-fix-unsigned-comparison-with-less-than-zero.patch40
-rw-r--r--patches.drm/0047-drm-nouveau-secboot-acr-fix-memory-leak.patch37
-rw-r--r--patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch50
-rw-r--r--patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch75
-rw-r--r--patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch45
-rw-r--r--patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch42
-rw-r--r--patches.drm/0056-amd-gpu-Don-t-undefine-READ-and-WRITE.patch37
-rw-r--r--patches.drm/0057-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_.patch68
-rw-r--r--patches.drm/0058-drm-i915-dp-Restrict-link-retrain-workaround-to-exte.patch63
-rw-r--r--patches.drm/0059-drm-sun4i-hdmi-Fix-double-flag-assignation.patch41
-rw-r--r--patches.drm/0060-drm-panel-simple-Innolux-TV123WAM-is-actually-P120ZD.patch92
-rw-r--r--patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch50
-rw-r--r--patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch42
-rw-r--r--patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch49
-rw-r--r--patches.drm/0064-drm-etnaviv-fix-bogus-fence-complete-check-in-timeou.patch36
-rw-r--r--patches.drm/0065-uapi-fix-linux-kfd_ioctl.h-userspace-compilation-err.patch52
-rw-r--r--patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch141
-rw-r--r--patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch37
-rw-r--r--patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch48
-rw-r--r--patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch47
-rw-r--r--patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch40
-rw-r--r--patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch53
-rw-r--r--patches.drm/0085-drm-msm-gpu-Fix-a-couple-memory-leaks-in-debugfs.patch60
-rw-r--r--patches.drm/0086-drm-msm-fix-handling-of-cmdstream-offset.patch52
-rw-r--r--patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch39
-rw-r--r--series.conf32
34 files changed, 3123 insertions, 47 deletions
diff --git a/blacklist.conf b/blacklist.conf
index 4c710672e7..07f3793d6b 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -876,59 +876,39 @@ b1f1c2c11fc6c6cd3e361061e30f9b2839897b28 # Duplicate of 5b2695fd4b20f9b8320e9ecb
5df52391ddbed869c7d67b00fbb013bd64334115 # Duplicate of 4fe967912ee83048beb45a6b4f0f6774fddcfa0a
3b5cf4ef541f1b2facaca58cae5e8e0b5f19ad4c # Duplicate of 2b82435cb90bed2c5f8398730d964dd11602217c
7a90938332d80faf973fbcffdf6e674e7b8f0914 # Duplicate of 4ca8ca9fe7dc792000c3762de5081a4d6dc33667
+e3118a038dfd1d6d902ea966e0ce3ce4e91e503b # Duplicate of 0b4bf7ca9be824dde6ff63dd2ceba2d1367f8a58
+83db37385306072eca403ed80c0a8cf7b0d39e05 # Duplicate of bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+b4ec5f39e4a0bc9844634faa88dd08ca94dca39d # Duplicate of 61cdfb9e194d2a327eef301e8fc80b63e3e1dc7a
+9349e23907be1954ccdf6d771d640e2788da1643 # Duplicate of aba118389a6fb2ad7958de0f37b5869852bd38cf
+76271ef2638ca8e4bf2884cad664a34be0d5a42b # Duplicate of bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+f42f343887016330b321dd40eebc68c7292e4f1b # Duplicate of 3b90946fcb6f13b65888c380461793a9dea9d1f4
+e528c2affcf216b3d02b22004895cb678769629b # Duplicate of b4335ec0a3ee6229a570755f8fb95dc8a7c694f2
+c4f224076d00ccf30c7bd3561cceaed82628c8ce # Duplicate of a33e1ece777996ddddb1f23a30f8c66422ed0b68
+44a7276b30c3c15f2b7790a5729640597fb6a1df # Duplicate of 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
+6a67a20366f894c172734f28c5646bdbe48a46e3 # Duplicate of 63ac3328f0d1d37f286e397b14d9596ed09d7ca5
+a22612301ae61d78a7c0c82dc556931a35db0e91 # Duplicate of 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
+6e8adf6f4a4fa57dd3bef6b70de96e2b7b311204 # Duplicate of e7a278a329dd8aa2c70c564849f164cb5673689c
+cedde71cc61bdf5e2f386f06bada29fe9fe11b78 # Duplicate of 07e3a1cfb0568b6d8d7862077029af96af6690ea
+e3118a038dfd1d6d902ea966e0ce3ce4e91e503b # Duplicate of 0b4bf7ca9be824dde6ff63dd2ceba2d1367f8a58
+83db37385306072eca403ed80c0a8cf7b0d39e05 # Duplicate of bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+b4ec5f39e4a0bc9844634faa88dd08ca94dca39d # Duplicate of 61cdfb9e194d2a327eef301e8fc80b63e3e1dc7a
+9349e23907be1954ccdf6d771d640e2788da1643 # Duplicate of aba118389a6fb2ad7958de0f37b5869852bd38cf
+76271ef2638ca8e4bf2884cad664a34be0d5a42b # Duplicate of bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+f42f343887016330b321dd40eebc68c7292e4f1b # Duplicate of 3b90946fcb6f13b65888c380461793a9dea9d1f4
+e528c2affcf216b3d02b22004895cb678769629b # Duplicate of b4335ec0a3ee6229a570755f8fb95dc8a7c694f2
+c4f224076d00ccf30c7bd3561cceaed82628c8ce # Duplicate of a33e1ece777996ddddb1f23a30f8c66422ed0b68
+44a7276b30c3c15f2b7790a5729640597fb6a1df # Duplicate of 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
+6a67a20366f894c172734f28c5646bdbe48a46e3 # Duplicate of 63ac3328f0d1d37f286e397b14d9596ed09d7ca5
+a22612301ae61d78a7c0c82dc556931a35db0e91 # Duplicate of 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
+6e8adf6f4a4fa57dd3bef6b70de96e2b7b311204 # Duplicate of e7a278a329dd8aa2c70c564849f164cb5673689c
+cedde71cc61bdf5e2f386f06bada29fe9fe11b78 # Duplicate of 07e3a1cfb0568b6d8d7862077029af96af6690ea
+4a15c75c42460252a63d30f03b4766a52945fb47 # Duplicate of 90098efacc4c3e2e4f6262a657d6b520ecfb2555
# temporarily blacklisted for the DRM backport
-47658556da857c66c5865f192408639f524cca40
-2c043eeffea4813b8f569e84b46035a08de5eb47
-6969019f65b43afb6da6a26f1d9e55bbdfeebcd5
-dfdb3be43ef1195c491e6c3760b922acb52e3575
-74a07c0a59fa372b069d879971ba4d9e341979cf
-0b4bf7ca9be824dde6ff63dd2ceba2d1367f8a58
-34c2c4f632f232ed2fdb66d4e42cc72d322273fe
-2f20fa8d12e859a03f68bdd81d75830141bc9ac9
bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
-61cdfb9e194d2a327eef301e8fc80b63e3e1dc7a
-e3118a038dfd1d6d902ea966e0ce3ce4e91e503b
-83db37385306072eca403ed80c0a8cf7b0d39e05
-b4ec5f39e4a0bc9844634faa88dd08ca94dca39d
-1fcb748d187d0c7732a75a509e924ead6d070e04
-49af5d95b9b3c21a84ad115a9db9acbc036d849a
-f9776280c29e77a18cbc7ebb6d48f7885e494990
-1e0ff648940e603cab6c52cf3723017d30d78f30
-8f054b6f53ff34fb787bde4c5940f86a9c175177
-09209662618f9fdc38b8d4da39040c8829fd2d57
-3b90946fcb6f13b65888c380461793a9dea9d1f4
-b4335ec0a3ee6229a570755f8fb95dc8a7c694f2
-6fce3a406108ee6c8a61e2a33e52e9198a626ea0
-aba118389a6fb2ad7958de0f37b5869852bd38cf
-9349e23907be1954ccdf6d771d640e2788da1643
-76271ef2638ca8e4bf2884cad664a34be0d5a42b
-f42f343887016330b321dd40eebc68c7292e4f1b
-e528c2affcf216b3d02b22004895cb678769629b
a33e1ece777996ddddb1f23a30f8c66422ed0b68
-5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
-c4f224076d00ccf30c7bd3561cceaed82628c8ce
-44a7276b30c3c15f2b7790a5729640597fb6a1df
-63ac3328f0d1d37f286e397b14d9596ed09d7ca5
-e7a278a329dd8aa2c70c564849f164cb5673689c
-8577c319b6511fbc391f3775225fecd8b979bc26
-6a67a20366f894c172734f28c5646bdbe48a46e3
-a22612301ae61d78a7c0c82dc556931a35db0e91
-6e8adf6f4a4fa57dd3bef6b70de96e2b7b311204
-fcc86cb45d38ca2f24bcea9c29c7f4742041caed
07e3a1cfb0568b6d8d7862077029af96af6690ea
-cedde71cc61bdf5e2f386f06bada29fe9fe11b78
-8d4d7c58994759bbd9f4fec32d88bf0e0b89302e
-8fd3b90300bec541806dac271de2fd44e2e4e2d2
-51270de91412b819f654b849db3bf92dac0a0855
-47e7f506ee6590ceb2efa1f08aca7f9f2ee5c1d3
-62d1a752874962f072de8a779e960fcd2ab4847b
f1f90e254e46e0a14220e4090041f68256fbe297
-46592892e1a60f9e9de3287719143a148fce93cf
-4a15c75c42460252a63d30f03b4766a52945fb47
-009367791f31afa0842854e7ea0acc9edf70ccaf
-90098efacc4c3e2e4f6262a657d6b520ecfb2555
-970a5ee41c72df46e3b0f307528c7d8ef7734a2e
bb8c13d61a629276a162c1d2b1a20a815cbcfbb7 # deprecated late loading method
a5321aec6412b20b5ad15db2d6b916c05349dbff # ditto
diff --git a/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch b/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
new file mode 100644
index 0000000000..c505394948
--- /dev/null
+++ b/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
@@ -0,0 +1,151 @@
+From 46592892e1a60f9e9de3287719143a148fce93cf Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Fri, 30 Nov 2018 12:59:54 +0000
+Subject: drm/i915/vgpu: Disallow loading on old vGPU hosts
+Git-commit: 46592892e1a60f9e9de3287719143a148fce93cf
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
+actually broke the force-mmio mode for our execlists implementation. No
+one noticed, so ergo no one is actually using an old vGPU host (where we
+required the older method) and so can simply remove the broken support.
+
+v2: csb_read can go as well (Mika)
+
+Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181130125954.11924-1-chris@chris-wilson.co.uk
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++++
+ drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++------------------------
+ drivers/gpu/drm/i915/intel_ringbuffer.h | 16 ---------------
+ 3 files changed, 23 insertions(+), 41 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -1084,6 +1084,20 @@ static int i915_driver_init_hw(struct dr
+
+ intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
+
++ if (HAS_EXECLISTS(dev_priv)) {
++ /*
++ * Older GVT emulation depends upon intercepting CSB mmio,
++ * which we no longer use, preferring to use the HWSP cache
++ * instead.
++ */
++ if (intel_vgpu_active(dev_priv) &&
++ !intel_vgpu_has_hwsp_emulation(dev_priv)) {
++ i915_report_error(dev_priv,
++ "old vGPU host found, support for HWSP emulation required\n");
++ return -ENXIO;
++ }
++ }
++
+ intel_sanitize_options(dev_priv);
+
+ i915_perf_init(dev_priv);
+--- a/drivers/gpu/drm/i915/intel_lrc.c
++++ b/drivers/gpu/drm/i915/intel_lrc.c
+@@ -825,6 +825,8 @@ execlists_cancel_port_requests(struct in
+
+ static void reset_csb_pointers(struct intel_engine_execlists *execlists)
+ {
++ const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
++
+ /*
+ * After a reset, the HW starts writing into CSB entry [0]. We
+ * therefore have to set our HEAD pointer back one entry so that
+@@ -834,8 +836,8 @@ static void reset_csb_pointers(struct in
+ * inline comparison of our cached head position against the last HW
+ * write works even before the first interrupt.
+ */
+- execlists->csb_head = execlists->csb_write_reset;
+- WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
++ execlists->csb_head = reset_value;
++ WRITE_ONCE(*execlists->csb_write, reset_value);
+ }
+
+ static void nop_submission_tasklet(unsigned long data)
+@@ -2403,12 +2405,6 @@ logical_ring_setup(struct intel_engine_c
+ logical_ring_default_irqs(engine);
+ }
+
+-static bool csb_force_mmio(struct drm_i915_private *i915)
+-{
+- /* Older GVT emulation depends upon intercepting CSB mmio */
+- return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
+-}
+-
+ static int logical_ring_init(struct intel_engine_cs *engine)
+ {
+ struct drm_i915_private *i915 = engine->i915;
+@@ -2438,24 +2434,12 @@ static int logical_ring_init(struct inte
+ upper_32_bits(ce->lrc_desc);
+ }
+
+- execlists->csb_read =
+- i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
+- if (csb_force_mmio(i915)) {
+- execlists->csb_status = (u32 __force *)
+- (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+-
+- execlists->csb_write = (u32 __force *)execlists->csb_read;
+- execlists->csb_write_reset =
+- _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
+- GEN8_CSB_ENTRIES - 1);
+- } else {
+- execlists->csb_status =
+- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
++ execlists->csb_status =
++ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
++
++ execlists->csb_write =
++ &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
+
+- execlists->csb_write =
+- &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
+- execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
+- }
+ reset_csb_pointers(execlists);
+
+ intel_engine_init_workarounds(engine);
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
+@@ -300,13 +300,6 @@ struct intel_engine_execlists {
+ struct rb_root_cached queue;
+
+ /**
+- * @csb_read: control register for Context Switch buffer
+- *
+- * Note this register is always in mmio.
+- */
+- u32 __iomem *csb_read;
+-
+- /**
+ * @csb_write: control register for Context Switch buffer
+ *
+ * Note this register may be either mmio or HWSP shadow.
+@@ -326,15 +319,6 @@ struct intel_engine_execlists {
+ u32 preempt_complete_status;
+
+ /**
+- * @csb_write_reset: reset value for CSB write pointer
+- *
+- * As the CSB write pointer maybe either in HWSP or as a field
+- * inside an mmio register, we want to reprogram it slightly
+- * differently to avoid later confusion.
+- */
+- u32 csb_write_reset;
+-
+- /**
+ * @csb_head: context status buffer head
+ */
+ u8 csb_head;
diff --git a/patches.drm/0003-drm-i915-Record-GT-workarounds-in-a-list.patch b/patches.drm/0003-drm-i915-Record-GT-workarounds-in-a-list.patch
new file mode 100644
index 0000000000..7819deecbf
--- /dev/null
+++ b/patches.drm/0003-drm-i915-Record-GT-workarounds-in-a-list.patch
@@ -0,0 +1,793 @@
+From 009367791f31afa0842854e7ea0acc9edf70ccaf Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Wed, 5 Dec 2018 11:33:23 +0000
+Subject: drm/i915: Record GT workarounds in a list
+Git-commit: 009367791f31afa0842854e7ea0acc9edf70ccaf
+Patch-mainline: v4.20-rc7
+References: bsc#1113956
+
+To enable later verification of GT workaround state at various stages of
+driver lifetime, we record the list of applicable ones per platforms to a
+list, from which they are also applied.
+
+The added data structure is a simple array of register, mask and value
+items, which is allocated on demand as workarounds are added to the list.
+
+This is a temporary implementation which later in the series gets fused
+with the existing per context workaround list handling. It is separated at
+this stage since the following patch fixes a bug which needs to be as easy
+to backport as possible.
+
+Also, since in the following patch we will be adding a new class of
+workarounds (per engine) which can be applied from interrupt context, we
+straight away make the provision for safe read-modify-write cycle.
+
+v2:
+ * Change dev_priv to i915 along the init path. (Chris Wilson)
+ * API rename. (Chris Wilson)
+
+v3:
+ * Remove explicit list size tracking in favour of growing the allocation
+ in power of two chunks. (Chris Wilson)
+
+v4:
+ Chris Wilson:
+ * Change wa_list_finish to early return.
+ * Copy workarounds using the compiler for static checking.
+ * Do not bother zeroing unused entries.
+ * Re-order struct i915_wa_list.
+
+v5:
+ * kmalloc_array.
+ * Whitespace cleanup.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181203133319.10174-1-tvrtko.ursulin@linux.intel.com
+(cherry picked from commit 25d140faaa25f728159eb8c304eae53d88a7f14e)
+Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_drv.c | 1
+ drivers/gpu/drm/i915/i915_drv.h | 2
+ drivers/gpu/drm/i915/i915_gem.c | 4
+ drivers/gpu/drm/i915/intel_workarounds.c | 482 ++++++++++++++++++++-----------
+ drivers/gpu/drm/i915/intel_workarounds.h | 23 +
+ 5 files changed, 352 insertions(+), 160 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -1153,6 +1153,7 @@ static int i915_driver_init_hw(struct dr
+
+ intel_uncore_sanitize(dev_priv);
+
++ intel_gt_init_workarounds(dev_priv);
+ i915_gem_load_init_fences(dev_priv);
+
+ /* On the 945G/GM, the chipset reports the MSI capability on the
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -65,6 +65,7 @@
+ #include "intel_ringbuffer.h"
+ #include "intel_uncore.h"
+ #include "intel_wopcm.h"
++#include "intel_workarounds.h"
+ #include "intel_uc.h"
+
+ #include "i915_gem.h"
+@@ -1770,6 +1771,7 @@ struct drm_i915_private {
+ int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
+
+ struct i915_workarounds workarounds;
++ struct i915_wa_list gt_wa_list;
+
+ struct i915_frontbuffer_tracking fb_tracking;
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -5281,7 +5281,7 @@ int i915_gem_init_hw(struct drm_i915_pri
+ }
+ }
+
+- intel_gt_workarounds_apply(dev_priv);
++ intel_gt_apply_workarounds(dev_priv);
+
+ i915_gem_init_swizzling(dev_priv);
+
+@@ -5622,6 +5622,8 @@ void i915_gem_fini(struct drm_i915_priva
+ i915_gem_contexts_fini(dev_priv);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
++ intel_wa_list_free(&dev_priv->gt_wa_list);
++
+ intel_uc_fini_misc(dev_priv);
+ i915_gem_cleanup_userptr(dev_priv);
+
+--- a/drivers/gpu/drm/i915/intel_workarounds.c
++++ b/drivers/gpu/drm/i915/intel_workarounds.c
+@@ -48,6 +48,20 @@
+ * - Public functions to init or apply the given workaround type.
+ */
+
++static void wa_init_start(struct i915_wa_list *wal, const char *name)
++{
++ wal->name = name;
++}
++
++static void wa_init_finish(struct i915_wa_list *wal)
++{
++ if (!wal->count)
++ return;
++
++ DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
++ wal->count, wal->name);
++}
++
+ static void wa_add(struct drm_i915_private *i915,
+ i915_reg_t reg, const u32 mask, const u32 val)
+ {
+@@ -580,160 +594,239 @@ int intel_ctx_workarounds_emit(struct i9
+ return 0;
+ }
+
+-static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void
++wal_add(struct i915_wa_list *wal, const struct i915_wa *wa)
++{
++ const unsigned int grow = 1 << 4;
++
++ GEM_BUG_ON(!is_power_of_2(grow));
++
++ if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
++ struct i915_wa *list;
++
++ list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
++ GFP_KERNEL);
++ if (!list) {
++ DRM_ERROR("No space for workaround init!\n");
++ return;
++ }
++
++ if (wal->list)
++ memcpy(list, wal->list, sizeof(*wa) * wal->count);
++
++ wal->list = list;
++ }
++
++ wal->list[wal->count++] = *wa;
++}
++
++static void
++wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
++{
++ struct i915_wa wa = {
++ .reg = reg,
++ .mask = val,
++ .val = _MASKED_BIT_ENABLE(val)
++ };
++
++ wal_add(wal, &wa);
++}
++
++static void
++wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
++ u32 val)
+ {
++ struct i915_wa wa = {
++ .reg = reg,
++ .mask = mask,
++ .val = val
++ };
++
++ wal_add(wal, &wa);
+ }
+
+-static void chv_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void
++wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+ {
++ wa_write_masked_or(wal, reg, ~0, val);
+ }
+
+-static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void
++wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+ {
++ wa_write_masked_or(wal, reg, val, val);
++}
++
++static void gen9_gt_workarounds_init(struct drm_i915_private *i915)
++{
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
+ /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
+- I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
+- _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
++ wa_masked_en(wal,
++ GEN9_CSFE_CHICKEN1_RCS,
++ GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
++
+
+ /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
+- I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
+- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
++ wa_write_or(wal,
++ BDW_SCRATCH1,
++ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+
+ /* WaDisableKillLogic:bxt,skl,kbl */
+- if (!IS_COFFEELAKE(dev_priv))
+- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+- ECOCHK_DIS_TLB);
++ if (!IS_COFFEELAKE(i915))
++ wa_write_or(wal,
++ GAM_ECOCHK,
++ ECOCHK_DIS_TLB);
+
+- if (HAS_LLC(dev_priv)) {
++ if (HAS_LLC(i915)) {
+ /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
+ *
+ * Must match Display Engine. See
+ * WaCompressedResourceDisplayNewHashMode.
+ */
+- I915_WRITE(MMCD_MISC_CTRL,
+- I915_READ(MMCD_MISC_CTRL) |
+- MMCD_PCLA |
+- MMCD_HOTSPOT_EN);
++ wa_write_or(wal,
++ MMCD_MISC_CTRL,
++ MMCD_PCLA | MMCD_HOTSPOT_EN);
+ }
+
+ /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
+- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+- BDW_DISABLE_HDC_INVALIDATION);
++ wa_write_or(wal,
++ GAM_ECOCHK,
++ BDW_DISABLE_HDC_INVALIDATION);
+
+ /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+- if (IS_GEN9_LP(dev_priv)) {
+- u32 val = I915_READ(GEN8_L3SQCREG1);
+-
+- val &= ~L3_PRIO_CREDITS_MASK;
+- val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
+- I915_WRITE(GEN8_L3SQCREG1, val);
+- }
++ if (IS_GEN9_LP(i915))
++ wa_write_masked_or(wal,
++ GEN8_L3SQCREG1,
++ L3_PRIO_CREDITS_MASK,
++ L3_GENERAL_PRIO_CREDITS(62) |
++ L3_HIGH_PRIO_CREDITS(2));
+
+ /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
+- I915_WRITE(GEN8_L3SQCREG4,
+- I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES);
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
+- I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
+- _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
++ wa_masked_en(wal,
++ GEN7_FF_SLICE_CS_CHICKEN1,
++ GEN9_FFSC_PERCTX_PREEMPT_CTRL);
+ }
+
+-static void skl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void skl_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- gen9_gt_workarounds_apply(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ gen9_gt_workarounds_init(i915);
+
+ /* WaEnableGapsTsvCreditFix:skl */
+- I915_WRITE(GEN8_GARBCNTL,
+- I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN9_GAPS_TSV_CREDIT_DISABLE);
+
+ /* WaDisableGafsUnitClkGating:skl */
+- I915_WRITE(GEN7_UCGCTL4,
+- I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
++ wa_write_or(wal,
++ GEN7_UCGCTL4,
++ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaInPlaceDecompressionHang:skl */
+- if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+- I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ }
+
+-static void bxt_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void bxt_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- gen9_gt_workarounds_apply(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ gen9_gt_workarounds_init(i915);
+
+ /* WaDisablePooledEuLoadBalancingFix:bxt */
+- I915_WRITE(FF_SLICE_CS_CHICKEN2,
+- _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
++ wa_masked_en(wal,
++ FF_SLICE_CS_CHICKEN2,
++ GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+
+ /* WaInPlaceDecompressionHang:bxt */
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+- I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ }
+
+-static void kbl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void kbl_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- gen9_gt_workarounds_apply(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ gen9_gt_workarounds_init(i915);
+
+ /* WaEnableGapsTsvCreditFix:kbl */
+- I915_WRITE(GEN8_GARBCNTL,
+- I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN9_GAPS_TSV_CREDIT_DISABLE);
+
+ /* WaDisableDynamicCreditSharing:kbl */
+- if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+- I915_WRITE(GAMT_CHKN_BIT_REG,
+- I915_READ(GAMT_CHKN_BIT_REG) |
+- GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
++ if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
++ wa_write_or(wal,
++ GAMT_CHKN_BIT_REG,
++ GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+
+ /* WaDisableGafsUnitClkGating:kbl */
+- I915_WRITE(GEN7_UCGCTL4,
+- I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
++ wa_write_or(wal,
++ GEN7_UCGCTL4,
++ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaInPlaceDecompressionHang:kbl */
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+- I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaKBLVECSSemaphoreWaitPoll:kbl */
+- if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_E0)) {
++ if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+
+- for_each_engine(engine, dev_priv, tmp) {
++ for_each_engine(engine, i915, tmp) {
+ if (engine->id == RCS)
+ continue;
+
+- I915_WRITE(RING_SEMA_WAIT_POLL(engine->mmio_base), 1);
++ wa_write(wal,
++ RING_SEMA_WAIT_POLL(engine->mmio_base),
++ 1);
+ }
+ }
+ }
+
+-static void glk_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void glk_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- gen9_gt_workarounds_apply(dev_priv);
++ gen9_gt_workarounds_init(i915);
+ }
+
+-static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void cfl_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- gen9_gt_workarounds_apply(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ gen9_gt_workarounds_init(i915);
+
+ /* WaEnableGapsTsvCreditFix:cfl */
+- I915_WRITE(GEN8_GARBCNTL,
+- I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE);
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN9_GAPS_TSV_CREDIT_DISABLE);
+
+ /* WaDisableGafsUnitClkGating:cfl */
+- I915_WRITE(GEN7_UCGCTL4,
+- I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
++ wa_write_or(wal,
++ GEN7_UCGCTL4,
++ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaInPlaceDecompressionHang:cfl */
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+- I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ }
+
+ static void wa_init_mcr(struct drm_i915_private *dev_priv)
+ {
+ const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+- u32 mcr;
++ struct i915_wa_list *wal = &dev_priv->gt_wa_list;
+ u32 mcr_slice_subslice_mask;
+
+ /*
+@@ -770,8 +863,6 @@ static void wa_init_mcr(struct drm_i915_
+ WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+ }
+
+- mcr = I915_READ(GEN8_MCR_SELECTOR);
+-
+ if (INTEL_GEN(dev_priv) >= 11)
+ mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+ GEN11_MCR_SUBSLICE_MASK;
+@@ -789,148 +880,223 @@ static void wa_init_mcr(struct drm_i915_
+ * occasions, such as INSTDONE, where this value is dependent
+ * on s/ss combo, the read should be done with read_subslice_reg.
+ */
+- mcr &= ~mcr_slice_subslice_mask;
+- mcr |= intel_calculate_mcr_s_ss_select(dev_priv);
+- I915_WRITE(GEN8_MCR_SELECTOR, mcr);
++ wa_write_masked_or(wal,
++ GEN8_MCR_SELECTOR,
++ mcr_slice_subslice_mask,
++ intel_calculate_mcr_s_ss_select(dev_priv));
+ }
+
+-static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void cnl_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- wa_init_mcr(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ wa_init_mcr(i915);
+
+ /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
+- if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
+- I915_WRITE(GAMT_CHKN_BIT_REG,
+- I915_READ(GAMT_CHKN_BIT_REG) |
+- GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
++ if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
++ wa_write_or(wal,
++ GAMT_CHKN_BIT_REG,
++ GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
+
+ /* WaInPlaceDecompressionHang:cnl */
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+- I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaEnablePreemptionGranularityControlByUMD:cnl */
+- I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
+- _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
++ wa_masked_en(wal,
++ GEN7_FF_SLICE_CS_CHICKEN1,
++ GEN9_FFSC_PERCTX_PREEMPT_CTRL);
+ }
+
+-static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++static void icl_gt_workarounds_init(struct drm_i915_private *i915)
+ {
+- wa_init_mcr(dev_priv);
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ wa_init_mcr(i915);
+
+ /* This is not an Wa. Enable for better image quality */
+- I915_WRITE(_3D_CHICKEN3,
+- _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
++ wa_masked_en(wal,
++ _3D_CHICKEN3,
++ _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
+
+ /* WaInPlaceDecompressionHang:icl */
+- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
++ wa_write_or(wal,
++ GEN9_GAMT_ECO_REG_RW_IA,
++ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+ /* WaPipelineFlushCoherentLines:icl */
+- I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+- GEN8_LQSC_FLUSH_COHERENT_LINES);
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Wa_1405543622:icl
+ * Formerly known as WaGAPZPriorityScheme
+ */
+- I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
+- GEN11_ARBITRATION_PRIO_ORDER_MASK);
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN11_ARBITRATION_PRIO_ORDER_MASK);
+
+ /* Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
+ */
+- I915_WRITE(GEN8_GARBCNTL,
+- (I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+- GEN11_HASH_CTRL_EXCL_BIT0);
+- I915_WRITE(GEN11_GLBLINVL,
+- (I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
++ wa_write_masked_or(wal,
++ GEN8_GARBCNTL,
++ GEN11_HASH_CTRL_EXCL_MASK,
++ GEN11_HASH_CTRL_EXCL_BIT0);
++ wa_write_masked_or(wal,
++ GEN11_GLBLINVL,
++ GEN11_BANK_HASH_ADDR_EXCL_MASK,
++ GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+
+ /* WaModifyGamTlbPartitioning:icl */
+- I915_WRITE(GEN11_GACB_PERF_CTRL,
+- (I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+- GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
++ wa_write_masked_or(wal,
++ GEN11_GACB_PERF_CTRL,
++ GEN11_HASH_CTRL_MASK,
++ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+
+ /* Wa_1405733216:icl
+ * Formerly known as WaDisableCleanEvicts
+ */
+- I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+- GEN11_LQSC_CLEAN_EVICT_DISABLE);
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+ /* Wa_1405766107:icl
+ * Formerly known as WaCL2SFHalfMaxAlloc
+ */
+- I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
+- GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+- GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
++ wa_write_or(wal,
++ GEN11_LSN_UNSLCVC,
++ GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
++ GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
+
+ /* Wa_220166154:icl
+ * Formerly known as WaDisCtxReload
+ */
+- I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+- GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
++ wa_write_or(wal,
++ GEN8_GAMW_ECO_DEV_RW_IA,
++ GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
+
+ /* Wa_1405779004:icl (pre-prod) */
+- if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+- I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+- I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+- MSCUNIT_CLKGATE_DIS);
++ if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
++ wa_write_or(wal,
++ SLICE_UNIT_LEVEL_CLKGATE,
++ MSCUNIT_CLKGATE_DIS);
+
+ /* Wa_1406680159:icl */
+- I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+- I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+- GWUNIT_CLKGATE_DIS);
++ wa_write_or(wal,
++ SUBSLICE_UNIT_LEVEL_CLKGATE,
++ GWUNIT_CLKGATE_DIS);
+
+ /* Wa_1604302699:icl */
+- I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+- I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+- GEN11_I2M_WRITE_DISABLE);
++ wa_write_or(wal,
++ GEN10_L3_CHICKEN_MODE_REGISTER,
++ GEN11_I2M_WRITE_DISABLE);
+
+ /* Wa_1406838659:icl (pre-prod) */
+- if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+- I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+- I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+- CGPSF_CLKGATE_DIS);
++ if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
++ wa_write_or(wal,
++ INF_UNIT_LEVEL_CLKGATE,
++ CGPSF_CLKGATE_DIS);
+
+ /* WaForwardProgressSoftReset:icl */
+- I915_WRITE(GEN10_SCRATCH_LNCF2,
+- I915_READ(GEN10_SCRATCH_LNCF2) |
+- PMFLUSHDONE_LNICRSDROP |
+- PMFLUSH_GAPL3UNBLOCK |
+- PMFLUSHDONE_LNEBLK);
++ wa_write_or(wal,
++ GEN10_SCRATCH_LNCF2,
++ PMFLUSHDONE_LNICRSDROP |
++ PMFLUSH_GAPL3UNBLOCK |
++ PMFLUSHDONE_LNEBLK);
+
+ /* Wa_1406463099:icl
+ * Formerly known as WaGamTlbPendError
+ */
+- I915_WRITE(GAMT_CHKN_BIT_REG,
+- I915_READ(GAMT_CHKN_BIT_REG) |
+- GAMT_CHKN_DISABLE_L3_COH_PIPE);
++ wa_write_or(wal,
++ GAMT_CHKN_BIT_REG,
++ GAMT_CHKN_DISABLE_L3_COH_PIPE);
+ }
+
+-void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
++void intel_gt_init_workarounds(struct drm_i915_private *i915)
+ {
+- if (INTEL_GEN(dev_priv) < 8)
++ struct i915_wa_list *wal = &i915->gt_wa_list;
++
++ wa_init_start(wal, "GT");
++
++ if (INTEL_GEN(i915) < 8)
+ return;
+- else if (IS_BROADWELL(dev_priv))
+- bdw_gt_workarounds_apply(dev_priv);
+- else if (IS_CHERRYVIEW(dev_priv))
+- chv_gt_workarounds_apply(dev_priv);
+- else if (IS_SKYLAKE(dev_priv))
+- skl_gt_workarounds_apply(dev_priv);
+- else if (IS_BROXTON(dev_priv))
+- bxt_gt_workarounds_apply(dev_priv);
+- else if (IS_KABYLAKE(dev_priv))
+- kbl_gt_workarounds_apply(dev_priv);
+- else if (IS_GEMINILAKE(dev_priv))
+- glk_gt_workarounds_apply(dev_priv);
+- else if (IS_COFFEELAKE(dev_priv))
+- cfl_gt_workarounds_apply(dev_priv);
+- else if (IS_CANNONLAKE(dev_priv))
+- cnl_gt_workarounds_apply(dev_priv);
+- else if (IS_ICELAKE(dev_priv))
+- icl_gt_workarounds_apply(dev_priv);
++ else if (IS_BROADWELL(i915))
++ return;
++ else if (IS_CHERRYVIEW(i915))
++ return;
++ else if (IS_SKYLAKE(i915))
++ skl_gt_workarounds_init(i915);
++ else if (IS_BROXTON(i915))
++ bxt_gt_workarounds_init(i915);
++ else if (IS_KABYLAKE(i915))
++ kbl_gt_workarounds_init(i915);
++ else if (IS_GEMINILAKE(i915))
++ glk_gt_workarounds_init(i915);
++ else if (IS_COFFEELAKE(i915))
++ cfl_gt_workarounds_init(i915);
++ else if (IS_CANNONLAKE(i915))
++ cnl_gt_workarounds_init(i915);
++ else if (IS_ICELAKE(i915))
++ icl_gt_workarounds_init(i915);
+ else
+- MISSING_CASE(INTEL_GEN(dev_priv));
++ MISSING_CASE(INTEL_GEN(i915));
++
++ wa_init_finish(wal);
++}
++
++static enum forcewake_domains
++wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
++ const struct i915_wa_list *wal)
++{
++ enum forcewake_domains fw = 0;
++ struct i915_wa *wa;
++ unsigned int i;
++
++ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
++ fw |= intel_uncore_forcewake_for_reg(dev_priv,
++ wa->reg,
++ FW_REG_READ |
++ FW_REG_WRITE);
++
++ return fw;
++}
++
++static void
++wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
++{
++ enum forcewake_domains fw;
++ unsigned long flags;
++ struct i915_wa *wa;
++ unsigned int i;
++
++ if (!wal->count)
++ return;
++
++ fw = wal_get_fw_for_rmw(dev_priv, wal);
++
++ spin_lock_irqsave(&dev_priv->uncore.lock, flags);
++ intel_uncore_forcewake_get__locked(dev_priv, fw);
++
++ for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
++ u32 val = I915_READ_FW(wa->reg);
++
++ val &= ~wa->mask;
++ val |= wa->val;
++
++ I915_WRITE_FW(wa->reg, val);
++ }
++
++ intel_uncore_forcewake_put__locked(dev_priv, fw);
++ spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
++
++ DRM_DEBUG_DRIVER("Applied %u %s workarounds\n", wal->count, wal->name);
++}
++
++void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv)
++{
++ wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
+ }
+
+ struct whitelist {
+--- a/drivers/gpu/drm/i915/intel_workarounds.h
++++ b/drivers/gpu/drm/i915/intel_workarounds.h
+@@ -7,10 +7,31 @@
+ #ifndef _I915_WORKAROUNDS_H_
+ #define _I915_WORKAROUNDS_H_
+
++#include <linux/slab.h>
++
++struct i915_wa {
++ i915_reg_t reg;
++ u32 mask;
++ u32 val;
++};
++
++struct i915_wa_list {
++ const char *name;
++ struct i915_wa *list;
++ unsigned int count;
++};
++
++static inline void intel_wa_list_free(struct i915_wa_list *wal)
++{
++ kfree(wal->list);
++ memset(wal, 0, sizeof(*wal));
++}
++
+ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
+ int intel_ctx_workarounds_emit(struct i915_request *rq);
+
+-void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
++void intel_gt_init_workarounds(struct drm_i915_private *dev_priv);
++void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv);
+
+ void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
+
diff --git a/patches.drm/0004-drm-i915-Introduce-per-engine-workarounds.patch b/patches.drm/0004-drm-i915-Introduce-per-engine-workarounds.patch
new file mode 100644
index 0000000000..facdf513d4
--- /dev/null
+++ b/patches.drm/0004-drm-i915-Introduce-per-engine-workarounds.patch
@@ -0,0 +1,474 @@
+From 90098efacc4c3e2e4f6262a657d6b520ecfb2555 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Wed, 5 Dec 2018 11:33:24 +0000
+Subject: drm/i915: Introduce per-engine workarounds
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 90098efacc4c3e2e4f6262a657d6b520ecfb2555
+Patch-mainline: v4.20-rc7
+References: bsc#1113956
+
+We stopped re-applying the GT workarounds after engine reset since commit
+59b449d5c82a ("drm/i915: Split out functions for different kinds of
+workarounds").
+
+Issue with this is that some of the GT workarounds live in the MMIO space
+which gets lost during engine resets. So far the registers in 0x2xxx and
+0xbxxx address range have been identified to be affected.
+
+This losing of applied workarounds has obvious negative effects and can
+even lead to hard system hangs (see the linked Bugzilla).
+
+Rather than just restoring this re-application, because we have also
+observed that it is not safe to just re-write all GT workarounds after
+engine resets (GPU might be live and weird hardware states can happen),
+we introduce a new class of per-engine workarounds and move only the
+affected GT workarounds over.
+
+Using the framework introduced in the previous patch, we therefore after
+engine reset, re-apply only the workarounds living in the affected MMIO
+address ranges.
+
+v2:
+ * Move Wa_1406609255:icl to engine workarounds as well.
+ * Rename API. (Chris Wilson)
+ * Drop redundant IS_KABYLAKE. (Chris Wilson)
+ * Re-order engine wa/ init so latest platforms are first. (Rodrigo Vivi)
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945
+Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: intel-gfx@lists.freedesktop.org
+Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181203133341.10258-1-tvrtko.ursulin@linux.intel.com
+(cherry picked from commit 4a15c75c42460252a63d30f03b4766a52945fb47)
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_engine_cs.c | 2
+ drivers/gpu/drm/i915/intel_lrc.c | 4
+ drivers/gpu/drm/i915/intel_ringbuffer.h | 2
+ drivers/gpu/drm/i915/intel_workarounds.c | 257 ++++++++++++++++---------------
+ drivers/gpu/drm/i915/intel_workarounds.h | 3
+ 5 files changed, 151 insertions(+), 117 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_engine_cs.c
++++ b/drivers/gpu/drm/i915/intel_engine_cs.c
+@@ -739,6 +739,8 @@ void intel_engine_cleanup_common(struct
+ __intel_context_unpin(i915->kernel_context, engine);
+
+ i915_timeline_fini(&engine->timeline);
++
++ intel_wa_list_free(&engine->wa_list);
+ }
+
+ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
+--- a/drivers/gpu/drm/i915/intel_lrc.c
++++ b/drivers/gpu/drm/i915/intel_lrc.c
+@@ -1789,6 +1789,8 @@ static int gen8_init_common_ring(struct
+ {
+ int ret;
+
++ intel_engine_apply_workarounds(engine);
++
+ ret = intel_mocs_init_engine(engine);
+ if (ret)
+ return ret;
+@@ -2451,6 +2453,8 @@ static int logical_ring_init(struct inte
+ }
+ reset_csb_pointers(execlists);
+
++ intel_engine_init_workarounds(engine);
++
+ return 0;
+
+ error:
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
+@@ -12,6 +12,7 @@
+ #include "i915_selftest.h"
+ #include "i915_timeline.h"
+ #include "intel_gpu_commands.h"
++#include "intel_workarounds.h"
+
+ struct drm_printer;
+ struct i915_sched_attr;
+@@ -437,6 +438,7 @@ struct intel_engine_cs {
+
+ struct intel_hw_status_page status_page;
+ struct i915_ctx_workarounds wa_ctx;
++ struct i915_wa_list wa_list;
+ struct i915_vma *scratch;
+
+ u32 irq_keep_mask; /* always keep these interrupts */
+--- a/drivers/gpu/drm/i915/intel_workarounds.c
++++ b/drivers/gpu/drm/i915/intel_workarounds.c
+@@ -661,17 +661,6 @@ static void gen9_gt_workarounds_init(str
+ {
+ struct i915_wa_list *wal = &i915->gt_wa_list;
+
+- /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
+- wa_masked_en(wal,
+- GEN9_CSFE_CHICKEN1_RCS,
+- GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
+-
+-
+- /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
+- wa_write_or(wal,
+- BDW_SCRATCH1,
+- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+-
+ /* WaDisableKillLogic:bxt,skl,kbl */
+ if (!IS_COFFEELAKE(i915))
+ wa_write_or(wal,
+@@ -693,24 +682,6 @@ static void gen9_gt_workarounds_init(str
+ wa_write_or(wal,
+ GAM_ECOCHK,
+ BDW_DISABLE_HDC_INVALIDATION);
+-
+- /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+- if (IS_GEN9_LP(i915))
+- wa_write_masked_or(wal,
+- GEN8_L3SQCREG1,
+- L3_PRIO_CREDITS_MASK,
+- L3_GENERAL_PRIO_CREDITS(62) |
+- L3_HIGH_PRIO_CREDITS(2));
+-
+- /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
+- wa_write_or(wal,
+- GEN8_L3SQCREG4,
+- GEN8_LQSC_FLUSH_COHERENT_LINES);
+-
+- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
+- wa_masked_en(wal,
+- GEN7_FF_SLICE_CS_CHICKEN1,
+- GEN9_FFSC_PERCTX_PREEMPT_CTRL);
+ }
+
+ static void skl_gt_workarounds_init(struct drm_i915_private *i915)
+@@ -719,11 +690,6 @@ static void skl_gt_workarounds_init(stru
+
+ gen9_gt_workarounds_init(i915);
+
+- /* WaEnableGapsTsvCreditFix:skl */
+- wa_write_or(wal,
+- GEN8_GARBCNTL,
+- GEN9_GAPS_TSV_CREDIT_DISABLE);
+-
+ /* WaDisableGafsUnitClkGating:skl */
+ wa_write_or(wal,
+ GEN7_UCGCTL4,
+@@ -742,11 +708,6 @@ static void bxt_gt_workarounds_init(stru
+
+ gen9_gt_workarounds_init(i915);
+
+- /* WaDisablePooledEuLoadBalancingFix:bxt */
+- wa_masked_en(wal,
+- FF_SLICE_CS_CHICKEN2,
+- GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+-
+ /* WaInPlaceDecompressionHang:bxt */
+ wa_write_or(wal,
+ GEN9_GAMT_ECO_REG_RW_IA,
+@@ -759,11 +720,6 @@ static void kbl_gt_workarounds_init(stru
+
+ gen9_gt_workarounds_init(i915);
+
+- /* WaEnableGapsTsvCreditFix:kbl */
+- wa_write_or(wal,
+- GEN8_GARBCNTL,
+- GEN9_GAPS_TSV_CREDIT_DISABLE);
+-
+ /* WaDisableDynamicCreditSharing:kbl */
+ if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
+ wa_write_or(wal,
+@@ -779,21 +735,6 @@ static void kbl_gt_workarounds_init(stru
+ wa_write_or(wal,
+ GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+-
+- /* WaKBLVECSSemaphoreWaitPoll:kbl */
+- if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
+- struct intel_engine_cs *engine;
+- unsigned int tmp;
+-
+- for_each_engine(engine, i915, tmp) {
+- if (engine->id == RCS)
+- continue;
+-
+- wa_write(wal,
+- RING_SEMA_WAIT_POLL(engine->mmio_base),
+- 1);
+- }
+- }
+ }
+
+ static void glk_gt_workarounds_init(struct drm_i915_private *i915)
+@@ -807,11 +748,6 @@ static void cfl_gt_workarounds_init(stru
+
+ gen9_gt_workarounds_init(i915);
+
+- /* WaEnableGapsTsvCreditFix:cfl */
+- wa_write_or(wal,
+- GEN8_GARBCNTL,
+- GEN9_GAPS_TSV_CREDIT_DISABLE);
+-
+ /* WaDisableGafsUnitClkGating:cfl */
+ wa_write_or(wal,
+ GEN7_UCGCTL4,
+@@ -902,11 +838,6 @@ static void cnl_gt_workarounds_init(stru
+ wa_write_or(wal,
+ GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+-
+- /* WaEnablePreemptionGranularityControlByUMD:cnl */
+- wa_masked_en(wal,
+- GEN7_FF_SLICE_CS_CHICKEN1,
+- GEN9_FFSC_PERCTX_PREEMPT_CTRL);
+ }
+
+ static void icl_gt_workarounds_init(struct drm_i915_private *i915)
+@@ -915,53 +846,17 @@ static void icl_gt_workarounds_init(stru
+
+ wa_init_mcr(i915);
+
+- /* This is not an Wa. Enable for better image quality */
+- wa_masked_en(wal,
+- _3D_CHICKEN3,
+- _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
+-
+ /* WaInPlaceDecompressionHang:icl */
+ wa_write_or(wal,
+ GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+- /* WaPipelineFlushCoherentLines:icl */
+- wa_write_or(wal,
+- GEN8_L3SQCREG4,
+- GEN8_LQSC_FLUSH_COHERENT_LINES);
+-
+- /* Wa_1405543622:icl
+- * Formerly known as WaGAPZPriorityScheme
+- */
+- wa_write_or(wal,
+- GEN8_GARBCNTL,
+- GEN11_ARBITRATION_PRIO_ORDER_MASK);
+-
+- /* Wa_1604223664:icl
+- * Formerly known as WaL3BankAddressHashing
+- */
+- wa_write_masked_or(wal,
+- GEN8_GARBCNTL,
+- GEN11_HASH_CTRL_EXCL_MASK,
+- GEN11_HASH_CTRL_EXCL_BIT0);
+- wa_write_masked_or(wal,
+- GEN11_GLBLINVL,
+- GEN11_BANK_HASH_ADDR_EXCL_MASK,
+- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+-
+ /* WaModifyGamTlbPartitioning:icl */
+ wa_write_masked_or(wal,
+ GEN11_GACB_PERF_CTRL,
+ GEN11_HASH_CTRL_MASK,
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+
+- /* Wa_1405733216:icl
+- * Formerly known as WaDisableCleanEvicts
+- */
+- wa_write_or(wal,
+- GEN8_L3SQCREG4,
+- GEN11_LQSC_CLEAN_EVICT_DISABLE);
+-
+ /* Wa_1405766107:icl
+ * Formerly known as WaCL2SFHalfMaxAlloc
+ */
+@@ -988,24 +883,12 @@ static void icl_gt_workarounds_init(stru
+ SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GWUNIT_CLKGATE_DIS);
+
+- /* Wa_1604302699:icl */
+- wa_write_or(wal,
+- GEN10_L3_CHICKEN_MODE_REGISTER,
+- GEN11_I2M_WRITE_DISABLE);
+-
+ /* Wa_1406838659:icl (pre-prod) */
+ if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
+ wa_write_or(wal,
+ INF_UNIT_LEVEL_CLKGATE,
+ CGPSF_CLKGATE_DIS);
+
+- /* WaForwardProgressSoftReset:icl */
+- wa_write_or(wal,
+- GEN10_SCRATCH_LNCF2,
+- PMFLUSHDONE_LNICRSDROP |
+- PMFLUSH_GAPL3UNBLOCK |
+- PMFLUSHDONE_LNEBLK);
+-
+ /* Wa_1406463099:icl
+ * Formerly known as WaGamTlbPendError
+ */
+@@ -1243,6 +1126,146 @@ void intel_whitelist_workarounds_apply(s
+ whitelist_apply(engine, whitelist_build(engine, &w));
+ }
+
++static void rcs_engine_wa_init(struct intel_engine_cs *engine)
++{
++ struct drm_i915_private *i915 = engine->i915;
++ struct i915_wa_list *wal = &engine->wa_list;
++
++ if (IS_ICELAKE(i915)) {
++ /* This is not an Wa. Enable for better image quality */
++ wa_masked_en(wal,
++ _3D_CHICKEN3,
++ _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
++
++ /* WaPipelineFlushCoherentLines:icl */
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN8_LQSC_FLUSH_COHERENT_LINES);
++
++ /*
++ * Wa_1405543622:icl
++ * Formerly known as WaGAPZPriorityScheme
++ */
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN11_ARBITRATION_PRIO_ORDER_MASK);
++
++ /*
++ * Wa_1604223664:icl
++ * Formerly known as WaL3BankAddressHashing
++ */
++ wa_write_masked_or(wal,
++ GEN8_GARBCNTL,
++ GEN11_HASH_CTRL_EXCL_MASK,
++ GEN11_HASH_CTRL_EXCL_BIT0);
++ wa_write_masked_or(wal,
++ GEN11_GLBLINVL,
++ GEN11_BANK_HASH_ADDR_EXCL_MASK,
++ GEN11_BANK_HASH_ADDR_EXCL_BIT0);
++
++ /*
++ * Wa_1405733216:icl
++ * Formerly known as WaDisableCleanEvicts
++ */
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN11_LQSC_CLEAN_EVICT_DISABLE);
++
++ /* Wa_1604302699:icl */
++ wa_write_or(wal,
++ GEN10_L3_CHICKEN_MODE_REGISTER,
++ GEN11_I2M_WRITE_DISABLE);
++
++ /* WaForwardProgressSoftReset:icl */
++ wa_write_or(wal,
++ GEN10_SCRATCH_LNCF2,
++ PMFLUSHDONE_LNICRSDROP |
++ PMFLUSH_GAPL3UNBLOCK |
++ PMFLUSHDONE_LNEBLK);
++ }
++
++ if (IS_GEN9(i915) || IS_CANNONLAKE(i915)) {
++ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
++ wa_masked_en(wal,
++ GEN7_FF_SLICE_CS_CHICKEN1,
++ GEN9_FFSC_PERCTX_PREEMPT_CTRL);
++ }
++
++ if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
++ /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
++ wa_write_or(wal,
++ GEN8_GARBCNTL,
++ GEN9_GAPS_TSV_CREDIT_DISABLE);
++ }
++
++ if (IS_BROXTON(i915)) {
++ /* WaDisablePooledEuLoadBalancingFix:bxt */
++ wa_masked_en(wal,
++ FF_SLICE_CS_CHICKEN2,
++ GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
++ }
++
++ if (IS_GEN9(i915)) {
++ /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
++ wa_masked_en(wal,
++ GEN9_CSFE_CHICKEN1_RCS,
++ GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
++
++ /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
++ wa_write_or(wal,
++ BDW_SCRATCH1,
++ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
++
++ /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
++ if (IS_GEN9_LP(i915))
++ wa_write_masked_or(wal,
++ GEN8_L3SQCREG1,
++ L3_PRIO_CREDITS_MASK,
++ L3_GENERAL_PRIO_CREDITS(62) |
++ L3_HIGH_PRIO_CREDITS(2));
++
++ /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
++ wa_write_or(wal,
++ GEN8_L3SQCREG4,
++ GEN8_LQSC_FLUSH_COHERENT_LINES);
++ }
++}
++
++static void xcs_engine_wa_init(struct intel_engine_cs *engine)
++{
++ struct drm_i915_private *i915 = engine->i915;
++ struct i915_wa_list *wal = &engine->wa_list;
++
++ /* WaKBLVECSSemaphoreWaitPoll:kbl */
++ if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
++ wa_write(wal,
++ RING_SEMA_WAIT_POLL(engine->mmio_base),
++ 1);
++ }
++}
++
++void intel_engine_init_workarounds(struct intel_engine_cs *engine)
++{
++ struct i915_wa_list *wal = &engine->wa_list;
++
++ if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
++ return;
++
++ wa_init_start(wal, engine->name);
++
++ if (engine->id == RCS)
++ rcs_engine_wa_init(engine);
++ else
++ xcs_engine_wa_init(engine);
++
++ wa_init_finish(wal);
++}
++
++void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
++{
++ wa_list_apply(engine->i915, &engine->wa_list);
++}
++
+ #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+ #include "selftests/intel_workarounds.c"
+ #endif
+--- a/drivers/gpu/drm/i915/intel_workarounds.h
++++ b/drivers/gpu/drm/i915/intel_workarounds.h
+@@ -35,4 +35,7 @@ void intel_gt_apply_workarounds(struct d
+
+ void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
+
++void intel_engine_init_workarounds(struct intel_engine_cs *engine);
++void intel_engine_apply_workarounds(struct intel_engine_cs *engine);
++
+ #endif
diff --git a/patches.drm/0005-drm-nouveau-kms-nv50-also-flush-fb-writes-when-rewin.patch b/patches.drm/0005-drm-nouveau-kms-nv50-also-flush-fb-writes-when-rewin.patch
new file mode 100644
index 0000000000..6dcc4d1a05
--- /dev/null
+++ b/patches.drm/0005-drm-nouveau-kms-nv50-also-flush-fb-writes-when-rewin.patch
@@ -0,0 +1,77 @@
+From 970a5ee41c72df46e3b0f307528c7d8ef7734a2e Mon Sep 17 00:00:00 2001
+From: Ben Skeggs <bskeggs@redhat.com>
+Date: Wed, 12 Dec 2018 16:51:17 +1000
+Subject: drm/nouveau/kms/nv50-: also flush fb writes when rewinding push
+ buffer
+Git-commit: 970a5ee41c72df46e3b0f307528c7d8ef7734a2e
+Patch-mainline: v4.20-rc7
+References: bsc#1113956
+
+Should hopefully fix a regression some people have been seeing since EVO
+push buffers were moved to VRAM by default on Pascal GPUs.
+
+Fixes: d00ddd9da ("drm/nouveau/kms/nv50-: allocate push buffers in vidmem on pascal")
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Cc: <stable@vger.kernel.org> # 4.19+
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/nouveau/dispnv50/disp.c | 29 +++++++++++++++----------
+ 1 file changed, 18 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
+index 5f163a025e89..03e3ce9e6f28 100644
+--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
++++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
+@@ -198,6 +198,22 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
+ /******************************************************************************
+ * EVO channel helpers
+ *****************************************************************************/
++static void
++evo_flush(struct nv50_dmac *dmac)
++{
++ /* Push buffer fetches are not coherent with BAR1, we need to ensure
++ * writes have been flushed right through to VRAM before writing PUT.
++ */
++ if (dmac->push.type & NVIF_MEM_VRAM) {
++ struct nvif_device *device = dmac->base.device;
++ nvif_wr32(&device->object, 0x070000, 0x00000001);
++ nvif_msec(device, 2000,
++ if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
++ break;
++ );
++ }
++}
++
+ u32 *
+ evo_wait(struct nv50_dmac *evoc, int nr)
+ {
+@@ -208,6 +224,7 @@ evo_wait(struct nv50_dmac *evoc, int nr)
+ mutex_lock(&dmac->lock);
+ if (put + nr >= (PAGE_SIZE / 4) - 8) {
+ dmac->ptr[put] = 0x20000000;
++ evo_flush(dmac);
+
+ nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
+ if (nvif_msec(device, 2000,
+@@ -230,17 +247,7 @@ evo_kick(u32 *push, struct nv50_dmac *evoc)
+ {
+ struct nv50_dmac *dmac = evoc;
+
+- /* Push buffer fetches are not coherent with BAR1, we need to ensure
+- * writes have been flushed right through to VRAM before writing PUT.
+- */
+- if (dmac->push.type & NVIF_MEM_VRAM) {
+- struct nvif_device *device = dmac->base.device;
+- nvif_wr32(&device->object, 0x070000, 0x00000001);
+- nvif_msec(device, 2000,
+- if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
+- break;
+- );
+- }
++ evo_flush(dmac);
+
+ nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
+ mutex_unlock(&dmac->lock);
+--
+2.20.1
+
diff --git a/patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch b/patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch
new file mode 100644
index 0000000000..f8e9e96dfd
--- /dev/null
+++ b/patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch
@@ -0,0 +1,67 @@
+From 47658556da857c66c5865f192408639f524cca40 Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Thu, 27 Sep 2018 13:57:33 -0700
+Subject: drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 47658556da857c66c5865f192408639f524cca40
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+A crtc modeset lock was added for link retraining but
+intel_dp_retrain_link() knows to take the necessary locks since
+commit c85d200e8321 ("drm/i915: Move SST DP link retraining into the
+->post_hotplug() hook")
+v2: Drop AUX power domain reference in the early return path
+
+Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the ->post_hotplug() hook")
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180927205735.16651-4-dhinakaran.pandiyan@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 21 ++++++++-------------
+ 1 file changed, 8 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -4747,8 +4747,14 @@ intel_dp_long_pulse(struct intel_connect
+ */
+ if (!intel_dp_is_edp(intel_dp)) {
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
++ int ret;
+
+- intel_dp_retrain_link(encoder, ctx);
++ ret = intel_dp_retrain_link(encoder, ctx);
++ if (ret) {
++ intel_display_power_put(dev_priv,
++ intel_dp->aux_power_domain);
++ return ret;
++ }
+ }
+
+ /*
+@@ -4799,19 +4805,8 @@ intel_dp_detect(struct drm_connector *co
+ connector->base.id, connector->name);
+
+ /* If full detect is not performed yet, do a full detect */
+- if (!intel_dp->detect_done) {
+- struct drm_crtc *crtc;
+- int ret;
+-
+- crtc = connector->state->crtc;
+- if (crtc) {
+- ret = drm_modeset_lock(&crtc->mutex, ctx);
+- if (ret)
+- return ret;
+- }
+-
++ if (!intel_dp->detect_done)
+ status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
+- }
+
+ intel_dp->detect_done = false;
+
diff --git a/patches.drm/0044-drm-msm-disp-dpu-Use-proper-define-for-drm_encoder_i.patch b/patches.drm/0044-drm-msm-disp-dpu-Use-proper-define-for-drm_encoder_i.patch
new file mode 100644
index 0000000000..73229133cf
--- /dev/null
+++ b/patches.drm/0044-drm-msm-disp-dpu-Use-proper-define-for-drm_encoder_i.patch
@@ -0,0 +1,111 @@
+From 2c043eeffea4813b8f569e84b46035a08de5eb47 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <swboyd@chromium.org>
+Date: Thu, 16 Aug 2018 16:36:16 -0700
+Subject: drm/msm/disp/dpu: Use proper define for drm_encoder_init()
+ 'encoder_type'
+Git-commit: 2c043eeffea4813b8f569e84b46035a08de5eb47
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+We got a bug report that this function oopses when trying to do a kasprintf().
+
+PC is at string+0x2c/0x60
+LR is at vsnprintf+0x28c/0x4ec
+pc : [<ffffff80088d35d8>] lr : [<ffffff80088d5fc4>] pstate: a0c00049
+sp : ffffff80095fb540
+x29: ffffff80095fb540 x28: ffffff8008ad42bc
+x27: 00000000ffffffd8 x26: 0000000000000000
+x25: ffffff8008c216c8 x24: 0000000000000000
+x23: 0000000000000000 x22: ffffff80095fb720
+x21: 0000000000000000 x20: ffffff80095fb720
+x19: ffffff80095fb6f0 x18: 000000000000000a
+x17: 00000000b42ba473 x16: ffffff800805bbe8
+x15: 00000000000a157d x14: 000000000000000c
+x13: 0000000000000000 x12: 0000ffff0000000f
+x11: 0000000000000003 x10: 0000000000000001
+x9 : 0000000000000040 x8 : 000000000000001c
+x7 : ffffffffffffffff x6 : 0000000000000000
+x5 : 0000000000000228 x4 : 0000000000000000
+x3 : ffff0a00ffffff04 x2 : 0000000000007961
+x1 : 0000000000000000 x0 : 0000000000000000
+Process kworker/3:1 (pid: 61, stack limit = 0xffffff80095f8000)
+Call trace:
+Exception stack(0xffffff80095fb400 to 0xffffff80095fb540)
+b400: 0000000000000000 0000000000000000 0000000000007961 ffff0a00ffffff04
+b420: 0000000000000000 0000000000000228 0000000000000000 ffffffffffffffff
+b440: 000000000000001c 0000000000000040 0000000000000001 0000000000000003
+b460: 0000ffff0000000f 0000000000000000 000000000000000c 00000000000a157d
+b480: ffffff800805bbe8 00000000b42ba473 000000000000000a ffffff80095fb6f0
+b4a0: ffffff80095fb720 0000000000000000 ffffff80095fb720 0000000000000000
+b4c0: 0000000000000000 ffffff8008c216c8 0000000000000000 00000000ffffffd8
+b4e0: ffffff8008ad42bc ffffff80095fb540 ffffff80088d5fc4 ffffff80095fb540
+b500: ffffff80088d35d8 00000000a0c00049 ffffff80095fb550 ffffff80080d06a4
+b520: ffffffffffffffff ffffff80088d5e0c ffffff80095fb540 ffffff80088d35d8
+[<ffffff80088d35d8>] string+0x2c/0x60
+[<ffffff80088d5fc4>] vsnprintf+0x28c/0x4ec
+[<ffffff80083973b8>] kvasprintf+0x68/0x100
+[<ffffff800839755c>] kasprintf+0x60/0x80
+[<ffffff800849cc24>] drm_encoder_init+0x134/0x164
+[<ffffff80084d9a7c>] dpu_encoder_init+0x60/0x94
+[<ffffff80084eced0>] _dpu_kms_drm_obj_init+0xa0/0x424
+[<ffffff80084ed870>] dpu_kms_hw_init+0x61c/0x6bc
+[<ffffff80084f7614>] msm_drm_bind+0x380/0x67c
+[<ffffff80085114e4>] try_to_bring_up_master+0x228/0x264
+[<ffffff80085116e8>] component_master_add_with_match+0x90/0xc0
+[<ffffff80084f722c>] msm_pdev_probe+0x260/0x2c8
+[<ffffff800851a910>] platform_drv_probe+0x58/0xa8
+[<ffffff80085185c8>] driver_probe_device+0x2d8/0x40c
+[<ffffff8008518928>] __device_attach_driver+0xd4/0x10c
+[<ffffff800851644c>] bus_for_each_drv+0xb4/0xd0
+[<ffffff8008518230>] __device_attach+0xd0/0x160
+[<ffffff8008518984>] device_initial_probe+0x24/0x30
+[<ffffff800851744c>] bus_probe_device+0x38/0x98
+[<ffffff8008517aac>] deferred_probe_work_func+0x144/0x148
+[<ffffff80080c8654>] process_one_work+0x218/0x3bc
+[<ffffff80080c883c>] process_scheduled_works+0x44/0x48
+[<ffffff80080c95bc>] worker_thread+0x288/0x32c
+[<ffffff80080cea30>] kthread+0x134/0x13c
+[<ffffff8008084750>] ret_from_fork+0x10/0x18
+Code: 910003fd 2a0403e6 eb0400ff 54000060 (38646845)
+
+Looking at the code I see that drm_encoder_init() is called from the DPU
+code with 'DRM_MODE_CONNECTOR_DSI' passed in as the 'encoder_type'
+argument (follow from _dpu_kms_initialize_dsi()). That corresponds to
+the integer 16. That is then indexed into drm_encoder_enum_list in
+drm_encoder_init() to look up the name of the encoder. If you're still
+following along, that's an encoder not a connector! We really want to
+use DRM_MODE_ENCODER_DSI (integer 6) instead of DRM_MODE_CONNECTOR_DSI
+here, or we'll go out of bounds of the encoder array. Pass the right
+thing and everything is fine.
+
+Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
+Cc: Jordan Crouse <jcrouse@codeaurora.org>
+Cc: Sean Paul <seanpaul@chromium.org>
+Fixes: 25fdd5933e4c (drm/msm: Add SDM845 DPU support)
+Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
+Signed-off-by: Stephen Boyd <swboyd@chromium.org>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+index 7dd6bd2d6d37..74cc204b07e8 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+@@ -450,7 +450,7 @@ static void _dpu_kms_initialize_dsi(struct drm_device *dev,
+ int i, rc;
+
+ /*TODO: Support two independent DSI connectors */
+- encoder = dpu_encoder_init(dev, DRM_MODE_CONNECTOR_DSI);
++ encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
+ if (IS_ERR_OR_NULL(encoder)) {
+ DPU_ERROR("encoder init failed for dsi display\n");
+ return;
+--
+2.20.1
+
diff --git a/patches.drm/0045-drm-msm-gpu-fix-parameters-in-function-msm_gpu_crash.patch b/patches.drm/0045-drm-msm-gpu-fix-parameters-in-function-msm_gpu_crash.patch
new file mode 100644
index 0000000000..0f7c884176
--- /dev/null
+++ b/patches.drm/0045-drm-msm-gpu-fix-parameters-in-function-msm_gpu_crash.patch
@@ -0,0 +1,55 @@
+From 6969019f65b43afb6da6a26f1d9e55bbdfeebcd5 Mon Sep 17 00:00:00 2001
+From: Anders Roxell <anders.roxell@linaro.org>
+Date: Tue, 31 Jul 2018 22:45:32 +0200
+Subject: drm/msm/gpu: fix parameters in function msm_gpu_crashstate_capture
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 6969019f65b43afb6da6a26f1d9e55bbdfeebcd5
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+When CONFIG_DEV_COREDUMP isn't defined msm_gpu_crashstate_capture
+doesn't pass the correct parameters.
+drivers/gpu/drm/msm/msm_gpu.c: In function ‘recover_worker’:
+drivers/gpu/drm/msm/msm_gpu.c:479:34: error: passing argument 2 of ‘msm_gpu_crashstate_capture’ from incompatible pointer type [-Werror=incompatible-pointer-types]
+ msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
+ ^~~~~~
+drivers/gpu/drm/msm/msm_gpu.c:388:13: note: expected ‘char *’ but argument is of type ‘struct msm_gem_submit *’
+ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/msm/msm_gpu.c:479:2: error: too many arguments to function ‘msm_gpu_crashstate_capture’
+ msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/msm/msm_gpu.c:388:13: note: declared here
+ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
+
+In current code the function msm_gpu_crashstate_capture parameters.
+
+Fixes: cdb95931dea3 ("drm/msm/gpu: Add the buffer objects from the submit to the crash dump")
+Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
+Reviewed-By: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/msm/msm_gpu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
+index 5e808cfec345..46e6b82f7b66 100644
+--- a/drivers/gpu/drm/msm/msm_gpu.c
++++ b/drivers/gpu/drm/msm/msm_gpu.c
+@@ -367,8 +367,8 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
+ msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
+ }
+ #else
+-static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
+- char *cmd)
++static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
++ struct msm_gem_submit *submit, char *comm, char *cmd)
+ {
+ }
+ #endif
+--
+2.20.1
+
diff --git a/patches.drm/0046-drm-msm-fix-unsigned-comparison-with-less-than-zero.patch b/patches.drm/0046-drm-msm-fix-unsigned-comparison-with-less-than-zero.patch
new file mode 100644
index 0000000000..04687f0cef
--- /dev/null
+++ b/patches.drm/0046-drm-msm-fix-unsigned-comparison-with-less-than-zero.patch
@@ -0,0 +1,40 @@
+From dfdb3be43ef1195c491e6c3760b922acb52e3575 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Tue, 21 Aug 2018 12:55:19 +0100
+Subject: drm/msm: fix unsigned comparison with less than zero
+Git-commit: dfdb3be43ef1195c491e6c3760b922acb52e3575
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+The return from the call to _mixer_stages can be a negative error
+code however this is being assigned to an unsigned variable 'stages'
+hence the check is always false. Fix this by making 'stages' an
+int.
+
+Detected by Coccinelle ("Unsigned expression compared with zero:
+stages < 0")
+
+Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+index b394a1818c5d..eec1051f2afc 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+@@ -297,7 +297,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
+ u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
+ u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
+ int i, j;
+- u8 stages;
++ int stages;
+ int pipes_per_stage;
+
+ stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
+--
+2.20.1
+
diff --git a/patches.drm/0047-drm-nouveau-secboot-acr-fix-memory-leak.patch b/patches.drm/0047-drm-nouveau-secboot-acr-fix-memory-leak.patch
new file mode 100644
index 0000000000..f8fb6be6c3
--- /dev/null
+++ b/patches.drm/0047-drm-nouveau-secboot-acr-fix-memory-leak.patch
@@ -0,0 +1,37 @@
+From 74a07c0a59fa372b069d879971ba4d9e341979cf Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <gustavo@embeddedor.com>
+Date: Tue, 24 Jul 2018 08:27:19 -0500
+Subject: drm/nouveau/secboot/acr: fix memory leak
+Git-commit: 74a07c0a59fa372b069d879971ba4d9e341979cf
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+In case memory resources for *bl_desc* were allocated, release
+them before return.
+
+Addresses-Coverity-ID: 1472021 ("Resource leak")
+Fixes: 0d466901552a ("drm/nouveau/secboot/acr: Remove VLA usage")
+Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
+Reviewed-by: John Hubbard <jhubbard@nvidia.com>
+Reviewed-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c
+index d02e183717dc..5c14d6ac855d 100644
+--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c
++++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c
+@@ -801,6 +801,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon,
+ bl = acr->hsbl_unload_blob;
+ } else {
+ nvkm_error(_acr->subdev, "invalid secure boot blob!\n");
++ kfree(bl_desc);
+ return -EINVAL;
+ }
+
+--
+2.20.1
+
diff --git a/patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch b/patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch
new file mode 100644
index 0000000000..87af075a19
--- /dev/null
+++ b/patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch
@@ -0,0 +1,50 @@
+From 0b4bf7ca9be824dde6ff63dd2ceba2d1367f8a58 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 11 Oct 2018 11:37:48 +0100
+Subject: drm/i915/selftests: Disable shrinker across mmap-exhaustion
+Git-commit: 0b4bf7ca9be824dde6ff63dd2ceba2d1367f8a58
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+For mmap-exhaustion, we deliberately put the system under a large amount
+of pressure to ensure that we are able to reap mmap-offsets from dead
+objects. If background activity does that reaping for us, that defeats
+the purpose of the test and in some cases will fail our sanity checks
+(because of the fake activity we use to prevent the idle worker).
+
+Fixes: 932cac10c8fb ("drm/i915/selftests: Prevent background reaping of acti
+ve objects")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Matthew Auld <matthew.auld@intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181011103748.18387-1-chris@chris-wilson.co.uk
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/selftests/i915_gem_object.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+index 6d3516d5bff9..c3999dd2021e 100644
+--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
++++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+@@ -501,6 +501,8 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
+
+ static void disable_retire_worker(struct drm_i915_private *i915)
+ {
++ i915_gem_shrinker_unregister(i915);
++
+ mutex_lock(&i915->drm.struct_mutex);
+ if (!i915->gt.active_requests++) {
+ intel_runtime_pm_get(i915);
+@@ -613,6 +615,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
+ else
+ queue_delayed_work(i915->wq, &i915->gt.idle_work, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
++ i915_gem_shrinker_register(i915);
+ return err;
+ err_obj:
+ i915_gem_object_put(obj);
+--
+2.20.1
+
diff --git a/patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch b/patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
new file mode 100644
index 0000000000..60e47fe5c1
--- /dev/null
+++ b/patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
@@ -0,0 +1,75 @@
+From 34c2c4f632f232ed2fdb66d4e42cc72d322273fe Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 28 Sep 2018 16:21:23 -0700
+Subject: drm/v3d: Fix a use-after-free race accessing the scheduler's fences.
+Git-commit: 34c2c4f632f232ed2fdb66d4e42cc72d322273fe
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Once we push the job, the scheduler could run it and free it. So, if
+we want to reference their fences, we need to grab them before then.
+I haven't seen this happen in many days of conformance test runtime,
+but let's still close the race.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
+Link: https://patchwork.freedesktop.org/patch/254119/
+Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/v3d/v3d_drv.h | 5 +++++
+ drivers/gpu/drm/v3d/v3d_gem.c | 8 ++++++--
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/v3d/v3d_drv.h
++++ b/drivers/gpu/drm/v3d/v3d_drv.h
+@@ -197,6 +197,11 @@ struct v3d_exec_info {
+ */
+ struct dma_fence *bin_done_fence;
+
++ /* Fence for when the scheduler considers the render to be
++ * done, for when the BOs reservations should be complete.
++ */
++ struct dma_fence *render_done_fence;
++
+ struct kref refcount;
+
+ /* This is the array of BOs that were looked up at the start of exec. */
+--- a/drivers/gpu/drm/v3d/v3d_gem.c
++++ b/drivers/gpu/drm/v3d/v3d_gem.c
+@@ -209,7 +209,7 @@ v3d_flush_caches(struct v3d_dev *v3d)
+ static void
+ v3d_attach_object_fences(struct v3d_exec_info *exec)
+ {
+- struct dma_fence *out_fence = &exec->render.base.s_fence->finished;
++ struct dma_fence *out_fence = exec->render_done_fence;
+ struct v3d_bo *bo;
+ int i;
+
+@@ -409,6 +409,7 @@ v3d_exec_cleanup(struct kref *ref)
+ dma_fence_put(exec->render.done_fence);
+
+ dma_fence_put(exec->bin_done_fence);
++ dma_fence_put(exec->render_done_fence);
+
+ for (i = 0; i < exec->bo_count; i++)
+ drm_gem_object_put_unlocked(&exec->bo[i]->base);
+@@ -572,6 +573,9 @@ v3d_submit_cl_ioctl(struct drm_device *d
+ if (ret)
+ goto fail_unreserve;
+
++ exec->render_done_fence =
++ dma_fence_get(&exec->render.base.s_fence->finished);
++
+ kref_get(&exec->refcount); /* put by scheduler job completion */
+ drm_sched_entity_push_job(&exec->render.base,
+ &v3d_priv->sched_entity[V3D_RENDER]);
+@@ -585,7 +589,7 @@ v3d_submit_cl_ioctl(struct drm_device *d
+ sync_out = drm_syncobj_find(file_priv, args->out_sync);
+ if (sync_out) {
+ drm_syncobj_replace_fence(sync_out,
+- &exec->render.base.s_fence->finished);
++ exec->render_done_fence);
+ drm_syncobj_put(sync_out);
+ }
+
diff --git a/patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch b/patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
new file mode 100644
index 0000000000..347b999e39
--- /dev/null
+++ b/patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
@@ -0,0 +1,45 @@
+From 2f20fa8d12e859a03f68bdd81d75830141bc9ac9 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 28 Sep 2018 16:21:26 -0700
+Subject: drm/v3d: Skip debugfs dumping GCA on platforms without GCA.
+Git-commit: 2f20fa8d12e859a03f68bdd81d75830141bc9ac9
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Fixes an oops reading this debugfs entry on BCM7278.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180928232126.4332-4-eric@anholt.net
+Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
+Cc: <stable@vger.kernel.org>
+Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/v3d/v3d_debugfs.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c
+index d48008adb085..eb2b2d2f8553 100644
+--- a/drivers/gpu/drm/v3d/v3d_debugfs.c
++++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
+@@ -71,10 +71,13 @@ static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
+ V3D_READ(v3d_hub_reg_defs[i].reg));
+ }
+
+- for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
+- seq_printf(m, "%s (0x%04x): 0x%08x\n",
+- v3d_gca_reg_defs[i].name, v3d_gca_reg_defs[i].reg,
+- V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
++ if (v3d->ver < 41) {
++ for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
++ seq_printf(m, "%s (0x%04x): 0x%08x\n",
++ v3d_gca_reg_defs[i].name,
++ v3d_gca_reg_defs[i].reg,
++ V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
++ }
+ }
+
+ for (core = 0; core < v3d->cores; core++) {
+--
+2.20.1
+
diff --git a/patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch b/patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch
new file mode 100644
index 0000000000..87f626840b
--- /dev/null
+++ b/patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch
@@ -0,0 +1,42 @@
+From 61cdfb9e194d2a327eef301e8fc80b63e3e1dc7a Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Wed, 17 Oct 2018 14:56:52 -0700
+Subject: drm/i915/icl: Fix signal_levels
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 61cdfb9e194d2a327eef301e8fc80b63e3e1dc7a
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Since when it was introduced we forgot to add
+this case so ICL was using a wrong signal_levels
+as reference.
+
+Fixes: fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI")
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181017215652.26841-1-rodrigo.vivi@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 1f098e509143..3384a9bbdafd 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -3790,7 +3790,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
+ uint32_t signal_levels, mask = 0;
+ uint8_t train_set = intel_dp->train_set[0];
+
+- if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
++ if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
+ signal_levels = bxt_signal_levels(intel_dp);
+ } else if (HAS_DDI(dev_priv)) {
+ signal_levels = ddi_signal_levels(intel_dp);
+--
+2.20.1
+
diff --git a/patches.drm/0056-amd-gpu-Don-t-undefine-READ-and-WRITE.patch b/patches.drm/0056-amd-gpu-Don-t-undefine-READ-and-WRITE.patch
new file mode 100644
index 0000000000..7e93debc03
--- /dev/null
+++ b/patches.drm/0056-amd-gpu-Don-t-undefine-READ-and-WRITE.patch
@@ -0,0 +1,37 @@
+From 1fcb748d187d0c7732a75a509e924ead6d070e04 Mon Sep 17 00:00:00 2001
+From: David Howells <dhowells@redhat.com>
+Date: Wed, 24 Oct 2018 00:36:12 +0100
+Subject: amd-gpu: Don't undefine READ and WRITE
+Git-commit: 1fcb748d187d0c7732a75a509e924ead6d070e04
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Remove the undefinition of READ and WRITE because these constants may be
+used elsewhere in subsequently included header files, thus breaking them.
+
+These constants don't actually appear to be used in the driver, so the
+undefinition seems pointless.
+
+Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
+Signed-off-by: David Howells <dhowells@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/amd/display/dc/os_types.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
+index a407892905af..c0d9f332baed 100644
+--- a/drivers/gpu/drm/amd/display/dc/os_types.h
++++ b/drivers/gpu/drm/amd/display/dc/os_types.h
+@@ -40,8 +40,6 @@
+ #define LITTLEENDIAN_CPU
+ #endif
+
+-#undef READ
+-#undef WRITE
+ #undef FRAME_SIZE
+
+ #define dm_output_to_console(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
+--
+2.20.1
+
diff --git a/patches.drm/0057-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_.patch b/patches.drm/0057-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_.patch
new file mode 100644
index 0000000000..9301942aba
--- /dev/null
+++ b/patches.drm/0057-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_.patch
@@ -0,0 +1,68 @@
+From 49af5d95b9b3c21a84ad115a9db9acbc036d849a Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Thu, 27 Sep 2018 13:57:30 -0700
+Subject: drm/i915/dp: Fix link retraining comment in intel_dp_long_pulse()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 49af5d95b9b3c21a84ad115a9db9acbc036d849a
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Comment claims link needs to be retrained because the connected sink raised
+a long pulse to indicate link loss. If the sink did so,
+intel_dp_hotplug() would have handled link retraining. Looking at the
+logs in Bugzilla referenced in commit '3cf71bc9904d ("drm/i915: Re-apply
+Perform link quality check, unconditionally during long pulse"")', the
+issue is that the sink does not trigger an interrupt. What we want is
+->detect() from user space to check link status and retrain. Ville's
+review for the original patch also indicates the same root cause. So,
+rewrite the comment.
+
+v2: Patch split and rewrote comment.
+
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Jan-Marek Glogowski <glogow@fbihome.de>
+References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180927205735.16651-1-dhinakaran.pandiyan@intel.com
+(cherry picked from commit 9ebd8202393dde9d3678c9ec162c1aa63ba17eac)
+Fixes: 399334708b4f ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Cc: stable@vger.kernel.org
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 13 +++----------
+ 1 file changed, 3 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 3fae4dab295f..e2a1af0a3492 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -5104,16 +5104,9 @@ intel_dp_long_pulse(struct intel_connector *connector,
+ goto out;
+ } else {
+ /*
+- * If display is now connected check links status,
+- * there has been known issues of link loss triggering
+- * long pulse.
+- *
+- * Some sinks (eg. ASUS PB287Q) seem to perform some
+- * weird HPD ping pong during modesets. So we can apparently
+- * end up with HPD going low during a modeset, and then
+- * going back up soon after. And once that happens we must
+- * retrain the link to get a picture. That's in case no
+- * userspace component reacted to intermittent HPD dip.
++ * Some external monitors do not signal loss of link
++ * synchronization with an IRQ_HPD, so force a link status
++ * check.
+ */
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+
+--
+2.20.1
+
diff --git a/patches.drm/0058-drm-i915-dp-Restrict-link-retrain-workaround-to-exte.patch b/patches.drm/0058-drm-i915-dp-Restrict-link-retrain-workaround-to-exte.patch
new file mode 100644
index 0000000000..b6df17e746
--- /dev/null
+++ b/patches.drm/0058-drm-i915-dp-Restrict-link-retrain-workaround-to-exte.patch
@@ -0,0 +1,63 @@
+From f9776280c29e77a18cbc7ebb6d48f7885e494990 Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Thu, 27 Sep 2018 13:57:31 -0700
+Subject: drm/i915/dp: Restrict link retrain workaround to external monitors
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: f9776280c29e77a18cbc7ebb6d48f7885e494990
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
+unconditionally during long pulse"")' applies a work around for sinks
+that don't signal link loss. The work around does not need to have to be
+that broad as the issue was seen with only one particular monitor; limit
+this only for external displays as eDP features like PSR turn off the link
+and the driver ends up retraining the link seeeing that link is not
+synchronized.
+
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Jan-Marek Glogowski <glogow@fbihome.de>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180927205735.16651-2-dhinakaran.pandiyan@intel.com
+(cherry picked from commit f24f6eb95807bca0dbd8dc5b2f3a4099000f4472)
+Fixes: 399334708b4f ("drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"")
+Cc: stable@vger.kernel.org
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index e2a1af0a3492..13f9b56a9ce7 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -5102,12 +5102,13 @@ intel_dp_long_pulse(struct intel_connector *connector,
+ */
+ status = connector_status_disconnected;
+ goto out;
+- } else {
+- /*
+- * Some external monitors do not signal loss of link
+- * synchronization with an IRQ_HPD, so force a link status
+- * check.
+- */
++ }
++
++ /*
++ * Some external monitors do not signal loss of link synchronization
++ * with an IRQ_HPD, so force a link status check.
++ */
++ if (!intel_dp_is_edp(intel_dp)) {
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+
+ intel_dp_retrain_link(encoder, ctx);
+--
+2.20.1
+
diff --git a/patches.drm/0059-drm-sun4i-hdmi-Fix-double-flag-assignation.patch b/patches.drm/0059-drm-sun4i-hdmi-Fix-double-flag-assignation.patch
new file mode 100644
index 0000000000..f838878c23
--- /dev/null
+++ b/patches.drm/0059-drm-sun4i-hdmi-Fix-double-flag-assignation.patch
@@ -0,0 +1,41 @@
+From 1e0ff648940e603cab6c52cf3723017d30d78f30 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@bootlin.com>
+Date: Sun, 21 Oct 2018 18:34:46 +0200
+Subject: drm/sun4i: hdmi: Fix double flag assignation
+Git-commit: 1e0ff648940e603cab6c52cf3723017d30d78f30
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+The is_double flag is a boolean currently assigned to the value of the d
+variable, that is either 1 or 2. It means that this is_double variable is
+always set to true, even though the initial intent was to have it set to
+true when d is 2.
+
+Fix this.
+
+Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Reviewed-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181021163446.29135-2-maxime.ripard@bootlin.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+index cd2348554bac..fb985ba1a176 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+@@ -52,7 +52,7 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
+ (rate - tmp_rate) < (rate - best_rate)) {
+ best_rate = tmp_rate;
+ best_m = m;
+- is_double = d;
++ is_double = (d == 2) ? true : false;
+ }
+ }
+ }
+--
+2.20.1
+
diff --git a/patches.drm/0060-drm-panel-simple-Innolux-TV123WAM-is-actually-P120ZD.patch b/patches.drm/0060-drm-panel-simple-Innolux-TV123WAM-is-actually-P120ZD.patch
new file mode 100644
index 0000000000..382e9ab976
--- /dev/null
+++ b/patches.drm/0060-drm-panel-simple-Innolux-TV123WAM-is-actually-P120ZD.patch
@@ -0,0 +1,92 @@
+From 8f054b6f53ff34fb787bde4c5940f86a9c175177 Mon Sep 17 00:00:00 2001
+From: Douglas Anderson <dianders@chromium.org>
+Date: Thu, 25 Oct 2018 15:21:34 -0700
+Subject: drm/panel: simple: Innolux TV123WAM is actually P120ZDG-BF1
+Git-commit: 8f054b6f53ff34fb787bde4c5940f86a9c175177
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+As far as I can tell the panel that was added in commit da50bd4258db
+("drm/panel: simple: Add Innolux TV123WAM panel driver support")
+wasn't actually an Innolux TV123WAM but was actually an Innolux
+P120ZDG-BF1.
+
+As far as I can tell the Innolux TV123WAM isn't a real panel and but
+it's a mosh between the TI TV123WAM and the Innolux P120ZDG-BF1.
+Let's unmosh.
+
+Here's my evidence:
+
+* Searching for TV123WAM on the Internet turns up a TI panel. While
+ it's possible that an Innolux panel has the same model number as the
+ TI Panel, it seems a little doubtful. Looking up the datasheet from
+ the TI Panel shows that it's 1920 x 1280 and 259.2 mm x 172.8 mm.
+
+* As far as I know, the patch adding the Innolux Panel was supposed to
+ be for the board that's sitting in front of me as I type this
+ (support for that board is not yet upstream). On the back of that
+ panel I see Innolux P120ZDZ-EZ1 rev B1.
+
+* Someone pointed me at a datasheet that's supposed to be for the
+ panel in front of me (sorry, I can't share the datasheet). That
+ datasheet has the string "p120zdg-bf1"
+
+* If I search for "P120ZDG-BF1" on the Internet I get hits for panels
+ that are 2160x1440. They don't have datasheets, but the fact that
+ the resolution matches is a good sign.
+
+In any case, let's update the name and also the physical size to match
+the correct panel.
+
+Fixes: da50bd4258db ("drm/panel: simple: Add Innolux TV123WAM panel driver support")
+Cc: Sandeep Panda <spanda@codeaurora.org>
+Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
+Reviewed-by: Sean Paul <sean@poorly.run>
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181025222134.174583-6-dianders@chromium.org
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/panel/panel-simple.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/panel/panel-simple.c
++++ b/drivers/gpu/drm/panel/panel-simple.c
+@@ -1363,7 +1363,7 @@ static const struct panel_desc innolux_n
+ },
+ };
+
+-static const struct drm_display_mode innolux_tv123wam_mode = {
++static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
+ .clock = 206016,
+ .hdisplay = 2160,
+ .hsync_start = 2160 + 48,
+@@ -1377,13 +1377,13 @@ static const struct drm_display_mode inn
+ .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ };
+
+-static const struct panel_desc innolux_tv123wam = {
+- .modes = &innolux_tv123wam_mode,
++static const struct panel_desc innolux_p120zdg_bf1 = {
++ .modes = &innolux_p120zdg_bf1_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+- .width = 259,
+- .height = 173,
++ .width = 254,
++ .height = 169,
+ },
+ .delay = {
+ .unprepare = 500,
+@@ -2445,8 +2445,8 @@ static const struct of_device_id platfor
+ .compatible = "innolux,n156bge-l21",
+ .data = &innolux_n156bge_l21,
+ }, {
+- .compatible = "innolux,tv123wam",
+- .data = &innolux_tv123wam,
++ .compatible = "innolux,p120zdg-bf1",
++ .data = &innolux_p120zdg_bf1,
+ }, {
+ .compatible = "innolux,zj070na-01p",
+ .data = &innolux_zj070na_01p,
diff --git a/patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch b/patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch
new file mode 100644
index 0000000000..6d34c7e5ec
--- /dev/null
+++ b/patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch
@@ -0,0 +1,50 @@
+From 09209662618f9fdc38b8d4da39040c8829fd2d57 Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Fri, 5 Oct 2018 11:56:42 -0700
+Subject: drm/i915: Fix VIDEO_DIP_CTL bit shifts
+Git-commit: 09209662618f9fdc38b8d4da39040c8829fd2d57
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
+definitions are unused.
+
+v2: Moves definitions in another patch (Manasi)
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Fixes: 7af2be6d54d4 ("drm/i915/icl: Add VIDEO_DIP registers")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-1-dhinakaran.pandiyan@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index 934722693477..11b273f159c1 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -4573,12 +4573,12 @@ enum {
+
+ #define DRM_DIP_ENABLE (1 << 28)
+ #define PSR_VSC_BIT_7_SET (1 << 27)
+-#define VSC_SELECT_MASK (0x3 << 26)
+-#define VSC_SELECT_SHIFT 26
+-#define VSC_DIP_HW_HEA_DATA (0 << 26)
+-#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
+-#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
+-#define VSC_DIP_SW_HEA_DATA (3 << 26)
++#define VSC_SELECT_MASK (0x3 << 25)
++#define VSC_SELECT_SHIFT 25
++#define VSC_DIP_HW_HEA_DATA (0 << 25)
++#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
++#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
++#define VSC_DIP_SW_HEA_DATA (3 << 25)
+ #define VDIP_ENABLE_PPS (1 << 24)
+
+ /* Panel power sequencing */
+--
+2.20.1
+
diff --git a/patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch b/patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch
new file mode 100644
index 0000000000..d303da43d6
--- /dev/null
+++ b/patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch
@@ -0,0 +1,42 @@
+From 3b90946fcb6f13b65888c380461793a9dea9d1f4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Mon, 29 Oct 2018 16:00:31 +0200
+Subject: drm/i915: Fix error handling for the NV12 fb dimensions check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 3b90946fcb6f13b65888c380461793a9dea9d1f4
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Let's not leak obj->framebuffer_references when we decide that
+the framebuffer domensions are not suitable for NV12.
+
+Cc: stable@vger.kernel.org
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Cc: Vidya Srinivas <vidya.srinivas@intel.com>
+Fixes: e44134f2673c ("drm/i915: Add NV12 support to intel_framebuffer_init")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181029140031.11765-1-ville.syrjala@linux.intel.com
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_display.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 5f0436b8e544..3ea715f1c711 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -14544,7 +14544,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
+ fb->height < SKL_MIN_YUV_420_SRC_H ||
+ (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+ DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
+- return -EINVAL;
++ goto err;
+ }
+
+ for (i = 0; i < fb->format->num_planes; i++) {
+--
+2.20.1
+
diff --git a/patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch b/patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch
new file mode 100644
index 0000000000..55b35e895b
--- /dev/null
+++ b/patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch
@@ -0,0 +1,49 @@
+From b4335ec0a3ee6229a570755f8fb95dc8a7c694f2 Mon Sep 17 00:00:00 2001
+From: Manasi Navare <manasi.d.navare@intel.com>
+Date: Tue, 23 Oct 2018 12:12:47 -0700
+Subject: drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: b4335ec0a3ee6229a570755f8fb95dc8a7c694f2
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+This patch fixes the macros used for defining the DFLEXDPMLE
+register bit fields. This accounts for changes in the spec.
+
+Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
+Cc: Animesh Manna <animesh.manna@intel.com>
+Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Cc: Jose Roberto de Souza <jose.souza@intel.com>
+Cc: <stable@vger.kernel.org> # v4.19+
+Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181023191248.26418-1-manasi.d.navare@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index 55d32ca2051b..6f2e6233f4f5 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -2059,8 +2059,12 @@ enum i915_power_well_id {
+
+ /* ICL PHY DFLEX registers */
+ #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+-#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
+-#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
++#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
++#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
++#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
++#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
++#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
++#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
+
+ /* BXT PHY Ref registers */
+ #define _PORT_REF_DW3_A 0x16218C
+--
+2.20.1
+
diff --git a/patches.drm/0064-drm-etnaviv-fix-bogus-fence-complete-check-in-timeou.patch b/patches.drm/0064-drm-etnaviv-fix-bogus-fence-complete-check-in-timeou.patch
new file mode 100644
index 0000000000..74baa38751
--- /dev/null
+++ b/patches.drm/0064-drm-etnaviv-fix-bogus-fence-complete-check-in-timeou.patch
@@ -0,0 +1,36 @@
+From 6fce3a406108ee6c8a61e2a33e52e9198a626ea0 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Thu, 4 Oct 2018 11:37:00 +0200
+Subject: drm/etnaviv: fix bogus fence complete check in timeout handler
+Git-commit: 6fce3a406108ee6c8a61e2a33e52e9198a626ea0
+Patch-mainline: v4.20-rc2
+References: bsc#1113956
+
+The GPU hardware fences and the job out-fences are on different timelines
+so it's wrong to compare them. Fix this by only looking at the out-fence.
+
+Cc: <stable@vger.kernel.org>
+Fixes: 2c83a726d6fb (drm/etnaviv: bring back progress check in job
+ timeout handler)
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/etnaviv/etnaviv_sched.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+index 69e9b431bf1f..e5a9fae31ab7 100644
+--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
++++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+@@ -93,7 +93,7 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
+ * If the GPU managed to complete this jobs fence, the timout is
+ * spurious. Bail out.
+ */
+- if (fence_completed(gpu, submit->out_fence->seqno))
++ if (dma_fence_is_signaled(submit->out_fence))
+ return;
+
+ /*
+--
+2.20.1
+
diff --git a/patches.drm/0065-uapi-fix-linux-kfd_ioctl.h-userspace-compilation-err.patch b/patches.drm/0065-uapi-fix-linux-kfd_ioctl.h-userspace-compilation-err.patch
new file mode 100644
index 0000000000..6b40a11faf
--- /dev/null
+++ b/patches.drm/0065-uapi-fix-linux-kfd_ioctl.h-userspace-compilation-err.patch
@@ -0,0 +1,52 @@
+From aba118389a6fb2ad7958de0f37b5869852bd38cf Mon Sep 17 00:00:00 2001
+From: "Dmitry V. Levin" <ldv@altlinux.org>
+Date: Thu, 1 Nov 2018 14:03:08 +0300
+Subject: uapi: fix linux/kfd_ioctl.h userspace compilation errors
+Git-commit: aba118389a6fb2ad7958de0f37b5869852bd38cf
+Patch-mainline: v4.20-rc2
+References: bsc#1113956
+
+Consistently use types provided by <linux/types.h> via <drm/drm.h>
+to fix the following linux/kfd_ioctl.h userspace compilation errors:
+
+/usr/include/linux/kfd_ioctl.h:250:2: error: unknown type name 'uint32_t'
+ uint32_t reset_type;
+/usr/include/linux/kfd_ioctl.h:251:2: error: unknown type name 'uint32_t'
+ uint32_t reset_cause;
+/usr/include/linux/kfd_ioctl.h:252:2: error: unknown type name 'uint32_t'
+ uint32_t memory_lost;
+/usr/include/linux/kfd_ioctl.h:253:2: error: unknown type name 'uint32_t'
+ uint32_t gpu_id;
+
+Fixes: 0c119abad7f0d ("drm/amd: Add kfd ioctl defines for hw_exception event")
+Cc: <stable@vger.kernel.org> # v4.19
+Signed-off-by: Dmitry V. Levin <ldv@altlinux.org>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ include/uapi/linux/kfd_ioctl.h | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index f5ff8a76e208..dae897f38e59 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -255,10 +255,10 @@ struct kfd_hsa_memory_exception_data {
+
+ /* hw exception data */
+ struct kfd_hsa_hw_exception_data {
+- uint32_t reset_type;
+- uint32_t reset_cause;
+- uint32_t memory_lost;
+- uint32_t gpu_id;
++ __u32 reset_type;
++ __u32 reset_cause;
++ __u32 memory_lost;
++ __u32 gpu_id;
+ };
+
+ /* Event data */
+--
+2.20.1
+
diff --git a/patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch b/patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch
new file mode 100644
index 0000000000..e6f4bfb6fe
--- /dev/null
+++ b/patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch
@@ -0,0 +1,141 @@
+From 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 8 Nov 2018 22:04:24 +0200
+Subject: drm/i915: Fix hpd handling for pins with two encoders
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 5a3aeca97af1b6b3498d59a7fd4e8bb95814c108
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+In my haste to remove irq_port[] I accidentally changed the
+way we deal with hpd pins that are shared by multiple encoders
+(DP and HDMI for pre-DDI platforms). Previously we would only
+handle such pins via ->hpd_pulse(), but now we queue up the
+hotplug work for the HDMI encoder directly. Worse yet, we now
+count each hpd twice and this increment the hpd storm count
+twice as fast. This can lead to spurious storms being detected.
+
+Go back to the old way of doing things, ie. delegate to
+->hpd_pulse() for any pin which has an encoder with that hook
+implemented. I don't really like the idea of adding irq_port[]
+back so let's loop through the encoders first to check if we
+have an encoder with ->hpd_pulse() for the pin, and then go
+through all the pins and decided on the correct course of action
+based on the earlier findings.
+
+I have occasionally toyed with the idea of unifying the pre-DDI
+HDMI and DP encoders into a single encoder as well. Besides the
+hotplug processing it would have the other benefit of preventing
+userspace from trying to enable both encoders at the same time.
+That is simply illegal as they share the same clock/data pins.
+We have some testcases that will attempt that and thus fail on
+many older machines. But for now let's stick to fixing just the
+hotplug code.
+
+Cc: stable@vger.kernel.org # 4.19+
+Cc: Lyude Paul <lyude@redhat.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Fixes: b6ca3eee18ba ("drm/i915: Nuke dev_priv->irq_port[]")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181108200424.28371-1-ville.syrjala@linux.intel.com
+Reviewed-by: Lyude Paul <lyude@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_hotplug.c | 63 ++++++++++++++++++++++++-----------
+ 1 file changed, 44 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_hotplug.c
++++ b/drivers/gpu/drm/i915/intel_hotplug.c
+@@ -395,37 +395,54 @@ void intel_hpd_irq_handler(struct drm_i9
+ struct intel_encoder *encoder;
+ bool storm_detected = false;
+ bool queue_dig = false, queue_hp = false;
++ u32 long_hpd_pulse_mask = 0;
++ u32 short_hpd_pulse_mask = 0;
++ enum hpd_pin pin;
+
+ if (!pin_mask)
+ return;
+
+ spin_lock(&dev_priv->irq_lock);
++
++ /*
++ * Determine whether ->hpd_pulse() exists for each pin, and
++ * whether we have a short or a long pulse. This is needed
++ * as each pin may have up to two encoders (HDMI and DP) and
++ * only the one of them (DP) will have ->hpd_pulse().
++ */
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+- enum hpd_pin pin = encoder->hpd_pin;
+ bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
++ enum port port = encoder->port;
++ bool long_hpd;
+
++ pin = encoder->hpd_pin;
+ if (!(BIT(pin) & pin_mask))
+ continue;
+
+- if (has_hpd_pulse) {
+- bool long_hpd = long_mask & BIT(pin);
+- enum port port = encoder->port;
++ if (!has_hpd_pulse)
++ continue;
+
+- DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
+- long_hpd ? "long" : "short");
+- /*
+- * For long HPD pulses we want to have the digital queue happen,
+- * but we still want HPD storm detection to function.
+- */
+- queue_dig = true;
+- if (long_hpd) {
+- dev_priv->hotplug.long_port_mask |= (1 << port);
+- } else {
+- /* for short HPD just trigger the digital queue */
+- dev_priv->hotplug.short_port_mask |= (1 << port);
+- continue;
+- }
++ long_hpd = long_mask & BIT(pin);
++
++ DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
++ long_hpd ? "long" : "short");
++ queue_dig = true;
++
++ if (long_hpd) {
++ long_hpd_pulse_mask |= BIT(pin);
++ dev_priv->hotplug.long_port_mask |= BIT(port);
++ } else {
++ short_hpd_pulse_mask |= BIT(pin);
++ dev_priv->hotplug.short_port_mask |= BIT(port);
+ }
++ }
++
++ /* Now process each pin just once */
++ for_each_hpd_pin(pin) {
++ bool long_hpd;
++
++ if (!(BIT(pin) & pin_mask))
++ continue;
+
+ if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
+ /*
+@@ -442,8 +459,16 @@ void intel_hpd_irq_handler(struct drm_i9
+ if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
+ continue;
+
+- if (!has_hpd_pulse) {
++ /*
++ * Delegate to ->hpd_pulse() if one of the encoders for this
++ * pin has it, otherwise let the hotplug_work deal with this
++ * pin directly.
++ */
++ if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
++ long_hpd = long_hpd_pulse_mask & BIT(pin);
++ } else {
+ dev_priv->hotplug.event_bits |= BIT(pin);
++ long_hpd = true;
+ queue_hp = true;
+ }
+
diff --git a/patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch b/patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch
new file mode 100644
index 0000000000..6b7bf8d62c
--- /dev/null
+++ b/patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch
@@ -0,0 +1,37 @@
+From 63ac3328f0d1d37f286e397b14d9596ed09d7ca5 Mon Sep 17 00:00:00 2001
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Date: Mon, 12 Nov 2018 12:39:31 +0000
+Subject: drm/i915: fix broadwell EU computation
+Git-commit: 63ac3328f0d1d37f286e397b14d9596ed09d7ca5
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+subslice_mask is an array indexed by slice, not subslice.
+
+Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Fixes: 8cc7669355136f ("drm/i915: store all subslice masks")
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108712
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181112123931.2815-1-lionel.g.landwerlin@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_device_info.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
+index 89ed3a84a4fa..ceecb5bd5226 100644
+--- a/drivers/gpu/drm/i915/intel_device_info.c
++++ b/drivers/gpu/drm/i915/intel_device_info.c
+@@ -474,7 +474,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
+ u8 eu_disabled_mask;
+ u32 n_disabled;
+
+- if (!(sseu->subslice_mask[ss] & BIT(ss)))
++ if (!(sseu->subslice_mask[s] & BIT(ss)))
+ /* skip disabled subslice */
+ continue;
+
+--
+2.20.1
+
diff --git a/patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch b/patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch
new file mode 100644
index 0000000000..48ac08c36a
--- /dev/null
+++ b/patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch
@@ -0,0 +1,48 @@
+From 8577c319b6511fbc391f3775225fecd8b979bc26 Mon Sep 17 00:00:00 2001
+From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Date: Fri, 9 Nov 2018 16:09:23 +0200
+Subject: drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update
+Git-commit: 8577c319b6511fbc391f3775225fecd8b979bc26
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Register DBUF_CTL_S2 is read and it's value is not used. As
+there is no explanation why we should prime the hardware with
+read, remove it as spurious.
+
+Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
+Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Reviewed-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181109140924.2663-1-mika.kuoppala@linux.intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
+index f945db6ea420..770de2632530 100644
+--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
++++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
+@@ -3236,8 +3236,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ u8 req_slices)
+ {
+- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+- u32 val;
++ const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ bool ret;
+
+ if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+@@ -3248,7 +3247,6 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ if (req_slices == hw_enabled_slices || req_slices == 0)
+ return;
+
+- val = I915_READ(DBUF_CTL_S2);
+ if (req_slices > hw_enabled_slices)
+ ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
+ else
+--
+2.20.1
+
diff --git a/patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch b/patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch
new file mode 100644
index 0000000000..ed9e93369b
--- /dev/null
+++ b/patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch
@@ -0,0 +1,47 @@
+From fcc86cb45d38ca2f24bcea9c29c7f4742041caed Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 15 Nov 2018 11:58:52 +0100
+Subject: drm/vc4: Set ->legacy_cursor_update to false when doing non-async
+ updates
+Git-commit: fcc86cb45d38ca2f24bcea9c29c7f4742041caed
+Patch-mainline: v4.20-rc4
+References: bsc#1113956
+
+drm_atomic_helper_setup_commit() auto-completes commit->flip_done when
+state->legacy_cursor_update is true, but we know for sure that we want
+a sync update when we call drm_atomic_helper_setup_commit() from
+vc4_atomic_commit().
+
+Explicitly set state->legacy_cursor_update to false to prevent this
+auto-completion.
+
+Fixes: 184d3cf4f738 ("drm/vc4: Use wait_for_flip_done() instead of wait_for_vblanks()")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181115105852.9844-2-boris.brezillon@bootlin.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/vc4/vc4_kms.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
+index 127468785f74..1f94b9affe4b 100644
+--- a/drivers/gpu/drm/vc4/vc4_kms.c
++++ b/drivers/gpu/drm/vc4/vc4_kms.c
+@@ -214,6 +214,12 @@ static int vc4_atomic_commit(struct drm_device *dev,
+ return 0;
+ }
+
++ /* We know for sure we don't want an async update here. Set
++ * state->legacy_cursor_update to false to prevent
++ * drm_atomic_helper_setup_commit() from auto-completing
++ * commit->flip_done.
++ */
++ state->legacy_cursor_update = false;
+ ret = drm_atomic_helper_setup_commit(state, nonblock);
+ if (ret)
+ return ret;
+--
+2.20.1
+
diff --git a/patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch b/patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch
new file mode 100644
index 0000000000..4025fbcf7c
--- /dev/null
+++ b/patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch
@@ -0,0 +1,40 @@
+From 8d4d7c58994759bbd9f4fec32d88bf0e0b89302e Mon Sep 17 00:00:00 2001
+From: Takashi Iwai <tiwai@suse.de>
+Date: Mon, 19 Nov 2018 12:55:12 +0100
+Subject: drm/amdgpu: Add missing firmware entry for HAINAN
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 8d4d7c58994759bbd9f4fec32d88bf0e0b89302e
+Patch-mainline: v4.20-rc4
+References: bsc#1113956
+
+Due to lack of MODULE_FIRMWARE() with hainan_mc.bin, the driver
+doesn't work properly in initrd. Let's add it.
+
+Bugzilla: https://bugzilla.suse.com/show_bug.cgi?id=1116239
+Fixes: 8eaf2b1faaf4 ("drm/amdgpu: switch firmware path for SI parts")
+Cc: <stable@vger.kernel.org>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index e1c2b4e9c7b2..73ad02aea2b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
+ MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
+ MODULE_FIRMWARE("amdgpu/verde_mc.bin");
+ MODULE_FIRMWARE("amdgpu/oland_mc.bin");
++MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
+ MODULE_FIRMWARE("amdgpu/si58_mc.bin");
+
+ #define MC_SEQ_MISC0__MT__MASK 0xf0000000
+--
+2.20.1
+
diff --git a/patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch b/patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch
new file mode 100644
index 0000000000..51815fe63e
--- /dev/null
+++ b/patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch
@@ -0,0 +1,53 @@
+From 8fd3b90300bec541806dac271de2fd44e2e4e2d2 Mon Sep 17 00:00:00 2001
+From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+Date: Thu, 15 Nov 2018 17:32:48 +0100
+Subject: drm/fb-helper: Blacklist writeback when adding connectors to fbdev
+Git-commit: 8fd3b90300bec541806dac271de2fd44e2e4e2d2
+Patch-mainline: v4.20-rc4
+References: bsc#1113956
+
+Writeback connectors do not produce any on-screen output and require
+special care for use. Such connectors are hidden from enumeration in
+DRM resources by default, but they are still picked-up by fbdev.
+This makes rather little sense since fbdev is not really adapted for
+dealing with writeback.
+
+Moreover, this is also a source of issues when userspace disables the
+CRTC (and associated plane) without detaching the CRTC from the
+connector (which is hidden by default). In this case, the connector is
+still using the CRTC, leading to am "enabled/connectors mismatch" and
+eventually the failure of the associated atomic commit. This situation
+happens with VC4 testing under IGT GPU Tools.
+
+Filter out writeback connectors in the fbdev helper to solve this.
+
+Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Fixes: 935774cd71fe ("drm: Add writeback connector type")
+Cc: <stable@vger.kernel.org> # v4.19+
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181115163248.21168-1-paul.kocialkowski@bootlin.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/drm_fb_helper.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
+index a502f3e519fd..dd852a25d375 100644
+--- a/drivers/gpu/drm/drm_fb_helper.c
++++ b/drivers/gpu/drm/drm_fb_helper.c
+@@ -219,6 +219,9 @@ int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper *fb_helper)
+ mutex_lock(&fb_helper->lock);
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
++ if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
++ continue;
++
+ ret = __drm_fb_helper_add_one_connector(fb_helper, connector);
+ if (ret)
+ goto fail;
+--
+2.20.1
+
diff --git a/patches.drm/0085-drm-msm-gpu-Fix-a-couple-memory-leaks-in-debugfs.patch b/patches.drm/0085-drm-msm-gpu-Fix-a-couple-memory-leaks-in-debugfs.patch
new file mode 100644
index 0000000000..062db64b3b
--- /dev/null
+++ b/patches.drm/0085-drm-msm-gpu-Fix-a-couple-memory-leaks-in-debugfs.patch
@@ -0,0 +1,60 @@
+From 51270de91412b819f654b849db3bf92dac0a0855 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Sat, 13 Oct 2018 13:28:06 +0300
+Subject: drm/msm/gpu: Fix a couple memory leaks in debugfs
+Git-commit: 51270de91412b819f654b849db3bf92dac0a0855
+Patch-mainline: v4.20-rc6
+References: bsc#1113956
+
+The msm_gpu_open() function should free "show_priv" on error or it
+causes static checker warnings.
+
+Fixes: 4f776f4511c7 ("drm/msm/gpu: Convert the GPU show function to use the GPU state")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/msm/msm_debugfs.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c
+index f0da0d3c8a80..d756436c1fcd 100644
+--- a/drivers/gpu/drm/msm/msm_debugfs.c
++++ b/drivers/gpu/drm/msm/msm_debugfs.c
+@@ -84,7 +84,7 @@ static int msm_gpu_open(struct inode *inode, struct file *file)
+
+ ret = mutex_lock_interruptible(&dev->struct_mutex);
+ if (ret)
+- return ret;
++ goto free_priv;
+
+ pm_runtime_get_sync(&gpu->pdev->dev);
+ show_priv->state = gpu->funcs->gpu_state_get(gpu);
+@@ -94,13 +94,20 @@ static int msm_gpu_open(struct inode *inode, struct file *file)
+
+ if (IS_ERR(show_priv->state)) {
+ ret = PTR_ERR(show_priv->state);
+- kfree(show_priv);
+- return ret;
++ goto free_priv;
+ }
+
+ show_priv->dev = dev;
+
+- return single_open(file, msm_gpu_show, show_priv);
++ ret = single_open(file, msm_gpu_show, show_priv);
++ if (ret)
++ goto free_priv;
++
++ return 0;
++
++free_priv:
++ kfree(show_priv);
++ return ret;
+ }
+
+ static const struct file_operations msm_gpu_fops = {
+--
+2.20.1
+
diff --git a/patches.drm/0086-drm-msm-fix-handling-of-cmdstream-offset.patch b/patches.drm/0086-drm-msm-fix-handling-of-cmdstream-offset.patch
new file mode 100644
index 0000000000..fdf401122d
--- /dev/null
+++ b/patches.drm/0086-drm-msm-fix-handling-of-cmdstream-offset.patch
@@ -0,0 +1,52 @@
+From 47e7f506ee6590ceb2efa1f08aca7f9f2ee5c1d3 Mon Sep 17 00:00:00 2001
+From: Rob Clark <robdclark@gmail.com>
+Date: Mon, 15 Oct 2018 11:22:57 -0400
+Subject: drm/msm: fix handling of cmdstream offset
+Git-commit: 47e7f506ee6590ceb2efa1f08aca7f9f2ee5c1d3
+Patch-mainline: v4.20-rc6
+References: bsc#1113956
+
+Userspace hasn't used submit cmds with submit_offset != 0 for a while,
+but this starts cropping up again with cmdstream sub-buffer-allocation
+in libdrm_freedreno.
+
+Doesn't do much good to increment the buf ptr before assigning it.
+
+Fixes: 78b8e5b847b4 drm/msm: dump a rd GPUADDR header for all buffers in the command
+Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/msm/msm_rd.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
+index cca933458439..0c2c8d2c631f 100644
+--- a/drivers/gpu/drm/msm/msm_rd.c
++++ b/drivers/gpu/drm/msm/msm_rd.c
+@@ -316,10 +316,11 @@ static void snapshot_buf(struct msm_rd_state *rd,
+ uint64_t iova, uint32_t size)
+ {
+ struct msm_gem_object *obj = submit->bos[idx].obj;
++ unsigned offset = 0;
+ const char *buf;
+
+ if (iova) {
+- buf += iova - submit->bos[idx].iova;
++ offset = iova - submit->bos[idx].iova;
+ } else {
+ iova = submit->bos[idx].iova;
+ size = obj->base.size;
+@@ -340,6 +341,8 @@ static void snapshot_buf(struct msm_rd_state *rd,
+ if (IS_ERR(buf))
+ return;
+
++ buf += offset;
++
+ rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
+
+ msm_gem_put_vaddr(&obj->base);
+--
+2.20.1
+
diff --git a/patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch b/patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch
new file mode 100644
index 0000000000..71e53a14e3
--- /dev/null
+++ b/patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch
@@ -0,0 +1,39 @@
+From 62d1a752874962f072de8a779e960fcd2ab4847b Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 28 Nov 2018 15:09:27 -0800
+Subject: drm/v3d: Fix prime imports of buffers from other drivers.
+Git-commit: 62d1a752874962f072de8a779e960fcd2ab4847b
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+v3d_bo_get_pages() checks this to decide to map the imported buffer
+instead of the backing shmem file. The caller was about to set this
+value anyway, and there's no error path in between. Ideally we
+wouldn't even allocate the shmem file for our imports, but that's a
+more invasive fix.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
+Link: https://patchwork.freedesktop.org/patch/msgid/20181128230927.10951-3-eric@anholt.net
+Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Reviewed-by: Dave Emett <david.emett@broadcom.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/v3d/v3d_bo.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/v3d/v3d_bo.c b/drivers/gpu/drm/v3d/v3d_bo.c
+index 54d96518a131..a08766d39eab 100644
+--- a/drivers/gpu/drm/v3d/v3d_bo.c
++++ b/drivers/gpu/drm/v3d/v3d_bo.c
+@@ -293,6 +293,7 @@ v3d_prime_import_sg_table(struct drm_device *dev,
+ bo->resv = attach->dmabuf->resv;
+
+ bo->sgt = sgt;
++ obj->import_attach = attach;
+ v3d_bo_get_pages(bo);
+
+ v3d_mmu_insert_ptes(bo);
+--
+2.20.1
+
diff --git a/series.conf b/series.conf
index 9e300ec2f8..e0d92b0236 100644
--- a/series.conf
+++ b/series.conf
@@ -41150,7 +41150,11 @@
patches.drm/0001-drm-hisilicon-hibmc-Do-not-carry-error-code-in-HiBMC.patch
patches.drm/0001-drm-hisilicon-hibmc-Don-t-overwrite-fb-helper-surfac.patch
patches.drm/drm-omap-fix-memory-barrier-bug-in-DMM-driver.patch
+ patches.drm/0044-drm-msm-disp-dpu-Use-proper-define-for-drm_encoder_i.patch
+ patches.drm/0045-drm-msm-gpu-fix-parameters-in-function-msm_gpu_crash.patch
+ patches.drm/0046-drm-msm-fix-unsigned-comparison-with-less-than-zero.patch
patches.drm/drm-nouveau-Check-backlight-IDs-are-0-not-0.patch
+ patches.drm/0047-drm-nouveau-secboot-acr-fix-memory-leak.patch
patches.drm/0001-drm-amdgpu-powerplay-fix-missing-break-in-switch-sta.patch
patches.drm/drm-i915-Restore-vblank-interrupts-earlier.patch
patches.drm/drm-i915-Don-t-unset-intel_connector-mst_port.patch
@@ -41426,11 +41430,15 @@
patches.suse/net-stmmac-Fix-stmmac_mdio_reset-when-building-stmma.patch
patches.suse/openvswitch-Fix-push-pop-ethernet-validation.patch
patches.drivers/vhost-scsi-truncate-T10-PI-iov_iter-to-prot_bytes.patch
+ patches.drm/0056-amd-gpu-Don-t-undefine-READ-and-WRITE.patch
patches.arch/powerpc-pseries-Export-maximum-memory-value.patch
patches.apparmor/apparmor-dont-try-to-replace-stale-label-in-ptrace-access-check.patch
patches.apparmor/apparmor-dont-try-to-replace-stale-label-in-ptraceme-check.patch
patches.apparmor/apparmor-Fix-uninitialized-value-in-aa_split_fqname.patch
patches.drm/drm-edid-Add-6-bpc-quirk-for-BOE-panel.patch
+ patches.drm/0060-drm-panel-simple-Innolux-TV123WAM-is-actually-P120ZD.patch
+ patches.drm/0057-drm-i915-dp-Fix-link-retraining-comment-in-intel_dp_.patch
+ patches.drm/0058-drm-i915-dp-Restrict-link-retrain-workaround-to-exte.patch
patches.drivers/ALSA-ca0106-Disable-IZD-on-SB0570-DAC-to-fix-audio-p.patch
patches.drivers/edac-skx_edac-add-address-translation-for-non-volatile-dimms.patch
patches.drivers/edac-skx-fix-randconfig-builds.patch
@@ -41499,11 +41507,13 @@
patches.fixes/mount-Retest-MNT_LOCKED-in-do_umount.patch
patches.fixes/mount-Don-t-allow-copying-MNT_UNBINDABLE-MNT_LOCKED-.patch
patches.fixes/mount-Prevent-MNT_DETACH-from-disconnecting-locked-m.patch
+ patches.drm/0064-drm-etnaviv-fix-bogus-fence-complete-check-in-timeou.patch
patches.drm/drm-i915-hdmi-Add-HDMI-2.0-audio-clock-recovery-N-va.patch
patches.drm/drm-i915-glk-Remove-99-limitation.patch
patches.drm/drm-i915-Mark-pin-flags-as-u64.patch
patches.drm/drm-i915-Don-t-oops-during-modeset-shutdown-after-lp.patch
patches.drm/drm-i915-Fix-ilk-watermarks-when-disabling-pipes.patch
+ patches.drm/0065-uapi-fix-linux-kfd_ioctl.h-userspace-compilation-err.patch
patches.drivers/termios-tty-tty_baudrate.c-fix-buffer-overrun.patch
patches.drivers/watchdog-core-add-missing-prototypes-for-weak-functions.patch
patches.drivers/clockevents-drivers-i8253-Add-support-for-PIT-shutdo.patch
@@ -41643,6 +41653,9 @@
patches.drm/drm-ast-remove-existing-framebuffers-before-loading-driver.patch
patches.drm/drm-ast-change-resolution-may-cause-screen-blurred.patch
patches.drm/drm-ast-fixed-cursor-may-disappear-sometimes.patch
+ patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch
+ patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch
+ patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch
patches.drm/drm-i915-Write-GPU-relocs-harder-with-gen3.patch
patches.drivers/gpio-don-t-free-unallocated-ida-on-gpiochip_add_data.patch
patches.fixes/tools-power-cpupower-fix-compilation-with-static-true.patch
@@ -41875,6 +41888,8 @@
patches.drivers/ALSA-hda-realtek-Add-support-for-Acer-Aspire-C24-860.patch
patches.drivers/ALSA-hda-realtek-Fix-mic-issue-on-Acer-AIO-Veriton-Z.patch
patches.drivers/ALSA-hda-realtek-Fix-mic-issue-on-Acer-AIO-Veriton-2.patch
+ patches.drm/0085-drm-msm-gpu-Fix-a-couple-memory-leaks-in-debugfs.patch
+ patches.drm/0086-drm-msm-fix-handling-of-cmdstream-offset.patch
patches.drm/0001-drm-amdgpu-update-mc-firmware-image-for-polaris12-va.patch
patches.drm/0001-drm-amdgpu-gmc8-update-MC-firmware-for-polaris.patch
patches.drivers/i2c-axxia-properly-handle-master-timeout.patch
@@ -41968,8 +41983,11 @@
patches.drivers/IB-mlx5-Fix-implicit-ODP-interrupted-page-fault.patch
patches.drivers/IB-mlx5-Block-DEVX-umem-from-the-non-applicable-case.patch
patches.drivers/IB-core-Fix-oops-in-netdev_next_upper_dev_rcu.patch
+ patches.drm/0003-drm-i915-Record-GT-workarounds-in-a-list.patch
+ patches.drm/0004-drm-i915-Introduce-per-engine-workarounds.patch
patches.drm/0001-drm-i915-execlists-Apply-a-full-mb-before-execution-.patch
patches.drm/0001-drm-amdgpu-update-SMC-firmware-image-for-polaris10-v.patch
+ patches.drm/0005-drm-nouveau-kms-nv50-also-flush-fb-writes-when-rewin.patch
patches.drm/0001-drm-nouveau-kms-Fix-memory-leak-in-nv50_mstm_del.patch
patches.arch/powerpc-boot-Fix-build-failures-with-j-1.patch
patches.arch/powerpc-papr_scm-Use-depend-instead-of-select.patch
@@ -42067,12 +42085,26 @@
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Introduce-IOAPIC-.patch
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Allow-to-have-sam.patch
patches.drivers/0001-ACPI-scan-Create-platform-device-for-INT3515-ACPI-no.patch
+ patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
+ patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
patches.drm/0001-drm-rockchip-psr-do-not-dereference-encoder-before-i.patch
patches.drm/0001-drm-vc4-Set-is_yuv-to-false-when-num_planes-1.patch
+ patches.drm/0059-drm-sun4i-hdmi-Fix-double-flag-assignation.patch
patches.drm/0001-drm-vc4-x_scaling-1-should-never-be-set-to-VC4_SCALI.patch
+ patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch
+ patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch
+ patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch
+ patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch
+ patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch
+ patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch
patches.drivers/ALSA-x86-Fix-runtime-PM-for-hdmi-lpe-audio.patch
+ patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch
+ patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch
+ patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch
patches.drm/0001-drm-rcar-du-Fix-vblank-initialization.patch
patches.drm/0001-drm-rcar-du-Fix-external-clock-error-checks.patch
+ patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
+ patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch
patches.drivers/ALSA-usb-audio-Define-registers-for-CM6206.patch
patches.drivers/ALSA-hda-ca0132-Optimize-for-non-PCI-configuration.patch
patches.drivers/ALSA-control-Consolidate-helpers-for-adding-and-repl.patch