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authorPetr Tesarik <ptesarik@suse.cz>2019-07-19 22:19:02 +0200
committerPetr Tesarik <ptesarik@suse.cz>2019-07-19 22:44:47 +0200
commit91e59e7ef7e72ad99c1e174f3844984936340c5a (patch)
treecd97f19fab0a8b6790a83022b334bb491a77a299
parenta5ef41ae75cb5239946a468c0eb738bbf18f3b09 (diff)
s390/cpu_mf: add store cpu counter multiple instruction support
(jsc#SLE-6904 FATE#327581).
-rw-r--r--patches.suse/s390-cpu_mf-add-store-cpu-counter-multiple-instruction-support80
-rw-r--r--series.conf1
2 files changed, 81 insertions, 0 deletions
diff --git a/patches.suse/s390-cpu_mf-add-store-cpu-counter-multiple-instruction-support b/patches.suse/s390-cpu_mf-add-store-cpu-counter-multiple-instruction-support
new file mode 100644
index 0000000000..bd8ea5e281
--- /dev/null
+++ b/patches.suse/s390-cpu_mf-add-store-cpu-counter-multiple-instruction-support
@@ -0,0 +1,80 @@
+From: Hendrik Brueckner <brueckner@linux.ibm.com>
+Date: Wed, 29 Aug 2018 17:46:06 +0200
+Subject: s390/cpu_mf: add store cpu counter multiple instruction support
+Git-commit: 778fb10ccc18b16c022be898d8497767c20ea7b5
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-6904 FATE#327581
+
+Add support for the STORE CPU COUNTER MULTIPLE instruction to extract
+a range of counters from a counter set.
+
+An assembler macro is used to create the instruction opcode because
+the counter set identifier is part of the instruction and, thus,
+cannot be easily specified as parameter.
+
+Signed-off-by: Hendrik Brueckner <brueckner@linux.ibm.com>
+Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ arch/s390/include/asm/cpu_mf-insn.h | 22 ++++++++++++++++++++++
+ arch/s390/include/asm/cpu_mf.h | 17 +++++++++++++++++
+ 2 files changed, 39 insertions(+)
+
+--- /dev/null
++++ b/arch/s390/include/asm/cpu_mf-insn.h
+@@ -0,0 +1,22 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Support for CPU-MF instructions
++ *
++ * Copyright IBM Corp. 2019
++ * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
++ */
++#ifndef _ASM_S390_CPU_MF_INSN_H
++#define _ASM_S390_CPU_MF_INSN_H
++
++#ifdef __ASSEMBLY__
++
++/* Macro to generate the STCCTM instruction with a customized
++ * M3 field designating the counter set.
++ */
++.macro STCCTM r1 m3 db2
++ .insn rsy,0xeb0000000017,\r1,\m3 & 0xf,\db2
++.endm
++
++#endif /* __ASSEMBLY__ */
++
++#endif
+--- a/arch/s390/include/asm/cpu_mf.h
++++ b/arch/s390/include/asm/cpu_mf.h
+@@ -15,6 +15,8 @@
+ #include <linux/errno.h>
+ #include <asm/facility.h>
+
++asm(".include \"asm/cpu_mf-insn.h\"\n");
++
+ #define CPU_MF_INT_SF_IAE (1 << 31) /* invalid entry address */
+ #define CPU_MF_INT_SF_ISE (1 << 30) /* incorrect SDBT entry */
+ #define CPU_MF_INT_SF_PRA (1 << 29) /* program request alert */
+@@ -200,6 +202,21 @@ static inline int ecctr(u64 ctr, u64 *va
+ return cc;
+ }
+
++/* Store CPU counter multiple for a particular counter set */
++static inline int stcctm(u8 set, u64 range, u64 *dest)
++{
++ int cc;
++
++ asm volatile (
++ " STCCTM %2,%3,%1\n"
++ " ipm %0\n"
++ " srl %0,28\n"
++ : "=d" (cc)
++ : "Q" (*dest), "d" (range), "i" (set)
++ : "cc", "memory");
++ return cc;
++}
++
+ /* Store CPU counter multiple for the MT utilization counter set */
+ static inline int stcctm5(u64 num, u64 *val)
+ {
diff --git a/series.conf b/series.conf
index 35ad2a6f85..51bf9a41dd 100644
--- a/series.conf
+++ b/series.conf
@@ -45471,6 +45471,7 @@
patches.suse/s390-cpu_mf-move-struct-cpu_cf_events-and-per-cpu-variable-to-header-file
patches.suse/s390-cpum_cf-introduce-kernel_cpumcf_alert-to-obtain-measurement-alerts
patches.suse/s390-cpum_cf-add-minimal-in-kernel-interface-for-counter-measurements
+ patches.suse/s390-cpu_mf-add-store-cpu-counter-multiple-instruction-support
patches.fixes/0001-s390-vfio_ap-link-the-vfio_ap-devices-to-the-vfio_ap.patch
patches.drivers/clocksource-drivers-sun5i-Fail-gracefully-when-clock.patch
patches.drivers/clocksource-drivers-exynos_mct-Move-one-shot-check-f.patch