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authorPetr Tesarik <ptesarik@suse.cz>2019-01-18 18:35:32 +0100
committerPetr Tesarik <ptesarik@suse.cz>2019-01-18 18:35:32 +0100
commita810c3c0e6628cd93782f23f2a46cad43f5c2786 (patch)
tree7ff052a1f8f64c05df70167c666770d7e4dc6b87
parent48781811101feed3714a54d7f492b0fea910bfc4 (diff)
parente5e69d586163b9946454438e37f45cd34b3e884f (diff)
Merge branch 'users/tzimmermann/SLE15-SP1/for-next' into SLE15-SP1
Pull DRM fixes from Thomas Zimmermann
-rw-r--r--blacklist.conf6
-rw-r--r--patches.drm/0001-drm-amd-display-Support-amdgpu-max-bpc-connector-pro.patch104
-rw-r--r--patches.drm/0001-drm-amdgpu-Add-amdgpu-max-bpc-connector-property-v2.patch74
-rw-r--r--patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch89
-rw-r--r--patches.drm/0001-drm-i915-icl-Fix-power-well-2-wrt.-DC-off-toggling-o.patch55
-rw-r--r--patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch126
-rw-r--r--series.conf5
7 files changed, 453 insertions, 6 deletions
diff --git a/blacklist.conf b/blacklist.conf
index e9767a763c..c9d8ef2152 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -904,12 +904,6 @@ a22612301ae61d78a7c0c82dc556931a35db0e91 # Duplicate of 5a3aeca97af1b6b3498d59a7
cedde71cc61bdf5e2f386f06bada29fe9fe11b78 # Duplicate of 07e3a1cfb0568b6d8d7862077029af96af6690ea
4a15c75c42460252a63d30f03b4766a52945fb47 # Duplicate of 90098efacc4c3e2e4f6262a657d6b520ecfb2555
-# temporarily blacklisted for the DRM backport
-bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
-a33e1ece777996ddddb1f23a30f8c66422ed0b68
-07e3a1cfb0568b6d8d7862077029af96af6690ea
-f1f90e254e46e0a14220e4090041f68256fbe297
-
bb8c13d61a629276a162c1d2b1a20a815cbcfbb7 # deprecated late loading method
a5321aec6412b20b5ad15db2d6b916c05349dbff # ditto
07d981ad4cf1e78361c6db1c28ee5ba105f96cc1 # ditto
diff --git a/patches.drm/0001-drm-amd-display-Support-amdgpu-max-bpc-connector-pro.patch b/patches.drm/0001-drm-amd-display-Support-amdgpu-max-bpc-connector-pro.patch
new file mode 100644
index 0000000000..ad307d5975
--- /dev/null
+++ b/patches.drm/0001-drm-amd-display-Support-amdgpu-max-bpc-connector-pro.patch
@@ -0,0 +1,104 @@
+From 07e3a1cfb0568b6d8d7862077029af96af6690ea Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 15 Nov 2018 17:21:34 -0500
+Subject: drm/amd/display: Support amdgpu "max bpc" connector property (v2)
+Git-commit: 07e3a1cfb0568b6d8d7862077029af96af6690ea
+Patch-mainline: v4.20-rc4
+References: bsc#1113956
+
+[Why]
+Many panels support more than 8bpc but some modes are unavailable while
+running at greater than 8bpc due to DP/HDMI bandwidth constraints.
+
+Support for more than 8bpc was added recently in the driver but it
+defaults to the maximum supported bpc - locking out these modes.
+
+This should be a user configurable option such that the user can select
+what bpc configuration they would like.
+
+[How]
+This patch adds support for getting and setting the amdgpu driver
+specific "max bpc" property on the connector.
+
+It also adds support for limiting the output bpc based on the property
+value. The default limitation is the lowest value in the range, 8bpc.
+This was the old value before the range was uncapped.
+
+This patch should be updated/replaced later once common drm support
+for max bpc lands.
+
+Bugzilla: https://bugs.freedesktop.org/108542
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201585
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=200645
+Fixes: e03fd3f300f6 ("drm/amd/display: Do not limit color depth to 8bpc")
+
+v2: rebase on upstream (Alex)
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
+ 2 files changed, 17 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2213,8 +2213,15 @@ static void update_stream_scaling_settin
+ static enum dc_color_depth
+ convert_color_depth_from_display_info(const struct drm_connector *connector)
+ {
++ struct dm_connector_state *dm_conn_state =
++ to_dm_connector_state(connector->state);
+ uint32_t bpc = connector->display_info.bpc;
+
++ /* TODO: Remove this when there's support for max_bpc in drm */
++ if (dm_conn_state && bpc > dm_conn_state->max_bpc)
++ /* Round down to nearest even number. */
++ bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
++
+ switch (bpc) {
+ case 0:
+ /* Temporary Work around, DRM don't parse color depth for
+@@ -2796,6 +2803,9 @@ int amdgpu_dm_connector_atomic_set_prope
+ } else if (property == adev->mode_info.underscan_property) {
+ dm_new_state->underscan_enable = val;
+ ret = 0;
++ } else if (property == adev->mode_info.max_bpc_property) {
++ dm_new_state->max_bpc = val;
++ ret = 0;
+ }
+
+ return ret;
+@@ -2838,6 +2848,9 @@ int amdgpu_dm_connector_atomic_get_prope
+ } else if (property == adev->mode_info.underscan_property) {
+ *val = dm_state->underscan_enable;
+ ret = 0;
++ } else if (property == adev->mode_info.max_bpc_property) {
++ *val = dm_state->max_bpc;
++ ret = 0;
+ }
+ return ret;
+ }
+@@ -3658,6 +3671,9 @@ void amdgpu_dm_connector_init_helper(str
+ drm_object_attach_property(&aconnector->base.base,
+ adev->mode_info.underscan_vborder_property,
+ 0);
++ drm_object_attach_property(&aconnector->base.base,
++ adev->mode_info.max_bpc_property,
++ 0);
+
+ }
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -215,6 +215,7 @@ struct dm_connector_state {
+ enum amdgpu_rmx_type scaling;
+ uint8_t underscan_vborder;
+ uint8_t underscan_hborder;
++ uint8_t max_bpc;
+ bool underscan_enable;
+ struct mod_freesync_user_enable user_enable;
+ bool freesync_capable;
diff --git a/patches.drm/0001-drm-amdgpu-Add-amdgpu-max-bpc-connector-property-v2.patch b/patches.drm/0001-drm-amdgpu-Add-amdgpu-max-bpc-connector-property-v2.patch
new file mode 100644
index 0000000000..ce35e5d6a7
--- /dev/null
+++ b/patches.drm/0001-drm-amdgpu-Add-amdgpu-max-bpc-connector-property-v2.patch
@@ -0,0 +1,74 @@
+From e2306cc6a07aefc458982b3d7ae1e146515ed656 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 15 Nov 2018 17:19:12 -0500
+Subject: drm/amdgpu: Add amdgpu "max bpc" connector property (v2)
+Git-commit: e2306cc6a07aefc458982b3d7ae1e146515ed656
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+[Why]
+Many panels support more than 8bpc but some modes are unavailable while
+running at greater than 8bpc due to DP/HDMI bandwidth constraints.
+
+Support for more than 8bpc was added recently in the driver but it
+defaults to the maximum supported bpc - locking out these modes.
+
+This should be a user configurable option such that the user can select
+what bpc configuration they would like.
+
+[How]
+This patch introduces the "max bpc" amdgpu driver specific connector
+property so the user can limit the maximum bpc. It ranges from 8 to 16.
+
+This doesn't directly set the preferred bpc for the panel since it
+follows Intel's existing driver conventions.
+
+This proprety should be removed once common drm support for max bpc
+lands.
+
+v2: rebase on upstream (Alex)
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 7 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 ++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index 6748cd7fc129..686a26de50f9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -626,6 +626,13 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
+ "dither",
+ amdgpu_dither_enum_list, sz);
+
++ if (amdgpu_device_has_dc_support(adev)) {
++ adev->mode_info.max_bpc_property =
++ drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
++ if (!adev->mode_info.max_bpc_property)
++ return -ENOMEM;
++ }
++
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+index 11723d8fffbd..0dc2c5c57015 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+@@ -338,6 +338,8 @@ struct amdgpu_mode_info {
+ struct drm_property *audio_property;
+ /* FMT dithering */
+ struct drm_property *dither_property;
++ /* maximum number of bits per channel for monitor color */
++ struct drm_property *max_bpc_property;
+ /* hardcoded DFP edid from BIOS */
+ struct edid *bios_hardcoded_edid;
+ int bios_hardcoded_edid_size;
+--
+2.20.1
+
diff --git a/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch b/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
new file mode 100644
index 0000000000..fab0813271
--- /dev/null
+++ b/patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
@@ -0,0 +1,89 @@
+From bb1c7edc6d4d5cc6917814d858d47b22d2e93cde Mon Sep 17 00:00:00 2001
+From: Mahesh Kumar <mahesh1.kumar@intel.com>
+Date: Mon, 15 Oct 2018 19:37:52 -0700
+Subject: drm/i915/icl: Fix DDI/TC port clk_off bits
+Git-commit: bb1c7edc6d4d5cc6917814d858d47b22d2e93cde
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
+from offset 12 & TC4 is at offset 21.
+Create a function to choose correct clk-off bit.
+
+v2: Add fixes tag (Lucas)
+
+Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
+Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
+Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181016023752.9285-1-lucas.demarchi@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_reg.h | 3 +++
+ drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
+ 2 files changed, 21 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -9313,6 +9313,9 @@ enum skl_power_gate {
+ #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
+ #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
+ (port) + 10))
++#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
++#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
++ 21 : (tc_port) + 12))
+ #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port) * 2)
+ #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -2535,6 +2535,21 @@ uint32_t ddi_signal_levels(struct intel_
+ return DDI_BUF_TRANS_SELECT(level);
+ }
+
++static inline
++uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
++ enum port port)
++{
++ if (intel_port_is_combophy(dev_priv, port)) {
++ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
++ } else if (intel_port_is_tc(dev_priv, port)) {
++ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
++
++ return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
++ }
++
++ return 0;
++}
++
+ void icl_map_plls_to_ports(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct drm_atomic_state *old_state)
+@@ -2558,7 +2573,7 @@ void icl_map_plls_to_ports(struct drm_cr
+ mutex_lock(&dev_priv->dpll_lock);
+
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+- WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
++ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+
+ if (intel_port_is_combophy(dev_priv, port)) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+@@ -2567,7 +2582,7 @@ void icl_map_plls_to_ports(struct drm_cr
+ POSTING_READ(DPCLKA_CFGCR0_ICL);
+ }
+
+- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
++ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ mutex_unlock(&dev_priv->dpll_lock);
+@@ -2595,7 +2610,7 @@ void icl_unmap_plls_to_ports(struct drm_
+ mutex_lock(&dev_priv->dpll_lock);
+ I915_WRITE(DPCLKA_CFGCR0_ICL,
+ I915_READ(DPCLKA_CFGCR0_ICL) |
+- DPCLKA_CFGCR0_DDI_CLK_OFF(port));
++ icl_dpclka_cfgcr0_clk_off(dev_priv, port));
+ mutex_unlock(&dev_priv->dpll_lock);
+ }
+ }
diff --git a/patches.drm/0001-drm-i915-icl-Fix-power-well-2-wrt.-DC-off-toggling-o.patch b/patches.drm/0001-drm-i915-icl-Fix-power-well-2-wrt.-DC-off-toggling-o.patch
new file mode 100644
index 0000000000..a216b77eab
--- /dev/null
+++ b/patches.drm/0001-drm-i915-icl-Fix-power-well-2-wrt.-DC-off-toggling-o.patch
@@ -0,0 +1,55 @@
+From a33e1ece777996ddddb1f23a30f8c66422ed0b68 Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@intel.com>
+Date: Fri, 2 Nov 2018 20:22:00 +0200
+Subject: drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: a33e1ece777996ddddb1f23a30f8c66422ed0b68
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+To enable DC5/6 power well 2 has to be disabled as for previous
+platforms, so fix things up.
+
+Bspec: 4234
+Fixes: 67ca07e7ac10 ("drm/i915/icl: Add power well support")
+Cc: Animesh Manna <animesh.manna@intel.com>
+Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Imre Deak <imre.deak@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181102182200.17219-1-imre.deak@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
++++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
+@@ -2623,6 +2623,12 @@ static struct i915_power_well icl_power_
+ .hsw.has_fuses = true,
+ },
+ {
++ .name = "DC off",
++ .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
++ .ops = &gen9_dc_off_power_well_ops,
++ .id = SKL_DISP_PW_DC_OFF,
++ },
++ {
+ .name = "power well 2",
+ .domains = ICL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+@@ -2630,12 +2636,6 @@ static struct i915_power_well icl_power_
+ .hsw.has_fuses = true,
+ },
+ {
+- .name = "DC off",
+- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+- .ops = &gen9_dc_off_power_well_ops,
+- .id = SKL_DISP_PW_DC_OFF,
+- },
+- {
+ .name = "power well 3",
+ .domains = ICL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
diff --git a/patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch b/patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch
new file mode 100644
index 0000000000..bfd2669ccc
--- /dev/null
+++ b/patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch
@@ -0,0 +1,126 @@
+From 176597a12d61709727d1639836e5d68a6e7c437b Mon Sep 17 00:00:00 2001
+From: Mahesh Kumar <mahesh1.kumar@intel.com>
+Date: Thu, 4 Oct 2018 14:20:43 +0530
+Subject: drm/i915/icl: create function to identify combophy port
+Git-commit: 176597a12d61709727d1639836e5d68a6e7c437b
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+This patch creates a function/wrapper to check if port is combophy port
+instead of explicitly comparing ports.
+
+Changes since V1:
+ - keep all intel_port_is_* helper together (Lucas)
+
+Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
+Cc: Madhav Chauhan <madhav.chauhan@intel.com>
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181004085043.10154-1-mahesh1.kumar@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_ddi.c | 15 ++++++++-------
+ drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
+ drivers/gpu/drm/i915/intel_drv.h | 1 +
+ 3 files changed, 20 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct d
+ level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
+
+ if (IS_ICELAKE(dev_priv)) {
+- if (port == PORT_A || port == PORT_B)
++ if (intel_port_is_combophy(dev_priv, port))
+ icl_get_combo_buf_trans(dev_priv, port,
+ INTEL_OUTPUT_HDMI, &n_entries);
+ else
+@@ -1460,7 +1460,7 @@ static void icl_ddi_clock_get(struct int
+ uint32_t pll_id;
+
+ pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+- if (port == PORT_A || port == PORT_B) {
++ if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
+ link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ else
+@@ -2158,7 +2158,7 @@ u8 intel_ddi_dp_voltage_max(struct intel
+ int n_entries;
+
+ if (IS_ICELAKE(dev_priv)) {
+- if (port == PORT_A || port == PORT_B)
++ if (intel_port_is_combophy(dev_priv, port))
+ icl_get_combo_buf_trans(dev_priv, port, encoder->type,
+ &n_entries);
+ else
+@@ -2471,9 +2471,10 @@ static void icl_combo_phy_ddi_vswing_seq
+ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
+ enum intel_output_type type)
+ {
++ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+- if (port == PORT_A || port == PORT_B)
++ if (intel_port_is_combophy(dev_priv, port))
+ icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+ else
+ /* Not Implemented Yet */
+@@ -2559,7 +2560,7 @@ void icl_map_plls_to_ports(struct drm_cr
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
+
+- if (port == PORT_A || port == PORT_B) {
++ if (intel_port_is_combophy(dev_priv, port)) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+ val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+@@ -2612,7 +2613,7 @@ static void intel_ddi_clk_select(struct
+ mutex_lock(&dev_priv->dpll_lock);
+
+ if (IS_ICELAKE(dev_priv)) {
+- if (port >= PORT_C)
++ if (!intel_port_is_combophy(dev_priv, port))
+ I915_WRITE(DDI_CLK_SEL(port),
+ icl_pll_to_ddi_pll_sel(encoder, pll));
+ } else if (IS_CANNONLAKE(dev_priv)) {
+@@ -2654,7 +2655,7 @@ static void intel_ddi_clk_disable(struct
+ enum port port = encoder->port;
+
+ if (IS_ICELAKE(dev_priv)) {
+- if (port >= PORT_C)
++ if (!intel_port_is_combophy(dev_priv, port))
+ I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -5899,6 +5899,17 @@ static void i9xx_pfit_enable(struct inte
+ I915_WRITE(BCLRPAT(crtc->pipe), 0);
+ }
+
++bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
++{
++ if (port == PORT_NONE)
++ return false;
++
++ if (IS_ICELAKE(dev_priv))
++ return port <= PORT_B;
++
++ return false;
++}
++
+ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
+ {
+ if (IS_ICELAKE(dev_priv))
+--- a/drivers/gpu/drm/i915/intel_drv.h
++++ b/drivers/gpu/drm/i915/intel_drv.h
+@@ -1507,6 +1507,7 @@ void intel_connector_attach_encoder(stru
+ struct intel_encoder *encoder);
+ struct drm_display_mode *
+ intel_encoder_current_mode(struct intel_encoder *encoder);
++bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
+ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
+ enum port port);
diff --git a/series.conf b/series.conf
index 8f0e7cb12b..9528ede4b0 100644
--- a/series.conf
+++ b/series.conf
@@ -41659,6 +41659,7 @@
patches.drm/drm-ast-fixed-cursor-may-disappear-sometimes.patch
patches.drm/0080-drm-vc4-Set-legacy_cursor_update-to-false-when-doing.patch
patches.drm/0084-drm-fb-helper-Blacklist-writeback-when-adding-connec.patch
+ patches.drm/0001-drm-amd-display-Support-amdgpu-max-bpc-connector-pro.patch
patches.drm/0083-drm-amdgpu-Add-missing-firmware-entry-for-HAINAN.patch
patches.drm/drm-i915-Write-GPU-relocs-harder-with-gen3.patch
patches.drivers/gpio-don-t-free-unallocated-ida-on-gpiochip_add_data.patch
@@ -42103,17 +42104,21 @@
patches.drm/0001-drm-vc4-x_scaling-1-should-never-be-set-to-VC4_SCALI.patch
patches.drm/0043-drm-i915-dp-Do-not-grab-crtc-modeset-lock-in-intel_d.patch
patches.drm/0048-drm-i915-selftests-Disable-shrinker-across-mmap-exha.patch
+ patches.drm/0001-drm-i915-icl-create-function-to-identify-combophy-po.patch
+ patches.drm/0001-drm-i915-icl-Fix-DDI-TC-port-clk_off-bits.patch
patches.drm/0052-drm-i915-icl-Fix-signal_levels.patch
patches.drm/0061-drm-i915-Fix-VIDEO_DIP_CTL-bit-shifts.patch
patches.drm/0062-drm-i915-Fix-error-handling-for-the-NV12-fb-dimensio.patch
patches.drm/0063-drm-i915-icl-Fix-the-macros-for-DFLEXDPMLE-register-.patch
patches.drivers/ALSA-x86-Fix-runtime-PM-for-hdmi-lpe-audio.patch
+ patches.drm/0001-drm-i915-icl-Fix-power-well-2-wrt.-DC-off-toggling-o.patch
patches.drm/0071-drm-i915-Fix-hpd-handling-for-pins-with-two-encoders.patch
patches.drm/0074-drm-i915-fix-broadwell-EU-computation.patch
patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch
patches.drm/0001-drm-rcar-du-Fix-vblank-initialization.patch
patches.drm/0001-drm-rcar-du-Fix-external-clock-error-checks.patch
patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
+ patches.drm/0001-drm-amdgpu-Add-amdgpu-max-bpc-connector-property-v2.patch
patches.drm/0087-drm-v3d-Fix-prime-imports-of-buffers-from-other-driv.patch
patches.drivers/ALSA-usb-audio-Define-registers-for-CM6206.patch
patches.drivers/ALSA-hda-ca0132-Optimize-for-non-PCI-configuration.patch