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authorThomas Zimmermann <tzimmermann@suse.de>2019-01-16 14:02:34 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-01-17 15:28:27 +0100
commite1ae48d883b4605456bafc1892cf4bdcace843e7 (patch)
tree14f445b7cfe3ff7aa7ef240b500877da8660640c
parent61fa2ce5f36bab8ef07c0fdc43965c6714abc172 (diff)
drm/i915/vgpu: Disallow loading on old vGPU hosts (bsc#1113956)
-rw-r--r--patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch151
-rw-r--r--series.conf1
2 files changed, 152 insertions, 0 deletions
diff --git a/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch b/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
new file mode 100644
index 0000000000..c505394948
--- /dev/null
+++ b/patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
@@ -0,0 +1,151 @@
+From 46592892e1a60f9e9de3287719143a148fce93cf Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Fri, 30 Nov 2018 12:59:54 +0000
+Subject: drm/i915/vgpu: Disallow loading on old vGPU hosts
+Git-commit: 46592892e1a60f9e9de3287719143a148fce93cf
+Patch-mainline: v5.0-rc1
+References: bsc#1113956
+
+Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
+actually broke the force-mmio mode for our execlists implementation. No
+one noticed, so ergo no one is actually using an old vGPU host (where we
+required the older method) and so can simply remove the broken support.
+
+v2: csb_read can go as well (Mika)
+
+Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20181130125954.11924-1-chris@chris-wilson.co.uk
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++++
+ drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++------------------------
+ drivers/gpu/drm/i915/intel_ringbuffer.h | 16 ---------------
+ 3 files changed, 23 insertions(+), 41 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -1084,6 +1084,20 @@ static int i915_driver_init_hw(struct dr
+
+ intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
+
++ if (HAS_EXECLISTS(dev_priv)) {
++ /*
++ * Older GVT emulation depends upon intercepting CSB mmio,
++ * which we no longer use, preferring to use the HWSP cache
++ * instead.
++ */
++ if (intel_vgpu_active(dev_priv) &&
++ !intel_vgpu_has_hwsp_emulation(dev_priv)) {
++ i915_report_error(dev_priv,
++ "old vGPU host found, support for HWSP emulation required\n");
++ return -ENXIO;
++ }
++ }
++
+ intel_sanitize_options(dev_priv);
+
+ i915_perf_init(dev_priv);
+--- a/drivers/gpu/drm/i915/intel_lrc.c
++++ b/drivers/gpu/drm/i915/intel_lrc.c
+@@ -825,6 +825,8 @@ execlists_cancel_port_requests(struct in
+
+ static void reset_csb_pointers(struct intel_engine_execlists *execlists)
+ {
++ const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
++
+ /*
+ * After a reset, the HW starts writing into CSB entry [0]. We
+ * therefore have to set our HEAD pointer back one entry so that
+@@ -834,8 +836,8 @@ static void reset_csb_pointers(struct in
+ * inline comparison of our cached head position against the last HW
+ * write works even before the first interrupt.
+ */
+- execlists->csb_head = execlists->csb_write_reset;
+- WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
++ execlists->csb_head = reset_value;
++ WRITE_ONCE(*execlists->csb_write, reset_value);
+ }
+
+ static void nop_submission_tasklet(unsigned long data)
+@@ -2403,12 +2405,6 @@ logical_ring_setup(struct intel_engine_c
+ logical_ring_default_irqs(engine);
+ }
+
+-static bool csb_force_mmio(struct drm_i915_private *i915)
+-{
+- /* Older GVT emulation depends upon intercepting CSB mmio */
+- return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
+-}
+-
+ static int logical_ring_init(struct intel_engine_cs *engine)
+ {
+ struct drm_i915_private *i915 = engine->i915;
+@@ -2438,24 +2434,12 @@ static int logical_ring_init(struct inte
+ upper_32_bits(ce->lrc_desc);
+ }
+
+- execlists->csb_read =
+- i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
+- if (csb_force_mmio(i915)) {
+- execlists->csb_status = (u32 __force *)
+- (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+-
+- execlists->csb_write = (u32 __force *)execlists->csb_read;
+- execlists->csb_write_reset =
+- _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
+- GEN8_CSB_ENTRIES - 1);
+- } else {
+- execlists->csb_status =
+- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
++ execlists->csb_status =
++ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
++
++ execlists->csb_write =
++ &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
+
+- execlists->csb_write =
+- &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
+- execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
+- }
+ reset_csb_pointers(execlists);
+
+ intel_engine_init_workarounds(engine);
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
+@@ -300,13 +300,6 @@ struct intel_engine_execlists {
+ struct rb_root_cached queue;
+
+ /**
+- * @csb_read: control register for Context Switch buffer
+- *
+- * Note this register is always in mmio.
+- */
+- u32 __iomem *csb_read;
+-
+- /**
+ * @csb_write: control register for Context Switch buffer
+ *
+ * Note this register may be either mmio or HWSP shadow.
+@@ -326,15 +319,6 @@ struct intel_engine_execlists {
+ u32 preempt_complete_status;
+
+ /**
+- * @csb_write_reset: reset value for CSB write pointer
+- *
+- * As the CSB write pointer maybe either in HWSP or as a field
+- * inside an mmio register, we want to reprogram it slightly
+- * differently to avoid later confusion.
+- */
+- u32 csb_write_reset;
+-
+- /**
+ * @csb_head: context status buffer head
+ */
+ u8 csb_head;
diff --git a/series.conf b/series.conf
index 393022fe0e..bbb9301ee1 100644
--- a/series.conf
+++ b/series.conf
@@ -42103,6 +42103,7 @@
patches.drm/0076-drm-i915-icl-Drop-spurious-register-read-from-icl_db.patch
patches.drm/0001-drm-rcar-du-Fix-vblank-initialization.patch
patches.drm/0001-drm-rcar-du-Fix-external-clock-error-checks.patch
+ patches.drm/0001-drm-i915-vgpu-Disallow-loading-on-old-vGPU-hosts.patch
patches.drivers/ALSA-usb-audio-Define-registers-for-CM6206.patch
patches.drivers/ALSA-hda-ca0132-Optimize-for-non-PCI-configuration.patch
patches.drivers/ALSA-control-Consolidate-helpers-for-adding-and-repl.patch