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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:04:43 +0200
commit0099650eb94859ece956622130121091fbf8de22 (patch)
treeba57ab8aa614ae0bb89ef3ea779ab44beb72231d
parent74245cb7e924b5472ba2fdc44f9d53968e4c12a6 (diff)
platform/x86: mlx-platform: Add support for fan capability
registers (bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch315
-rw-r--r--series.conf1
2 files changed, 316 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
new file mode 100644
index 0000000000..7aed8cd9d0
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
@@ -0,0 +1,315 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:15 +0000
+Subject: platform/x86: mlx-platform: Add support for fan capability registers
+Patch-mainline: v5.1-rc1
+Git-commit: 83cdb2c11173ee4aa621c8cce6e1c33fb564d2be
+References: bsc#1112374
+
+Provide support for the fan capability registers for the next generation
+systems of types MQM87xx, MSN34xx, MSN37xx. These new registers provide
+configuration for tachometers and fan drawers connectivity. Use these
+registers for next generation led, fan and hotplug structures in order
+to distinguish between the systems which have minor configuration
+differences. This reduces the amount of code used to describe such
+systems.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/mellanox/mlxreg-hotplug.c | 23 +++++++++
+ drivers/platform/x86/mlx-platform.c | 69 +++++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/mellanox/mlxreg-hotplug.c
++++ b/drivers/platform/mellanox/mlxreg-hotplug.c
+@@ -494,7 +494,9 @@ static int mlxreg_hotplug_set_irq(struct
+ {
+ struct mlxreg_core_hotplug_platform_data *pdata;
+ struct mlxreg_core_item *item;
+- int i, ret;
++ struct mlxreg_core_data *data;
++ u32 regval;
++ int i, j, ret;
+
+ pdata = dev_get_platdata(&priv->pdev->dev);
+ item = pdata->items;
+@@ -506,6 +508,25 @@ static int mlxreg_hotplug_set_irq(struct
+ if (ret)
+ goto out;
+
++ /*
++ * Verify if hardware configuration requires to disable
++ * interrupt capability for some of components.
++ */
++ data = item->data;
++ for (j = 0; j < item->count; j++, data++) {
++ /* Verify if the attribute has capability register. */
++ if (data->capability) {
++ /* Read capability register. */
++ ret = regmap_read(priv->regmap,
++ data->capability, &regval);
++ if (ret)
++ goto out;
++
++ if (!(regval & data->bit))
++ item->mask &= ~BIT(j);
++ }
++ }
++
+ /* Set group initial status as mask and unmask group event. */
+ if (item->inversed) {
+ item->cache = item->mask;
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -68,6 +68,9 @@
+ #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
+ #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
+ #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
++#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
+@@ -585,36 +588,48 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan2",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(1),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan3",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(2),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan4",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(3),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan5",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(4),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan6",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(5),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ };
+@@ -817,61 +832,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan1:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan2:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan2:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan3:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan3:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan4:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan4:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan5:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan5:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan6:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "fan6:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ };
+
+@@ -1208,61 +1247,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "tacho1",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho2",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho3",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho4",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "tacho5",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "tacho6",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "tacho7",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(6),
+ },
+ {
+ .label = "tacho8",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(7),
+ },
+ {
+ .label = "tacho9",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho10",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho11",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho12",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(3),
+ },
+ };
+
+@@ -1349,6 +1412,9 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1401,6 +1467,9 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
diff --git a/series.conf b/series.conf
index 5b68a72476..400fdadd12 100644
--- a/series.conf
+++ b/series.conf
@@ -45716,6 +45716,7 @@
patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
+ patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
patches.drivers/platform-x86-intel_pmc_core-Handle-CFL-regmap-proper.patch
patches.drivers/platform-x86-intel_pmc_core-Fix-PCH-IP-sts-reading.patch
patches.drivers/platform-x86-intel_pmc_core-Fix-PCH-IP-name.patch