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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:04:54 +0200
commit24f7cdf5c1f2d97bebf4a09451b9a1df675a2bbd (patch)
tree90f0ec55f448aa4c7c22aa8254128dbf604f42db
parent5f00254254c60b035772fc1a1e72cf4062ac4946 (diff)
platform/x86: mlx-platform: Add extra CPLD for next generation
systems (bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch61
-rw-r--r--series.conf1
2 files changed, 62 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
new file mode 100644
index 0000000000..624e97f80b
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
@@ -0,0 +1,61 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:32 +0000
+Subject: platform/x86: mlx-platform: Add extra CPLD for next generation
+ systems
+Patch-mainline: v5.1-rc1
+Git-commit: eb480b41f2c5eea72bf9a58dd166409e3b0731f3
+References: bsc#1112374
+
+Add support for CPLD4 for the next generation systems MQMB7xx, MSN37xx,
+MSN34xx, MSN38xx.
+
+All these systems are equipped with four programmable device.
+The version of this new device is to be exposed to sysfs through
+mlxreg-io register.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -25,6 +25,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
+ #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
++#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+@@ -1140,6 +1141,12 @@ static struct mlxreg_core_data mlxplat_m
+ .mode = 0444,
+ },
+ {
++ .label = "cpld4_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
+ .label = "reset_long_pb",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+@@ -1369,6 +1376,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+@@ -1426,6 +1434,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
diff --git a/series.conf b/series.conf
index 8404f55013..26fac347dd 100644
--- a/series.conf
+++ b/series.conf
@@ -45729,6 +45729,7 @@
patches.drivers/platform-x86-intel_pmc_core-Add-ICL-platform-support.patch
patches.drivers/platform-x86-intel_pmc_core-Add-Package-cstates-resi.patch
patches.drivers/platform-x86-intel_pmc_core-Quirk-to-ignore-XTAL-shu.patch
+ patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
patches.suse/msft-hv-1855-x86-hyperv-Fix-kernel-panic-when-kexec-on-HyperV.patch
patches.fixes/tools-lib-traceevent-fix-buffer-overflow-in-arg_eval.patch
patches.drivers/tpm-tpm_crb-Avoid-unaligned-reads-in-crb_recv.patch