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authorPetr Tesarik <ptesarik@suse.cz>2019-06-21 21:02:37 +0200
committerPetr Tesarik <ptesarik@suse.cz>2019-06-21 21:02:37 +0200
commit2b8119b142fb27db7a928cd7e54a570098dab11d (patch)
tree47a83660e77b7f1fe0ab2820090d4dd9028fc4a8
parenta1191eae6fac2bef1dd65753c65f1c642d15129d (diff)
parenteebc916691c25fc7c9526c8314cb1a24232e2ec0 (diff)
Merge branch 'users/tbogendoerfer/SLE15-SP1/for-next' into SLE15-SP1
Pull Mellanox driver update from Thomas Bogendoerfer - Refresh patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main Conflicts: series.conf
-rw-r--r--config/arm64/default4
-rw-r--r--patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch31
-rw-r--r--patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch64
-rw-r--r--patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch41
-rw-r--r--patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch1410
-rw-r--r--patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch59
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch196
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch396
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch36
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch54
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch61
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch376
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch270
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch350
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch315
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch59
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch46
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch57
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch151
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch138
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch38
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch57
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch43
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch32
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch32
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch47
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch26
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch49
-rw-r--r--patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch36
-rw-r--r--patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch31
-rw-r--r--patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch63
-rw-r--r--patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main2
-rw-r--r--series.conf30
-rw-r--r--supported.conf1
34 files changed, 4600 insertions, 1 deletions
diff --git a/config/arm64/default b/config/arm64/default
index 4229d329d6..41af0f8f76 100644
--- a/config/arm64/default
+++ b/config/arm64/default
@@ -6385,6 +6385,10 @@ CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC_CHARDEV=m
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
+CONFIG_MELLANOX_PLATFORM=y
+CONFIG_MLXREG_HOTPLUG=m
+CONFIG_MLXREG_IO=m
+CONFIG_MLXBF_TMFIFO=m
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
diff --git a/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch b/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch
new file mode 100644
index 0000000000..10644b7f70
--- /dev/null
+++ b/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch
@@ -0,0 +1,31 @@
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Mon, 1 Apr 2019 10:16:35 +0200
+Subject: drivers: fix a typo in the kernel doc for
+ devm_platform_ioremap_resource()
+Patch-mainline: v5.2-rc1
+Git-commit: 7067c96ee8d2d77039aeb49670acfe160f484ef9
+References: bsc#1136333 jsc#SLE-4994
+
+It should have been 'management' not 'managemend'.
+
+Fixes: 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()")
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
+Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/base/platform.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -84,7 +84,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource)
+ * device
+ *
+ * @pdev: platform device to use both for memory resource lookup as well as
+- * resource managemend
++ * resource management
+ * @index: resource index
+ */
+ void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
diff --git a/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch b/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch
new file mode 100644
index 0000000000..26051d1bab
--- /dev/null
+++ b/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch
@@ -0,0 +1,64 @@
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Wed, 20 Feb 2019 11:12:39 +0000
+Subject: drivers: provide devm_platform_ioremap_resource()
+Patch-mainline: v5.1-rc1
+Git-commit: 7945f929f1a77a1c8887a97ca07f87626858ff42
+References: bsc#1136333 jsc#SLE-4994
+
+There are currently 1200+ instances of using platform_get_resource()
+and devm_ioremap_resource() together in the kernel tree.
+
+This patch wraps these two calls in a single helper. Thanks to that
+we don't have to declare a local variable for struct resource * and can
+omit the redundant argument for resource type. We also have one
+function call less.
+
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/base/platform.c | 18 ++++++++++++++++++
+ include/linux/platform_device.h | 3 +++
+ 2 files changed, 21 insertions(+)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -80,6 +80,24 @@ struct resource *platform_get_resource(s
+ EXPORT_SYMBOL_GPL(platform_get_resource);
+
+ /**
++ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
++ * device
++ *
++ * @pdev: platform device to use both for memory resource lookup as well as
++ * resource managemend
++ * @index: resource index
++ */
++void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
++ unsigned int index)
++{
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
++ return devm_ioremap_resource(&pdev->dev, res);
++}
++EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
++
++/**
+ * platform_get_irq - get an IRQ for a device
+ * @dev: platform device
+ * @num: IRQ number index
+--- a/include/linux/platform_device.h
++++ b/include/linux/platform_device.h
+@@ -51,6 +51,9 @@ extern struct device platform_bus;
+ extern void arch_setup_pdev_archdata(struct platform_device *);
+ extern struct resource *platform_get_resource(struct platform_device *,
+ unsigned int, unsigned int);
++extern void __iomem *
++devm_platform_ioremap_resource(struct platform_device *pdev,
++ unsigned int index);
+ extern int platform_get_irq(struct platform_device *, unsigned int);
+ extern int platform_irq_count(struct platform_device *);
+ extern struct resource *platform_get_resource_byname(struct platform_device *,
diff --git a/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch b/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch
new file mode 100644
index 0000000000..0d801ac374
--- /dev/null
+++ b/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch
@@ -0,0 +1,41 @@
+From: Ido Schimmel <idosch@mellanox.com>
+Date: Thu, 3 Aug 2017 13:28:21 +0200
+Subject: ipv6: fib: Don't assume only nodes hold a reference on routes
+Patch-mainline: v4.14-rc1
+Git-commit: c5b12410fa591acb1d48e167b9bd0d2a7a38498d
+References: bsc#1138732
+
+The code currently assumes that only FIB nodes can hold a reference on
+routes. Therefore, after fib6_purge_rt() has run and the route is no
+longer present in any intermediate nodes, it's assumed that its
+reference count would be 1 - taken by the node where it's currently
+stored.
+
+However, we're going to allow users other than the FIB to take a
+reference on a route, so this assumption is no longer valid and the
+BUG_ON() needs to be removed.
+
+Note that purging only takes place if the initial reference count is
+different than 1. I've left that check intact, as in the majority of
+systems (where routes are only referenced by the FIB), it does actually
+mean the route is present in intermediate nodes.
+
+Signed-off-by: Ido Schimmel <idosch@mellanox.com>
+Signed-off-by: Jiri Pirko <jiri@mellanox.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ net/ipv6/ip6_fib.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/net/ipv6/ip6_fib.c
++++ b/net/ipv6/ip6_fib.c
+@@ -763,8 +763,6 @@ static void fib6_purge_rt(struct rt6_inf
+ }
+ fn = fn->parent;
+ }
+- /* No more references are possible at this point. */
+- BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
+ }
+ }
+
diff --git a/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch b/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch
new file mode 100644
index 0000000000..231a9e17a8
--- /dev/null
+++ b/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch
@@ -0,0 +1,1410 @@
+From: Liming Sun <lsun@mellanox.com>
+Date: Fri, 3 May 2019 09:49:08 -0400
+Subject: platform/mellanox: Add TmFifo driver for Mellanox BlueField Soc
+Patch-mainline: v5.2-rc1
+Git-commit: 1357dfd7261fc2f625bf895f77bb57e8827b8f63
+References: bsc#1136333 jsc#SLE-4994
+
+This commit adds the TmFifo platform driver for Mellanox BlueField
+Soc. TmFifo is a shared FIFO which enables external host machine
+to exchange data with the SoC via USB or PCIe. The driver is based
+on virtio framework and has console and network access enabled.
+
+Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Liming Sun <lsun@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/mellanox/Kconfig | 12
+ drivers/platform/mellanox/Makefile | 1
+ drivers/platform/mellanox/mlxbf-tmfifo-regs.h | 63 +
+ drivers/platform/mellanox/mlxbf-tmfifo.c | 1281 ++++++++++++++++++++++++++
+ 4 files changed, 1356 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+ create mode 100644 drivers/platform/mellanox/mlxbf-tmfifo.c
+
+--- a/drivers/platform/mellanox/Kconfig
++++ b/drivers/platform/mellanox/Kconfig
+@@ -5,7 +5,7 @@
+
+ menuconfig MELLANOX_PLATFORM
+ bool "Platform support for Mellanox hardware"
+- depends on X86 || ARM || COMPILE_TEST
++ depends on X86 || ARM || ARM64 || COMPILE_TEST
+ ---help---
+ Say Y here to get to see options for platform support for
+ Mellanox systems. This option alone does not add any kernel code.
+@@ -34,4 +34,14 @@ config MLXREG_IO
+ to system resets operation, system reset causes monitoring and some
+ kinds of mux selection.
+
++config MLXBF_TMFIFO
++ tristate "Mellanox BlueField SoC TmFifo platform driver"
++ depends on ARM64
++ depends on ACPI
++ depends on VIRTIO_CONSOLE && VIRTIO_NET
++ help
++ Say y here to enable TmFifo support. The TmFifo driver provides
++ platform driver support for the TmFifo which supports console
++ and networking based on the virtio framework.
++
+ endif # MELLANOX_PLATFORM
+--- a/drivers/platform/mellanox/Makefile
++++ b/drivers/platform/mellanox/Makefile
+@@ -3,5 +3,6 @@
+ # Makefile for linux/drivers/platform/mellanox
+ # Mellanox Platform-Specific Drivers
+ #
++obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o
+ obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o
+ obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o
+--- /dev/null
++++ b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+@@ -0,0 +1,63 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
++ */
++
++#ifndef __MLXBF_TMFIFO_REGS_H__
++#define __MLXBF_TMFIFO_REGS_H__
++
++#include <linux/types.h>
++#include <linux/bits.h>
++
++#define MLXBF_TMFIFO_TX_DATA 0x00
++#define MLXBF_TMFIFO_TX_STS 0x08
++#define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001
++#define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0
++#define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9
++#define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0
++#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_CTL 0x10
++#define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001
++#define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0
++#define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8
++#define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128
++#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8
++#define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8
++#define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128
++#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
++#define MLXBF_TMFIFO_RX_DATA 0x00
++#define MLXBF_TMFIFO_RX_STS 0x08
++#define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001
++#define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0
++#define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9
++#define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0
++#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_CTL 0x10
++#define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001
++#define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0
++#define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8
++#define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128
++#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8
++#define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8
++#define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128
++#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
++
++#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
+--- /dev/null
++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c
+@@ -0,0 +1,1281 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Mellanox BlueField SoC TmFifo driver
++ *
++ * Copyright (C) 2019 Mellanox Technologies
++ */
++
++#include <linux/acpi.h>
++#include <linux/bitfield.h>
++#include <linux/circ_buf.h>
++#include <linux/efi.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/types.h>
++
++#include <linux/virtio_config.h>
++#include <linux/virtio_console.h>
++#include <linux/virtio_ids.h>
++#include <linux/virtio_net.h>
++#include <linux/virtio_ring.h>
++
++#include "mlxbf-tmfifo-regs.h"
++
++/* Vring size. */
++#define MLXBF_TMFIFO_VRING_SIZE SZ_1K
++
++/* Console Tx buffer size. */
++#define MLXBF_TMFIFO_CON_TX_BUF_SIZE SZ_32K
++
++/* Console Tx buffer reserved space. */
++#define MLXBF_TMFIFO_CON_TX_BUF_RSV_SIZE 8
++
++/* House-keeping timer interval. */
++#define MLXBF_TMFIFO_TIMER_INTERVAL (HZ / 10)
++
++/* Virtual devices sharing the TM FIFO. */
++#define MLXBF_TMFIFO_VDEV_MAX (VIRTIO_ID_CONSOLE + 1)
++
++/*
++ * Reserve 1/16 of TmFifo space, so console messages are not starved by
++ * the networking traffic.
++ */
++#define MLXBF_TMFIFO_RESERVE_RATIO 16
++
++/* Message with data needs at least two words (for header & data). */
++#define MLXBF_TMFIFO_DATA_MIN_WORDS 2
++
++struct mlxbf_tmfifo;
++
++/**
++ * mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
++ * @va: virtual address of the ring
++ * @dma: dma address of the ring
++ * @vq: pointer to the virtio virtqueue
++ * @desc: current descriptor of the pending packet
++ * @desc_head: head descriptor of the pending packet
++ * @cur_len: processed length of the current descriptor
++ * @rem_len: remaining length of the pending packet
++ * @pkt_len: total length of the pending packet
++ * @next_avail: next avail descriptor id
++ * @num: vring size (number of descriptors)
++ * @align: vring alignment size
++ * @index: vring index
++ * @vdev_id: vring virtio id (VIRTIO_ID_xxx)
++ * @fifo: pointer to the tmfifo structure
++ */
++struct mlxbf_tmfifo_vring {
++ void *va;
++ dma_addr_t dma;
++ struct virtqueue *vq;
++ struct vring_desc *desc;
++ struct vring_desc *desc_head;
++ int cur_len;
++ int rem_len;
++ u32 pkt_len;
++ u16 next_avail;
++ int num;
++ int align;
++ int index;
++ int vdev_id;
++ struct mlxbf_tmfifo *fifo;
++};
++
++/* Interrupt types. */
++enum {
++ MLXBF_TM_RX_LWM_IRQ,
++ MLXBF_TM_RX_HWM_IRQ,
++ MLXBF_TM_TX_LWM_IRQ,
++ MLXBF_TM_TX_HWM_IRQ,
++ MLXBF_TM_MAX_IRQ
++};
++
++/* Ring types (Rx & Tx). */
++enum {
++ MLXBF_TMFIFO_VRING_RX,
++ MLXBF_TMFIFO_VRING_TX,
++ MLXBF_TMFIFO_VRING_MAX
++};
++
++/**
++ * mlxbf_tmfifo_vdev - Structure of the TmFifo virtual device
++ * @vdev: virtio device, in which the vdev.id.device field has the
++ * VIRTIO_ID_xxx id to distinguish the virtual device.
++ * @status: status of the device
++ * @features: supported features of the device
++ * @vrings: array of tmfifo vrings of this device
++ * @config.cons: virtual console config -
++ * select if vdev.id.device is VIRTIO_ID_CONSOLE
++ * @config.net: virtual network config -
++ * select if vdev.id.device is VIRTIO_ID_NET
++ * @tx_buf: tx buffer used to buffer data before writing into the FIFO
++ */
++struct mlxbf_tmfifo_vdev {
++ struct virtio_device vdev;
++ u8 status;
++ u64 features;
++ struct mlxbf_tmfifo_vring vrings[MLXBF_TMFIFO_VRING_MAX];
++ union {
++ struct virtio_console_config cons;
++ struct virtio_net_config net;
++ } config;
++ struct circ_buf tx_buf;
++};
++
++/**
++ * mlxbf_tmfifo_irq_info - Structure of the interrupt information
++ * @fifo: pointer to the tmfifo structure
++ * @irq: interrupt number
++ * @index: index into the interrupt array
++ */
++struct mlxbf_tmfifo_irq_info {
++ struct mlxbf_tmfifo *fifo;
++ int irq;
++ int index;
++};
++
++/**
++ * mlxbf_tmfifo - Structure of the TmFifo
++ * @vdev: array of the virtual devices running over the TmFifo
++ * @lock: lock to protect the TmFifo access
++ * @rx_base: mapped register base address for the Rx FIFO
++ * @tx_base: mapped register base address for the Tx FIFO
++ * @rx_fifo_size: number of entries of the Rx FIFO
++ * @tx_fifo_size: number of entries of the Tx FIFO
++ * @pend_events: pending bits for deferred events
++ * @irq_info: interrupt information
++ * @work: work struct for deferred process
++ * @timer: background timer
++ * @vring: Tx/Rx ring
++ * @spin_lock: spin lock
++ * @is_ready: ready flag
++ */
++struct mlxbf_tmfifo {
++ struct mlxbf_tmfifo_vdev *vdev[MLXBF_TMFIFO_VDEV_MAX];
++ struct mutex lock; /* TmFifo lock */
++ void __iomem *rx_base;
++ void __iomem *tx_base;
++ int rx_fifo_size;
++ int tx_fifo_size;
++ unsigned long pend_events;
++ struct mlxbf_tmfifo_irq_info irq_info[MLXBF_TM_MAX_IRQ];
++ struct work_struct work;
++ struct timer_list timer;
++ struct mlxbf_tmfifo_vring *vring[2];
++ spinlock_t spin_lock; /* spin lock */
++ bool is_ready;
++};
++
++/**
++ * mlxbf_tmfifo_msg_hdr - Structure of the TmFifo message header
++ * @type: message type
++ * @len: payload length in network byte order. Messages sent into the FIFO
++ * will be read by the other side as data stream in the same byte order.
++ * The length needs to be encoded into network order so both sides
++ * could understand it.
++ */
++struct mlxbf_tmfifo_msg_hdr {
++ u8 type;
++ __be16 len;
++ u8 unused[5];
++} __packed __aligned(sizeof(u64));
++
++/*
++ * Default MAC.
++ * This MAC address will be read from EFI persistent variable if configured.
++ * It can also be reconfigured with standard Linux tools.
++ */
++static u8 mlxbf_tmfifo_net_default_mac[ETH_ALEN] = {
++ 0x00, 0x1A, 0xCA, 0xFF, 0xFF, 0x01
++};
++
++/* EFI variable name of the MAC address. */
++static efi_char16_t mlxbf_tmfifo_efi_name[] = L"RshimMacAddr";
++
++/* Maximum L2 header length. */
++#define MLXBF_TMFIFO_NET_L2_OVERHEAD 36
++
++/* Supported virtio-net features. */
++#define MLXBF_TMFIFO_NET_FEATURES \
++ (BIT_ULL(VIRTIO_NET_F_MTU) | BIT_ULL(VIRTIO_NET_F_STATUS) | \
++ BIT_ULL(VIRTIO_NET_F_MAC))
++
++#define mlxbf_vdev_to_tmfifo(d) container_of(d, struct mlxbf_tmfifo_vdev, vdev)
++
++/* Free vrings of the FIFO device. */
++static void mlxbf_tmfifo_free_vrings(struct mlxbf_tmfifo *fifo,
++ struct mlxbf_tmfifo_vdev *tm_vdev)
++{
++ struct mlxbf_tmfifo_vring *vring;
++ int i, size;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++ if (vring->va) {
++ size = vring_size(vring->num, vring->align);
++ dma_free_coherent(tm_vdev->vdev.dev.parent, size,
++ vring->va, vring->dma);
++ vring->va = NULL;
++ if (vring->vq) {
++ vring_del_virtqueue(vring->vq);
++ vring->vq = NULL;
++ }
++ }
++ }
++}
++
++/* Allocate vrings for the FIFO. */
++static int mlxbf_tmfifo_alloc_vrings(struct mlxbf_tmfifo *fifo,
++ struct mlxbf_tmfifo_vdev *tm_vdev)
++{
++ struct mlxbf_tmfifo_vring *vring;
++ struct device *dev;
++ dma_addr_t dma;
++ int i, size;
++ void *va;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++ vring->fifo = fifo;
++ vring->num = MLXBF_TMFIFO_VRING_SIZE;
++ vring->align = SMP_CACHE_BYTES;
++ vring->index = i;
++ vring->vdev_id = tm_vdev->vdev.id.device;
++ dev = &tm_vdev->vdev.dev;
++
++ size = vring_size(vring->num, vring->align);
++ va = dma_alloc_coherent(dev->parent, size, &dma, GFP_KERNEL);
++ if (!va) {
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ dev_err(dev->parent, "dma_alloc_coherent failed\n");
++ return -ENOMEM;
++ }
++
++ vring->va = va;
++ vring->dma = dma;
++ }
++
++ return 0;
++}
++
++/* Disable interrupts of the FIFO device. */
++static void mlxbf_tmfifo_disable_irqs(struct mlxbf_tmfifo *fifo)
++{
++ int i, irq;
++
++ for (i = 0; i < MLXBF_TM_MAX_IRQ; i++) {
++ irq = fifo->irq_info[i].irq;
++ fifo->irq_info[i].irq = 0;
++ disable_irq(irq);
++ }
++}
++
++/* Interrupt handler. */
++static irqreturn_t mlxbf_tmfifo_irq_handler(int irq, void *arg)
++{
++ struct mlxbf_tmfifo_irq_info *irq_info = arg;
++
++ if (!test_and_set_bit(irq_info->index, &irq_info->fifo->pend_events))
++ schedule_work(&irq_info->fifo->work);
++
++ return IRQ_HANDLED;
++}
++
++/* Get the next packet descriptor from the vring. */
++static struct vring_desc *
++mlxbf_tmfifo_get_next_desc(struct mlxbf_tmfifo_vring *vring)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ unsigned int idx, head;
++
++ if (vring->next_avail == virtio16_to_cpu(vdev, vr->avail->idx))
++ return NULL;
++
++ idx = vring->next_avail % vr->num;
++ head = virtio16_to_cpu(vdev, vr->avail->ring[idx]);
++ if (WARN_ON(head >= vr->num))
++ return NULL;
++
++ vring->next_avail++;
++
++ return &vr->desc[head];
++}
++
++/* Release virtio descriptor. */
++static void mlxbf_tmfifo_release_desc(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc, u32 len)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ u16 idx, vr_idx;
++
++ vr_idx = virtio16_to_cpu(vdev, vr->used->idx);
++ idx = vr_idx % vr->num;
++ vr->used->ring[idx].id = cpu_to_virtio32(vdev, desc - vr->desc);
++ vr->used->ring[idx].len = cpu_to_virtio32(vdev, len);
++
++ /*
++ * Virtio could poll and check the 'idx' to decide whether the desc is
++ * done or not. Add a memory barrier here to make sure the update above
++ * completes before updating the idx.
++ */
++ mb();
++ vr->used->idx = cpu_to_virtio16(vdev, vr_idx + 1);
++}
++
++/* Get the total length of the descriptor chain. */
++static u32 mlxbf_tmfifo_get_pkt_len(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ u32 len = 0, idx;
++
++ while (desc) {
++ len += virtio32_to_cpu(vdev, desc->len);
++ if (!(virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT))
++ break;
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ }
++
++ return len;
++}
++
++static void mlxbf_tmfifo_release_pending_pkt(struct mlxbf_tmfifo_vring *vring)
++{
++ struct vring_desc *desc_head;
++ u32 len = 0;
++
++ if (vring->desc_head) {
++ desc_head = vring->desc_head;
++ len = vring->pkt_len;
++ } else {
++ desc_head = mlxbf_tmfifo_get_next_desc(vring);
++ len = mlxbf_tmfifo_get_pkt_len(vring, desc_head);
++ }
++
++ if (desc_head)
++ mlxbf_tmfifo_release_desc(vring, desc_head, len);
++
++ vring->pkt_len = 0;
++ vring->desc = NULL;
++ vring->desc_head = NULL;
++}
++
++static void mlxbf_tmfifo_init_net_desc(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc, bool is_rx)
++{
++ struct virtio_device *vdev = vring->vq->vdev;
++ struct virtio_net_hdr *net_hdr;
++
++ net_hdr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++ memset(net_hdr, 0, sizeof(*net_hdr));
++}
++
++/* Get and initialize the next packet. */
++static struct vring_desc *
++mlxbf_tmfifo_get_next_pkt(struct mlxbf_tmfifo_vring *vring, bool is_rx)
++{
++ struct vring_desc *desc;
++
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ if (desc && is_rx && vring->vdev_id == VIRTIO_ID_NET)
++ mlxbf_tmfifo_init_net_desc(vring, desc, is_rx);
++
++ vring->desc_head = desc;
++ vring->desc = desc;
++
++ return desc;
++}
++
++/* House-keeping timer. */
++static void mlxbf_tmfifo_timer(struct timer_list *t)
++{
++ struct mlxbf_tmfifo *fifo = container_of(t, struct mlxbf_tmfifo, timer);
++ int rx, tx;
++
++ rx = !test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events);
++ tx = !test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
++
++ if (rx || tx)
++ schedule_work(&fifo->work);
++
++ mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
++}
++
++/* Copy one console packet into the output buffer. */
++static void mlxbf_tmfifo_console_output_one(struct mlxbf_tmfifo_vdev *cons,
++ struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = &cons->vdev;
++ u32 len, idx, seg;
++ void *addr;
++
++ while (desc) {
++ addr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++ len = virtio32_to_cpu(vdev, desc->len);
++
++ seg = CIRC_SPACE_TO_END(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (len <= seg) {
++ memcpy(cons->tx_buf.buf + cons->tx_buf.head, addr, len);
++ } else {
++ memcpy(cons->tx_buf.buf + cons->tx_buf.head, addr, seg);
++ addr += seg;
++ memcpy(cons->tx_buf.buf, addr, len - seg);
++ }
++ cons->tx_buf.head = (cons->tx_buf.head + len) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++
++ if (!(virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT))
++ break;
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ }
++}
++
++/* Copy console data into the output buffer. */
++static void mlxbf_tmfifo_console_output(struct mlxbf_tmfifo_vdev *cons,
++ struct mlxbf_tmfifo_vring *vring)
++{
++ struct vring_desc *desc;
++ u32 len, avail;
++
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ while (desc) {
++ /* Release the packet if not enough space. */
++ len = mlxbf_tmfifo_get_pkt_len(vring, desc);
++ avail = CIRC_SPACE(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (len + MLXBF_TMFIFO_CON_TX_BUF_RSV_SIZE > avail) {
++ mlxbf_tmfifo_release_desc(vring, desc, len);
++ break;
++ }
++
++ mlxbf_tmfifo_console_output_one(cons, vring, desc);
++ mlxbf_tmfifo_release_desc(vring, desc, len);
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ }
++}
++
++/* Get the number of available words in Rx FIFO for receiving. */
++static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
++{
++ u64 sts;
++
++ sts = readq(fifo->rx_base + MLXBF_TMFIFO_RX_STS);
++ return FIELD_GET(MLXBF_TMFIFO_RX_STS__COUNT_MASK, sts);
++}
++
++/* Get the number of available words in the TmFifo for sending. */
++static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
++{
++ int tx_reserve;
++ u32 count;
++ u64 sts;
++
++ /* Reserve some room in FIFO for console messages. */
++ if (vdev_id == VIRTIO_ID_NET)
++ tx_reserve = fifo->tx_fifo_size / MLXBF_TMFIFO_RESERVE_RATIO;
++ else
++ tx_reserve = 1;
++
++ sts = readq(fifo->tx_base + MLXBF_TMFIFO_TX_STS);
++ count = FIELD_GET(MLXBF_TMFIFO_TX_STS__COUNT_MASK, sts);
++ return fifo->tx_fifo_size - tx_reserve - count;
++}
++
++/* Console Tx (move data from the output buffer into the TmFifo). */
++static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
++{
++ struct mlxbf_tmfifo_msg_hdr hdr;
++ struct mlxbf_tmfifo_vdev *cons;
++ unsigned long flags;
++ int size, seg;
++ void *addr;
++ u64 data;
++
++ /* Return if not enough space available. */
++ if (avail < MLXBF_TMFIFO_DATA_MIN_WORDS)
++ return;
++
++ cons = fifo->vdev[VIRTIO_ID_CONSOLE];
++ if (!cons || !cons->tx_buf.buf)
++ return;
++
++ /* Return if no data to send. */
++ size = CIRC_CNT(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (size == 0)
++ return;
++
++ /* Adjust the size to available space. */
++ if (size + sizeof(hdr) > avail * sizeof(u64))
++ size = avail * sizeof(u64) - sizeof(hdr);
++
++ /* Write header. */
++ hdr.type = VIRTIO_ID_CONSOLE;
++ hdr.len = htons(size);
++ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++
++ /* Use spin-lock to protect the 'cons->tx_buf'. */
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++
++ while (size > 0) {
++ addr = cons->tx_buf.buf + cons->tx_buf.tail;
++
++ seg = CIRC_CNT_TO_END(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (seg >= sizeof(u64)) {
++ memcpy(&data, addr, sizeof(u64));
++ } else {
++ memcpy(&data, addr, seg);
++ memcpy((u8 *)&data + seg, cons->tx_buf.buf,
++ sizeof(u64) - seg);
++ }
++ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++
++ if (size >= sizeof(u64)) {
++ cons->tx_buf.tail = (cons->tx_buf.tail + sizeof(u64)) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++ size -= sizeof(u64);
++ } else {
++ cons->tx_buf.tail = (cons->tx_buf.tail + size) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++ size = 0;
++ }
++ }
++
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++}
++
++/* Rx/Tx one word in the descriptor buffer. */
++static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc,
++ bool is_rx, int len)
++{
++ struct virtio_device *vdev = vring->vq->vdev;
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ void *addr;
++ u64 data;
++
++ /* Get the buffer address of this desc. */
++ addr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++
++ /* Read a word from FIFO for Rx. */
++ if (is_rx)
++ data = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
++
++ if (vring->cur_len + sizeof(u64) <= len) {
++ /* The whole word. */
++ if (is_rx)
++ memcpy(addr + vring->cur_len, &data, sizeof(u64));
++ else
++ memcpy(&data, addr + vring->cur_len, sizeof(u64));
++ vring->cur_len += sizeof(u64);
++ } else {
++ /* Leftover bytes. */
++ if (is_rx)
++ memcpy(addr + vring->cur_len, &data,
++ len - vring->cur_len);
++ else
++ memcpy(&data, addr + vring->cur_len,
++ len - vring->cur_len);
++ vring->cur_len = len;
++ }
++
++ /* Write the word into FIFO for Tx. */
++ if (!is_rx)
++ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++}
++
++/*
++ * Rx/Tx packet header.
++ *
++ * In Rx case, the packet might be found to belong to a different vring since
++ * the TmFifo is shared by different services. In such case, the 'vring_change'
++ * flag is set.
++ */
++static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc,
++ bool is_rx, bool *vring_change)
++{
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ struct virtio_net_config *config;
++ struct mlxbf_tmfifo_msg_hdr hdr;
++ int vdev_id, hdr_len;
++
++ /* Read/Write packet header. */
++ if (is_rx) {
++ /* Drain one word from the FIFO. */
++ *(u64 *)&hdr = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
++
++ /* Skip the length 0 packets (keepalive). */
++ if (hdr.len == 0)
++ return;
++
++ /* Check packet type. */
++ if (hdr.type == VIRTIO_ID_NET) {
++ vdev_id = VIRTIO_ID_NET;
++ hdr_len = sizeof(struct virtio_net_hdr);
++ config = &fifo->vdev[vdev_id]->config.net;
++ if (ntohs(hdr.len) > config->mtu +
++ MLXBF_TMFIFO_NET_L2_OVERHEAD)
++ return;
++ } else {
++ vdev_id = VIRTIO_ID_CONSOLE;
++ hdr_len = 0;
++ }
++
++ /*
++ * Check whether the new packet still belongs to this vring.
++ * If not, update the pkt_len of the new vring.
++ */
++ if (vdev_id != vring->vdev_id) {
++ struct mlxbf_tmfifo_vdev *tm_dev2 = fifo->vdev[vdev_id];
++
++ if (!tm_dev2)
++ return;
++ vring->desc = desc;
++ vring = &tm_dev2->vrings[MLXBF_TMFIFO_VRING_RX];
++ *vring_change = true;
++ }
++ vring->pkt_len = ntohs(hdr.len) + hdr_len;
++ } else {
++ /* Network virtio has an extra header. */
++ hdr_len = (vring->vdev_id == VIRTIO_ID_NET) ?
++ sizeof(struct virtio_net_hdr) : 0;
++ vring->pkt_len = mlxbf_tmfifo_get_pkt_len(vring, desc);
++ hdr.type = (vring->vdev_id == VIRTIO_ID_NET) ?
++ VIRTIO_ID_NET : VIRTIO_ID_CONSOLE;
++ hdr.len = htons(vring->pkt_len - hdr_len);
++ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++ }
++
++ vring->cur_len = hdr_len;
++ vring->rem_len = vring->pkt_len;
++ fifo->vring[is_rx] = vring;
++}
++
++/*
++ * Rx/Tx one descriptor.
++ *
++ * Return true to indicate more data available.
++ */
++static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring,
++ bool is_rx, int *avail)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ struct virtio_device *vdev;
++ bool vring_change = false;
++ struct vring_desc *desc;
++ unsigned long flags;
++ u32 len, idx;
++
++ vdev = &fifo->vdev[vring->vdev_id]->vdev;
++
++ /* Get the descriptor of the next packet. */
++ if (!vring->desc) {
++ desc = mlxbf_tmfifo_get_next_pkt(vring, is_rx);
++ if (!desc)
++ return false;
++ } else {
++ desc = vring->desc;
++ }
++
++ /* Beginning of a packet. Start to Rx/Tx packet header. */
++ if (vring->pkt_len == 0) {
++ mlxbf_tmfifo_rxtx_header(vring, desc, is_rx, &vring_change);
++ (*avail)--;
++
++ /* Return if new packet is for another ring. */
++ if (vring_change)
++ return false;
++ goto mlxbf_tmfifo_desc_done;
++ }
++
++ /* Get the length of this desc. */
++ len = virtio32_to_cpu(vdev, desc->len);
++ if (len > vring->rem_len)
++ len = vring->rem_len;
++
++ /* Rx/Tx one word (8 bytes) if not done. */
++ if (vring->cur_len < len) {
++ mlxbf_tmfifo_rxtx_word(vring, desc, is_rx, len);
++ (*avail)--;
++ }
++
++ /* Check again whether it's done. */
++ if (vring->cur_len == len) {
++ vring->cur_len = 0;
++ vring->rem_len -= len;
++
++ /* Get the next desc on the chain. */
++ if (vring->rem_len > 0 &&
++ (virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT)) {
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ goto mlxbf_tmfifo_desc_done;
++ }
++
++ /* Done and release the pending packet. */
++ mlxbf_tmfifo_release_pending_pkt(vring);
++ desc = NULL;
++ fifo->vring[is_rx] = NULL;
++
++ /* Notify upper layer that packet is done. */
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++ vring_interrupt(0, vring->vq);
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++ }
++
++mlxbf_tmfifo_desc_done:
++ /* Save the current desc. */
++ vring->desc = desc;
++
++ return true;
++}
++
++/* Rx & Tx processing of a queue. */
++static void mlxbf_tmfifo_rxtx(struct mlxbf_tmfifo_vring *vring, bool is_rx)
++{
++ int avail = 0, devid = vring->vdev_id;
++ struct mlxbf_tmfifo *fifo;
++ bool more;
++
++ fifo = vring->fifo;
++
++ /* Return if vdev is not ready. */
++ if (!fifo->vdev[devid])
++ return;
++
++ /* Return if another vring is running. */
++ if (fifo->vring[is_rx] && fifo->vring[is_rx] != vring)
++ return;
++
++ /* Only handle console and network for now. */
++ if (WARN_ON(devid != VIRTIO_ID_NET && devid != VIRTIO_ID_CONSOLE))
++ return;
++
++ do {
++ /* Get available FIFO space. */
++ if (avail == 0) {
++ if (is_rx)
++ avail = mlxbf_tmfifo_get_rx_avail(fifo);
++ else
++ avail = mlxbf_tmfifo_get_tx_avail(fifo, devid);
++ if (avail <= 0)
++ break;
++ }
++
++ /* Console output always comes from the Tx buffer. */
++ if (!is_rx && devid == VIRTIO_ID_CONSOLE) {
++ mlxbf_tmfifo_console_tx(fifo, avail);
++ break;
++ }
++
++ /* Handle one descriptor. */
++ more = mlxbf_tmfifo_rxtx_one_desc(vring, is_rx, &avail);
++ } while (more);
++}
++
++/* Handle Rx or Tx queues. */
++static void mlxbf_tmfifo_work_rxtx(struct mlxbf_tmfifo *fifo, int queue_id,
++ int irq_id, bool is_rx)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++ struct mlxbf_tmfifo_vring *vring;
++ int i;
++
++ if (!test_and_clear_bit(irq_id, &fifo->pend_events) ||
++ !fifo->irq_info[irq_id].irq)
++ return;
++
++ for (i = 0; i < MLXBF_TMFIFO_VDEV_MAX; i++) {
++ tm_vdev = fifo->vdev[i];
++ if (tm_vdev) {
++ vring = &tm_vdev->vrings[queue_id];
++ if (vring->vq)
++ mlxbf_tmfifo_rxtx(vring, is_rx);
++ }
++ }
++}
++
++/* Work handler for Rx and Tx case. */
++static void mlxbf_tmfifo_work_handler(struct work_struct *work)
++{
++ struct mlxbf_tmfifo *fifo;
++
++ fifo = container_of(work, struct mlxbf_tmfifo, work);
++ if (!fifo->is_ready)
++ return;
++
++ mutex_lock(&fifo->lock);
++
++ /* Tx (Send data to the TmFifo). */
++ mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_TX,
++ MLXBF_TM_TX_LWM_IRQ, false);
++
++ /* Rx (Receive data from the TmFifo). */
++ mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_RX,
++ MLXBF_TM_RX_HWM_IRQ, true);
++
++ mutex_unlock(&fifo->lock);
++}
++
++/* The notify function is called when new buffers are posted. */
++static bool mlxbf_tmfifo_virtio_notify(struct virtqueue *vq)
++{
++ struct mlxbf_tmfifo_vring *vring = vq->priv;
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++ struct mlxbf_tmfifo *fifo;
++ unsigned long flags;
++
++ fifo = vring->fifo;
++
++ /*
++ * Virtio maintains vrings in pairs, even number ring for Rx
++ * and odd number ring for Tx.
++ */
++ if (vring->index & BIT(0)) {
++ /*
++ * Console could make blocking call with interrupts disabled.
++ * In such case, the vring needs to be served right away. For
++ * other cases, just set the TX LWM bit to start Tx in the
++ * worker handler.
++ */
++ if (vring->vdev_id == VIRTIO_ID_CONSOLE) {
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++ tm_vdev = fifo->vdev[VIRTIO_ID_CONSOLE];
++ mlxbf_tmfifo_console_output(tm_vdev, vring);
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++ } else if (test_and_set_bit(MLXBF_TM_TX_LWM_IRQ,
++ &fifo->pend_events)) {
++ return true;
++ }
++ } else {
++ if (test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events))
++ return true;
++ }
++
++ schedule_work(&fifo->work);
++
++ return true;
++}
++
++/* Get the array of feature bits for this device. */
++static u64 mlxbf_tmfifo_virtio_get_features(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ return tm_vdev->features;
++}
++
++/* Confirm device features to use. */
++static int mlxbf_tmfifo_virtio_finalize_features(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->features = vdev->features;
++
++ return 0;
++}
++
++/* Free virtqueues found by find_vqs(). */
++static void mlxbf_tmfifo_virtio_del_vqs(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++ struct mlxbf_tmfifo_vring *vring;
++ struct virtqueue *vq;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++
++ /* Release the pending packet. */
++ if (vring->desc)
++ mlxbf_tmfifo_release_pending_pkt(vring);
++ vq = vring->vq;
++ if (vq) {
++ vring->vq = NULL;
++ vring_del_virtqueue(vq);
++ }
++ }
++}
++
++/* Create and initialize the virtual queues. */
++static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev,
++ unsigned int nvqs,
++ struct virtqueue *vqs[],
++ vq_callback_t *callbacks[],
++ const char * const names[],
++ const bool *ctx,
++ struct irq_affinity *desc)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++ struct mlxbf_tmfifo_vring *vring;
++ struct virtqueue *vq;
++ int i, ret, size;
++
++ if (nvqs > ARRAY_SIZE(tm_vdev->vrings))
++ return -EINVAL;
++
++ for (i = 0; i < nvqs; ++i) {
++ if (!names[i]) {
++ ret = -EINVAL;
++ goto error;
++ }
++ vring = &tm_vdev->vrings[i];
++
++ /* zero vring */
++ size = vring_size(vring->num, vring->align);
++ memset(vring->va, 0, size);
++ vq = vring_new_virtqueue(i, vring->num, vring->align, vdev,
++ false, false, vring->va,
++ mlxbf_tmfifo_virtio_notify,
++ callbacks[i], names[i]);
++ if (!vq) {
++ dev_err(&vdev->dev, "vring_new_virtqueue failed\n");
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ vqs[i] = vq;
++ vring->vq = vq;
++ vq->priv = vring;
++ }
++
++ return 0;
++
++error:
++ mlxbf_tmfifo_virtio_del_vqs(vdev);
++ return ret;
++}
++
++/* Read the status byte. */
++static u8 mlxbf_tmfifo_virtio_get_status(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ return tm_vdev->status;
++}
++
++/* Write the status byte. */
++static void mlxbf_tmfifo_virtio_set_status(struct virtio_device *vdev,
++ u8 status)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->status = status;
++}
++
++/* Reset the device. Not much here for now. */
++static void mlxbf_tmfifo_virtio_reset(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->status = 0;
++}
++
++/* Read the value of a configuration field. */
++static void mlxbf_tmfifo_virtio_get(struct virtio_device *vdev,
++ unsigned int offset,
++ void *buf,
++ unsigned int len)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ if ((u64)offset + len > sizeof(tm_vdev->config))
++ return;
++
++ memcpy(buf, (u8 *)&tm_vdev->config + offset, len);
++}
++
++/* Write the value of a configuration field. */
++static void mlxbf_tmfifo_virtio_set(struct virtio_device *vdev,
++ unsigned int offset,
++ const void *buf,
++ unsigned int len)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ if ((u64)offset + len > sizeof(tm_vdev->config))
++ return;
++
++ memcpy((u8 *)&tm_vdev->config + offset, buf, len);
++}
++
++static void tmfifo_virtio_dev_release(struct device *device)
++{
++ struct virtio_device *vdev =
++ container_of(device, struct virtio_device, dev);
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ kfree(tm_vdev);
++}
++
++/* Virtio config operations. */
++static const struct virtio_config_ops mlxbf_tmfifo_virtio_config_ops = {
++ .get_features = mlxbf_tmfifo_virtio_get_features,
++ .finalize_features = mlxbf_tmfifo_virtio_finalize_features,
++ .find_vqs = mlxbf_tmfifo_virtio_find_vqs,
++ .del_vqs = mlxbf_tmfifo_virtio_del_vqs,
++ .reset = mlxbf_tmfifo_virtio_reset,
++ .set_status = mlxbf_tmfifo_virtio_set_status,
++ .get_status = mlxbf_tmfifo_virtio_get_status,
++ .get = mlxbf_tmfifo_virtio_get,
++ .set = mlxbf_tmfifo_virtio_set,
++};
++
++/* Create vdev for the FIFO. */
++static int mlxbf_tmfifo_create_vdev(struct device *dev,
++ struct mlxbf_tmfifo *fifo,
++ int vdev_id, u64 features,
++ void *config, u32 size)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev, *reg_dev = NULL;
++ int ret;
++
++ mutex_lock(&fifo->lock);
++
++ tm_vdev = fifo->vdev[vdev_id];
++ if (tm_vdev) {
++ dev_err(dev, "vdev %d already exists\n", vdev_id);
++ ret = -EEXIST;
++ goto fail;
++ }
++
++ tm_vdev = kzalloc(sizeof(*tm_vdev), GFP_KERNEL);
++ if (!tm_vdev) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ tm_vdev->vdev.id.device = vdev_id;
++ tm_vdev->vdev.config = &mlxbf_tmfifo_virtio_config_ops;
++ tm_vdev->vdev.dev.parent = dev;
++ tm_vdev->vdev.dev.release = tmfifo_virtio_dev_release;
++ tm_vdev->features = features;
++ if (config)
++ memcpy(&tm_vdev->config, config, size);
++
++ if (mlxbf_tmfifo_alloc_vrings(fifo, tm_vdev)) {
++ dev_err(dev, "unable to allocate vring\n");
++ ret = -ENOMEM;
++ goto vdev_fail;
++ }
++
++ /* Allocate an output buffer for the console device. */
++ if (vdev_id == VIRTIO_ID_CONSOLE)
++ tm_vdev->tx_buf.buf = devm_kmalloc(dev,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE,
++ GFP_KERNEL);
++ fifo->vdev[vdev_id] = tm_vdev;
++
++ /* Register the virtio device. */
++ ret = register_virtio_device(&tm_vdev->vdev);
++ reg_dev = tm_vdev;
++ if (ret) {
++ dev_err(dev, "register_virtio_device failed\n");
++ goto vdev_fail;
++ }
++
++ mutex_unlock(&fifo->lock);
++ return 0;
++
++vdev_fail:
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ fifo->vdev[vdev_id] = NULL;
++ if (reg_dev)
++ put_device(&tm_vdev->vdev.dev);
++ else
++ kfree(tm_vdev);
++fail:
++ mutex_unlock(&fifo->lock);
++ return ret;
++}
++
++/* Delete vdev for the FIFO. */
++static int mlxbf_tmfifo_delete_vdev(struct mlxbf_tmfifo *fifo, int vdev_id)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++
++ mutex_lock(&fifo->lock);
++
++ /* Unregister vdev. */
++ tm_vdev = fifo->vdev[vdev_id];
++ if (tm_vdev) {
++ unregister_virtio_device(&tm_vdev->vdev);
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ fifo->vdev[vdev_id] = NULL;
++ }
++
++ mutex_unlock(&fifo->lock);
++
++ return 0;
++}
++
++/* Read the configured network MAC address from efi variable. */
++static void mlxbf_tmfifo_get_cfg_mac(u8 *mac)
++{
++ efi_guid_t guid = EFI_GLOBAL_VARIABLE_GUID;
++ unsigned long size = ETH_ALEN;
++ u8 buf[ETH_ALEN];
++ efi_status_t rc;
++
++ rc = efi.get_variable(mlxbf_tmfifo_efi_name, &guid, NULL, &size, buf);
++ if (rc == EFI_SUCCESS && size == ETH_ALEN)
++ ether_addr_copy(mac, buf);
++ else
++ ether_addr_copy(mac, mlxbf_tmfifo_net_default_mac);
++}
++
++/* Set TmFifo thresolds which is used to trigger interrupts. */
++static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
++{
++ u64 ctl;
++
++ /* Get Tx FIFO size and set the low/high watermark. */
++ ctl = readq(fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
++ fifo->tx_fifo_size =
++ FIELD_GET(MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK, ctl);
++ ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__LWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_TX_CTL__LWM_MASK,
++ fifo->tx_fifo_size / 2);
++ ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__HWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_TX_CTL__HWM_MASK,
++ fifo->tx_fifo_size - 1);
++ writeq(ctl, fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
++
++ /* Get Rx FIFO size and set the low/high watermark. */
++ ctl = readq(fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
++ fifo->rx_fifo_size =
++ FIELD_GET(MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK, ctl);
++ ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__LWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_RX_CTL__LWM_MASK, 0);
++ ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__HWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_RX_CTL__HWM_MASK, 1);
++ writeq(ctl, fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
++}
++
++static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
++{
++ int i;
++
++ fifo->is_ready = false;
++ del_timer_sync(&fifo->timer);
++ mlxbf_tmfifo_disable_irqs(fifo);
++ cancel_work_sync(&fifo->work);
++ for (i = 0; i < MLXBF_TMFIFO_VDEV_MAX; i++)
++ mlxbf_tmfifo_delete_vdev(fifo, i);
++}
++
++/* Probe the TMFIFO. */
++static int mlxbf_tmfifo_probe(struct platform_device *pdev)
++{
++ struct virtio_net_config net_config;
++ struct device *dev = &pdev->dev;
++ struct mlxbf_tmfifo *fifo;
++ int i, rc;
++
++ fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
++ if (!fifo)
++ return -ENOMEM;
++
++ spin_lock_init(&fifo->spin_lock);
++ INIT_WORK(&fifo->work, mlxbf_tmfifo_work_handler);
++ mutex_init(&fifo->lock);
++
++ /* Get the resource of the Rx FIFO. */
++ fifo->rx_base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(fifo->rx_base))
++ return PTR_ERR(fifo->rx_base);
++
++ /* Get the resource of the Tx FIFO. */
++ fifo->tx_base = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(fifo->tx_base))
++ return PTR_ERR(fifo->tx_base);
++
++ platform_set_drvdata(pdev, fifo);
++
++ timer_setup(&fifo->timer, mlxbf_tmfifo_timer, 0);
++
++ for (i = 0; i < MLXBF_TM_MAX_IRQ; i++) {
++ fifo->irq_info[i].index = i;
++ fifo->irq_info[i].fifo = fifo;
++ fifo->irq_info[i].irq = platform_get_irq(pdev, i);
++ rc = devm_request_irq(dev, fifo->irq_info[i].irq,
++ mlxbf_tmfifo_irq_handler, 0,
++ "tmfifo", &fifo->irq_info[i]);
++ if (rc) {
++ dev_err(dev, "devm_request_irq failed\n");
++ fifo->irq_info[i].irq = 0;
++ return rc;
++ }
++ }
++
++ mlxbf_tmfifo_set_threshold(fifo);
++
++ /* Create the console vdev. */
++ rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_CONSOLE, 0, NULL, 0);
++ if (rc)
++ goto fail;
++
++ /* Create the network vdev. */
++ memset(&net_config, 0, sizeof(net_config));
++ net_config.mtu = ETH_DATA_LEN;
++ net_config.status = VIRTIO_NET_S_LINK_UP;
++ mlxbf_tmfifo_get_cfg_mac(net_config.mac);
++ rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_NET,
++ MLXBF_TMFIFO_NET_FEATURES, &net_config,
++ sizeof(net_config));
++ if (rc)
++ goto fail;
++
++ mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
++
++ fifo->is_ready = true;
++ return 0;
++
++fail:
++ mlxbf_tmfifo_cleanup(fifo);
++ return rc;
++}
++
++/* Device remove function. */
++static int mlxbf_tmfifo_remove(struct platform_device *pdev)
++{
++ struct mlxbf_tmfifo *fifo = platform_get_drvdata(pdev);
++
++ mlxbf_tmfifo_cleanup(fifo);
++
++ return 0;
++}
++
++static const struct acpi_device_id mlxbf_tmfifo_acpi_match[] = {
++ { "MLNXBF01", 0 },
++ {}
++};
++MODULE_DEVICE_TABLE(acpi, mlxbf_tmfifo_acpi_match);
++
++static struct platform_driver mlxbf_tmfifo_driver = {
++ .probe = mlxbf_tmfifo_probe,
++ .remove = mlxbf_tmfifo_remove,
++ .driver = {
++ .name = "bf-tmfifo",
++ .acpi_match_table = mlxbf_tmfifo_acpi_match,
++ },
++};
++
++module_platform_driver(mlxbf_tmfifo_driver);
++
++MODULE_DESCRIPTION("Mellanox BlueField SoC TmFifo Driver");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Mellanox Technologies");
diff --git a/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch b/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch
new file mode 100644
index 0000000000..9ab2d9bb2d
--- /dev/null
+++ b/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch
@@ -0,0 +1,59 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 7 May 2018 06:48:52 +0000
+Subject: platform/mellanox: Add new ODM system types to mlx-platform
+Patch-mainline: v4.18-rc1
+Git-commit: cbf7ff8cdb03a81ae81680ac133c7b1bf5194001
+References: bsc#1112374
+
+Add new ODM system types, matched according to DMI_BOARD_NAME. The
+supported ODM Ids are: VMOD0001, VMOD0002, VMOD0003, VMOD0004, VMOD0005.
+Patch does not introduce new systems, but allows to ODM companies to set
+DMI_BOARD_VENDOR and DMI_PRODUCT_NAME on their own. It assumes that ODM
+company can't change DMI_BOARD_NAME.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -844,6 +844,36 @@ static struct dmi_system_id mlxplat_dmi_
+ DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
+ },
+ },
++ {
++ .callback = mlxplat_dmi_default_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn21xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn274x_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn201x_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
++ },
++ },
+ { }
+ };
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch b/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
new file mode 100644
index 0000000000..5a77582824
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
@@ -0,0 +1,196 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:00 +0000
+Subject: platform/x86: mlx-platform: Add ASIC hotplug device configuration
+Patch-mainline: v4.19-rc1
+Git-commit: 0404a0b2ca3b88eab1e44b7a1d80c2aeb37fb2f1
+References: bsc#1112374
+
+Add support for ASIC hotplug device events for the all system types. The
+ASIC hotplug event is sent in cases ASIC reaches the good health state or
+dropped to the bad health state. The health state is used to change, when
+device is reset or in case of some system failures. In such cases hwmon
+uevent notification will be sent.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 74 ++++++++++++++++++++++++++++++++++--
+ 1 file changed, 71 insertions(+), 3 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -65,6 +65,8 @@
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
+ #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
++#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
++#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
+ #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
+ #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
+@@ -100,17 +102,21 @@
+ MLXPLAT_CPLD_LPC_PIO_OFFSET)
+
+ /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
++#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
+ #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
+ #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
+ #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
+-#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
++#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
++ MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
+ MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
++#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
+ #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
+-#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc0
++#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
+ #define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
+ #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
++#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
+ #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
+ #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
+@@ -315,6 +321,15 @@ static struct mlxreg_core_data mlxplat_m
+ },
+ };
+
++static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
++ {
++ .label = "asic1",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
++ },
++};
++
+ static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
+ {
+ .data = mlxplat_mlxcpld_default_psu_items_data,
+@@ -343,6 +358,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -351,6 +375,8 @@ struct mlxreg_core_hotplug_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items),
+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+ .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+ };
+
+ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
+@@ -379,6 +405,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 0,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -481,6 +516,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -519,6 +563,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 0,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -616,6 +669,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -935,7 +997,7 @@ static struct mlxreg_core_data mlxplat_m
+ {
+ .label = "asic_health",
+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
+- .mask = GENMASK(1, 0),
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
+ .bit = 1,
+ .mode = 0444,
+ },
+@@ -1033,6 +1095,8 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
+@@ -1066,6 +1130,8 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -1112,6 +1178,8 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch b/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch
new file mode 100644
index 0000000000..d51bd0618c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch
@@ -0,0 +1,396 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 7 May 2018 06:48:53 +0000
+Subject: platform/x86: mlx-platform: Add LED platform driver activation
+Patch-mainline: v4.18-rc1
+Git-commit: 1189456b1cce36f653622d15c0f38410bf6c37c5
+References: bsc#1112374
+
+Add LED platform driver activation from mlx-platform. This LED driver uses
+the same regmap infrastructure as others Mellanox platform drivers, so LED
+specific registers description is added.
+
+System LED configuration depends on system type. To support all the
+relevant types per system type LED descriptions are defined for passing
+to LED platform driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 259 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 258 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -47,6 +47,11 @@
+ /* LPC bus IO offsets */
+ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
++#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
++#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
++#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
++#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
++#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+@@ -84,6 +89,8 @@
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
+ #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
++#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
++#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
+
+ /* Default I2C parent bus number */
+ #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
+@@ -114,11 +121,13 @@
+ * @pdev_i2c - i2c controller platform device
+ * @pdev_mux - array of mux platform devices
+ * @pdev_hotplug - hotplug platform devices
++ * @pdev_led - led platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+ struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
+ struct platform_device *pdev_hotplug;
++ struct platform_device *pdev_led;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -592,9 +601,227 @@ struct mlxreg_core_hotplug_platform_data
+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+ };
+
++/* Platform led default data */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "psu:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_led_data = {
++ .data = mlxplat_mlxcpld_default_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
++};
++
++/* Platform led MSN21xx system family data */
++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "fan:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu1:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu2:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "uid:blue",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {
++ .data = mlxplat_mlxcpld_msn21xx_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data),
++};
++
++/* Platform led for default data for 200GbE systems */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "psu:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan5:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan5:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan6:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan6:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
++ .data = mlxplat_mlxcpld_default_ng_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
++};
++
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+@@ -611,6 +838,11 @@ static bool mlxplat_mlxcpld_writeable_re
+ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+@@ -632,6 +864,11 @@ static bool mlxplat_mlxcpld_readable_reg
+ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+@@ -692,6 +929,7 @@ static struct resource mlxplat_mlxcpld_r
+
+ static struct platform_device *mlxplat_dev;
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
++static struct mlxreg_core_platform_data *mlxplat_led;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -705,6 +943,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_led_data;
+
+ return 1;
+ };
+@@ -721,6 +960,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+
+ return 1;
+ };
+@@ -737,6 +977,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_led_data;
+
+ return 1;
+ };
+@@ -753,6 +994,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_ng_led_data;
+
+ return 1;
+ };
+@@ -769,6 +1011,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+
+ return 1;
+ };
+@@ -990,14 +1233,27 @@ static int __init mlxplat_init(void)
+ goto fail_platform_mux_register;
+ }
+
++ /* Add LED driver. */
++ mlxplat_led->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_led = platform_device_register_resndata(
++ &mlxplat_dev->dev, "leds-mlxreg",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_led, sizeof(*mlxplat_led));
++ if (IS_ERR(priv->pdev_led)) {
++ err = PTR_ERR(priv->pdev_led);
++ goto fail_platform_hotplug_register;
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_hotplug_register;
++ goto fail_platform_led_register;
+
+ return 0;
+
++fail_platform_led_register:
++ platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+ platform_device_unregister(priv->pdev_hotplug);
+ fail_platform_mux_register:
+@@ -1016,6 +1272,7 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ platform_device_unregister(priv->pdev_led);
+ platform_device_unregister(priv->pdev_hotplug);
+
+ for (i = ARRAY_SIZE(mlxplat_mux_data) - 1; i >= 0 ; i--)
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch b/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch
new file mode 100644
index 0000000000..1943ca9e9f
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch
@@ -0,0 +1,36 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:33 +0000
+Subject: platform/x86: mlx-platform: Add UID LED for the next generation
+ systems
+Patch-mainline: v5.1-rc1
+Git-commit: cc2597eb8eeb4634408e206a7374463868805d41
+References: bsc#1112374
+
+Add support for UID LED for the next generation systems MQMB7xx,
+MSN37xx, MSN34xx, MSN38xx.
+
+All these systems support UID LED control through the programmable
+device.
+The UID LED is to be exposed to leds-mlxreg driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -913,6 +913,11 @@ static struct mlxreg_core_data mlxplat_m
+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
+ .bit = BIT(5),
+ },
++ {
++ .label = "uid:blue",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
new file mode 100644
index 0000000000..c28060b3ee
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
@@ -0,0 +1,54 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:54 +0000
+Subject: platform/x86: mlx-platform: Add definitions for new registers
+Patch-mainline: v5.0-rc1
+Git-commit: 59e96ec85e8e59170f6d5cba028e199a2e5dfe67
+References: bsc#1112374
+
+Add definitions for new registers:
+- CPLD3 version - next generation systems are equipped with three CPLD;
+- Two reset cause registers, which store the system reset reason (like
+ system failures, upgrade failures and so on;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -49,7 +49,10 @@
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+@@ -1208,7 +1211,10 @@ static bool mlxplat_mlxcpld_readable_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+@@ -1258,7 +1264,10 @@ static bool mlxplat_mlxcpld_volatile_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
new file mode 100644
index 0000000000..624e97f80b
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
@@ -0,0 +1,61 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:32 +0000
+Subject: platform/x86: mlx-platform: Add extra CPLD for next generation
+ systems
+Patch-mainline: v5.1-rc1
+Git-commit: eb480b41f2c5eea72bf9a58dd166409e3b0731f3
+References: bsc#1112374
+
+Add support for CPLD4 for the next generation systems MQMB7xx, MSN37xx,
+MSN34xx, MSN38xx.
+
+All these systems are equipped with four programmable device.
+The version of this new device is to be exposed to sysfs through
+mlxreg-io register.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -25,6 +25,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
+ #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
++#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+@@ -1140,6 +1141,12 @@ static struct mlxreg_core_data mlxplat_m
+ .mode = 0444,
+ },
+ {
++ .label = "cpld4_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
+ .label = "reset_long_pb",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+@@ -1369,6 +1376,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+@@ -1426,6 +1434,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch
new file mode 100644
index 0000000000..3f075acaf5
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch
@@ -0,0 +1,376 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 18 Mar 2019 10:58:23 +0000
+Subject: platform/x86: mlx-platform: Add mlx-wdt platform driver activation
+Patch-mainline: v5.2-rc1
+Git-commit: 9b9f2f5416ef24260c5a5c041ba15b67fd5889b7
+References: bsc#1112374
+
+Add mlx-wdt platform driver activation. Watchdog driver uses the same
+regmap infrastructure as others Mellanox platform drivers. Specific
+registers description for watchdog platform data configuration are
+added to mlx-platform. There are the registers for watchdog timer
+manipulation, and action setting on watchdog timer expiration.
+The watchdog action function could be configured to perform one of the
+following: system reset, setting PWM to full speed or counter
+increment.
+Two types of watchdog devices are supported main and auxiliary.
+These devices are co-exist and each of them could be configured to
+handle the specific action.
+
+Signed-off-by: Michael Shych <michealsh@mellanox.com>
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 221 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 219 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -56,6 +56,16 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
+ #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
+ #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
++#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
++#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
++#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
++#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
++#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
++#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
++#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
++#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
++#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
++#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
+ #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
+ #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
+ #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
+@@ -129,6 +139,18 @@
+ #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
+ #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
+
++/* Masks and default values for watchdogs */
++#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
++#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
++
++#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
++#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
++#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
++#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
++#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
++#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
++#define MLXPLAT_CPLD_WD_MAX_DEVS 2
++
+ /* mlxplat_priv - platform private data
+ * @pdev_i2c - i2c controller platform device
+ * @pdev_mux - array of mux platform devices
+@@ -136,6 +158,7 @@
+ * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
+ * @pdev_fan - FAN platform devices
++ * @pdev_wd - array of watchdog platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+@@ -144,6 +167,7 @@ struct mlxplat_priv {
+ struct platform_device *pdev_led;
+ struct platform_device *pdev_io_regs;
+ struct platform_device *pdev_fan;
++ struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -1351,6 +1375,148 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
+ };
+
++/* Watchdog type1: hardware implementation version1
++ * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
++ */
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .bit = 6,
++ },
++};
++
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
++ .bit = 1,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
++ {
++ .data = mlxplat_mlxcpld_wd_main_regs_type1,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
++ .version = MLX_WDT_TYPE1,
++ .identity = "mlx-wdt-main",
++ },
++ {
++ .data = mlxplat_mlxcpld_wd_aux_regs_type1,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
++ .version = MLX_WDT_TYPE1,
++ .identity = "mlx-wdt-aux",
++ },
++};
++
++/* Watchdog type2: hardware implementation version 2
++ * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
++ */
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "timeleft",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .bit = 6,
++ },
++};
++
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "timeleft",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
++ {
++ .data = mlxplat_mlxcpld_wd_main_regs_type2,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
++ .version = MLX_WDT_TYPE2,
++ .identity = "mlx-wdt-main",
++ },
++ {
++ .data = mlxplat_mlxcpld_wd_aux_regs_type2,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
++ .version = MLX_WDT_TYPE2,
++ .identity = "mlx-wdt-aux",
++ },
++};
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -1373,6 +1539,14 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+@@ -1416,6 +1590,16 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
+@@ -1473,6 +1657,10 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
+@@ -1500,6 +1688,7 @@ static const struct reg_default mlxplat_
+ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
+ };
+
+ struct mlxplat_mlxcpld_regmap_context {
+@@ -1549,6 +1738,8 @@ static struct mlxreg_core_hotplug_platfo
+ static struct mlxreg_core_platform_data *mlxplat_led;
+ static struct mlxreg_core_platform_data *mlxplat_regs_io;
+ static struct mlxreg_core_platform_data *mlxplat_fan;
++static struct mlxreg_core_platform_data
++ *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -1564,6 +1755,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+ mlxplat_regs_io = &mlxplat_default_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1582,6 +1774,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1600,6 +1793,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1618,6 +1812,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1637,6 +1832,8 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_led = &mlxplat_default_ng_led_data;
+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
+
+ return 1;
+ };
+@@ -1919,15 +2116,33 @@ static int __init mlxplat_init(void)
+ }
+ }
+
++ /* Add WD drivers. */
++ for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
++ if (mlxplat_wd_data[j]) {
++ mlxplat_wd_data[j]->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_wd[j] = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlx-wdt",
++ j, NULL, 0,
++ mlxplat_wd_data[j],
++ sizeof(*mlxplat_wd_data[j]));
++ if (IS_ERR(priv->pdev_wd[j])) {
++ err = PTR_ERR(priv->pdev_wd[j]);
++ goto fail_platform_wd_register;
++ }
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_fan_register;
++ goto fail_platform_wd_register;
+
+ return 0;
+
+-fail_platform_fan_register:
++fail_platform_wd_register:
++ while (--j >= 0)
++ platform_device_unregister(priv->pdev_wd[j]);
+ if (mlxplat_fan)
+ platform_device_unregister(priv->pdev_fan);
+ fail_platform_io_regs_register:
+@@ -1953,6 +2168,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
++ platform_device_unregister(priv->pdev_wd[i]);
+ if (priv->pdev_fan)
+ platform_device_unregister(priv->pdev_fan);
+ if (priv->pdev_io_regs)
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch
new file mode 100644
index 0000000000..fdfb1f8187
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch
@@ -0,0 +1,270 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:40:57 +0000
+Subject: platform/x86: mlx-platform: Add mlxreg-fan platform driver activation
+Patch-mainline: v4.19-rc1
+Git-commit: 0378123c580091b4c2972a6e4fcb3dcb4686667a
+References: bsc#1112374
+
+Add mlxreg-fan platform driver activation. FAN driver uses the same regmap
+infrastructure as others Mellanox platform drivers. Specific registers
+description for default FAN platform data configuration are added to
+mlx-platform. There are the registers for tachometers reading, PWM
+control and FAN ownership control. The last one has a default value,
+which is set at initialization time through the regmap infrastructure,
+which is necessary for moving FAN control ownership from hardware to
+software.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 144 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 143 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -59,6 +59,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
+ #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
+ #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
++#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+@@ -73,9 +74,23 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
+ #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
+ #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
++#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
++#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
++#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
++#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6
++#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
++#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
++#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
++#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xea
++#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xeb
++#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xec
++#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xed
++#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xee
++#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xef
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
++
+ #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
+ #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
+ MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
+@@ -131,6 +146,7 @@
+ * @pdev_hotplug - hotplug platform devices
+ * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
++ * @pdev_fan - FAN platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+@@ -138,6 +154,7 @@ struct mlxplat_priv {
+ struct platform_device *pdev_hotplug;
+ struct platform_device *pdev_led;
+ struct platform_device *pdev_io_regs;
++ struct platform_device *pdev_fan;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -929,6 +946,79 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
++/* Platform FAN default */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
++ {
++ .label = "pwm1",
++ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
++ },
++ {
++ .label = "tacho1",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho2",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho3",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho4",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho5",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho6",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho7",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho8",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho9",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho10",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho11",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho12",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
++ .data = mlxplat_mlxcpld_default_fan_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
++};
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -949,6 +1039,8 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -983,6 +1075,20 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1015,6 +1121,20 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1023,6 +1143,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
+ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
+ };
+
+ struct mlxplat_mlxcpld_regmap_context {
+@@ -1071,6 +1192,7 @@ static struct platform_device *mlxplat_d
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
+ static struct mlxreg_core_platform_data *mlxplat_led;
+ static struct mlxreg_core_platform_data *mlxplat_regs_io;
++static struct mlxreg_core_platform_data *mlxplat_fan;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -1155,6 +1277,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
+ };
+@@ -1410,14 +1533,31 @@ static int __init mlxplat_init(void)
+ }
+ }
+
++ /* Add FAN driver. */
++ if (mlxplat_fan) {
++ mlxplat_fan->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_fan = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlxreg-fan",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_fan,
++ sizeof(*mlxplat_fan));
++ if (IS_ERR(priv->pdev_io_regs)) {
++ err = PTR_ERR(priv->pdev_io_regs);
++ goto fail_platform_io_regs_register;
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_io_regs_register;
++ goto fail_platform_fan_register;
+
+ return 0;
+
++fail_platform_fan_register:
++ if (mlxplat_fan)
++ platform_device_unregister(priv->pdev_fan);
+ fail_platform_io_regs_register:
+ if (mlxplat_regs_io)
+ platform_device_unregister(priv->pdev_io_regs);
+@@ -1441,6 +1581,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ if (priv->pdev_fan)
++ platform_device_unregister(priv->pdev_fan);
+ if (priv->pdev_io_regs)
+ platform_device_unregister(priv->pdev_io_regs);
+ platform_device_unregister(priv->pdev_led);
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
new file mode 100644
index 0000000000..f5ed364ac1
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
@@ -0,0 +1,350 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Sun, 17 Jun 2018 16:56:54 +0000
+Subject: platform/x86: mlx-platform: Add mlxreg-io platform driver activation
+Patch-mainline: v4.19-rc1
+Git-commit: 8871f5e4234112f02b8afe1000c18f49827c8d01
+References: bsc#1112374
+
+Add mlxreg-io platform driver activation. Access driver uses the same
+regmap infrastructure as others Mellanox platform drivers.
+Specific registers description for default platform data configuration are
+added to mlx-platform. There are the registers for resets control, reset
+causes monitoring, programmable devices version reading and mux select
+control. This platform data is passed to mlxreg-io driver. Also some
+default values for the register are set at initialization time through
+the regmap infrastructure, which are necessary for moving write protection
+from the general purpose registers, which are used by mlxreg-io for
+write access.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+v4-v5:
+ Changes added by Vadim:
+ - Add two new attributes for ASIC health and main power domain shutdown.
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 175 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 173 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -47,15 +47,23 @@
+ /* LPC bus IO offsets */
+ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
++#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
++#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+ #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
+ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
++#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
++#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
++#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
++#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
++#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
+ #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
+ #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
+@@ -122,12 +130,14 @@
+ * @pdev_mux - array of mux platform devices
+ * @pdev_hotplug - hotplug platform devices
+ * @pdev_led - led platform devices
++ * @pdev_io_regs - register access platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+ struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
+ struct platform_device *pdev_hotplug;
+ struct platform_device *pdev_led;
++ struct platform_device *pdev_io_regs;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -813,6 +823,111 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
+ };
+
++/* Platform register access default */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_fw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_wd",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "select_iio",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = GENMASK(1, 0),
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
++};
+
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+@@ -822,6 +937,10 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+@@ -838,15 +957,23 @@ static bool mlxplat_mlxcpld_writeable_re
+ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -864,15 +991,21 @@ static bool mlxplat_mlxcpld_readable_reg
+ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -887,6 +1020,11 @@ static bool mlxplat_mlxcpld_volatile_reg
+ return false;
+ }
+
++static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
++ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
++};
++
+ struct mlxplat_mlxcpld_regmap_context {
+ void __iomem *base;
+ };
+@@ -919,6 +1057,8 @@ static const struct regmap_config mlxpla
+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
+ .readable_reg = mlxplat_mlxcpld_readable_reg,
+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
++ .reg_defaults = mlxplat_mlxcpld_regmap_default,
++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
+ .reg_read = mlxplat_mlxcpld_reg_read,
+ .reg_write = mlxplat_mlxcpld_reg_write,
+ };
+@@ -930,6 +1070,7 @@ static struct resource mlxplat_mlxcpld_r
+ static struct platform_device *mlxplat_dev;
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
+ static struct mlxreg_core_platform_data *mlxplat_led;
++static struct mlxreg_core_platform_data *mlxplat_regs_io;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -944,6 +1085,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -978,6 +1120,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -1163,7 +1306,7 @@ static int mlxplat_mlxcpld_verify_bus_to
+ static int __init mlxplat_init(void)
+ {
+ struct mlxplat_priv *priv;
+- int i, nr, err;
++ int i, j, nr, err;
+
+ if (!dmi_check_system(mlxplat_dmi_table))
+ return -ENODEV;
+@@ -1233,6 +1376,15 @@ static int __init mlxplat_init(void)
+ goto fail_platform_mux_register;
+ }
+
++ /* Set default registers. */
++ for (j = 0; j < mlxplat_mlxcpld_regmap_config.num_reg_defaults; j++) {
++ err = regmap_write(mlxplat_hotplug->regmap,
++ mlxplat_mlxcpld_regmap_default[j].reg,
++ mlxplat_mlxcpld_regmap_default[j].def);
++ if (err)
++ goto fail_platform_mux_register;
++ }
++
+ /* Add LED driver. */
+ mlxplat_led->regmap = mlxplat_hotplug->regmap;
+ priv->pdev_led = platform_device_register_resndata(
+@@ -1244,14 +1396,31 @@ static int __init mlxplat_init(void)
+ goto fail_platform_hotplug_register;
+ }
+
++ /* Add registers io access driver. */
++ if (mlxplat_regs_io) {
++ mlxplat_regs_io->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_io_regs = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlxreg-io",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_regs_io,
++ sizeof(*mlxplat_regs_io));
++ if (IS_ERR(priv->pdev_io_regs)) {
++ err = PTR_ERR(priv->pdev_io_regs);
++ goto fail_platform_led_register;
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_led_register;
++ goto fail_platform_io_regs_register;
+
+ return 0;
+
++fail_platform_io_regs_register:
++ if (mlxplat_regs_io)
++ platform_device_unregister(priv->pdev_io_regs);
+ fail_platform_led_register:
+ platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+@@ -1272,6 +1441,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ if (priv->pdev_io_regs)
++ platform_device_unregister(priv->pdev_io_regs);
+ platform_device_unregister(priv->pdev_led);
+ platform_device_unregister(priv->pdev_hotplug);
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
new file mode 100644
index 0000000000..7aed8cd9d0
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
@@ -0,0 +1,315 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:15 +0000
+Subject: platform/x86: mlx-platform: Add support for fan capability registers
+Patch-mainline: v5.1-rc1
+Git-commit: 83cdb2c11173ee4aa621c8cce6e1c33fb564d2be
+References: bsc#1112374
+
+Provide support for the fan capability registers for the next generation
+systems of types MQM87xx, MSN34xx, MSN37xx. These new registers provide
+configuration for tachometers and fan drawers connectivity. Use these
+registers for next generation led, fan and hotplug structures in order
+to distinguish between the systems which have minor configuration
+differences. This reduces the amount of code used to describe such
+systems.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/mellanox/mlxreg-hotplug.c | 23 +++++++++
+ drivers/platform/x86/mlx-platform.c | 69 +++++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/mellanox/mlxreg-hotplug.c
++++ b/drivers/platform/mellanox/mlxreg-hotplug.c
+@@ -494,7 +494,9 @@ static int mlxreg_hotplug_set_irq(struct
+ {
+ struct mlxreg_core_hotplug_platform_data *pdata;
+ struct mlxreg_core_item *item;
+- int i, ret;
++ struct mlxreg_core_data *data;
++ u32 regval;
++ int i, j, ret;
+
+ pdata = dev_get_platdata(&priv->pdev->dev);
+ item = pdata->items;
+@@ -506,6 +508,25 @@ static int mlxreg_hotplug_set_irq(struct
+ if (ret)
+ goto out;
+
++ /*
++ * Verify if hardware configuration requires to disable
++ * interrupt capability for some of components.
++ */
++ data = item->data;
++ for (j = 0; j < item->count; j++, data++) {
++ /* Verify if the attribute has capability register. */
++ if (data->capability) {
++ /* Read capability register. */
++ ret = regmap_read(priv->regmap,
++ data->capability, &regval);
++ if (ret)
++ goto out;
++
++ if (!(regval & data->bit))
++ item->mask &= ~BIT(j);
++ }
++ }
++
+ /* Set group initial status as mask and unmask group event. */
+ if (item->inversed) {
+ item->cache = item->mask;
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -68,6 +68,9 @@
+ #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
+ #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
+ #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
++#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
+@@ -585,36 +588,48 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan2",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(1),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan3",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(2),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan4",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(3),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan5",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(4),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan6",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(5),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ };
+@@ -817,61 +832,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan1:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan2:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan2:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan3:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan3:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan4:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan4:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan5:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan5:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan6:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "fan6:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ };
+
+@@ -1208,61 +1247,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "tacho1",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho2",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho3",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho4",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "tacho5",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "tacho6",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "tacho7",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(6),
+ },
+ {
+ .label = "tacho8",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(7),
+ },
+ {
+ .label = "tacho9",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho10",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho11",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho12",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(3),
+ },
+ };
+
+@@ -1349,6 +1412,9 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1401,6 +1467,9 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
new file mode 100644
index 0000000000..67ee8f53f2
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
@@ -0,0 +1,59 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:11 +0000
+Subject: platform/x86: mlx-platform: Add support for fan direction register
+Patch-mainline: v5.1-rc1
+Git-commit: aff475804f608c5375dc1c5df6f0fdeb63459ccb
+References: bsc#1112374
+
+Provide support for the fan direction register.
+This register shows configuration for system fans direction, which could
+be forward or reversed.
+For forward direction - relevant bit is set 0;
+For reversed direction - relevant bit is set 1.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -33,6 +33,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+ #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
+ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
++#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
+ #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
+ #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
+ #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
+@@ -1184,6 +1185,12 @@ static struct mlxreg_core_data mlxplat_m
+ .bit = 1,
+ .mode = 0444,
+ },
++ {
++ .label = "fan_dir",
++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
++ .bit = GENMASK(7, 0),
++ .mode = 0200,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
+@@ -1307,6 +1314,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
+ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+@@ -1360,6 +1368,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
+ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch
new file mode 100644
index 0000000000..ccf1abfcf7
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch
@@ -0,0 +1,46 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:16 +0000
+Subject: platform/x86: mlx-platform: Add support for new VMOD0007 board name
+Patch-mainline: v5.1-rc1
+Git-commit: e7706a4359f0f172b5f2ab6807f421145041c393
+References: bsc#1112374
+
+Add support for new Mellanox system type MSN3700C, which is
+a cost reduced flavor of the MSN37 system class.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1692,6 +1692,13 @@ static struct dmi_system_id mlxplat_dmi_
+ },
+ },
+ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
++ },
++ },
++ {
+ .callback = mlxplat_dmi_default_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
+@@ -1721,6 +1728,12 @@ static struct dmi_system_id mlxplat_dmi_
+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
+ },
+ },
++ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
++ },
++ },
+ { }
+ };
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch
new file mode 100644
index 0000000000..21dfc3fb4d
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch
@@ -0,0 +1,57 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 18 Mar 2019 10:58:22 +0000
+Subject: platform/x86: mlx-platform: Add support for tachometer speed register
+Patch-mainline: v5.2-rc1
+Git-commit: 584814af9f8ca07cd38e5c554ddd10e85c4e2053
+References: bsc#1112374
+
+Add support for tachometer speed register for the next generation
+systems MQMB7xx, MSN37xx, MSN34xx, MSN38xx.
+
+All these systems support tachometer speed capability register.
+This register is to be provided mlxreg-fan driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -72,6 +72,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
+ #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
+ #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
++#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
+@@ -1339,6 +1340,10 @@ static struct mlxreg_core_data mlxplat_m
+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
+ .bit = BIT(3),
+ },
++ {
++ .label = "conf",
++ .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
+@@ -1428,6 +1433,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1484,6 +1490,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
+ return true;
+ }
+ return false;
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
new file mode 100644
index 0000000000..8b2d814b83
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
@@ -0,0 +1,151 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:58 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for new
+ systems
+Patch-mainline: v5.0-rc1
+Git-commit: e2883859dd0b4ee6fc70151e417fed8680efaa4b
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for the next generation
+systems, in particular for MQM87xx, MSN34xx, MSN37xx types, which have:
+- extended reset causes bits related to ComEx reset, voltage devices
+ firmware upgrade, system platform reset;
+- additional CPLD device;
+- JTAG select capability;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 113 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 113 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1104,6 +1104,118 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
+ };
+
++/* Platform register access for next generation systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld3_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_from_comex",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_comex_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_voltmon_upgrade_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_system",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "jtag_enable",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_ng_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1449,6 +1561,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
new file mode 100644
index 0000000000..5ce8b1dc81
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
@@ -0,0 +1,138 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:01 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for
+ more systems
+Patch-mainline: v4.19-rc1
+Git-commit: 2ac24d336c95fb2525574d4fd46f0673d27464e7
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for more system types, in
+particular for MSN21xx, MSN201x types, which have reset causes bits
+slightly different from the default configuration.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 96 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1008,6 +1008,100 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
++/* Platform register access MSN21xx, MSN201x systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_halt",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
++ .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1293,6 +1387,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
+@@ -1328,6 +1423,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
diff --git a/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch b/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch
new file mode 100644
index 0000000000..45973731be
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch
@@ -0,0 +1,38 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:03 +0000
+Subject: platform/x86: mlx-platform: Change mlxreg-io configuration for
+ MSN274x systems
+Patch-mainline: v4.19-rc1
+Git-commit: da80c7aece1619c2c299432d3d498885ca6d757b
+References: bsc#1112374
+
+Change mlxreg-io platform driver configuration for MSN274x system types
+from the default to MSN21xx.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1008,7 +1008,7 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
+-/* Platform register access MSN21xx, MSN201x systems families data */
++/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */
+ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
+ {
+ .label = "cpld1_version",
+@@ -1405,7 +1405,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+- mlxplat_regs_io = &mlxplat_default_regs_io_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
diff --git a/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch b/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch
new file mode 100644
index 0000000000..77ea7f90d4
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch
@@ -0,0 +1,57 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:27:00 +0000
+Subject: platform/x86: mlx-platform: Convert to use SPDX identifier
+Patch-mainline: v5.0-rc1
+Git-commit: fb7255a923115188ac134bb562d1c44f4f3a413b
+References: bsc#1112374
+
+Reduce size of duplicated comments by switching to use SPDX identifier.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 33 ++++-----------------------------
+ 1 file changed, 4 insertions(+), 29 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1,34 +1,9 @@
++// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+ /*
+- * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
+- * Copyright (c) 2016 Vadim Pasternak <vadimp@mellanox.com>
++ * Mellanox platform driver
+ *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *
+- * 1. Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * 2. Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * 3. Neither the names of the copyright holders nor the names of its
+- * contributors may be used to endorse or promote products derived from
+- * this software without specific prior written permission.
+- *
+- * Alternatively, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") version 2 as published by the Free
+- * Software Foundation.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
++ * Copyright (C) 2016-2018 Mellanox Technologies
++ * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
+ */
+
+ #include <linux/device.h>
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch b/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
new file mode 100644
index 0000000000..61ac2a89be
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
@@ -0,0 +1,43 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:57 +0000
+Subject: platform/x86: mlx-platform: Fix LED configuration
+Patch-mainline: v5.0-rc1
+Git-commit: 440f343df1996302d9a3904647ff11b689bf27bc
+References: bsc#1112374
+
+Exchange LED configuration between msn201x and next generation systems
+types.
+
+Bug was introduced when LED driver activation was added to mlx-platform.
+LED configuration for the three new system MQMB7, MSN37, MSN34 was
+assigned to MSN21 and vice versa. This bug affects MSN21 only and
+likely requires backport to v4.19.
+
+Fixes: 1189456b1cce ("platform/x86: mlx-platform: Add LED platform driver activation")
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1430,7 +1430,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+- mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+@@ -1448,7 +1448,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+- mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_led = &mlxplat_default_ng_led_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch b/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch
new file mode 100644
index 0000000000..31a1e919bd
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch
@@ -0,0 +1,32 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:34 +0000
+Subject: platform/x86: mlx-platform: Fix access mode for fan_dir attribute
+Patch-mainline: v5.1-rc1
+Git-commit: 3ba29326b894e512db9ea7aaa7cb17b235f75d1b
+References: bsc#1112374
+
+Fix access mode for "fan_dir" attribute from "write only" to
+"read only". This attribute is exposed to leds-mlxreg driver.
+The purpose of this attribute is to provide information about FAN
+direction setting on the system (forward or backward).
+It is relevant for the next generation systems MQMB7xx, MSN37xx,
+MSN34xx, MSN38xx.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1240,7 +1240,7 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan_dir",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
+ .bit = GENMASK(7, 0),
+- .mode = 0200,
++ .mode = 0444,
+ },
+ };
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch b/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch
new file mode 100644
index 0000000000..ba9ff3ec8c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch
@@ -0,0 +1,32 @@
+From: Wei Yongjun <weiyongjun1@huawei.com>
+Date: Wed, 8 Aug 2018 04:00:30 +0000
+Subject: platform/x86: mlx-platform: Fix copy-paste error in mlxplat_init()
+Patch-mainline: v4.19-rc1
+Git-commit: 207da7128a6d61a1ce3d052b3dfb10d237af6078
+References: bsc#1112374
+
+The return value from platform_device_register_resndata() is not checked
+correctly. The test is done against a wrong variable. This patch fix it.
+
+Fixes: 0378123c5800 ("platform/x86: mlx-platform: Add mlxreg-fan platform driver activation")
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Acked-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1704,8 +1704,8 @@ static int __init mlxplat_init(void)
+ PLATFORM_DEVID_NONE, NULL, 0,
+ mlxplat_fan,
+ sizeof(*mlxplat_fan));
+- if (IS_ERR(priv->pdev_io_regs)) {
+- err = PTR_ERR(priv->pdev_io_regs);
++ if (IS_ERR(priv->pdev_fan)) {
++ err = PTR_ERR(priv->pdev_fan);
+ goto fail_platform_io_regs_register;
+ }
+ }
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch b/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
new file mode 100644
index 0000000000..8a35b4721c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
@@ -0,0 +1,47 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:56 +0000
+Subject: platform/x86: mlx-platform: Fix tachometer registers
+Patch-mainline: v5.0-rc1
+Git-commit: edd45cba5ed7f53974475ddc9a1453c2c87b3328
+References: bsc#1112374
+
+Shift by one the registers for tachometers (7 - 12).
+
+This fix is relevant for the same new systems MQMB7, MSN37, MSN34,
+which are about to be released to the customers.
+At the moment, none of them is at customers sites. The customers will
+not suffer from this change.
+This fix is necessary, because register used before for tachometer 7
+has been than reserved for the second PWM for newer systems, which are
+not supported yet in mlx-platform driver. So registers of tachometers
+7-12 have been shifted by one.
+
+Fixes: 0378123c5800 ("platform/x86: mlx-platform: Add mlxreg-fan platform driver activation")
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -86,12 +86,12 @@
+ #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
+ #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
+ #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
+-#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xea
+-#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xeb
+-#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xec
+-#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xed
+-#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xee
+-#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xef
++#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb
++#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec
++#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed
++#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
++#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
++#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
diff --git a/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch b/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch
new file mode 100644
index 0000000000..ea1fbb6fb3
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch
@@ -0,0 +1,26 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:04 +0000
+Subject: platform/x86: mlx-platform: Remove unused define
+Patch-mainline: v4.19-rc1
+Git-commit: 0b4e30f49aa44725cbaefa6e839bd82a768c385a
+References: bsc#1112374
+
+Remove unused define MLXPLAT_CPLD_AGGR_MASK_MSN21XX.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -112,7 +112,6 @@
+ #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
+ #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
+ #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
+-#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
+ #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
diff --git a/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch b/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
new file mode 100644
index 0000000000..926797f441
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
@@ -0,0 +1,49 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:55 +0000
+Subject: platform/x86: mlx-platform: Rename new systems product names
+Patch-mainline: v5.0-rc1
+Git-commit: 3752e5c764b4fb1abe43c78f635bf019c8e98db2
+References: bsc#1112374
+
+Rename product names for next generation systems QMB7, SN37, SN34 to
+respectively MQMB7, MSN37, MSN34.
+
+All these systems are about to be released to the customers.
+At the moment, none of them is at customers sites. The customers will
+not suffer from this change.
+The names have been changed due to marketing decision.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1508,21 +1508,21 @@ static struct dmi_system_id mlxplat_dmi_
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "QMB7"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
+ },
+ },
+ {
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "SN37"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
+ },
+ },
+ {
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
+ },
+ },
+ {
diff --git a/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch b/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
new file mode 100644
index 0000000000..585d85d1f3
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
@@ -0,0 +1,36 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:14 +0000
+Subject: platform_data/mlxreg: Add capability field to core platform data
+Patch-mainline: v5.1-rc1
+Git-commit: 946e4e02b11889cb161b15ff4712a8ba21a50eb6
+References: bsc#1112374
+
+Add capability field to "mlxreg_core_platform_data" structure.
+The purpose of this register is to provide additional info to platform
+driver through the atribute related capability register.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -61,6 +61,7 @@ struct mlxreg_hotplug_device {
+ * @reg: attribute register;
+ * @mask: attribute access mask;
+ * @bit: attribute effective bit;
++ * @capability: attribute capability register;
+ * @mode: access mode;
+ * @np - pointer to node platform associated with attribute;
+ * @hpdev - hotplug device data;
+@@ -72,6 +73,7 @@ struct mlxreg_core_data {
+ u32 reg;
+ u32 mask;
+ u32 bit;
++ u32 capability;
+ umode_t mode;
+ struct device_node *np;
+ struct mlxreg_hotplug_device hpdev;
diff --git a/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch b/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
new file mode 100644
index 0000000000..a69295d188
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
@@ -0,0 +1,31 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:13 +0000
+Subject: platform_data/mlxreg: Document fixes for core platform data
+Patch-mainline: v5.1-rc1
+Git-commit: 9b28aa1d0eae1be1016c8f4ba504545caff01da3
+References: bsc#1112374
+
+Remove "led" from the description, since the structure
+"mlxreg_core_platform_data" is used not only for led data.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -107,9 +107,9 @@ struct mlxreg_core_item {
+ /**
+ * struct mlxreg_core_platform_data - platform data:
+ *
+- * @led_data: led private data;
++ * @data: instance private data;
+ * @regmap: register map of parent device;
+- * @counter: number of led instances;
++ * @counter: number of instances;
+ */
+ struct mlxreg_core_platform_data {
+ struct mlxreg_core_data *data;
diff --git a/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch b/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch
new file mode 100644
index 0000000000..820917743e
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch
@@ -0,0 +1,63 @@
+From: Michael Shych <michaelsh@mellanox.com>
+Date: Wed, 20 Feb 2019 09:34:22 +0000
+Subject: platform_data/mlxreg: additions for Mellanox watchdog driver.
+Patch-mainline: v5.1-rc1
+Git-commit: 9f03161a1bd8cd9ccf11533e52326718c656036e
+References: bsc#1112374
+
+There are two new fields added to mlxreg core structure:
+features - supported features of device and
+identity - device identity name.
+Add new defines for watchdog features.
+
+Signed-off-by: Michael Shych <michaelsh@mellanox.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -35,6 +35,19 @@
+ #define __LINUX_PLATFORM_DATA_MLXREG_H
+
+ #define MLXREG_CORE_LABEL_MAX_SIZE 32
++#define MLXREG_CORE_WD_FEATURE_NOWAYOUT BIT(0)
++#define MLXREG_CORE_WD_FEATURE_START_AT_BOOT BIT(1)
++
++/**
++ * enum mlxreg_wdt_type - type of HW watchdog
++ *
++ * TYPE1 HW watchdog implementation exist in old systems.
++ * All new systems have TYPE2 HW watchdog.
++ */
++enum mlxreg_wdt_type {
++ MLX_WDT_TYPE1,
++ MLX_WDT_TYPE2,
++};
+
+ /**
+ * struct mlxreg_hotplug_device - I2C device data:
+@@ -111,12 +124,18 @@ struct mlxreg_core_item {
+ *
+ * @data: instance private data;
+ * @regmap: register map of parent device;
+- * @counter: number of instances;
++ * @counter: number of led instances;
++ * @features: supported features of device;
++ * @version: implementation version;
++ * @identity: device identity name;
+ */
+ struct mlxreg_core_platform_data {
+ struct mlxreg_core_data *data;
+ void *regmap;
+ int counter;
++ u32 features;
++ u32 version;
++ char identity[MLXREG_CORE_LABEL_MAX_SIZE];
+ };
+
+ /**
diff --git a/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main b/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
index 3bb9ba6856..1849004a8d 100644
--- a/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
+++ b/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
@@ -2,7 +2,7 @@ From: Gen Zhang <blackgod016574@gmail.com>
Date: Thu, 30 May 2019 09:10:30 +0800
Subject: scsi: mpt3sas_ctl: fix double-fetch bug in _ctl_ioctl_main()
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git
-Git-commit: 86e5aca7fa2927060839f3e3b40c8bd65a7e8d1e
+Git-commit: f9e3ebeea4521652318af903cddeaf033527e93e
Patch-mainline: Queued in subsystem maintainer repo
References: bsc#1136922 CVE-2019-12456
diff --git a/series.conf b/series.conf
index 391120d760..dd3f36c609 100644
--- a/series.conf
+++ b/series.conf
@@ -8505,6 +8505,7 @@
patches.drivers/ipv6-fib-Add-FIB-notifiers-callbacks.patch
patches.drivers/ipv6-fib-Add-in-kernel-notifications-for-route-add-d.patch
patches.drivers/ipv6-fib-Add-offload-indication-to-routes.patch
+ patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch
patches.drivers/ipv6-fib-Add-helpers-to-hold-drop-a-reference-on-rt6.patch
patches.drivers/mlxsw-spectrum_router-Demultiplex-FIB-event-based-on.patch
patches.drivers/mlxsw-spectrum_router-Sanitize-IPv6-FIB-rules.patch
@@ -34123,6 +34124,8 @@
patches.drivers/platform-x86-dell-wmi-Set-correct-keycode-for-Fn-lef.patch
patches.drivers/platform-x86-asus-wireless-Fix-format-specifier.patch
patches.drivers/platform-mellanox-mlxreg-hotplug-add-extra-cycle-for.patch
+ patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch
+ patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch
patches.drivers/platform-x86-dell-wmi-Ignore-new-rfkill-and-fn-lock-.patch
patches.drivers/platform-x86-dell-laptop-Fix-keyboard-backlight-time.patch
patches.drivers/scsi-aacraid-remove-bogus-GFP_DMA32-specifies.patch
@@ -39205,6 +39208,7 @@
patches.arch/kvm-x86-svm-call-x86_spec_ctrl_set_guest-host-with-interrupts-disabled.patch
patches.arch/kvm-vmx-fixes-for-vmentry_l1d_flush-module-parameter
patches.drivers/platform-mellanox-Introduce-support-for-Mellanox-reg.patch
+ patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
patches.drivers/platform-x86-wmi-Do-not-mix-pages-and-kmalloc.patch
patches.drivers/platform-x86-dell-smbios-base-Support-systems-withou.patch
patches.drivers/platform-x86-ideapad-laptop-Apply-no_hw_rfkill-to-Y2
@@ -39219,8 +39223,14 @@
patches.drivers/platform-x86-thinkpad_acpi-Proper-model-release-matc
patches.drivers/platform-x86-toshiba_acpi-Fix-defined-but-not-used-b.patch
patches.drivers/platform-x86-dell-laptop-Fix-backlight-detection.patch
+ patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch
patches.drivers/platform-mellanox-mlxreg-hotplug-Improve-mechanism-o.patch
patches.drivers/platform-mellanox-mlxreg-hotplug-Add-hotplug-hwmon-u.patch
+ patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
+ patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
+ patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch
+ patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch
+ patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch
patches.drivers/platform-x86-asus-nb-wmi-Add-keymap-entry-for-lid-fl.patch
patches.arch/ARM-hwmod-RTC-Don-t-assume-lock-unlock-will-be-calle.patch
patches.arch/ARM-mvebu-declare-asm-symbols-as-character-arrays-in.patch
@@ -43264,6 +43274,12 @@
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Introduce-IOAPIC-.patch
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Allow-to-have-sam.patch
patches.drivers/0001-ACPI-scan-Create-platform-device-for-INT3515-ACPI-no.patch
+ patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
+ patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
+ patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
+ patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
+ patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
+ patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch
patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
patches.drm/0001-drm-rockchip-psr-do-not-dereference-encoder-before-i.patch
@@ -45508,6 +45524,7 @@
patches.drivers/rtc-88pm80x-fix-unintended-sign-extension.patch
patches.drivers/rtc-pm8xxx-fix-unintended-sign-extension.patch
patches.fixes/0001-backlight-pwm_bl-Use-gpiod_get_value_cansleep-to-get.patch
+ patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch
patches.drivers/gpio-gpio-omap-fix-level-interrupt-idling.patch
patches.drivers/cdrom-Fix-race-condition-in-cdrom_sysctl_register.patch
patches.suse/0275-bcache-never-writeback-a-discard-operation.patch
@@ -45704,6 +45721,11 @@
patches.arch/0003-dma-introduce-dma_max_mapping_size
patches.arch/0004-virtio-introduce-virtio_max_dma_size
patches.arch/0005-virtio-blk-consider-virtio_max_dma_size-for-maximum-segment-size
+ patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
+ patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
+ patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
+ patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
+ patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch
patches.drivers/platform-x86-intel_pmc_core-Handle-CFL-regmap-proper.patch
patches.drivers/platform-x86-intel_pmc_core-Fix-PCH-IP-sts-reading.patch
patches.drivers/platform-x86-intel_pmc_core-Fix-PCH-IP-name.patch
@@ -45715,6 +45737,9 @@
patches.drivers/platform-x86-intel_pmc_core-Add-ICL-platform-support.patch
patches.drivers/platform-x86-intel_pmc_core-Add-Package-cstates-resi.patch
patches.drivers/platform-x86-intel_pmc_core-Quirk-to-ignore-XTAL-shu.patch
+ patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
+ patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch
+ patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch
patches.suse/msft-hv-1855-x86-hyperv-Fix-kernel-panic-when-kexec-on-HyperV.patch
patches.fixes/tools-lib-traceevent-fix-buffer-overflow-in-arg_eval.patch
patches.drivers/tpm-tpm_crb-Avoid-unaligned-reads-in-crb_recv.patch
@@ -45751,6 +45776,7 @@
patches.drivers/pinctrl-sh-pfc-r8a7791-Fix-scifb2_data_c-pin-group.patch
patches.drivers/pinctrl-sh-pfc-r8a7792-Fix-vin1_data18_b-pin-group.patch
patches.drivers/pinctrl-sh-pfc-sh73a0-Fix-fsic_spdif-pin-groups.patch
+ patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch
patches.suse/tracing-do-not-free-iter-trace-in-fail-path-of-tracing_open_pipe.patch
patches.suse/tracing-use-strncpy-instead-of-memcpy-for-string-keys-in-hist-triggers.patch
patches.fixes/0001-xen-pciback-Don-t-disable-PCI_COMMAND-on-PCI-device-.patch
@@ -46400,6 +46426,7 @@
patches.drivers/mmc-core-Verify-SD-bus-width.patch
patches.drivers/mmc-mmci-Prevent-polling-for-busy-detection-in-IRQ-c.patch
patches.drivers/mmc-core-Fix-tag-set-memory-leak.patch
+ patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch
patches.drivers/iio-common-ssp_sensors-Initialize-calculated_time-in.patch
patches.drivers/iio-hmc5843-fix-potential-NULL-pointer-dereferences.patch
patches.drivers/iio-ad_sigma_delta-Properly-handle-SPI-bus-locking-v.patch
@@ -46911,6 +46938,9 @@
patches.drivers/platform-x86-intel_pmc_ipc-adding-error-handling.patch
patches.drivers/platform-x86-intel_pmc_core-Mark-local-function-stat.patch
patches.drivers/platform-x86-intel_punit_ipc-Revert-Fix-resource-ior.patch
+ patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch
+ patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch
+ patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch
patches.drivers/platform-x86-alienware-wmi-printing-the-wrong-error-.patch
patches.drivers/platform-x86-sony-laptop-Fix-unintentional-fall-thro.patch
patches.fixes/vfio-mdev-Avoid-release-parent-reference-during-erro.patch
diff --git a/supported.conf b/supported.conf
index 69a2c59a42..00f215030c 100644
--- a/supported.conf
+++ b/supported.conf
@@ -1883,6 +1883,7 @@
- drivers/platform/x86/msi-wmi
- drivers/platform/mellanox/mlxreg-hotplug
- drivers/platform/mellanox/mlxreg-io
+ drivers/platform/mellanox/mlxbf-tmfifo
- drivers/platform/x86/mlx-platform
- drivers/platform/x86/mxm-wmi
- drivers/platform/x86/panasonic-laptop