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authorJiri Slaby <jslaby@suse.cz>2019-06-21 12:30:55 +0200
committerJiri Slaby <jslaby@suse.cz>2019-06-21 12:32:18 +0200
commit377ae8c7eacac528c159cddc9d48168de62f792a (patch)
tree8a9839af14d4714def03d7e732cd50c0e7a937f2
parent1f7d46c211138150dee6123476ce78ff643e6769 (diff)
x86/cpufeatures: Combine word 11 and 12 into a new scattered
features word (jsc#SLE-5382). This changes definitions of some bits, but they are intended to be used only by the core, so hopefully, no KMP uses the definitions.
-rw-r--r--patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch198
-rw-r--r--series.conf1
2 files changed, 199 insertions, 0 deletions
diff --git a/patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch b/patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch
new file mode 100644
index 0000000000..537db91873
--- /dev/null
+++ b/patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch
@@ -0,0 +1,198 @@
+From: Fenghua Yu <fenghua.yu@intel.com>
+Date: Wed, 19 Jun 2019 18:51:09 +0200
+Subject: x86/cpufeatures: Combine word 11 and 12 into a new scattered features
+ word
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#x86/cpu
+Git-commit: acec0ce081de0c36459eea91647faf99296445a3
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5382
+
+It's a waste for the four X86_FEATURE_CQM_* feature bits to occupy two
+whole feature bits words. To better utilize feature words, re-define
+word 11 to host scattered features and move the four X86_FEATURE_CQM_*
+features into Linux defined word 11. More scattered features can be
+added in word 11 in the future.
+
+Rename leaf 11 in cpuid_leafs to CPUID_LNX_4 to reflect it's a
+Linux-defined leaf.
+
+Rename leaf 12 as CPUID_DUMMY which will be replaced by a meaningful
+name in the next patch when CPUID.7.1:EAX occupies world 12.
+
+Maximum number of RMID and cache occupancy scale are retrieved from
+CPUID.0xf.1 after scattered CQM features are enumerated. Carve out the
+code into a separate function.
+
+KVM doesn't support resctrl now. So it's safe to move the
+X86_FEATURE_CQM_* features to scattered features word 11 for KVM.
+
+Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Aaron Lewis <aaronlewis@google.com>
+Cc: Andy Lutomirski <luto@kernel.org>
+Cc: Babu Moger <babu.moger@amd.com>
+Cc: "Chang S. Bae" <chang.seok.bae@intel.com>
+Cc: "Sean J Christopherson" <sean.j.christopherson@intel.com>
+Cc: Frederic Weisbecker <frederic@kernel.org>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Jann Horn <jannh@google.com>
+Cc: Juergen Gross <jgross@suse.com>
+Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Cc: kvm ML <kvm@vger.kernel.org>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Masami Hiramatsu <mhiramat@kernel.org>
+Cc: Nadav Amit <namit@vmware.com>
+Cc: Paolo Bonzini <pbonzini@redhat.com>
+Cc: Pavel Tatashin <pasha.tatashin@oracle.com>
+Cc: Peter Feiner <pfeiner@google.com>
+Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
+Cc: "Radim Krčmář" <rkrcmar@redhat.com>
+Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
+Cc: Ravi V Shankar <ravi.v.shankar@intel.com>
+Cc: Sherry Hurwitz <sherry.hurwitz@amd.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
+Cc: x86 <x86@kernel.org>
+Link: https://lkml.kernel.org/r/1560794416-217638-2-git-send-email-fenghua.yu@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/include/asm/cpufeature.h | 4 +--
+ arch/x86/include/asm/cpufeatures.h | 17 ++++++++------
+ arch/x86/kernel/cpu/common.c | 42 ++++++++++++++-----------------------
+ arch/x86/kernel/cpu/cpuid-deps.c | 3 ++
+ arch/x86/kernel/cpu/scattered.c | 4 +++
+ arch/x86/kvm/cpuid.h | 2 -
+ 6 files changed, 36 insertions(+), 36 deletions(-)
+
+--- a/arch/x86/include/asm/cpufeature.h
++++ b/arch/x86/include/asm/cpufeature.h
+@@ -21,8 +21,8 @@ enum cpuid_leafs
+ CPUID_LNX_3,
+ CPUID_7_0_EBX,
+ CPUID_D_1_EAX,
+- CPUID_F_0_EDX,
+- CPUID_F_1_EDX,
++ CPUID_LNX_4,
++ CPUID_DUMMY,
+ CPUID_8000_0008_EBX,
+ CPUID_6_EAX,
+ CPUID_8000_000A_EDX,
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -270,13 +270,16 @@
+ #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
+ #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
+
+-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
+-#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
+-
+-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
+-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
+-#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
+-#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
++/*
++ * Extended auxiliary flags: Linux defined - for features scattered in various
++ * CPUID levels like 0xf, etc.
++ *
++ * Reuse free bits when adding new feature flags!
++ */
++#define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
++#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
++#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
++#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
+
+ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -770,33 +770,25 @@ static void init_speculation_control(str
+
+ static void init_cqm(struct cpuinfo_x86 *c)
+ {
+- u32 eax, ebx, ecx, edx;
++ if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
++ c->x86_cache_max_rmid = -1;
++ c->x86_cache_occ_scale = -1;
++ return;
++ }
++
++ /* will be overridden if occupancy monitoring exists */
++ c->x86_cache_max_rmid = cpuid_ebx(0xf);
++
++ if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
++ cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
++ cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
++ u32 eax, ebx, ecx, edx;
+
+- /* Additional Intel-defined flags: level 0x0000000F */
+- if (c->cpuid_level >= 0x0000000F) {
++ /* QoS sub-leaf, EAX=0Fh, ECX=1 */
++ cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
+
+- /* QoS sub-leaf, EAX=0Fh, ECX=0 */
+- cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
+- c->x86_capability[CPUID_F_0_EDX] = edx;
+-
+- if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
+- /* will be overridden if occupancy monitoring exists */
+- c->x86_cache_max_rmid = ebx;
+-
+- /* QoS sub-leaf, EAX=0Fh, ECX=1 */
+- cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
+- c->x86_capability[CPUID_F_1_EDX] = edx;
+-
+- if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
+- ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
+- (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
+- c->x86_cache_max_rmid = ecx;
+- c->x86_cache_occ_scale = ebx;
+- }
+- } else {
+- c->x86_cache_max_rmid = -1;
+- c->x86_cache_occ_scale = -1;
+- }
++ c->x86_cache_max_rmid = ecx;
++ c->x86_cache_occ_scale = ebx;
+ }
+ }
+
+--- a/arch/x86/kernel/cpu/cpuid-deps.c
++++ b/arch/x86/kernel/cpu/cpuid-deps.c
+@@ -59,6 +59,9 @@ const static struct cpuid_dep cpuid_deps
+ { X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
+ { X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
+ { X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
++ { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
++ { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
++ { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
+ {}
+ };
+
+--- a/arch/x86/kernel/cpu/scattered.c
++++ b/arch/x86/kernel/cpu/scattered.c
+@@ -21,6 +21,10 @@ struct cpuid_bit {
+ static const struct cpuid_bit cpuid_bits[] = {
+ { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
+ { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
++ { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
++ { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
++ { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
++ { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
+ { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
+ { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
+ { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
+--- a/arch/x86/kvm/cpuid.h
++++ b/arch/x86/kvm/cpuid.h
+@@ -46,8 +46,6 @@ static const struct cpuid_reg reverse_cp
+ [CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX},
+ [CPUID_7_0_EBX] = { 7, 0, CPUID_EBX},
+ [CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX},
+- [CPUID_F_0_EDX] = { 0xf, 0, CPUID_EDX},
+- [CPUID_F_1_EDX] = { 0xf, 1, CPUID_EDX},
+ [CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX},
+ [CPUID_6_EAX] = { 6, 0, CPUID_EAX},
+ [CPUID_8000_000A_EDX] = {0x8000000a, 0, CPUID_EDX},
diff --git a/series.conf b/series.conf
index 1023352531..13f4a5d1b3 100644
--- a/series.conf
+++ b/series.conf
@@ -22666,6 +22666,7 @@
# tip/tip x86/cpu
patches.suse/x86-cpufeatures-Carve-out-CQM-features-retrieval.patch
+ patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch
########################################################
#