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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:21 +0200
commit42725a714c1abda4307f6c9b8bbaa12b01103d89 (patch)
tree3a4a54fd4f5cdc24dc5c162d15ee2b330caeea0d
parentbe2f98724ef865e522ae51544954351fd51c9a63 (diff)
platform/x86: mlx-platform: Add mlxreg-io platform driver
activation (bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch350
-rw-r--r--series.conf1
2 files changed, 351 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
new file mode 100644
index 0000000000..f5ed364ac1
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
@@ -0,0 +1,350 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Sun, 17 Jun 2018 16:56:54 +0000
+Subject: platform/x86: mlx-platform: Add mlxreg-io platform driver activation
+Patch-mainline: v4.19-rc1
+Git-commit: 8871f5e4234112f02b8afe1000c18f49827c8d01
+References: bsc#1112374
+
+Add mlxreg-io platform driver activation. Access driver uses the same
+regmap infrastructure as others Mellanox platform drivers.
+Specific registers description for default platform data configuration are
+added to mlx-platform. There are the registers for resets control, reset
+causes monitoring, programmable devices version reading and mux select
+control. This platform data is passed to mlxreg-io driver. Also some
+default values for the register are set at initialization time through
+the regmap infrastructure, which are necessary for moving write protection
+from the general purpose registers, which are used by mlxreg-io for
+write access.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+v4-v5:
+ Changes added by Vadim:
+ - Add two new attributes for ASIC health and main power domain shutdown.
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 175 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 173 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -47,15 +47,23 @@
+ /* LPC bus IO offsets */
+ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
++#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
++#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+ #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
+ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
++#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
++#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
++#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
++#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
++#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
+ #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
+ #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
+@@ -122,12 +130,14 @@
+ * @pdev_mux - array of mux platform devices
+ * @pdev_hotplug - hotplug platform devices
+ * @pdev_led - led platform devices
++ * @pdev_io_regs - register access platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+ struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
+ struct platform_device *pdev_hotplug;
+ struct platform_device *pdev_led;
++ struct platform_device *pdev_io_regs;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -813,6 +823,111 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
+ };
+
++/* Platform register access default */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_fw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_wd",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "select_iio",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = GENMASK(1, 0),
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
++};
+
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+@@ -822,6 +937,10 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+@@ -838,15 +957,23 @@ static bool mlxplat_mlxcpld_writeable_re
+ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -864,15 +991,21 @@ static bool mlxplat_mlxcpld_readable_reg
+ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -887,6 +1020,11 @@ static bool mlxplat_mlxcpld_volatile_reg
+ return false;
+ }
+
++static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
++ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
++};
++
+ struct mlxplat_mlxcpld_regmap_context {
+ void __iomem *base;
+ };
+@@ -919,6 +1057,8 @@ static const struct regmap_config mlxpla
+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
+ .readable_reg = mlxplat_mlxcpld_readable_reg,
+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
++ .reg_defaults = mlxplat_mlxcpld_regmap_default,
++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
+ .reg_read = mlxplat_mlxcpld_reg_read,
+ .reg_write = mlxplat_mlxcpld_reg_write,
+ };
+@@ -930,6 +1070,7 @@ static struct resource mlxplat_mlxcpld_r
+ static struct platform_device *mlxplat_dev;
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
+ static struct mlxreg_core_platform_data *mlxplat_led;
++static struct mlxreg_core_platform_data *mlxplat_regs_io;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -944,6 +1085,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -978,6 +1120,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -1163,7 +1306,7 @@ static int mlxplat_mlxcpld_verify_bus_to
+ static int __init mlxplat_init(void)
+ {
+ struct mlxplat_priv *priv;
+- int i, nr, err;
++ int i, j, nr, err;
+
+ if (!dmi_check_system(mlxplat_dmi_table))
+ return -ENODEV;
+@@ -1233,6 +1376,15 @@ static int __init mlxplat_init(void)
+ goto fail_platform_mux_register;
+ }
+
++ /* Set default registers. */
++ for (j = 0; j < mlxplat_mlxcpld_regmap_config.num_reg_defaults; j++) {
++ err = regmap_write(mlxplat_hotplug->regmap,
++ mlxplat_mlxcpld_regmap_default[j].reg,
++ mlxplat_mlxcpld_regmap_default[j].def);
++ if (err)
++ goto fail_platform_mux_register;
++ }
++
+ /* Add LED driver. */
+ mlxplat_led->regmap = mlxplat_hotplug->regmap;
+ priv->pdev_led = platform_device_register_resndata(
+@@ -1244,14 +1396,31 @@ static int __init mlxplat_init(void)
+ goto fail_platform_hotplug_register;
+ }
+
++ /* Add registers io access driver. */
++ if (mlxplat_regs_io) {
++ mlxplat_regs_io->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_io_regs = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlxreg-io",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_regs_io,
++ sizeof(*mlxplat_regs_io));
++ if (IS_ERR(priv->pdev_io_regs)) {
++ err = PTR_ERR(priv->pdev_io_regs);
++ goto fail_platform_led_register;
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_led_register;
++ goto fail_platform_io_regs_register;
+
+ return 0;
+
++fail_platform_io_regs_register:
++ if (mlxplat_regs_io)
++ platform_device_unregister(priv->pdev_io_regs);
+ fail_platform_led_register:
+ platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+@@ -1272,6 +1441,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ if (priv->pdev_io_regs)
++ platform_device_unregister(priv->pdev_io_regs);
+ platform_device_unregister(priv->pdev_led);
+ platform_device_unregister(priv->pdev_hotplug);
+
diff --git a/series.conf b/series.conf
index f87b4a721d..88e93fc2e0 100644
--- a/series.conf
+++ b/series.conf
@@ -39208,6 +39208,7 @@
patches.arch/kvm-x86-svm-call-x86_spec_ctrl_set_guest-host-with-interrupts-disabled.patch
patches.arch/kvm-vmx-fixes-for-vmentry_l1d_flush-module-parameter
patches.drivers/platform-mellanox-Introduce-support-for-Mellanox-reg.patch
+ patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
patches.drivers/platform-x86-wmi-Do-not-mix-pages-and-kmalloc.patch
patches.drivers/platform-x86-dell-smbios-base-Support-systems-withou.patch
patches.drivers/platform-x86-ideapad-laptop-Apply-no_hw_rfkill-to-Y2