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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:04:13 +0200
commit78365f26a9ac9ee12f42f5282e77e76409ddfe7b (patch)
tree3439d1842779940e2452c405ae07564831f9265e
parent658c85feb02664bf83856356646e65f23854fc74 (diff)
platform/x86: mlx-platform: Allow mlxreg-io driver activation
for new systems (bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch151
-rw-r--r--series.conf1
2 files changed, 152 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
new file mode 100644
index 0000000000..8b2d814b83
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
@@ -0,0 +1,151 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:58 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for new
+ systems
+Patch-mainline: v5.0-rc1
+Git-commit: e2883859dd0b4ee6fc70151e417fed8680efaa4b
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for the next generation
+systems, in particular for MQM87xx, MSN34xx, MSN37xx types, which have:
+- extended reset causes bits related to ComEx reset, voltage devices
+ firmware upgrade, system platform reset;
+- additional CPLD device;
+- JTAG select capability;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 113 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 113 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1104,6 +1104,118 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
+ };
+
++/* Platform register access for next generation systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld3_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_from_comex",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_comex_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_voltmon_upgrade_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_system",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "jtag_enable",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_ng_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1449,6 +1561,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
diff --git a/series.conf b/series.conf
index 12e1ec71bf..e71fff2a49 100644
--- a/series.conf
+++ b/series.conf
@@ -43276,6 +43276,7 @@
patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
+ patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
patches.drm/0001-drm-rockchip-psr-do-not-dereference-encoder-before-i.patch