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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:35 +0200
commita89b9c0d45af9a63005b7270a9a1e8b9f17b1920 (patch)
tree767a4d3da07f4213fa8c310e351b21f9962cebc1
parent6295e50dee5dd8980c2937a6afc149906f4fd03c (diff)
platform/x86: mlx-platform: Allow mlxreg-io driver activation
for more systems (bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch138
-rw-r--r--series.conf1
2 files changed, 139 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
new file mode 100644
index 0000000000..5ce8b1dc81
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
@@ -0,0 +1,138 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:01 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for
+ more systems
+Patch-mainline: v4.19-rc1
+Git-commit: 2ac24d336c95fb2525574d4fd46f0673d27464e7
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for more system types, in
+particular for MSN21xx, MSN201x types, which have reset causes bits
+slightly different from the default configuration.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 96 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1008,6 +1008,100 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
++/* Platform register access MSN21xx, MSN201x systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_halt",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
++ .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1293,6 +1387,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
+@@ -1328,6 +1423,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
diff --git a/series.conf b/series.conf
index f498439f64..068d880f93 100644
--- a/series.conf
+++ b/series.conf
@@ -39227,6 +39227,7 @@
patches.drivers/platform-mellanox-mlxreg-hotplug-Improve-mechanism-o.patch
patches.drivers/platform-mellanox-mlxreg-hotplug-Add-hotplug-hwmon-u.patch
patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
+ patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
patches.drivers/platform-x86-asus-nb-wmi-Add-keymap-entry-for-lid-fl.patch
patches.arch/ARM-hwmod-RTC-Don-t-assume-lock-unlock-will-be-calle.patch
patches.arch/ARM-mvebu-declare-asm-symbols-as-character-arrays-in.patch