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authorJiri Slaby <jslaby@suse.cz>2019-06-21 12:30:55 +0200
committerJiri Slaby <jslaby@suse.cz>2019-06-21 12:33:46 +0200
commitaa0aabb3877c140d32f53a4f0b272361119ea8fc (patch)
tree63d85f3d9026be84b5f70afdda347039c9ef5afb
parent377ae8c7eacac528c159cddc9d48168de62f792a (diff)
x86/cpufeatures: Enumerate the new AVX512 BFLOAT16 instructions
(jsc#SLE-5382).
-rw-r--r--patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch109
-rw-r--r--series.conf1
2 files changed, 110 insertions, 0 deletions
diff --git a/patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch b/patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch
new file mode 100644
index 0000000000..37ef2ab272
--- /dev/null
+++ b/patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch
@@ -0,0 +1,109 @@
+From: Fenghua Yu <fenghua.yu@intel.com>
+Date: Mon, 17 Jun 2019 11:00:16 -0700
+Subject: x86/cpufeatures: Enumerate the new AVX512 BFLOAT16 instructions
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#x86/cpu
+Git-commit: b302e4b176d00e1cbc80148c5d0aee36751f7480
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5382
+
+AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
+format (BF16) for deep learning optimization.
+
+BF16 is a short version of 32-bit single-precision floating-point
+format (FP32) and has several advantages over 16-bit half-precision
+floating-point format (FP16). BF16 keeps FP32 accumulation after
+multiplication without loss of precision, offers more than enough
+range for deep learning training tasks, and doesn't need to handle
+hardware exception.
+
+AVX512 BFLOAT16 instructions are enumerated in CPUID.7.1:EAX[bit 5]
+AVX512_BF16.
+
+CPUID.7.1:EAX contains only feature bits. Reuse the currently empty
+word 12 as a pure features word to hold the feature bits including
+AVX512_BF16.
+
+Detailed information of the CPUID bit and AVX512 BFLOAT16 instructions
+can be found in the latest Intel Architecture Instruction Set Extensions
+and Future Features Programming Reference.
+
+ [ bp: Check CPUID(7) subleaf validity before accessing subleaf 1. ]
+
+Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: "Chang S. Bae" <chang.seok.bae@intel.com>
+Cc: Frederic Weisbecker <frederic@kernel.org>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Jann Horn <jannh@google.com>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Michael Ellerman <mpe@ellerman.id.au>
+Cc: Nadav Amit <namit@vmware.com>
+Cc: Paolo Bonzini <pbonzini@redhat.com>
+Cc: Pavel Tatashin <pasha.tatashin@oracle.com>
+Cc: Peter Feiner <pfeiner@google.com>
+Cc: Radim Krcmar <rkrcmar@redhat.com>
+Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
+Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
+Cc: Robert Hoo <robert.hu@linux.intel.com>
+Cc: "Sean J Christopherson" <sean.j.christopherson@intel.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
+Cc: x86 <x86@kernel.org>
+Link: https://lkml.kernel.org/r/1560794416-217638-3-git-send-email-fenghua.yu@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/include/asm/cpufeature.h | 2 +-
+ arch/x86/include/asm/cpufeatures.h | 3 +++
+ arch/x86/kernel/cpu/common.c | 6 ++++++
+ arch/x86/kernel/cpu/cpuid-deps.c | 1 +
+ 4 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/arch/x86/include/asm/cpufeature.h
++++ b/arch/x86/include/asm/cpufeature.h
+@@ -22,7 +22,7 @@ enum cpuid_leafs
+ CPUID_7_0_EBX,
+ CPUID_D_1_EAX,
+ CPUID_LNX_4,
+- CPUID_DUMMY,
++ CPUID_7_1_EAX,
+ CPUID_8000_0008_EBX,
+ CPUID_6_EAX,
+ CPUID_8000_000A_EDX,
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -281,6 +281,9 @@
+ #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
+ #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
+
++/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
++#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
++
+ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
+ #define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -814,6 +814,12 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
+ c->x86_capability[CPUID_7_0_EBX] = ebx;
+ c->x86_capability[CPUID_7_ECX] = ecx;
+ c->x86_capability[CPUID_7_EDX] = edx;
++
++ /* Check valid sub-leaf index before accessing it */
++ if (eax >= 1) {
++ cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
++ c->x86_capability[CPUID_7_1_EAX] = eax;
++ }
+ }
+
+ /* Extended state features: level 0x0000000d */
+--- a/arch/x86/kernel/cpu/cpuid-deps.c
++++ b/arch/x86/kernel/cpu/cpuid-deps.c
+@@ -62,6 +62,7 @@ const static struct cpuid_dep cpuid_deps
+ { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
+ { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
+ { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
++ { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL },
+ {}
+ };
+
diff --git a/series.conf b/series.conf
index 13f4a5d1b3..364b77f39c 100644
--- a/series.conf
+++ b/series.conf
@@ -22667,6 +22667,7 @@
# tip/tip x86/cpu
patches.suse/x86-cpufeatures-Carve-out-CQM-features-retrieval.patch
patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch
+ patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch
########################################################
#