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authorThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:06 +0200
committerThomas Bogendoerfer <tbogendoerfer@suse.de>2019-06-19 18:03:54 +0200
commite6094e4b3aa0319f748578db49aa5209b6e4d942 (patch)
treed804a17f30c7050fce82ed3ebd8808004aeb55e1
parent08cc6e4701f20c2e62e6bc6236265519f93a73b8 (diff)
platform/x86: mlx-platform: Add definitions for new registers
(bsc#1112374).
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch54
-rw-r--r--series.conf1
2 files changed, 55 insertions, 0 deletions
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
new file mode 100644
index 0000000000..c28060b3ee
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
@@ -0,0 +1,54 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:54 +0000
+Subject: platform/x86: mlx-platform: Add definitions for new registers
+Patch-mainline: v5.0-rc1
+Git-commit: 59e96ec85e8e59170f6d5cba028e199a2e5dfe67
+References: bsc#1112374
+
+Add definitions for new registers:
+- CPLD3 version - next generation systems are equipped with three CPLD;
+- Two reset cause registers, which store the system reset reason (like
+ system failures, upgrade failures and so on;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -49,7 +49,10 @@
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+@@ -1208,7 +1211,10 @@ static bool mlxplat_mlxcpld_readable_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+@@ -1258,7 +1264,10 @@ static bool mlxplat_mlxcpld_volatile_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
diff --git a/series.conf b/series.conf
index 03caddcfdb..429a7b78e2 100644
--- a/series.conf
+++ b/series.conf
@@ -43272,6 +43272,7 @@
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Introduce-IOAPIC-.patch
patches.drivers/0001-platform-x86-i2c-multi-instantiate-Allow-to-have-sam.patch
patches.drivers/0001-ACPI-scan-Create-platform-device-for-INT3515-ACPI-no.patch
+ patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
patches.drm/0049-drm-v3d-Fix-a-use-after-free-race-accessing-the-sche.patch
patches.drm/0050-drm-v3d-Skip-debugfs-dumping-GCA-on-platforms-withou.patch
patches.drm/0001-drm-rockchip-psr-do-not-dereference-encoder-before-i.patch