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authorTakashi Iwai <tiwai@suse.de>2018-07-26 20:49:00 +0200
committerTakashi Iwai <tiwai@suse.de>2018-07-26 20:49:55 +0200
commit4b2acbbbb0ec506a31bd549c42f1f18bbb5fb0fd (patch)
treeda61dd984ede78eb328f5c477da80b7fc54c5981
parent2dc7c107857a659a8c9b2b785f789aa96a1d86b1 (diff)
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
(bsc#1051510).
-rw-r--r--patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI68
-rw-r--r--series.conf1
2 files changed, 69 insertions, 0 deletions
diff --git a/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI b/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
new file mode 100644
index 0000000000..59a1f00107
--- /dev/null
+++ b/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
@@ -0,0 +1,68 @@
+From a982e45dc150da3a08907b6dd676b735391704b4 Mon Sep 17 00:00:00 2001
+From: Marcin Ziemianowicz <marcin@ziemianowicz.com>
+Date: Sun, 29 Apr 2018 15:01:11 -0400
+Subject: [PATCH] clk: at91: PLL recalc_rate() now using cached MUL and DIV values
+Git-commit: a982e45dc150da3a08907b6dd676b735391704b4
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+When a USB device is connected to the USB host port on the SAM9N12 then
+you get "-62" error which seems to indicate USB replies from the device
+are timing out. Based on a logic sniffer, I saw the USB bus was running
+at half speed.
+
+The PLL code uses cached MUL and DIV values which get set in set_rate()
+and applied in prepare(), but the recalc_rate() function instead
+queries the hardware instead of using these cached values. Therefore,
+if recalc_rate() is called between a set_rate() and prepare(), the
+wrong frequency is calculated and later the USB clock divider for the
+SAM9N12 SOC will be configured for an incorrect clock.
+
+In my case, the PLL hardware was set to 96 Mhz before the OHCI
+driver loads, and therefore the usb clock divider was being set
+to /2 even though the OHCI driver set the PLL to 48 Mhz.
+
+As an alternative explanation, I noticed this was fixed in the past by
+87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
+driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
+At91: make use of syscon/regmap internally").
+
+Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com>
+Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/at91/clk-pll.c | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
+index 7d3223fc7161..72b6091eb7b9 100644
+--- a/drivers/clk/at91/clk-pll.c
++++ b/drivers/clk/at91/clk-pll.c
+@@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
+ struct clk_pll *pll = to_clk_pll(hw);
+- unsigned int pllr;
+- u16 mul;
+- u8 div;
+-
+- regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
+-
+- div = PLL_DIV(pllr);
+- mul = PLL_MUL(pllr, pll->layout);
+-
+- if (!div || !mul)
+- return 0;
+
+- return (parent_rate / div) * (mul + 1);
++ return (parent_rate / pll->div) * (pll->mul + 1);
+ }
+
+ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+--
+2.18.0
+
diff --git a/series.conf b/series.conf
index e976488a92..8ae39a015c 100644
--- a/series.conf
+++ b/series.conf
@@ -14572,6 +14572,7 @@
patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency
patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent
patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND
+ patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
patches.drivers/scsi-lpfc-fix-multiple-prli-completion-error-path.patch
patches.drivers/scsi-lpfc-correct-target-queue-depth-application-changes.patch
patches.drivers/scsi-lpfc-add-per-io-channel-nvme-io-statistics.patch