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authorTakashi Iwai <tiwai@suse.de>2019-05-13 14:59:58 +0200
committerTakashi Iwai <tiwai@suse.de>2019-05-15 11:46:07 +0200
commit61795dbb49a7ede40acbfb95f4fbd2b71f3d5350 (patch)
treea4a73fc78abe5a8591832cdbae957c899d1833be
parent5935cd64b2f3ad86c3996ac98eafdb5101227075 (diff)
drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
(bsc#1111666).
-rw-r--r--patches.drm/drm-i915-icl-Whitelist-GEN9_SLICE_COMMON_ECO_CHICKEN.patch59
-rw-r--r--series.conf1
2 files changed, 60 insertions, 0 deletions
diff --git a/patches.drm/drm-i915-icl-Whitelist-GEN9_SLICE_COMMON_ECO_CHICKEN.patch b/patches.drm/drm-i915-icl-Whitelist-GEN9_SLICE_COMMON_ECO_CHICKEN.patch
new file mode 100644
index 0000000000..80a942f2a1
--- /dev/null
+++ b/patches.drm/drm-i915-icl-Whitelist-GEN9_SLICE_COMMON_ECO_CHICKEN.patch
@@ -0,0 +1,59 @@
+From 9628e15ca9d5f7595ba886173e98a139d0a56cd1 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Thu, 18 Apr 2019 11:06:34 +0100
+Subject: [PATCH] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
+Git-commit: 9628e15ca9d5f7595ba886173e98a139d0a56cd1
+Patch-mainline: v5.2-rc1
+No-fix: 0fc2273b9ab7f07cdef448e99525e481535e1ab0
+References: bsc#1111666
+
+WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
+to benefit 3d workloads but media has different requirements.
+
+Remove the workaround and whitelist the register to allow any userspace
+configure the behaviour to their liking.
+
+V2: * Remove the workaround apart from adding the whitelist.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Cc: kevin.ma@intel.com
+Cc: xiaogang.li@intel.com
+Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190418100634.984-1-tvrtko.ursulin@linux.intel.com
+Fixes: f63c7b4880aa ("drm/i915/icl: WaEnableStateCacheRedirectToCS")
+Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+[tursulin: Anuj reported no GPU hangs or performance regressions with old Mesa on patched kernel.]
+(cherry picked from commit 0fc2273b9ab7f07cdef448e99525e481535e1ab0)
+
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_workarounds.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_workarounds.c
++++ b/drivers/gpu/drm/i915/intel_workarounds.c
+@@ -513,10 +513,6 @@ static int icl_ctx_workarounds_init(stru
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
+- /* WaEnableStateCacheRedirectToCS:icl */
+- WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+- GEN11_STATE_CACHE_REDIRECT_TO_CS);
+-
+ /* Wa_2006665173:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+@@ -1071,6 +1067,9 @@ static void icl_whitelist_build(struct w
+
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
++
++ /* WaEnableStateCacheRedirectToCS:icl */
++ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+ }
+
+ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
diff --git a/series.conf b/series.conf
index d6df8504d6..725277d72b 100644
--- a/series.conf
+++ b/series.conf
@@ -45670,6 +45670,7 @@
patches.drm/drm-fb-helper-generic-Call-drm_client_add-after-setu.patch
patches.drm/drm-vmwgfx-Remove-set-but-not-used-variable-restart.patch
patches.drm/drm-tegra-gem-Fix-CPU-cache-maintenance-for-BO-s-all.patch
+ patches.drm/drm-i915-icl-Whitelist-GEN9_SLICE_COMMON_ECO_CHICKEN.patch
patches.drivers/ALSA-hda-realtek-Support-low-power-consumption-for-A.patch
patches.drivers/ALSA-hda-realtek-Support-low-power-consumption-ALC256.patch