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authorPetr Tesarik <ptesarik@suse.cz>2019-01-11 15:39:28 +0100
committerPetr Tesarik <ptesarik@suse.cz>2019-01-11 15:39:28 +0100
commitb1541d1a8a56f224b1619daf88de749cbbe21b9a (patch)
tree03123a20374745e6f6d892ef92ed3224b7b32f46
parentc0878c5953e346ba26b077f7ab234552864b7d59 (diff)
parenta9353983e3ca6840ed988fc732884832d6406454 (diff)
Merge branch 'users/tzimmermann/SLE15-SP1/for-next' into SLE15-SP1
Pull DRM fixes from Thomas Zimmermann
-rw-r--r--blacklist.conf71
-rw-r--r--patches.drm/0001-fbdev-omapfb-remove-unused-variable.patch40
-rw-r--r--patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch46
-rw-r--r--patches.drm/0006-dt-bindings-remove-file-that-was-added-accidentally.patch918
-rw-r--r--patches.drm/0008-dt-bindings-display-panel-Fix-compatible-string-for-.patch41
-rw-r--r--patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch284
-rw-r--r--patches.drm/0031-dma-buf-Remove-requirement-for-ops-map-from-dma_buf_.patch36
-rw-r--r--patches.drm/0033-drm-panel-Fix-sphinx-warning.patch43
-rw-r--r--patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch41
-rw-r--r--patches.drm/0038-drm-i915-psr-Remove-wait_for_idle-for-PSR2.patch72
-rw-r--r--series.conf9
11 files changed, 1559 insertions, 42 deletions
diff --git a/blacklist.conf b/blacklist.conf
index 0f3f3f1e0d..35d2aaf778 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -847,50 +847,37 @@ e8f74a0f00113d74ac18d6de13096f9e2f95618a # only needed with CONFIG_SCSI=n
a37fb855f6e8e9eafac046721393f68f48eb5f91 # not applicable
ec9efb523cb8daf7b9d2e5c9cb80b255b716a777 # not applicable
f1782c9bc547754f4bd3043fe8cfda53db85f13f # userspace visible changes, lots of fixups needed
+5e0594fd77e0d4dfd728898814da43a065094ae0 # Does not apply; significant differences
+544c5048bcdc5d5c395d99d61ab7a52964a1420b # Duplicate of cb1dab0e01969d63717c7464cb5d75c77a39bf02
+50f365cde4ffb5ae70c3f02384bbb46698aba65c # Duplicate of e073db5c5d7ad311efa8f4192a2047b006bbc5f3
+9987da4b5dcfc8b94b702d4bb94b30955eb73c75 # Duplicate of fd50fbb6bfdea5daa4ae4dd7b7082485ac44bdf5
+29d384e34c55d696cf37bd4159e05f4b14d45da0 # Duplicate of c5bd1fc9a6c843c85a5cea5765cdc997f832df3c
+1fe699e30113ed6f6e853ff44710d256072ea627 # Duplicate of 4c83f0a788ccf58864f781585d8ae7c7e6a7e07d
+1e6aa7e55c28ecd842b8b4599e4273c2429ee061 # Duplicate of 84d4ebdb6c72988a1acddb1856b12427a287149d
+a59b3c80fd0041223ccf720504974a543b81b1d0 # Duplicate of b5e3241316973b9f01228d2fa5b8b2bb157d44aa
+eed7ec52f214bac2f25395ccaad610fbeb842a6e # Duplicate of 38057aa1639b74d5c1e0dc1ca7c22bc7a31de714
+bd4cd03c81010dcd4e6f0e02e4c15f44aefe12d1 # Duplicate of 660d88e74cf6e16252e366616f158d84dc9dc6a3
+96d4f03c20d04c80026b1ec3643c090cf4f0eb20 # Duplicate of dd166fbd8d468eae7a6e8f7adab4dd1e22b1a780
+84b510e22da7926522a257cfe295d3695346a0bd # Duplicate of 540ead8c5a0e2910fc7bf0839982921c8f11b31c
+20d4ac659c76034586a3ab79489b0940631a65de # Duplicate of 20fa2ff0441eabc8e6263b428191228d9599ea9d
+f619794d716c0615241b73a0a5e78dbc8442de7b # Duplicate of 72cb0d893343cd33e6ab62cf26f2625d5d3532c9
+012d79e6a33f095c293fe2a02b2b3b26d8c6402c # Duplicate of 47541443a62a278f0a0f9a03c5403cb15bd62ded
+c46ef57d2008e5195f086a538550488b49644db7 # Duplicate of 2f08b23d70324bb0f592c71bd36cdc1d2f12face
+6ceb7277173597eeed8d635e08db51e35235ab21 # Duplicate of 197af5f2131101f9a6118b238901cb1988f5d7f9
+467d35789e5a4f47428b65ef711b30fdabbb0fd4 # Duplicate of a5bfcdf0e16b33c1690ded31f863466136480ddc
+e4dd27aadd205417a2e9ea9902b698a0252ec3a0 # Duplicate of 541ab84d2b6ea79021d5df0b54d81600334fa2a4
+7a72c78bdd0a1ea1d879610542679cc680398220 # Duplicate of 656921a51244b72cd1105df61b0af15825bddb72
+60548c554be2830d29d2533dad0ac8133347ee51 # Duplicate of 027063b1606fea6df15c270e5f2a072d1dfa8fef
+7b5ee80a5da3ea44c5abff48e3621135ae9d8177 # Duplicate of 3012ea60c57dbdf21206c7e787d6d0cde76a18a7
+a4417b7b419a68540ad7945ac4efbb39d19afa63 # Duplicate of f013027e266553effa3e9d9d62236ae5ee3b25e7
+b1f1c2c11fc6c6cd3e361061e30f9b2839897b28 # Duplicate of 5b2695fd4b20f9b8320e9ecbfc232842bacf5b6f
+62d3a8deaa10b8346d979d0dabde56c33b742afa # Duplicate of 1b1b1162745e5f9e5c6c095afc8081df3edabc50
+3cf71bc9904d7ee4a25a822c5dcb54c7804ea388 # Duplicate of 399334708b4f07b107094e5db4a390f0f25d2d4f
+5df52391ddbed869c7d67b00fbb013bd64334115 # Duplicate of 4fe967912ee83048beb45a6b4f0f6774fddcfa0a
+3b5cf4ef541f1b2facaca58cae5e8e0b5f19ad4c # Duplicate of 2b82435cb90bed2c5f8398730d964dd11602217c
+7a90938332d80faf973fbcffdf6e674e7b8f0914 # Duplicate of 4ca8ca9fe7dc792000c3762de5081a4d6dc33667
# temporarily blacklisted for the DRM backport
-7b4dfbe7880cf2092db3c94c6a34ae6ffa8aa344
-5e0594fd77e0d4dfd728898814da43a065094ae0
-544c5048bcdc5d5c395d99d61ab7a52964a1420b
-cda77556447c782b3c9c068f81ef58136cb487c3
-50f365cde4ffb5ae70c3f02384bbb46698aba65c
-98ecf1a308977505381b5c360b039a84cf67513c
-9987da4b5dcfc8b94b702d4bb94b30955eb73c75
-81ee6f1ef9b1e93b2dc0a77211e9809ffbeb7ecb
-29d384e34c55d696cf37bd4159e05f4b14d45da0
-1fe699e30113ed6f6e853ff44710d256072ea627
-c77a6edb6d4d35204673cad7389c317bfb17492e
-1e6aa7e55c28ecd842b8b4599e4273c2429ee061
-a59b3c80fd0041223ccf720504974a543b81b1d0
-eed7ec52f214bac2f25395ccaad610fbeb842a6e
-8cd1b5bd70cccda6854088825e725a513ec919c6
-bd4cd03c81010dcd4e6f0e02e4c15f44aefe12d1
-96d4f03c20d04c80026b1ec3643c090cf4f0eb20
-84b510e22da7926522a257cfe295d3695346a0bd
-20d4ac659c76034586a3ab79489b0940631a65de
-f619794d716c0615241b73a0a5e78dbc8442de7b
-012d79e6a33f095c293fe2a02b2b3b26d8c6402c
-c46ef57d2008e5195f086a538550488b49644db7
-6ceb7277173597eeed8d635e08db51e35235ab21
-467d35789e5a4f47428b65ef711b30fdabbb0fd4
-e4dd27aadd205417a2e9ea9902b698a0252ec3a0
-57cb54e53bddb59f5f542ddd4b0bfe005d31a8d5
-7a72c78bdd0a1ea1d879610542679cc680398220
-dd18cedfa36fbbc19903aed12d6d94c06f5e6dea
-60548c554be2830d29d2533dad0ac8133347ee51
-7b5ee80a5da3ea44c5abff48e3621135ae9d8177
-f82aab2d521e4c1d4f9f98450b4a9a8abeaff1c4
-a4417b7b419a68540ad7945ac4efbb39d19afa63
-3eb3cd04e2d8cd930c7caa8d9e57f1c964792b6e
-b1f1c2c11fc6c6cd3e361061e30f9b2839897b28
-62d3a8deaa10b8346d979d0dabde56c33b742afa
-3cf71bc9904d7ee4a25a822c5dcb54c7804ea388
-ff30e9e8509cb877dc7cbc776b36c70f5bdd290f
-fd255f6e3704d183f6f5011efd01fcda70372cab
-5df52391ddbed869c7d67b00fbb013bd64334115
-2b5cf4ef541f1b2facaca58cae5e8e0b5f19ad4c
-37a3a98ef601f89100e3bb657fb0e190b857028c
-7a90938332d80faf973fbcffdf6e674e7b8f0914
47658556da857c66c5865f192408639f524cca40
2c043eeffea4813b8f569e84b46035a08de5eb47
6969019f65b43afb6da6a26f1d9e55bbdfeebcd5
diff --git a/patches.drm/0001-fbdev-omapfb-remove-unused-variable.patch b/patches.drm/0001-fbdev-omapfb-remove-unused-variable.patch
new file mode 100644
index 0000000000..fe360eaa6e
--- /dev/null
+++ b/patches.drm/0001-fbdev-omapfb-remove-unused-variable.patch
@@ -0,0 +1,40 @@
+From 7b4dfbe7880cf2092db3c94c6a34ae6ffa8aa344 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Mon, 31 Jul 2017 18:45:41 +0200
+Subject: fbdev: omapfb: remove unused variable
+Git-commit: 7b4dfbe7880cf2092db3c94c6a34ae6ffa8aa344
+Patch-mainline: v4.13-rc5
+References: bsc#1113956
+
+Removing the default display name left a harmless warning:
+
+fbdev/omap2/omapfb/dss/core.c: In function 'omap_dss_probe':
+fbdev/omap2/omapfb/dss/core.c:196:30: error: unused variable 'pdata' [-Werror=unused-variable]
+
+This removes the now-unused variable as well.
+
+Fixes: 278cba7eaf54 ("drm: omapdrm: Remove unused default display name support")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/video/fbdev/omap2/omapfb/dss/core.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/video/fbdev/omap2/omapfb/dss/core.c b/drivers/video/fbdev/omap2/omapfb/dss/core.c
+index eecf695c16f4..09e5bb013d28 100644
+--- a/drivers/video/fbdev/omap2/omapfb/dss/core.c
++++ b/drivers/video/fbdev/omap2/omapfb/dss/core.c
+@@ -193,7 +193,6 @@ static struct notifier_block omap_dss_pm_notif_block = {
+
+ static int __init omap_dss_probe(struct platform_device *pdev)
+ {
+- struct omap_dss_board_info *pdata = pdev->dev.platform_data;
+ int r;
+
+ core.pdev = pdev;
+--
+2.20.1
+
diff --git a/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch b/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
new file mode 100644
index 0000000000..5cffff80fc
--- /dev/null
+++ b/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
@@ -0,0 +1,46 @@
+From cda77556447c782b3c9c068f81ef58136cb487c3 Mon Sep 17 00:00:00 2001
+From: Philipp Zabel <p.zabel@pengutronix.de>
+Date: Tue, 10 Oct 2017 15:13:55 +0200
+Subject: gpu: ipu-v3: Allow channel burst locking on i.MX6 only
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: cda77556447c782b3c9c068f81ef58136cb487c3
+Patch-mainline: v4.14-rc5
+References: bsc#1113956
+
+The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
+i.MX53 enabling the lock feature causes bursts to get lost. Restrict
+enabling the burst lock feature to i.MX6.
+
+Reported-by: Patrick Brünn <P.Bruenn@beckhoff.com>
+Fixes: 790cb4c7c954 ("drm/imx: lock scanout transfers for consecutive bursts")
+Tested-by: Patrick Brünn <P.Bruenn@beckhoff.com>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/ipu-v3/ipu-common.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
+index 6a573d21d3cc..658fa2d3e40c 100644
+--- a/drivers/gpu/ipu-v3/ipu-common.c
++++ b/drivers/gpu/ipu-v3/ipu-common.c
+@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
+ return -EINVAL;
+ }
+
++ /*
++ * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
++ * i.MX53 channel arbitration locking doesn't seem to work properly.
++ * Allow enabling the lock feature on IPUv3H / i.MX6 only.
++ */
++ if (bursts && ipu->ipu_type != IPUV3H)
++ return -EINVAL;
++
+ for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
+ if (channel->num == idmac_lock_en_info[i].chnum)
+ break;
+--
+2.20.1
+
diff --git a/patches.drm/0006-dt-bindings-remove-file-that-was-added-accidentally.patch b/patches.drm/0006-dt-bindings-remove-file-that-was-added-accidentally.patch
new file mode 100644
index 0000000000..b4eba01626
--- /dev/null
+++ b/patches.drm/0006-dt-bindings-remove-file-that-was-added-accidentally.patch
@@ -0,0 +1,918 @@
+From 98ecf1a308977505381b5c360b039a84cf67513c Mon Sep 17 00:00:00 2001
+From: Rob Clark <robdclark@gmail.com>
+Date: Thu, 16 Nov 2017 09:05:57 -0500
+Subject: dt-bindings: remove file that was added accidentally
+Git-commit: 98ecf1a308977505381b5c360b039a84cf67513c
+Patch-mainline: v4.15-rc1
+References: bsc#1113956
+
+I think this snuck in when I applied the patch for f97decac5f4c (didn't
+apply cleanly, required some manual applying + git-add). It is unused
+and shouldn't be here. My bad.
+
+Fixes: f97decac5f4c "drm/msm: Support multiple ringbuffers"
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ include/dt-bindings/msm/msm-bus-ids.h | 887 --------------------------
+ 1 file changed, 887 deletions(-)
+ delete mode 100644 include/dt-bindings/msm/msm-bus-ids.h
+
+diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
+deleted file mode 100644
+index a75d304473d5..000000000000
+--- a/include/dt-bindings/msm/msm-bus-ids.h
++++ /dev/null
+@@ -1,887 +0,0 @@
+-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 and
+- * only version 2 as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- */
+-
+-#ifndef __MSM_BUS_IDS_H
+-#define __MSM_BUS_IDS_H
+-
+-/* Aggregation types */
+-#define AGG_SCHEME_NONE 0
+-#define AGG_SCHEME_LEG 1
+-#define AGG_SCHEME_1 2
+-
+-/* Topology related enums */
+-#define MSM_BUS_FAB_DEFAULT 0
+-#define MSM_BUS_FAB_APPSS 0
+-#define MSM_BUS_FAB_SYSTEM 1024
+-#define MSM_BUS_FAB_MMSS 2048
+-#define MSM_BUS_FAB_SYSTEM_FPB 3072
+-#define MSM_BUS_FAB_CPSS_FPB 4096
+-
+-#define MSM_BUS_FAB_BIMC 0
+-#define MSM_BUS_FAB_SYS_NOC 1024
+-#define MSM_BUS_FAB_MMSS_NOC 2048
+-#define MSM_BUS_FAB_OCMEM_NOC 3072
+-#define MSM_BUS_FAB_PERIPH_NOC 4096
+-#define MSM_BUS_FAB_CONFIG_NOC 5120
+-#define MSM_BUS_FAB_OCMEM_VNOC 6144
+-#define MSM_BUS_FAB_MMSS_AHB 2049
+-#define MSM_BUS_FAB_A0_NOC 6145
+-#define MSM_BUS_FAB_A1_NOC 6146
+-#define MSM_BUS_FAB_A2_NOC 6147
+-#define MSM_BUS_FAB_GNOC 6148
+-#define MSM_BUS_FAB_CR_VIRT 6149
+-
+-#define MSM_BUS_MASTER_FIRST 1
+-#define MSM_BUS_MASTER_AMPSS_M0 1
+-#define MSM_BUS_MASTER_AMPSS_M1 2
+-#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
+-#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
+-#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
+-#define MSM_BUS_MASTER_SPS 6
+-#define MSM_BUS_MASTER_ADM_PORT0 7
+-#define MSM_BUS_MASTER_ADM_PORT1 8
+-#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
+-#define MSM_BUS_MASTER_ADM1_PORT1 10
+-#define MSM_BUS_MASTER_LPASS_PROC 11
+-#define MSM_BUS_MASTER_MSS_PROCI 12
+-#define MSM_BUS_MASTER_MSS_PROCD 13
+-#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
+-#define MSM_BUS_MASTER_LPASS 15
+-#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
+-#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
+-#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
+-#define MSM_BUS_MASTER_ADM1_CI 19
+-#define MSM_BUS_MASTER_ADM0_CI 20
+-#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
+-#define MSM_BUS_MASTER_MDP_PORT0 22
+-#define MSM_BUS_MASTER_MDP_PORT1 23
+-#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
+-#define MSM_BUS_MASTER_ROTATOR 25
+-#define MSM_BUS_MASTER_GRAPHICS_3D 26
+-#define MSM_BUS_MASTER_JPEG_DEC 27
+-#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
+-#define MSM_BUS_MASTER_VFE 29
+-#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE
+-#define MSM_BUS_MASTER_VPE 30
+-#define MSM_BUS_MASTER_JPEG_ENC 31
+-#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
+-#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
+-#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
+-#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
+-#define MSM_BUS_MASTER_SPDM 36
+-#define MSM_BUS_MASTER_RPM 37
+-#define MSM_BUS_MASTER_MSS 38
+-#define MSM_BUS_MASTER_RIVA 39
+-#define MSM_BUS_MASTER_SNOC_VMEM 40
+-#define MSM_BUS_MASTER_MSS_SW_PROC 41
+-#define MSM_BUS_MASTER_MSS_FW_PROC 42
+-#define MSM_BUS_MASTER_HMSS 43
+-#define MSM_BUS_MASTER_GSS_NAV 44
+-#define MSM_BUS_MASTER_PCIE 45
+-#define MSM_BUS_MASTER_SATA 46
+-#define MSM_BUS_MASTER_CRYPTO 47
+-#define MSM_BUS_MASTER_VIDEO_CAP 48
+-#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
+-#define MSM_BUS_MASTER_VIDEO_ENC 50
+-#define MSM_BUS_MASTER_VIDEO_DEC 51
+-#define MSM_BUS_MASTER_LPASS_AHB 52
+-#define MSM_BUS_MASTER_QDSS_BAM 53
+-#define MSM_BUS_MASTER_SNOC_CFG 54
+-#define MSM_BUS_MASTER_CRYPTO_CORE0 55
+-#define MSM_BUS_MASTER_CRYPTO_CORE1 56
+-#define MSM_BUS_MASTER_MSS_NAV 57
+-#define MSM_BUS_MASTER_OCMEM_DMA 58
+-#define MSM_BUS_MASTER_WCSS 59
+-#define MSM_BUS_MASTER_QDSS_ETR 60
+-#define MSM_BUS_MASTER_USB3 61
+-#define MSM_BUS_MASTER_JPEG 62
+-#define MSM_BUS_MASTER_VIDEO_P0 63
+-#define MSM_BUS_MASTER_VIDEO_P1 64
+-#define MSM_BUS_MASTER_MSS_PROC 65
+-#define MSM_BUS_MASTER_JPEG_OCMEM 66
+-#define MSM_BUS_MASTER_MDP_OCMEM 67
+-#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
+-#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
+-#define MSM_BUS_MASTER_VFE_OCMEM 70
+-#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
+-#define MSM_BUS_MASTER_RPM_INST 72
+-#define MSM_BUS_MASTER_RPM_DATA 73
+-#define MSM_BUS_MASTER_RPM_SYS 74
+-#define MSM_BUS_MASTER_DEHR 75
+-#define MSM_BUS_MASTER_QDSS_DAP 76
+-#define MSM_BUS_MASTER_TIC 77
+-#define MSM_BUS_MASTER_SDCC_1 78
+-#define MSM_BUS_MASTER_SDCC_3 79
+-#define MSM_BUS_MASTER_SDCC_4 80
+-#define MSM_BUS_MASTER_SDCC_2 81
+-#define MSM_BUS_MASTER_TSIF 82
+-#define MSM_BUS_MASTER_BAM_DMA 83
+-#define MSM_BUS_MASTER_BLSP_2 84
+-#define MSM_BUS_MASTER_USB_HSIC 85
+-#define MSM_BUS_MASTER_BLSP_1 86
+-#define MSM_BUS_MASTER_USB_HS 87
+-#define MSM_BUS_MASTER_PNOC_CFG 88
+-#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
+-#define MSM_BUS_MASTER_IPA 90
+-#define MSM_BUS_MASTER_QPIC 91
+-#define MSM_BUS_MASTER_MDPE 92
+-#define MSM_BUS_MASTER_USB_HS2 93
+-#define MSM_BUS_MASTER_VPU 94
+-#define MSM_BUS_MASTER_UFS 95
+-#define MSM_BUS_MASTER_BCAST 96
+-#define MSM_BUS_MASTER_CRYPTO_CORE2 97
+-#define MSM_BUS_MASTER_EMAC 98
+-#define MSM_BUS_MASTER_VPU_1 99
+-#define MSM_BUS_MASTER_PCIE_1 100
+-#define MSM_BUS_MASTER_USB3_1 101
+-#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
+-#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
+-#define MSM_BUS_MASTER_TCU_0 104
+-#define MSM_BUS_MASTER_TCU_1 105
+-#define MSM_BUS_MASTER_CPP 106
+-#define MSM_BUS_MASTER_AUDIO 107
+-#define MSM_BUS_MASTER_PCIE_2 108
+-#define MSM_BUS_MASTER_VFE1 109
+-#define MSM_BUS_MASTER_XM_USB_HS1 110
+-#define MSM_BUS_MASTER_PCNOC_BIMC_1 111
+-#define MSM_BUS_MASTER_BIMC_PCNOC 112
+-#define MSM_BUS_MASTER_XI_USB_HSIC 113
+-#define MSM_BUS_MASTER_SGMII 114
+-#define MSM_BUS_SPMI_FETCHER 115
+-#define MSM_BUS_MASTER_GNOC_BIMC 116
+-#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
+-#define MSM_BUS_MASTER_CNOC_A2NOC 118
+-#define MSM_BUS_MASTER_WLAN 119
+-#define MSM_BUS_MASTER_MSS_CE 120
+-#define MSM_BUS_MASTER_CDSP_PROC 121
+-#define MSM_BUS_MASTER_GNOC_SNOC 122
+-#define MSM_BUS_MASTER_PIMEM 123
+-#define MSM_BUS_MASTER_MASTER_LAST 124
+-
+-#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
+-#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
+-
+-#define MSM_BUS_SNOC_MM_INT_0 10000
+-#define MSM_BUS_SNOC_MM_INT_1 10001
+-#define MSM_BUS_SNOC_MM_INT_2 10002
+-#define MSM_BUS_SNOC_MM_INT_BIMC 10003
+-#define MSM_BUS_SNOC_INT_0 10004
+-#define MSM_BUS_SNOC_INT_1 10005
+-#define MSM_BUS_SNOC_INT_BIMC 10006
+-#define MSM_BUS_SNOC_BIMC_0_MAS 10007
+-#define MSM_BUS_SNOC_BIMC_1_MAS 10008
+-#define MSM_BUS_SNOC_QDSS_INT 10009
+-#define MSM_BUS_PNOC_SNOC_MAS 10010
+-#define MSM_BUS_PNOC_SNOC_SLV 10011
+-#define MSM_BUS_PNOC_INT_0 10012
+-#define MSM_BUS_PNOC_INT_1 10013
+-#define MSM_BUS_PNOC_M_0 10014
+-#define MSM_BUS_PNOC_M_1 10015
+-#define MSM_BUS_BIMC_SNOC_MAS 10016
+-#define MSM_BUS_BIMC_SNOC_SLV 10017
+-#define MSM_BUS_PNOC_SLV_0 10018
+-#define MSM_BUS_PNOC_SLV_1 10019
+-#define MSM_BUS_PNOC_SLV_2 10020
+-#define MSM_BUS_PNOC_SLV_3 10021
+-#define MSM_BUS_PNOC_SLV_4 10022
+-#define MSM_BUS_PNOC_SLV_8 10023
+-#define MSM_BUS_PNOC_SLV_9 10024
+-#define MSM_BUS_SNOC_BIMC_0_SLV 10025
+-#define MSM_BUS_SNOC_BIMC_1_SLV 10026
+-#define MSM_BUS_MNOC_BIMC_MAS 10027
+-#define MSM_BUS_MNOC_BIMC_SLV 10028
+-#define MSM_BUS_BIMC_MNOC_MAS 10029
+-#define MSM_BUS_BIMC_MNOC_SLV 10030
+-#define MSM_BUS_SNOC_BIMC_MAS 10031
+-#define MSM_BUS_SNOC_BIMC_SLV 10032
+-#define MSM_BUS_CNOC_SNOC_MAS 10033
+-#define MSM_BUS_CNOC_SNOC_SLV 10034
+-#define MSM_BUS_SNOC_CNOC_MAS 10035
+-#define MSM_BUS_SNOC_CNOC_SLV 10036
+-#define MSM_BUS_OVNOC_SNOC_MAS 10037
+-#define MSM_BUS_OVNOC_SNOC_SLV 10038
+-#define MSM_BUS_SNOC_OVNOC_MAS 10039
+-#define MSM_BUS_SNOC_OVNOC_SLV 10040
+-#define MSM_BUS_SNOC_PNOC_MAS 10041
+-#define MSM_BUS_SNOC_PNOC_SLV 10042
+-#define MSM_BUS_BIMC_INT_APPS_EBI 10043
+-#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
+-#define MSM_BUS_SNOC_BIMC_2_MAS 10045
+-#define MSM_BUS_SNOC_BIMC_2_SLV 10046
+-#define MSM_BUS_PNOC_SLV_5 10047
+-#define MSM_BUS_PNOC_SLV_7 10048
+-#define MSM_BUS_PNOC_INT_2 10049
+-#define MSM_BUS_PNOC_INT_3 10050
+-#define MSM_BUS_PNOC_INT_4 10051
+-#define MSM_BUS_PNOC_INT_5 10052
+-#define MSM_BUS_PNOC_INT_6 10053
+-#define MSM_BUS_PNOC_INT_7 10054
+-#define MSM_BUS_BIMC_SNOC_1_MAS 10055
+-#define MSM_BUS_BIMC_SNOC_1_SLV 10056
+-#define MSM_BUS_PNOC_A1NOC_MAS 10057
+-#define MSM_BUS_PNOC_A1NOC_SLV 10058
+-#define MSM_BUS_CNOC_A1NOC_MAS 10059
+-#define MSM_BUS_A0NOC_SNOC_MAS 10060
+-#define MSM_BUS_A0NOC_SNOC_SLV 10061
+-#define MSM_BUS_A1NOC_SNOC_SLV 10062
+-#define MSM_BUS_A1NOC_SNOC_MAS 10063
+-#define MSM_BUS_A2NOC_SNOC_MAS 10064
+-#define MSM_BUS_A2NOC_SNOC_SLV 10065
+-#define MSM_BUS_SNOC_INT_2 10066
+-#define MSM_BUS_A0NOC_QDSS_INT 10067
+-#define MSM_BUS_INT_LAST 10068
+-
+-#define MSM_BUS_INT_TEST_ID 20000
+-#define MSM_BUS_INT_TEST_LAST 20050
+-
+-#define MSM_BUS_SLAVE_FIRST 512
+-#define MSM_BUS_SLAVE_EBI_CH0 512
+-#define MSM_BUS_SLAVE_EBI_CH1 513
+-#define MSM_BUS_SLAVE_AMPSS_L2 514
+-#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
+-#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
+-#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
+-#define MSM_BUS_SLAVE_SPS 518
+-#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
+-#define MSM_BUS_SLAVE_AMPSS 520
+-#define MSM_BUS_SLAVE_MSS 521
+-#define MSM_BUS_SLAVE_LPASS 522
+-#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
+-#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
+-#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
+-#define MSM_BUS_SLAVE_CORESIGHT 526
+-#define MSM_BUS_SLAVE_RIVA 527
+-#define MSM_BUS_SLAVE_SMI 528
+-#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
+-#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
+-#define MSM_BUS_SLAVE_MM_IMEM 531
+-#define MSM_BUS_SLAVE_CRYPTO 532
+-#define MSM_BUS_SLAVE_SPDM 533
+-#define MSM_BUS_SLAVE_RPM 534
+-#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
+-#define MSM_BUS_SLAVE_MPM 536
+-#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
+-#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
+-#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
+-#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
+-#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
+-#define MSM_BUS_SLAVE_GSBI1_UART 542
+-#define MSM_BUS_SLAVE_GSBI2_UART 543
+-#define MSM_BUS_SLAVE_GSBI3_UART 544
+-#define MSM_BUS_SLAVE_GSBI4_UART 545
+-#define MSM_BUS_SLAVE_GSBI5_UART 546
+-#define MSM_BUS_SLAVE_GSBI6_UART 547
+-#define MSM_BUS_SLAVE_GSBI7_UART 548
+-#define MSM_BUS_SLAVE_GSBI8_UART 549
+-#define MSM_BUS_SLAVE_GSBI9_UART 550
+-#define MSM_BUS_SLAVE_GSBI10_UART 551
+-#define MSM_BUS_SLAVE_GSBI11_UART 552
+-#define MSM_BUS_SLAVE_GSBI12_UART 553
+-#define MSM_BUS_SLAVE_GSBI1_QUP 554
+-#define MSM_BUS_SLAVE_GSBI2_QUP 555
+-#define MSM_BUS_SLAVE_GSBI3_QUP 556
+-#define MSM_BUS_SLAVE_GSBI4_QUP 557
+-#define MSM_BUS_SLAVE_GSBI5_QUP 558
+-#define MSM_BUS_SLAVE_GSBI6_QUP 559
+-#define MSM_BUS_SLAVE_GSBI7_QUP 560
+-#define MSM_BUS_SLAVE_GSBI8_QUP 561
+-#define MSM_BUS_SLAVE_GSBI9_QUP 562
+-#define MSM_BUS_SLAVE_GSBI10_QUP 563
+-#define MSM_BUS_SLAVE_GSBI11_QUP 564
+-#define MSM_BUS_SLAVE_GSBI12_QUP 565
+-#define MSM_BUS_SLAVE_EBI2_NAND 566
+-#define MSM_BUS_SLAVE_EBI2_CS0 567
+-#define MSM_BUS_SLAVE_EBI2_CS1 568
+-#define MSM_BUS_SLAVE_EBI2_CS2 569
+-#define MSM_BUS_SLAVE_EBI2_CS3 570
+-#define MSM_BUS_SLAVE_EBI2_CS4 571
+-#define MSM_BUS_SLAVE_EBI2_CS5 572
+-#define MSM_BUS_SLAVE_USB_FS1 573
+-#define MSM_BUS_SLAVE_USB_FS2 574
+-#define MSM_BUS_SLAVE_TSIF 575
+-#define MSM_BUS_SLAVE_MSM_TSSC 576
+-#define MSM_BUS_SLAVE_MSM_PDM 577
+-#define MSM_BUS_SLAVE_MSM_DIMEM 578
+-#define MSM_BUS_SLAVE_MSM_TCSR 579
+-#define MSM_BUS_SLAVE_MSM_PRNG 580
+-#define MSM_BUS_SLAVE_GSS 581
+-#define MSM_BUS_SLAVE_SATA 582
+-#define MSM_BUS_SLAVE_USB3 583
+-#define MSM_BUS_SLAVE_WCSS 584
+-#define MSM_BUS_SLAVE_OCIMEM 585
+-#define MSM_BUS_SLAVE_SNOC_OCMEM 586
+-#define MSM_BUS_SLAVE_SERVICE_SNOC 587
+-#define MSM_BUS_SLAVE_QDSS_STM 588
+-#define MSM_BUS_SLAVE_CAMERA_CFG 589
+-#define MSM_BUS_SLAVE_DISPLAY_CFG 590
+-#define MSM_BUS_SLAVE_OCMEM_CFG 591
+-#define MSM_BUS_SLAVE_CPR_CFG 592
+-#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
+-#define MSM_BUS_SLAVE_MISC_CFG 594
+-#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
+-#define MSM_BUS_SLAVE_VENUS_CFG 596
+-#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
+-#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
+-#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
+-#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
+-#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
+-#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
+-#define MSM_BUS_SLAVE_SERVICE_MNOC 603
+-#define MSM_BUS_SLAVE_OCMEM 604
+-#define MSM_BUS_SLAVE_SERVICE_ONOC 605
+-#define MSM_BUS_SLAVE_SDCC_1 606
+-#define MSM_BUS_SLAVE_SDCC_3 607
+-#define MSM_BUS_SLAVE_SDCC_2 608
+-#define MSM_BUS_SLAVE_SDCC_4 609
+-#define MSM_BUS_SLAVE_BAM_DMA 610
+-#define MSM_BUS_SLAVE_BLSP_2 611
+-#define MSM_BUS_SLAVE_USB_HSIC 612
+-#define MSM_BUS_SLAVE_BLSP_1 613
+-#define MSM_BUS_SLAVE_USB_HS 614
+-#define MSM_BUS_SLAVE_PDM 615
+-#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
+-#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
+-#define MSM_BUS_SLAVE_PRNG 618
+-#define MSM_BUS_SLAVE_SERVICE_PNOC 619
+-#define MSM_BUS_SLAVE_CLK_CTL 620
+-#define MSM_BUS_SLAVE_CNOC_MSS 621
+-#define MSM_BUS_SLAVE_SECURITY 622
+-#define MSM_BUS_SLAVE_TCSR 623
+-#define MSM_BUS_SLAVE_TLMM 624
+-#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
+-#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
+-#define MSM_BUS_SLAVE_IMEM_CFG 627
+-#define MSM_BUS_SLAVE_MESSAGE_RAM 628
+-#define MSM_BUS_SLAVE_BIMC_CFG 629
+-#define MSM_BUS_SLAVE_BOOT_ROM 630
+-#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
+-#define MSM_BUS_SLAVE_PMIC_ARB 632
+-#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
+-#define MSM_BUS_SLAVE_DEHR_CFG 634
+-#define MSM_BUS_SLAVE_QDSS_CFG 635
+-#define MSM_BUS_SLAVE_RBCPR_CFG 636
+-#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
+-#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
+-#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
+-#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
+-#define MSM_BUS_SLAVE_PNOC_CFG 641
+-#define MSM_BUS_SLAVE_SNOC_CFG 642
+-#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
+-#define MSM_BUS_SLAVE_PHY_APU_CFG 644
+-#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
+-#define MSM_BUS_SLAVE_SERVICE_CNOC 646
+-#define MSM_BUS_SLAVE_IPS_CFG 647
+-#define MSM_BUS_SLAVE_QPIC 648
+-#define MSM_BUS_SLAVE_DSI_CFG 649
+-#define MSM_BUS_SLAVE_UFS_CFG 650
+-#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
+-#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
+-#define MSM_BUS_SLAVE_PCIE_CFG 653
+-#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
+-#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
+-#define MSM_BUS_SLAVE_AVSYNC_CFG 656
+-#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
+-#define MSM_BUS_SLAVE_VPU_CFG 658
+-#define MSM_BUS_SLAVE_BCAST_CFG 659
+-#define MSM_BUS_SLAVE_KLM_CFG 660
+-#define MSM_BUS_SLAVE_GENI_IR_CFG 661
+-#define MSM_BUS_SLAVE_OCMEM_GFX 662
+-#define MSM_BUS_SLAVE_CATS_128 663
+-#define MSM_BUS_SLAVE_OCMEM_64 664
+-#define MSM_BUS_SLAVE_PCIE_0 665
+-#define MSM_BUS_SLAVE_PCIE_1 666
+-#define MSM_BUS_SLAVE_PCIE_0_CFG 667
+-#define MSM_BUS_SLAVE_PCIE_1_CFG 668
+-#define MSM_BUS_SLAVE_SRVC_MNOC 669
+-#define MSM_BUS_SLAVE_USB_HS2 670
+-#define MSM_BUS_SLAVE_AUDIO 671
+-#define MSM_BUS_SLAVE_TCU 672
+-#define MSM_BUS_SLAVE_APPSS 673
+-#define MSM_BUS_SLAVE_PCIE_PARF 674
+-#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
+-#define MSM_BUS_SLAVE_IPA_CFG 676
+-#define MSM_BUS_SLAVE_A0NOC_SNOC 677
+-#define MSM_BUS_SLAVE_A1NOC_SNOC 678
+-#define MSM_BUS_SLAVE_A2NOC_SNOC 679
+-#define MSM_BUS_SLAVE_HMSS_L3 680
+-#define MSM_BUS_SLAVE_PIMEM_CFG 681
+-#define MSM_BUS_SLAVE_DCC_CFG 682
+-#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
+-#define MSM_BUS_SLAVE_PCIE_2_CFG 684
+-#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
+-#define MSM_BUS_SLAVE_A0NOC_CFG 686
+-#define MSM_BUS_SLAVE_A1NOC_CFG 687
+-#define MSM_BUS_SLAVE_A2NOC_CFG 688
+-#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
+-#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
+-#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
+-#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
+-#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
+-#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
+-#define MSM_BUS_SLAVE_MMAGIC_CFG 695
+-#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
+-#define MSM_BUS_SLAVE_SSC_CFG 697
+-#define MSM_BUS_SLAVE_DSA_CFG 698
+-#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
+-#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
+-#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
+-#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
+-#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
+-#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
+-#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
+-#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
+-#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
+-#define MSM_BUS_SLAVE_VMEM_CFG 708
+-#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709
+-#define MSM_BUS_SLAVE_VMEM 710
+-#define MSM_BUS_SLAVE_AHB2PHY 711
+-#define MSM_BUS_SLAVE_PIMEM 712
+-#define MSM_BUS_SLAVE_SNOC_VMEM 713
+-#define MSM_BUS_SLAVE_PCIE_2 714
+-#define MSM_BUS_SLAVE_RBCPR_MX 715
+-#define MSM_BUS_SLAVE_RBCPR_CX 716
+-#define MSM_BUS_SLAVE_BIMC_PCNOC 717
+-#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
+-#define MSM_BUS_SLAVE_SGMII 719
+-#define MSM_BUS_SLAVE_SPMI_FETCHER 720
+-#define MSM_BUS_PNOC_SLV_6 721
+-#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
+-#define MSM_BUS_SLAVE_WLAN 723
+-#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
+-#define MSM_BUS_SLAVE_CNOC_A2NOC 725
+-#define MSM_BUS_SLAVE_GLM 726
+-#define MSM_BUS_SLAVE_GNOC_BIMC 727
+-#define MSM_BUS_SLAVE_GNOC_SNOC 728
+-#define MSM_BUS_SLAVE_QM_CFG 729
+-#define MSM_BUS_SLAVE_TLMM_EAST 730
+-#define MSM_BUS_SLAVE_TLMM_NORTH 731
+-#define MSM_BUS_SLAVE_TLMM_WEST 732
+-#define MSM_BUS_SLAVE_SKL 733
+-#define MSM_BUS_SLAVE_LPASS_TCM 734
+-#define MSM_BUS_SLAVE_TLMM_SOUTH 735
+-#define MSM_BUS_SLAVE_TLMM_CENTER 736
+-#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737
+-#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738
+-#define MSM_BUS_SLAVE_CDSP 739
+-#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740
+-#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741
+-#define MSM_BUS_SLAVE_CSI_PHY_CFG 742
+-#define MSM_BUS_SLAVE_LAST 743
+-
+-#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
+-#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
+-
+-/*
+- * ID's used in RPM messages
+- */
+-#define ICBID_MASTER_APPSS_PROC 0
+-#define ICBID_MASTER_MSS_PROC 1
+-#define ICBID_MASTER_MNOC_BIMC 2
+-#define ICBID_MASTER_SNOC_BIMC 3
+-#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
+-#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
+-#define ICBID_MASTER_CNOC_MNOC_CFG 5
+-#define ICBID_MASTER_GFX3D 6
+-#define ICBID_MASTER_JPEG 7
+-#define ICBID_MASTER_MDP 8
+-#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
+-#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
+-#define ICBID_MASTER_VIDEO 9
+-#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
+-#define ICBID_MASTER_VIDEO_P1 10
+-#define ICBID_MASTER_VFE 11
+-#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
+-#define ICBID_MASTER_CNOC_ONOC_CFG 12
+-#define ICBID_MASTER_JPEG_OCMEM 13
+-#define ICBID_MASTER_MDP_OCMEM 14
+-#define ICBID_MASTER_VIDEO_P0_OCMEM 15
+-#define ICBID_MASTER_VIDEO_P1_OCMEM 16
+-#define ICBID_MASTER_VFE_OCMEM 17
+-#define ICBID_MASTER_LPASS_AHB 18
+-#define ICBID_MASTER_QDSS_BAM 19
+-#define ICBID_MASTER_SNOC_CFG 20
+-#define ICBID_MASTER_BIMC_SNOC 21
+-#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
+-#define ICBID_MASTER_CNOC_SNOC 22
+-#define ICBID_MASTER_CRYPTO 23
+-#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
+-#define ICBID_MASTER_CRYPTO_CORE1 24
+-#define ICBID_MASTER_LPASS_PROC 25
+-#define ICBID_MASTER_MSS 26
+-#define ICBID_MASTER_MSS_NAV 27
+-#define ICBID_MASTER_OCMEM_DMA 28
+-#define ICBID_MASTER_PNOC_SNOC 29
+-#define ICBID_MASTER_WCSS 30
+-#define ICBID_MASTER_QDSS_ETR 31
+-#define ICBID_MASTER_USB3 32
+-#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
+-#define ICBID_MASTER_SDCC_1 33
+-#define ICBID_MASTER_SDCC_3 34
+-#define ICBID_MASTER_SDCC_2 35
+-#define ICBID_MASTER_SDCC_4 36
+-#define ICBID_MASTER_TSIF 37
+-#define ICBID_MASTER_BAM_DMA 38
+-#define ICBID_MASTER_BLSP_2 39
+-#define ICBID_MASTER_USB_HSIC 40
+-#define ICBID_MASTER_BLSP_1 41
+-#define ICBID_MASTER_USB_HS 42
+-#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
+-#define ICBID_MASTER_PNOC_CFG 43
+-#define ICBID_MASTER_SNOC_PNOC 44
+-#define ICBID_MASTER_RPM_INST 45
+-#define ICBID_MASTER_RPM_DATA 46
+-#define ICBID_MASTER_RPM_SYS 47
+-#define ICBID_MASTER_DEHR 48
+-#define ICBID_MASTER_QDSS_DAP 49
+-#define ICBID_MASTER_SPDM 50
+-#define ICBID_MASTER_TIC 51
+-#define ICBID_MASTER_SNOC_CNOC 52
+-#define ICBID_MASTER_GFX3D_OCMEM 53
+-#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
+-#define ICBID_MASTER_OVIRT_SNOC 54
+-#define ICBID_MASTER_SNOC_OVIRT 55
+-#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
+-#define ICBID_MASTER_ONOC_OVIRT 56
+-#define ICBID_MASTER_USB_HS2 57
+-#define ICBID_MASTER_QPIC 58
+-#define ICBID_MASTER_IPA 59
+-#define ICBID_MASTER_DSI 60
+-#define ICBID_MASTER_MDP1 61
+-#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
+-#define ICBID_MASTER_VPU_PROC 62
+-#define ICBID_MASTER_VPU 63
+-#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
+-#define ICBID_MASTER_CRYPTO_CORE2 64
+-#define ICBID_MASTER_PCIE_0 65
+-#define ICBID_MASTER_PCIE_1 66
+-#define ICBID_MASTER_SATA 67
+-#define ICBID_MASTER_UFS 68
+-#define ICBID_MASTER_USB3_1 69
+-#define ICBID_MASTER_VIDEO_OCMEM 70
+-#define ICBID_MASTER_VPU1 71
+-#define ICBID_MASTER_VCAP 72
+-#define ICBID_MASTER_EMAC 73
+-#define ICBID_MASTER_BCAST 74
+-#define ICBID_MASTER_MMSS_PROC 75
+-#define ICBID_MASTER_SNOC_BIMC_1 76
+-#define ICBID_MASTER_SNOC_PCNOC 77
+-#define ICBID_MASTER_AUDIO 78
+-#define ICBID_MASTER_MM_INT_0 79
+-#define ICBID_MASTER_MM_INT_1 80
+-#define ICBID_MASTER_MM_INT_2 81
+-#define ICBID_MASTER_MM_INT_BIMC 82
+-#define ICBID_MASTER_MSS_INT 83
+-#define ICBID_MASTER_PCNOC_CFG 84
+-#define ICBID_MASTER_PCNOC_INT_0 85
+-#define ICBID_MASTER_PCNOC_INT_1 86
+-#define ICBID_MASTER_PCNOC_M_0 87
+-#define ICBID_MASTER_PCNOC_M_1 88
+-#define ICBID_MASTER_PCNOC_S_0 89
+-#define ICBID_MASTER_PCNOC_S_1 90
+-#define ICBID_MASTER_PCNOC_S_2 91
+-#define ICBID_MASTER_PCNOC_S_3 92
+-#define ICBID_MASTER_PCNOC_S_4 93
+-#define ICBID_MASTER_PCNOC_S_6 94
+-#define ICBID_MASTER_PCNOC_S_7 95
+-#define ICBID_MASTER_PCNOC_S_8 96
+-#define ICBID_MASTER_PCNOC_S_9 97
+-#define ICBID_MASTER_QDSS_INT 98
+-#define ICBID_MASTER_SNOC_INT_0 99
+-#define ICBID_MASTER_SNOC_INT_1 100
+-#define ICBID_MASTER_SNOC_INT_BIMC 101
+-#define ICBID_MASTER_TCU_0 102
+-#define ICBID_MASTER_TCU_1 103
+-#define ICBID_MASTER_BIMC_INT_0 104
+-#define ICBID_MASTER_BIMC_INT_1 105
+-#define ICBID_MASTER_CAMERA 106
+-#define ICBID_MASTER_RICA 107
+-#define ICBID_MASTER_SNOC_BIMC_2 108
+-#define ICBID_MASTER_BIMC_SNOC_1 109
+-#define ICBID_MASTER_A0NOC_SNOC 110
+-#define ICBID_MASTER_A1NOC_SNOC 111
+-#define ICBID_MASTER_A2NOC_SNOC 112
+-#define ICBID_MASTER_PIMEM 113
+-#define ICBID_MASTER_SNOC_VMEM 114
+-#define ICBID_MASTER_CPP 115
+-#define ICBID_MASTER_CNOC_A1NOC 116
+-#define ICBID_MASTER_PNOC_A1NOC 117
+-#define ICBID_MASTER_HMSS 118
+-#define ICBID_MASTER_PCIE_2 119
+-#define ICBID_MASTER_ROTATOR 120
+-#define ICBID_MASTER_VENUS_VMEM 121
+-#define ICBID_MASTER_DCC 122
+-#define ICBID_MASTER_MCDMA 123
+-#define ICBID_MASTER_PCNOC_INT_2 124
+-#define ICBID_MASTER_PCNOC_INT_3 125
+-#define ICBID_MASTER_PCNOC_INT_4 126
+-#define ICBID_MASTER_PCNOC_INT_5 127
+-#define ICBID_MASTER_PCNOC_INT_6 128
+-#define ICBID_MASTER_PCNOC_S_5 129
+-#define ICBID_MASTER_SENSORS_AHB 130
+-#define ICBID_MASTER_SENSORS_PROC 131
+-#define ICBID_MASTER_QSPI 132
+-#define ICBID_MASTER_VFE1 133
+-#define ICBID_MASTER_SNOC_INT_2 134
+-#define ICBID_MASTER_SMMNOC_BIMC 135
+-#define ICBID_MASTER_CRVIRT_A1NOC 136
+-#define ICBID_MASTER_XM_USB_HS1 137
+-#define ICBID_MASTER_XI_USB_HS1 138
+-#define ICBID_MASTER_PCNOC_BIMC_1 139
+-#define ICBID_MASTER_BIMC_PCNOC 140
+-#define ICBID_MASTER_XI_HSIC 141
+-#define ICBID_MASTER_SGMII 142
+-#define ICBID_MASTER_SPMI_FETCHER 143
+-#define ICBID_MASTER_GNOC_BIMC 144
+-#define ICBID_MASTER_CRVIRT_A2NOC 145
+-#define ICBID_MASTER_CNOC_A2NOC 146
+-#define ICBID_MASTER_WLAN 147
+-#define ICBID_MASTER_MSS_CE 148
+-#define ICBID_MASTER_CDSP_PROC 149
+-#define ICBID_MASTER_GNOC_SNOC 150
+-
+-#define ICBID_SLAVE_EBI1 0
+-#define ICBID_SLAVE_APPSS_L2 1
+-#define ICBID_SLAVE_BIMC_SNOC 2
+-#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
+-#define ICBID_SLAVE_CAMERA_CFG 3
+-#define ICBID_SLAVE_DISPLAY_CFG 4
+-#define ICBID_SLAVE_OCMEM_CFG 5
+-#define ICBID_SLAVE_CPR_CFG 6
+-#define ICBID_SLAVE_CPR_XPU_CFG 7
+-#define ICBID_SLAVE_MISC_CFG 8
+-#define ICBID_SLAVE_MISC_XPU_CFG 9
+-#define ICBID_SLAVE_VENUS_CFG 10
+-#define ICBID_SLAVE_GFX3D_CFG 11
+-#define ICBID_SLAVE_MMSS_CLK_CFG 12
+-#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
+-#define ICBID_SLAVE_MNOC_MPU_CFG 14
+-#define ICBID_SLAVE_ONOC_MPU_CFG 15
+-#define ICBID_SLAVE_MNOC_BIMC 16
+-#define ICBID_SLAVE_SERVICE_MNOC 17
+-#define ICBID_SLAVE_OCMEM 18
+-#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
+-#define ICBID_SLAVE_SERVICE_ONOC 19
+-#define ICBID_SLAVE_APPSS 20
+-#define ICBID_SLAVE_LPASS 21
+-#define ICBID_SLAVE_USB3 22
+-#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
+-#define ICBID_SLAVE_WCSS 23
+-#define ICBID_SLAVE_SNOC_BIMC 24
+-#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
+-#define ICBID_SLAVE_SNOC_CNOC 25
+-#define ICBID_SLAVE_IMEM 26
+-#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
+-#define ICBID_SLAVE_SNOC_OVIRT 27
+-#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
+-#define ICBID_SLAVE_SNOC_PNOC 28
+-#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
+-#define ICBID_SLAVE_SERVICE_SNOC 29
+-#define ICBID_SLAVE_QDSS_STM 30
+-#define ICBID_SLAVE_SDCC_1 31
+-#define ICBID_SLAVE_SDCC_3 32
+-#define ICBID_SLAVE_SDCC_2 33
+-#define ICBID_SLAVE_SDCC_4 34
+-#define ICBID_SLAVE_TSIF 35
+-#define ICBID_SLAVE_BAM_DMA 36
+-#define ICBID_SLAVE_BLSP_2 37
+-#define ICBID_SLAVE_USB_HSIC 38
+-#define ICBID_SLAVE_BLSP_1 39
+-#define ICBID_SLAVE_USB_HS 40
+-#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
+-#define ICBID_SLAVE_PDM 41
+-#define ICBID_SLAVE_PERIPH_APU_CFG 42
+-#define ICBID_SLAVE_PNOC_MPU_CFG 43
+-#define ICBID_SLAVE_PRNG 44
+-#define ICBID_SLAVE_PNOC_SNOC 45
+-#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
+-#define ICBID_SLAVE_SERVICE_PNOC 46
+-#define ICBID_SLAVE_CLK_CTL 47
+-#define ICBID_SLAVE_CNOC_MSS 48
+-#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
+-#define ICBID_SLAVE_SECURITY 49
+-#define ICBID_SLAVE_TCSR 50
+-#define ICBID_SLAVE_TLMM 51
+-#define ICBID_SLAVE_CRYPTO_0_CFG 52
+-#define ICBID_SLAVE_CRYPTO_1_CFG 53
+-#define ICBID_SLAVE_IMEM_CFG 54
+-#define ICBID_SLAVE_MESSAGE_RAM 55
+-#define ICBID_SLAVE_BIMC_CFG 56
+-#define ICBID_SLAVE_BOOT_ROM 57
+-#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
+-#define ICBID_SLAVE_PMIC_ARB 59
+-#define ICBID_SLAVE_SPDM_WRAPPER 60
+-#define ICBID_SLAVE_DEHR_CFG 61
+-#define ICBID_SLAVE_MPM 62
+-#define ICBID_SLAVE_QDSS_CFG 63
+-#define ICBID_SLAVE_RBCPR_CFG 64
+-#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
+-#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
+-#define ICBID_SLAVE_CNOC_MNOC_CFG 66
+-#define ICBID_SLAVE_SNOC_MPU_CFG 67
+-#define ICBID_SLAVE_CNOC_ONOC_CFG 68
+-#define ICBID_SLAVE_PNOC_CFG 69
+-#define ICBID_SLAVE_SNOC_CFG 70
+-#define ICBID_SLAVE_EBI1_DLL_CFG 71
+-#define ICBID_SLAVE_PHY_APU_CFG 72
+-#define ICBID_SLAVE_EBI1_PHY_CFG 73
+-#define ICBID_SLAVE_RPM 74
+-#define ICBID_SLAVE_CNOC_SNOC 75
+-#define ICBID_SLAVE_SERVICE_CNOC 76
+-#define ICBID_SLAVE_OVIRT_SNOC 77
+-#define ICBID_SLAVE_OVIRT_OCMEM 78
+-#define ICBID_SLAVE_USB_HS2 79
+-#define ICBID_SLAVE_QPIC 80
+-#define ICBID_SLAVE_IPS_CFG 81
+-#define ICBID_SLAVE_DSI_CFG 82
+-#define ICBID_SLAVE_USB3_1 83
+-#define ICBID_SLAVE_PCIE_0 84
+-#define ICBID_SLAVE_PCIE_1 85
+-#define ICBID_SLAVE_PSS_SMMU_CFG 86
+-#define ICBID_SLAVE_CRYPTO_2_CFG 87
+-#define ICBID_SLAVE_PCIE_0_CFG 88
+-#define ICBID_SLAVE_PCIE_1_CFG 89
+-#define ICBID_SLAVE_SATA_CFG 90
+-#define ICBID_SLAVE_SPSS_GENI_IR 91
+-#define ICBID_SLAVE_UFS_CFG 92
+-#define ICBID_SLAVE_AVSYNC_CFG 93
+-#define ICBID_SLAVE_VPU_CFG 94
+-#define ICBID_SLAVE_USB_PHY_CFG 95
+-#define ICBID_SLAVE_RBCPR_MX_CFG 96
+-#define ICBID_SLAVE_PCIE_PARF 97
+-#define ICBID_SLAVE_VCAP_CFG 98
+-#define ICBID_SLAVE_EMAC_CFG 99
+-#define ICBID_SLAVE_BCAST_CFG 100
+-#define ICBID_SLAVE_KLM_CFG 101
+-#define ICBID_SLAVE_DISPLAY_PWM 102
+-#define ICBID_SLAVE_GENI 103
+-#define ICBID_SLAVE_SNOC_BIMC_1 104
+-#define ICBID_SLAVE_AUDIO 105
+-#define ICBID_SLAVE_CATS_0 106
+-#define ICBID_SLAVE_CATS_1 107
+-#define ICBID_SLAVE_MM_INT_0 108
+-#define ICBID_SLAVE_MM_INT_1 109
+-#define ICBID_SLAVE_MM_INT_2 110
+-#define ICBID_SLAVE_MM_INT_BIMC 111
+-#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
+-#define ICBID_SLAVE_MSS_INT 113
+-#define ICBID_SLAVE_PCNOC_INT_0 114
+-#define ICBID_SLAVE_PCNOC_INT_1 115
+-#define ICBID_SLAVE_PCNOC_M_0 116
+-#define ICBID_SLAVE_PCNOC_M_1 117
+-#define ICBID_SLAVE_PCNOC_S_0 118
+-#define ICBID_SLAVE_PCNOC_S_1 119
+-#define ICBID_SLAVE_PCNOC_S_2 120
+-#define ICBID_SLAVE_PCNOC_S_3 121
+-#define ICBID_SLAVE_PCNOC_S_4 122
+-#define ICBID_SLAVE_PCNOC_S_6 123
+-#define ICBID_SLAVE_PCNOC_S_7 124
+-#define ICBID_SLAVE_PCNOC_S_8 125
+-#define ICBID_SLAVE_PCNOC_S_9 126
+-#define ICBID_SLAVE_PRNG_XPU_CFG 127
+-#define ICBID_SLAVE_QDSS_INT 128
+-#define ICBID_SLAVE_RPM_XPU_CFG 129
+-#define ICBID_SLAVE_SNOC_INT_0 130
+-#define ICBID_SLAVE_SNOC_INT_1 131
+-#define ICBID_SLAVE_SNOC_INT_BIMC 132
+-#define ICBID_SLAVE_TCU 133
+-#define ICBID_SLAVE_BIMC_INT_0 134
+-#define ICBID_SLAVE_BIMC_INT_1 135
+-#define ICBID_SLAVE_RICA_CFG 136
+-#define ICBID_SLAVE_SNOC_BIMC_2 137
+-#define ICBID_SLAVE_BIMC_SNOC_1 138
+-#define ICBID_SLAVE_PNOC_A1NOC 139
+-#define ICBID_SLAVE_SNOC_VMEM 140
+-#define ICBID_SLAVE_A0NOC_SNOC 141
+-#define ICBID_SLAVE_A1NOC_SNOC 142
+-#define ICBID_SLAVE_A2NOC_SNOC 143
+-#define ICBID_SLAVE_A0NOC_CFG 144
+-#define ICBID_SLAVE_A0NOC_MPU_CFG 145
+-#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
+-#define ICBID_SLAVE_A1NOC_CFG 147
+-#define ICBID_SLAVE_A1NOC_MPU_CFG 148
+-#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
+-#define ICBID_SLAVE_A2NOC_CFG 150
+-#define ICBID_SLAVE_A2NOC_MPU_CFG 151
+-#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
+-#define ICBID_SLAVE_AHB2PHY 153
+-#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
+-#define ICBID_SLAVE_DCC_CFG 155
+-#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
+-#define ICBID_SLAVE_DSA_CFG 157
+-#define ICBID_SLAVE_DSA_MPU_CFG 158
+-#define ICBID_SLAVE_SSC_MPU_CFG 159
+-#define ICBID_SLAVE_HMSS_L3 160
+-#define ICBID_SLAVE_LPASS_SMMU_CFG 161
+-#define ICBID_SLAVE_MMAGIC_CFG 162
+-#define ICBID_SLAVE_PCIE20_AHB2PHY 163
+-#define ICBID_SLAVE_PCIE_2 164
+-#define ICBID_SLAVE_PCIE_2_CFG 165
+-#define ICBID_SLAVE_PIMEM 166
+-#define ICBID_SLAVE_PIMEM_CFG 167
+-#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
+-#define ICBID_SLAVE_RBCPR_CX 169
+-#define ICBID_SLAVE_RBCPR_MX 170
+-#define ICBID_SLAVE_SMMU_CPP_CFG 171
+-#define ICBID_SLAVE_SMMU_JPEG_CFG 172
+-#define ICBID_SLAVE_SMMU_MDP_CFG 173
+-#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
+-#define ICBID_SLAVE_SMMU_VENUS_CFG 175
+-#define ICBID_SLAVE_SMMU_VFE_CFG 176
+-#define ICBID_SLAVE_SSC_CFG 177
+-#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
+-#define ICBID_SLAVE_VMEM 179
+-#define ICBID_SLAVE_VMEM_CFG 180
+-#define ICBID_SLAVE_QDSS_MPU_CFG 181
+-#define ICBID_SLAVE_USB3_PHY_CFG 182
+-#define ICBID_SLAVE_IPA_CFG 183
+-#define ICBID_SLAVE_PCNOC_INT_2 184
+-#define ICBID_SLAVE_PCNOC_INT_3 185
+-#define ICBID_SLAVE_PCNOC_INT_4 186
+-#define ICBID_SLAVE_PCNOC_INT_5 187
+-#define ICBID_SLAVE_PCNOC_INT_6 188
+-#define ICBID_SLAVE_PCNOC_S_5 189
+-#define ICBID_SLAVE_QSPI 190
+-#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
+-#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
+-#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
+-#define ICBID_SLAVE_MSS_MPU_CFG 194
+-#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
+-#define ICBID_SLAVE_SKL 196
+-#define ICBID_SLAVE_SNOC_INT_2 197
+-#define ICBID_SLAVE_SMMNOC_BIMC 198
+-#define ICBID_SLAVE_CRVIRT_A1NOC 199
+-#define ICBID_SLAVE_SGMII 200
+-#define ICBID_SLAVE_QHS4_APPS 201
+-#define ICBID_SLAVE_BIMC_PCNOC 202
+-#define ICBID_SLAVE_PCNOC_BIMC_1 203
+-#define ICBID_SLAVE_SPMI_FETCHER 204
+-#define ICBID_SLAVE_MMSS_SMMU_CFG 205
+-#define ICBID_SLAVE_WLAN 206
+-#define ICBID_SLAVE_CRVIRT_A2NOC 207
+-#define ICBID_SLAVE_CNOC_A2NOC 208
+-#define ICBID_SLAVE_GLM 209
+-#define ICBID_SLAVE_GNOC_BIMC 210
+-#define ICBID_SLAVE_GNOC_SNOC 211
+-#define ICBID_SLAVE_QM_CFG 212
+-#define ICBID_SLAVE_TLMM_EAST 213
+-#define ICBID_SLAVE_TLMM_NORTH 214
+-#define ICBID_SLAVE_TLMM_WEST 215
+-#define ICBID_SLAVE_LPASS_TCM 216
+-#define ICBID_SLAVE_TLMM_SOUTH 217
+-#define ICBID_SLAVE_TLMM_CENTER 218
+-#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219
+-#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220
+-#define ICBID_SLAVE_CDSP 221
+-#define ICBID_SLAVE_CDSP_SMMU_CFG 222
+-#define ICBID_SLAVE_LPASS_MPU_CFG 223
+-#define ICBID_SLAVE_CSI_PHY_CFG 224
+-#endif
+--
+2.20.1
+
diff --git a/patches.drm/0008-dt-bindings-display-panel-Fix-compatible-string-for-.patch b/patches.drm/0008-dt-bindings-display-panel-Fix-compatible-string-for-.patch
new file mode 100644
index 0000000000..3acfaca5be
--- /dev/null
+++ b/patches.drm/0008-dt-bindings-display-panel-Fix-compatible-string-for-.patch
@@ -0,0 +1,41 @@
+From 81ee6f1ef9b1e93b2dc0a77211e9809ffbeb7ecb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
+Date: Sun, 17 Dec 2017 03:34:33 +0100
+Subject: dt-bindings: display: panel: Fix compatible string for Toshiba
+ LT089AC29000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: 81ee6f1ef9b1e93b2dc0a77211e9809ffbeb7ecb
+Patch-mainline: v4.16-rc1
+References: bsc#1113956
+
+The compatible string for this panel was specified as
+toshiba,lt089ac29000.txt. I believe this is a mistake.
+
+Fixes: 06e733e41f87 ("drm/panel: simple: add Toshiba LT089AC19000")
+Cc: Lucas Stach <l.stach@pengutronix.de>
+Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+Acked-by: Lucas Stach <l.stach@pengutronix.de>
+Signed-off-by: Rob Herring <robh@kernel.org>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ .../devicetree/bindings/display/panel/toshiba,lt089ac29000.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt b/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
+index 4c0caaf246c9..89826116628c 100644
+--- a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
++++ b/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
+@@ -1,7 +1,7 @@
+ Toshiba 8.9" WXGA (1280x768) TFT LCD panel
+
+ Required properties:
+-- compatible: should be "toshiba,lt089ac29000.txt"
++- compatible: should be "toshiba,lt089ac29000"
+ - power-supply: as specified in the base binding
+
+ This binding is compatible with the simple-panel binding, which is specified
+--
+2.20.1
+
diff --git a/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch b/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
new file mode 100644
index 0000000000..6c048f3499
--- /dev/null
+++ b/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
@@ -0,0 +1,284 @@
+From dd18cedfa36fbbc19903aed12d6d94c06f5e6dea Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jakub=20Bartmi=C5=84ski?= <jakub.bartminski@intel.com>
+Date: Fri, 27 Jul 2018 16:11:45 +0200
+Subject: drm/i915/guc: Move the pin bias value from GuC to GGTT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: dd18cedfa36fbbc19903aed12d6d94c06f5e6dea
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Removing the pin bias from GuC allows us to not check for GuC every time
+we pin a context, which fixes the assertion error on unresolved GuC
+platform default in mock contexts selftest.
+
+It also seems that we were using uninitialized WOPCM variables when
+setting the GuC pin bias. The pin bias has to be set after the WOPCM,
+but before the call to i915_gem_contexts_init where the first contexts
+are pinned.
+
+v2:
+This also makes it so that there's no need to set GuC variables from
+within the WOPCM init function or to move the WOPCM init, while keeping
+the correct initialization order. Also for mock tests the pin bias is
+left at 0 and we make sure that the pin bias with GuC will not be
+smaller than without GuC.
+
+v3:
+Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled.
+
+v4:
+Squash with WOPCM init reordering.
+Moved the i915_ggtt_pin_bias helper to this patch, and made some
+functions use it instead of directly dereferencing i915->ggtt.
+
+v5:
+Since we now don't use wopcm.guc.base for the pin bias there's no need to
+validate it. It also has already been verified in WOPCM init.
+
+v6:
+Deleted the now unnecessarily introduced includes from previous versions.
+Dropped naming changes from dev_priv to i915 for better patch readability.
+
+v7:
+Changed some comments to make more sense in the context they're in.
+
+v8:
+Moved and renamed the function which now returns the wopcm.guc.size to
+intel_guc.c:intel_guc_reserved_gtt_size to avoid any possible confusion
+with the pin_bias in ggtt, which should be used for pinning.
+Fixed patch not applying or the most recent upstream.
+
+Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init")
+Testcase: igt/drv_selftest/mock_contexts #GuC
+Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Michał Winiarski <michal.winiarski@intel.com>
+Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180727141148.30874-3-jakub.bartminski@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_gem_context.c | 10 -------
+ drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++++++
+ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +
+ drivers/gpu/drm/i915/i915_vma.h | 5 +++
+ drivers/gpu/drm/i915/intel_guc.c | 43 ++++++++++++++------------------
+ drivers/gpu/drm/i915/intel_guc.h | 12 +++-----
+ drivers/gpu/drm/i915/intel_huc.c | 2 -
+ drivers/gpu/drm/i915/intel_uc_fw.c | 2 -
+ 8 files changed, 44 insertions(+), 41 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_gem_context.c
++++ b/drivers/gpu/drm/i915/i915_gem_context.c
+@@ -329,15 +329,7 @@ __create_hw_context(struct drm_i915_priv
+ ctx->desc_template =
+ default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
+
+- /*
+- * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
+- * present or not in use we still need a small bias as ring wraparound
+- * at offset 0 sometimes hangs. No idea why.
+- */
+- if (USES_GUC(dev_priv))
+- ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
+- else
+- ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
++ ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
+
+ return ctx;
+
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
+@@ -2937,6 +2937,15 @@ int i915_gem_init_ggtt(struct drm_i915_p
+ struct drm_mm_node *entry;
+ int ret;
+
++ /*
++ * GuC requires all resources that we're sharing with it to be placed in
++ * non-WOPCM memory. If GuC is not present or not in use we still need a
++ * small bias as ring wraparound at offset 0 sometimes hangs. No idea
++ * why.
++ */
++ ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
++ intel_guc_reserved_gtt_size(&dev_priv->guc));
++
+ ret = intel_vgt_balloon(dev_priv);
+ if (ret)
+ return ret;
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
+@@ -401,6 +401,8 @@ struct i915_ggtt {
+
+ int mtrr;
+
++ u32 pin_bias;
++
+ struct drm_mm_node error_capture;
+ };
+
+--- a/drivers/gpu/drm/i915/i915_vma.h
++++ b/drivers/gpu/drm/i915/i915_vma.h
+@@ -207,6 +207,11 @@ static inline u32 i915_ggtt_offset(const
+ return lower_32_bits(vma->node.start);
+ }
+
++static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
++{
++ return i915_vm_to_ggtt(vma->vm)->pin_bias;
++}
++
+ static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
+ {
+ i915_gem_object_get(vma->obj);
+--- a/drivers/gpu/drm/i915/intel_guc.c
++++ b/drivers/gpu/drm/i915/intel_guc.c
+@@ -27,8 +27,6 @@
+ #include "intel_guc_submission.h"
+ #include "i915_drv.h"
+
+-static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
+-
+ static void gen8_guc_raise_irq(struct intel_guc *guc)
+ {
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+@@ -142,8 +140,6 @@ int intel_guc_init_misc(struct intel_guc
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
+
+- guc_init_ggtt_pin_bias(guc);
+-
+ ret = guc_init_wq(guc);
+ if (ret)
+ return ret;
+@@ -614,23 +610,6 @@ int intel_guc_resume(struct intel_guc *g
+ */
+
+ /**
+- * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
+- * @guc: intel_guc structure.
+- *
+- * This function will calculate and initialize the ggtt_pin_bias value based on
+- * overall WOPCM size and GuC WOPCM size.
+- */
+-static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
+-{
+- struct drm_i915_private *i915 = guc_to_i915(guc);
+-
+- GEM_BUG_ON(!i915->wopcm.size);
+- GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
+-
+- guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
+-}
+-
+-/**
+ * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
+ * @guc: the guc
+ * @size: size of area to allocate (both virtual space and memory)
+@@ -648,6 +627,7 @@ struct i915_vma *intel_guc_allocate_vma(
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
++ u64 flags;
+ int ret;
+
+ obj = i915_gem_object_create(dev_priv, size);
+@@ -658,8 +638,8 @@ struct i915_vma *intel_guc_allocate_vma(
+ if (IS_ERR(vma))
+ goto err;
+
+- ret = i915_vma_pin(vma, 0, PAGE_SIZE,
+- PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
++ flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
++ ret = i915_vma_pin(vma, 0, 0, flags);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+@@ -671,3 +651,20 @@ err:
+ i915_gem_object_put(obj);
+ return vma;
+ }
++
++/**
++ * intel_guc_reserved_gtt_size()
++ * @guc: intel_guc structure
++ *
++ * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
++ * GuC we can't have any objects pinned in that region. This function returns
++ * the size of the shadowed region.
++ *
++ * Returns:
++ * 0 if GuC is not present or not in use.
++ * Otherwise, the GuC WOPCM size.
++ */
++u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
++{
++ return guc_to_i915(guc)->wopcm.guc.size;
++}
+--- a/drivers/gpu/drm/i915/intel_guc.h
++++ b/drivers/gpu/drm/i915/intel_guc.h
+@@ -49,9 +49,6 @@ struct intel_guc {
+ struct intel_guc_log log;
+ struct intel_guc_ct ct;
+
+- /* Offset where Non-WOPCM memory starts. */
+- u32 ggtt_pin_bias;
+-
+ /* Log snapshot if GuC errors during load */
+ struct drm_i915_gem_object *load_err_log;
+
+@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_eve
+ * @vma: i915 graphics virtual memory area.
+ *
+ * GuC does not allow any gfx GGTT address that falls into range
+- * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+- * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
++ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
++ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
+ * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
+- * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
++ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
+ *
+ * Return: GGTT offset of the @vma.
+ */
+@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(
+ {
+ u32 offset = i915_ggtt_offset(vma);
+
+- GEM_BUG_ON(offset < guc->ggtt_pin_bias);
++ GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
+ GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
+
+ return offset;
+@@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc
+ int intel_guc_suspend(struct intel_guc *guc);
+ int intel_guc_resume(struct intel_guc *guc);
+ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
++u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
+
+ static inline int intel_guc_sanitize(struct intel_guc *guc)
+ {
+--- a/drivers/gpu/drm/i915/intel_huc.c
++++ b/drivers/gpu/drm/i915/intel_huc.c
+@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc
+ return -ENOEXEC;
+
+ vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+- PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
++ PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
+--- a/drivers/gpu/drm/i915/intel_uc_fw.c
++++ b/drivers/gpu/drm/i915/intel_uc_fw.c
+@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_f
+ goto fail;
+ }
+
+- ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
++ ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
+ vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
+ PIN_OFFSET_BIAS | ggtt_pin_bias);
+ if (IS_ERR(vma)) {
diff --git a/patches.drm/0031-dma-buf-Remove-requirement-for-ops-map-from-dma_buf_.patch b/patches.drm/0031-dma-buf-Remove-requirement-for-ops-map-from-dma_buf_.patch
new file mode 100644
index 0000000000..ba848cc74d
--- /dev/null
+++ b/patches.drm/0031-dma-buf-Remove-requirement-for-ops-map-from-dma_buf_.patch
@@ -0,0 +1,36 @@
+From f82aab2d521e4c1d4f9f98450b4a9a8abeaff1c4 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Tue, 7 Aug 2018 19:36:47 +0100
+Subject: dma-buf: Remove requirement for ops->map() from dma_buf_export
+Git-commit: f82aab2d521e4c1d4f9f98450b4a9a8abeaff1c4
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Since commit 9ea0dfbf972 ("dma-buf: make map_atomic and map function
+pointers optional"), the core provides the no-op functions when map and
+map_atomic are not provided, so we no longer need assert that are
+supplied by a dma-buf exporter.
+
+Fixes: 09ea0dfbf972 ("dma-buf: make map_atomic and map function pointers optional")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/20180807183647.22626-1-chris@chris-wilson.co.uk
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Cc: Gerd Hoffmann <kraxel@redhat.com>
+Cc: Sumit Semwal <sumit.semwal@linaro.org>
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/dma-buf/dma-buf.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/dma-buf/dma-buf.c
++++ b/drivers/dma-buf/dma-buf.c
+@@ -406,7 +406,6 @@ struct dma_buf *dma_buf_export(const str
+ || !exp_info->ops->unmap_dma_buf
+ || !exp_info->ops->release
+ || !exp_info->ops->map_atomic
+- || !exp_info->ops->map
+ || !exp_info->ops->mmap)) {
+ return ERR_PTR(-EINVAL);
+ }
diff --git a/patches.drm/0033-drm-panel-Fix-sphinx-warning.patch b/patches.drm/0033-drm-panel-Fix-sphinx-warning.patch
new file mode 100644
index 0000000000..d9eb06a9bc
--- /dev/null
+++ b/patches.drm/0033-drm-panel-Fix-sphinx-warning.patch
@@ -0,0 +1,43 @@
+From 3eb3cd04e2d8cd930c7caa8d9e57f1c964792b6e Mon Sep 17 00:00:00 2001
+From: Sean Paul <seanpaul@chromium.org>
+Date: Wed, 15 Aug 2018 16:38:28 -0400
+Subject: drm/panel: Fix sphinx warning
+Git-commit: 3eb3cd04e2d8cd930c7caa8d9e57f1c964792b6e
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Resolves the following warnings.
+../drivers/gpu/drm/drm_panel.c:158: WARNING: Unexpected indentation.
+../drivers/gpu/drm/drm_panel.c:159: WARNING: Block quote ends without a blank line; unexpected unindent.
+
+Fixes: c59eb3cfde1f ("drm/panel: Let of_drm_find_panel() return -ENODEV when the panel is disabled")
+Cc: Boris Brezillon <boris.brezillon@bootlin.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Cc: Thierry Reding <thierry.reding@gmail.com>
+Cc: Jyri Sarha <jsarha@ti.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Acked-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Sean Paul <seanpaul@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180815203833.210143-1-sean@poorly.run
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/drm_panel.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
+index b902361dee6e..0db486d10d1c 100644
+--- a/drivers/gpu/drm/drm_panel.c
++++ b/drivers/gpu/drm/drm_panel.c
+@@ -152,7 +152,9 @@ EXPORT_SYMBOL(drm_panel_detach);
+ *
+ * Return: A pointer to the panel registered for the specified device tree
+ * node or an ERR_PTR() if no panel matching the device tree node can be found.
++ *
+ * Possible error codes returned by this function:
++ *
+ * - EPROBE_DEFER: the panel device has not been probed yet, and the caller
+ * should retry later
+ * - ENODEV: the device is not available (status != "okay" or "ok")
+--
+2.20.1
+
diff --git a/patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch b/patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch
new file mode 100644
index 0000000000..65d221d0ef
--- /dev/null
+++ b/patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch
@@ -0,0 +1,41 @@
+From ff30e9e8509cb877dc7cbc776b36c70f5bdd290f Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Fri, 10 Aug 2018 18:50:32 +0800
+Subject: drm/amdgpu: fix integer overflow test in amdgpu_bo_list_create()
+Git-commit: ff30e9e8509cb877dc7cbc776b36c70f5bdd290f
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+We accidentally left out the size of the amdgpu_bo_list struct. It
+could lead to memory corruption on 32 bit systems. You'd have to
+pick the absolute maximum and set "num_entries == 59652323" then size
+would wrap to 16 bytes.
+
+Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+index d472a2c8399f..b80243d3972e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -67,7 +67,8 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
+ unsigned i;
+ int r;
+
+- if (num_entries > SIZE_MAX / sizeof(struct amdgpu_bo_list_entry))
++ if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list))
++ / sizeof(struct amdgpu_bo_list_entry))
+ return -EINVAL;
+
+ size = sizeof(struct amdgpu_bo_list);
+--
+2.20.1
+
diff --git a/patches.drm/0038-drm-i915-psr-Remove-wait_for_idle-for-PSR2.patch b/patches.drm/0038-drm-i915-psr-Remove-wait_for_idle-for-PSR2.patch
new file mode 100644
index 0000000000..340d14bafe
--- /dev/null
+++ b/patches.drm/0038-drm-i915-psr-Remove-wait_for_idle-for-PSR2.patch
@@ -0,0 +1,72 @@
+From fd255f6e3704d183f6f5011efd01fcda70372cab Mon Sep 17 00:00:00 2001
+From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Date: Fri, 24 Aug 2018 16:08:43 -0700
+Subject: drm/i915/psr: Remove wait_for_idle() for PSR2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: fd255f6e3704d183f6f5011efd01fcda70372cab
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+CI runs show PSR2 does not go to IDLE with selective update enabled on
+all PSR exit triggers. Specifically, logs indicate the hardware enters
+"SLEEP Selective Update" and not "IDLE Reset state', like the kernel
+expects, when vblank interrupts are enabled. This check was added for PSR1
+but incorrectly extended to PSR2, remove the check as it breaks tests
+and prints out misleading error messages.
+
+v2: Split out non-code changes (Rodrigo)
+
+Cc: Tarun Vyas <tarun.vyas@intel.com>
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Fixes: c43dbcbbcc8c ("drm/i915/psr: Lockless version of psr_wait_for_idle")
+Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180824230844.12428-1-dhinakaran.pandiyan@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/intel_psr.c | 18 +++++++-----------
+ 1 file changed, 7 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_psr.c
++++ b/drivers/gpu/drm/i915/intel_psr.c
+@@ -721,8 +721,6 @@ int intel_psr_wait_for_idle(const struct
+ {
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+- i915_reg_t reg;
+- u32 mask;
+
+ if (!new_crtc_state->has_psr)
+ return 0;
+@@ -737,21 +735,19 @@ int intel_psr_wait_for_idle(const struct
+ * not needed and will induce latencies in the atomic
+ * update path.
+ */
+- if (dev_priv->psr.psr2_enabled) {
+- reg = EDP_PSR2_STATUS;
+- mask = EDP_PSR2_STATUS_STATE_MASK;
+- } else {
+- reg = EDP_PSR_STATUS;
+- mask = EDP_PSR_STATUS_STATE_MASK;
+- }
++
++ /* FIXME: Update this for PSR2 if we need to wait for idle */
++ if (READ_ONCE(dev_priv->psr.psr2_enabled))
++ return 0;
+
+ /*
+ * Max time for PSR to idle = Inverse of the refresh rate +
+ * 6 ms of exit training time + 1.5 ms of aux channel
+ * handshake. 50 msec is defesive enough to cover everything.
+ */
+- return intel_wait_for_register(dev_priv, reg, mask,
+- EDP_PSR_STATUS_STATE_IDLE, 50);
++ return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
++ EDP_PSR_STATUS_STATE_MASK,
++ EDP_PSR_STATUS_STATE_IDLE, 50);
+ }
+
+ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
diff --git a/series.conf b/series.conf
index 305cd3fddd..647b046aed 100644
--- a/series.conf
+++ b/series.conf
@@ -6005,6 +6005,7 @@
patches.drm/0733-drm-make-drm_stm-default-n
patches.drm/drm-nouveau-disp-nv04-avoid-creation-of-output-paths
patches.arch/powerpc-cpuidle-0010-Disable-LOSE_FULL_CONTEXT-states-when-stop-api-fails.patch
+ patches.drm/0001-fbdev-omapfb-remove-unused-variable.patch
patches.drivers/mmc-block-fix-lockdep-splat-when-removing-mmc_block-module.patch
patches.suse/0127-bio-integrity-Fix-regression-if-profile-verify_fn-is.patch
patches.suse/0128-bio-integrity-only-verify-integrity-on-the-lowest-st.patch
@@ -11068,6 +11069,7 @@
patches.fixes/mm-page_vma_mapped-ensure-pmd-is-loaded-with-READ_ON.patch
patches.drm/drm-atomic-Unref-duplicated-drm_atomic_state-in-drm_
patches.drm/1387-drm-amdgpu-fix-placement-flags-in-amdgpu_ttm_bind
+ patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
patches.drm/1388-drm-msm-mdp5-add-missing-max-size-for-8x74-v1
patches.drm/1389-drm-msm-use-proper-memory-barriers-for-updating-tail-head
patches.drm/1390-drm-msm-fix-return-value-check-in-msm_gem_kernel_new
@@ -17473,6 +17475,7 @@
patches.drm/3436-drm-add-connector-info-property-for-non-desktop-displays
patches.drm/3437-drm-fb-add-support-for-not-enabling-fbcon-on-non-desktop-displays
patches.drm/3438-drm-edid-quirk-htc-vive-headset-as-non-desktop
+ patches.drm/0006-dt-bindings-remove-file-that-was-added-accidentally.patch
patches.drivers/ALSA-hda-realtek-Fix-ALC275-no-sound-issue
patches.drivers/ALSA-usb-audio-uac1-Invalidate-ctl-on-interrupt
patches.drivers/ALSA-hda-Fix-too-short-HDMI-DP-chmap-reporting
@@ -21570,6 +21573,7 @@
patches.drivers/Input-synaptics-rmi4-do-not-delete-interrupt-memory-
patches.fixes/Input-synaptics-rmi4-unmask-F03-interrupts-when-port
patches.drivers/Input-edt-ft5x06-fix-error-handling-for-factory-mode
+ patches.drm/0008-dt-bindings-display-panel-Fix-compatible-string-for-.patch
patches.fixes/kbuild-suppress-packed-not-aligned-warning-for-default-setting-only.patch
patches.fixes/kconfig-display-recursive-dependency-resolution-hint.patch
patches.fixes/kconfig-Don-t-leak-main-menus-during-parsing
@@ -41040,10 +41044,15 @@
patches.suse/0005-watchdog-hpwdt-Update-version-number.patch
patches.suse/0006-watchdog-hpwdt-Disable-PreTimeout-when-Timeout-is-sm.patch
patches.drm/0001-drm-sti-do-not-remove-the-drm_bridge-that-was-never-.patch
+ patches.drm/0031-dma-buf-Remove-requirement-for-ops-map-from-dma_buf_.patch
patches.drm/0001-drm-cirrus-Use-drm_framebuffer_put-to-avoid-kernel-o.patch
+ patches.drm/0033-drm-panel-Fix-sphinx-warning.patch
patches.drm/0001-drm-virtio-fix-bounds-check-in-virtio_gpu_cmd_get_ca.patch
patches.drm/drm-rockchip-Allow-driver-to-be-shutdown-on-reboot-k.patch
+ patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
patches.drm/drm-i915-cfl-Add-a-new-CFL-PCI-ID
+ patches.drm/0038-drm-i915-psr-Remove-wait_for_idle-for-PSR2.patch
+ patches.drm/0037-drm-amdgpu-fix-integer-overflow-test-in-amdgpu_bo_li.patch
patches.drm/drm-amdgpu-add-missing-CHIP_HAINAN-in-amdgpu_ucode_g.patch
patches.drm/0001-drm-hisilicon-hibmc-Do-not-carry-error-code-in-HiBMC.patch
patches.drm/0001-drm-hisilicon-hibmc-Don-t-overwrite-fb-helper-surfac.patch