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authorKernel Build Daemon <kbuild@suse.de>2019-06-22 07:23:02 +0200
committerKernel Build Daemon <kbuild@suse.de>2019-06-22 07:23:02 +0200
commitd3899dba3b40493002db660eee06af9262f515a3 (patch)
tree15e10e4e64335afc5e820abb7ffc6566e70afa81
parentf8a1872c2e97826e8e0333012932aa99b5041ddd (diff)
parent52b668b6e852151fea4e101da852c107e00fad4d (diff)
Merge branch 'SLE15-SP1' into openSUSE-15.1
-rw-r--r--blacklist.conf1
-rw-r--r--config/arm64/default4
-rw-r--r--patches.arch/PCI-Remove-reset-argument-from-pci_iov_-add-remove-_.patch8
-rw-r--r--patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch40
-rw-r--r--patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch57
-rw-r--r--patches.arch/powerpc-pseries-dlpar-Fix-a-missing-check-in-dlpar_p.patch40
-rw-r--r--patches.arch/s390-jump_label-Use-jdd-constraint-on-gcc9.patch72
-rw-r--r--patches.arch/s390-pci-improve-bar-check29
-rw-r--r--patches.arch/s390-pci-map-iov-resources53
-rw-r--r--patches.arch/s390-pci-move-everything-irq-related-to-pci_irq-c6
-rw-r--r--patches.arch/s390-pci-provide-support-for-mio-instructions4
-rw-r--r--patches.arch/s390-pci-skip-vf-scanning30
-rw-r--r--patches.arch/x86-amd_nb-add-pci-device-ids-for-family-17h-model-30h.patch19
-rw-r--r--patches.arch/x86-amd_nb-add-support-for-raven-ridge-cpus.patch56
-rw-r--r--patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch65
-rw-r--r--patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch103
-rw-r--r--patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch72
-rw-r--r--patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch42
-rw-r--r--patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch94
-rw-r--r--patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch70
-rw-r--r--patches.drivers/drivers-depend-on-has_iomem-for-devm_platform_ioremap_resource36
-rw-r--r--patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch31
-rw-r--r--patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch64
-rw-r--r--patches.drivers/drivers-rapidio-devices-rio_mport_cdev.c-fix-resourc.patch44
-rw-r--r--patches.drivers/drivers-rapidio-rio_cm.c-fix-potential-oops-in-riocm.patch44
-rw-r--r--patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch60
-rw-r--r--patches.drivers/hwmon-k10temp-27c-offset-needed-for-threadripper2.patch28
-rw-r--r--patches.drivers/hwmon-k10temp-add-hygon-dhyana-support.patch39
-rw-r--r--patches.drivers/hwmon-k10temp-add-support-for-amd-family-17h-model-30h-cpus.patch4
-rw-r--r--patches.drivers/hwmon-k10temp-add-support-for-amd-ryzen-w-vega-graphics.patch40
-rw-r--r--patches.drivers/hwmon-k10temp-add-support-for-family-17h.patch67
-rw-r--r--patches.drivers/hwmon-k10temp-add-support-for-stoney-ridge-and-bristol.patch38
-rw-r--r--patches.drivers/hwmon-k10temp-add-support-for-temperature-offsets.patch77
-rw-r--r--patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-1900x.patch25
-rw-r--r--patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-2700x.patch62
-rw-r--r--patches.drivers/hwmon-k10temp-correct-model-name-for-ryzen-1600x.patch25
-rw-r--r--patches.drivers/hwmon-k10temp-display-both-tctl-and-tdie.patch138
-rw-r--r--patches.drivers/hwmon-k10temp-fix-reading-critical-temperature-register.patch116
-rw-r--r--patches.drivers/hwmon-k10temp-make-function-get_raw_temp-static.patch31
-rw-r--r--patches.drivers/hwmon-k10temp-move-chip-specific-code-into-probe-function.patch129
-rw-r--r--patches.drivers/hwmon-k10temp-only-apply-temperature-offset-if-result-is.patch38
-rw-r--r--patches.drivers/hwmon-k10temp-support-all-family-15h-model-6xh-and-model.patch36
-rw-r--r--patches.drivers/hwmon-k10temp-support-threadripper-2920x-2970wx-simplify.patch39
-rw-r--r--patches.drivers/hwmon-k10temp-use-api-function-to-access-system-management.patch78
-rw-r--r--patches.drivers/hwmon-k10temp-x86-amd_nb-consolidate-shared-device-ids.patch32
-rw-r--r--patches.drivers/i2c-piix4-add-hygon-dhyana-smbus-support.patch91
-rw-r--r--patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch41
-rw-r--r--patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch1410
-rw-r--r--patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch59
-rw-r--r--patches.drivers/platform-x86-asus-wmi-Only-Tell-EC-the-OS-will-handl.patch102
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch196
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch396
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch36
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch54
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch61
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch376
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch270
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch350
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch315
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch59
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch46
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch57
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch151
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch138
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch38
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch57
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch43
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch32
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch32
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch47
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch26
-rw-r--r--patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch49
-rw-r--r--patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch36
-rw-r--r--patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch31
-rw-r--r--patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch63
-rw-r--r--patches.drivers/qmi_wwan-add-network-device-usage-statistics-for-qmi.patch156
-rw-r--r--patches.drivers/qmi_wwan-add-support-for-QMAP-padding-in-the-RX-path.patch66
-rw-r--r--patches.drivers/qmi_wwan-avoid-RCU-stalls-on-device-disconnect-when-.patch76
-rw-r--r--patches.drivers/qmi_wwan-extend-permitted-QMAP-mux_id-value-range.patch60
-rw-r--r--patches.drivers/rapidio-fix-a-NULL-pointer-dereference-when-create_w.patch44
-rw-r--r--patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch141
-rw-r--r--patches.drivers/ras-cec-fix-binary-search-function.patch90
-rw-r--r--patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main2
-rw-r--r--patches.drivers/scsi-qla2xxx-Fix-FC-AL-connection-target-discovery.patch44
-rw-r--r--patches.drivers/scsi-qla2xxx-Fix-N2N-target-discovery-with-Local-loo.patch2
-rw-r--r--patches.drivers/soc-mediatek-pwrap-Zero-initialize-rdata-in-pwrap_in.patch46
-rw-r--r--patches.drivers/soc-rockchip-Set-the-proper-PWM-for-rk3288.patch57
-rw-r--r--patches.drivers/tty-max310x-Fix-external-crystal-register-setup.patch47
-rw-r--r--patches.drm/drm-i915-Add-new-AML_ULX-support-list.patch39
-rw-r--r--patches.drm/drm-i915-Add-new-ICL-PCI-ID.patch42
-rw-r--r--patches.drm/drm-i915-Apply-correct-ddi-translation-table-for-AML.patch66
-rw-r--r--patches.drm/drm-i915-Attach-the-pci-match-data-to-the-device-upo.patch141
-rw-r--r--patches.drm/drm-i915-Fix-uninitialized-mask-in-intel_device_info.patch51
-rw-r--r--patches.drm/drm-i915-Introduce-concept-of-a-sub-platform.patch416
-rw-r--r--patches.drm/drm-i915-Mark-AML-0x87CA-as-ULX.patch44
-rw-r--r--patches.drm/drm-i915-Move-final-cleanup-of-drm_i915_private-to-i.patch64
-rw-r--r--patches.drm/drm-i915-Remove-redundant-device-id-from-IS_IRONLAKE.patch61
-rw-r--r--patches.drm/drm-i915-Split-Pineview-device-info-into-desktop-and.patch119
-rw-r--r--patches.drm/drm-i915-Split-some-PCI-ids-into-separate-groups.patch351
-rw-r--r--patches.drm/drm-i915-aml-Add-new-Amber-Lake-PCI-ID.patch93
-rw-r--r--patches.drm/drm-i915-cfl-Adding-another-PCI-Device-ID.patch67
-rw-r--r--patches.drm/drm-i915-cml-Add-CML-PCI-IDS.patch93
-rw-r--r--patches.drm/drm-i915-icl-Adding-few-more-device-IDs-for-Ice-Lake.patch48
-rw-r--r--patches.drm/drm-i915-start-moving-runtime-device-info-to-a-separ.patch734
-rw-r--r--patches.fixes/0001-USB-serial-pl2303-fix-tranceiver-suspend-mode.patch83
-rw-r--r--patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch3
-rw-r--r--patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch3
-rw-r--r--patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch3
-rw-r--r--patches.fixes/0001-usb-xhci-avoid-null-pointer-deref-when-bos-field-is-.patch105
-rw-r--r--patches.fixes/6lowpan-Off-by-one-handling-nexthdr.patch41
-rw-r--r--patches.fixes/SMB3-Fix-endian-warning.patch40
-rw-r--r--patches.fixes/af_key-unconditionally-clone-on-broadcast.patch132
-rw-r--r--patches.fixes/audit-fix-a-memory-leak-bug.patch68
-rw-r--r--patches.fixes/ceph-factor-out-ceph_lookup_inode.patch64
-rw-r--r--patches.fixes/ceph-fix-null-pointer-deref-when-debugging-is-enabled.patch25
-rw-r--r--patches.fixes/ceph-fix-potential-use-after-free-in-ceph_mdsc_build_path.patch57
-rw-r--r--patches.fixes/ceph-flush-dirty-inodes-before-proceeding-with-remount.patch48
-rw-r--r--patches.fixes/ceph-print-inode-number-in-_caps_issued_mask-debugging-messages.patch55
-rw-r--r--patches.fixes/ceph-quota-fix-quota-subdir-mounts.patch347
-rw-r--r--patches.fixes/ceph-remove-duplicated-filelock-ref-increase.patch53
-rw-r--r--patches.fixes/cfg80211-fix-memory-leak-of-wiphy-device-name.patch39
-rw-r--r--patches.fixes/drivers-thermal-tsens-Don-t-print-error-message-on-E.patch38
-rw-r--r--patches.fixes/nfsd-COPY-and-CLONE-operations-require-the-saved-fil.patch2
-rw-r--r--patches.fixes/nl-mac-80211-allow-4addr-AP-operation-on-crypto-cont.patch107
-rw-r--r--patches.fixes/nl80211-fix-station_info-pertid-memory-leak.patch43
-rw-r--r--patches.fixes/pci-disable-vf-decoding-before-pcibios_sriov_disable-updates-resources72
-rw-r--r--patches.fixes/rbd-don-t-assert-on-writes-to-snapshots.patch44
-rw-r--r--patches.fixes/sched-topology-Improve-load-balancing-on-AMD-EPYC.patch144
-rw-r--r--patches.fixes/scsi-vmw_pscsi-Fix-use-after-free-in-pvscsi_queue_lc.patch51
-rw-r--r--patches.fixes/tcp-add-tcp_min_snd_mss-sysctl.patch3
-rw-r--r--patches.fixes/tcp-enforce-tcp_min_snd_mss-in-tcp_mtu_probing.patch4
-rw-r--r--patches.fixes/tcp-fix-fack_count-accounting-on-tcp_shift_skb_data.patch50
-rw-r--r--patches.fixes/tcp-limit-payload-size-of-sacked-skbs.patch29
-rw-r--r--patches.fixes/tcp-tcp_fragment-should-apply-sane-memory-limits.patch3
-rw-r--r--patches.fixes/thermal-rcar_gen3_thermal-disable-interrupt-in-.remo.patch42
-rw-r--r--patches.fixes/tmpfs-fix-link-accounting-when-a-tmpfile-is-linked-i.patch64
-rw-r--r--patches.fixes/tmpfs-fix-uninitialized-return-value-in-shmem_link.patch42
-rw-r--r--patches.fixes/vlan-disable-SIOCSHWTSTAMP-in-container.patch44
-rw-r--r--patches.kabi/asus-wmi-kabi-workaround.patch27
-rw-r--r--patches.kabi/kabi-x86-microcode-hotplug-state-fix.patch40
-rw-r--r--patches.kabi/pci-iov-add-flag-so-platforms-can-skip-vf-scanning25
-rw-r--r--patches.kabi/x86-topology-Add-CPUID.1F-multi-die-package-support.patch36
-rw-r--r--patches.kabi/x86-topology-Define-topology_logical_die_id.patch34
-rw-r--r--patches.suse/NFS-optional-NFSv4_2-fix.patch30
-rw-r--r--patches.suse/cpu-topology-Export-die_id.patch94
-rw-r--r--patches.suse/hwmon-coretemp-Cosmetic-Rename-internal-variables-to.patch133
-rw-r--r--patches.suse/hwmon-coretemp-Support-multi-die-package.patch65
-rw-r--r--patches.suse/ibmveth-Update-ethtool-settings-to-reflect-virtual-p.patch162
-rw-r--r--patches.suse/module-fix-livepatch-ftrace-module-text-permissions-race.patch170
-rw-r--r--patches.suse/pci-iov-add-flag-so-platforms-can-skip-vf-scanning52
-rw-r--r--patches.suse/pci-iov-factor-out-sriov_add_vfs98
-rw-r--r--patches.suse/perf-x86-intel-cstate-Support-multi-die-package.patch73
-rw-r--r--patches.suse/perf-x86-intel-rapl-Cosmetic-rename-internal-variabl.patch82
-rw-r--r--patches.suse/perf-x86-intel-rapl-Support-multi-die-package.patch78
-rw-r--r--patches.suse/perf-x86-intel-uncore-Cosmetic-renames-in-response-t.patch326
-rw-r--r--patches.suse/perf-x86-intel-uncore-Support-multi-die-package.patch120
-rw-r--r--patches.suse/powercap-intel_rapl-Simplify-rapl_find_package.patch96
-rw-r--r--patches.suse/powercap-intel_rapl-Support-multi-die-package.patch49
-rw-r--r--patches.suse/powercap-intel_rapl-Update-RAPL-domain-name-and-debu.patch199
-rw-r--r--patches.suse/thermal-x86_pkg_temp_thermal-Cosmetic-Rename-interna.patch404
-rw-r--r--patches.suse/thermal-x86_pkg_temp_thermal-Support-multi-die-packa.patch64
-rw-r--r--patches.suse/topology-Create-core_cpus-and-die_cpus-sysfs-attribu.patch240
-rw-r--r--patches.suse/topology-Create-package_cpus-sysfs-attribute.patch81
-rw-r--r--patches.suse/x86-cpufeatures-Carve-out-CQM-features-retrieval.patch105
-rw-r--r--patches.suse/x86-cpufeatures-Combine-word-11-and-12-into-a-new-sc.patch198
-rw-r--r--patches.suse/x86-cpufeatures-Enumerate-the-new-AVX512-BFLOAT16-in.patch109
-rw-r--r--patches.suse/x86-smpboot-Rename-match_die-to-match_pkg.patch54
-rw-r--r--patches.suse/x86-topology-Add-CPUID.1F-multi-die-package-support.patch238
-rw-r--r--patches.suse/x86-topology-Create-topology_max_die_per_package.patch86
-rw-r--r--patches.suse/x86-topology-Define-topology_die_id.patch31
-rw-r--r--patches.suse/x86-topology-Define-topology_logical_die_id.patch147
-rw-r--r--series.conf175
-rw-r--r--supported.conf1
173 files changed, 15874 insertions, 104 deletions
diff --git a/blacklist.conf b/blacklist.conf
index 60dbd54602..d71d7d1d0b 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -1167,3 +1167,4 @@ b616b9dbc5f613d64224b2e430211211812eadd0 # reverting drm/nouveau kconfig change
a25d8c327bb41742dbd59f8c545f59f3b9c39983 # md/raid5: reverting the above
9421e45f5ff3d558cf8b75a8cc0824530caf3453 # uio: reverted by the below
3d27c4de8d4fb2d4099ff324671792aa2578c6f9 # uio: reverting the above
+9d8d0294e78a164d407133dea05caf4b84247d6a # documentation only
diff --git a/config/arm64/default b/config/arm64/default
index 2401bdc425..c2fbff4e04 100644
--- a/config/arm64/default
+++ b/config/arm64/default
@@ -7220,6 +7220,10 @@ CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC_CHARDEV=m
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
+CONFIG_MELLANOX_PLATFORM=y
+CONFIG_MLXREG_HOTPLUG=m
+CONFIG_MLXREG_IO=m
+CONFIG_MLXBF_TMFIFO=m
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
diff --git a/patches.arch/PCI-Remove-reset-argument-from-pci_iov_-add-remove-_.patch b/patches.arch/PCI-Remove-reset-argument-from-pci_iov_-add-remove-_.patch
index 659991163c..61508aae86 100644
--- a/patches.arch/PCI-Remove-reset-argument-from-pci_iov_-add-remove-_.patch
+++ b/patches.arch/PCI-Remove-reset-argument-from-pci_iov_-add-remove-_.patch
@@ -68,7 +68,7 @@ index d9dc7363ac77..12c9779e02a0 100644
pci_device_add(virtfn, virtfn->bus);
pci_bus_add_device(virtfn);
-@@ -187,7 +184,7 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
+@@ -187,7 +184,7 @@ failed:
return rc;
}
@@ -105,8 +105,8 @@ index d9dc7363ac77..12c9779e02a0 100644
- pci_iov_remove_virtfn(dev, i, 0);
+ pci_iov_remove_virtfn(dev, i);
- pcibios_sriov_disable(dev);
err_pcibios:
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
@@ -355,7 +347,7 @@ static void sriov_disable(struct pci_dev *dev)
return;
@@ -114,8 +114,8 @@ index d9dc7363ac77..12c9779e02a0 100644
- pci_iov_remove_virtfn(dev, i, 0);
+ pci_iov_remove_virtfn(dev, i);
- pcibios_sriov_disable(dev);
-
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ pci_cfg_access_lock(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3a84c5f7fc94..8ae0fd23cb30 100644
--- a/include/linux/pci.h
diff --git a/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch b/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch
new file mode 100644
index 0000000000..6b9f1eb7d7
--- /dev/null
+++ b/patches.arch/kvm-x86-include-cpuid-leaf-0x8000001e-in-kvm-s-supported-cpuid.patch
@@ -0,0 +1,40 @@
+From: Jim Mattson <jmattson@google.com>
+Date: Wed, 27 Mar 2019 13:15:37 -0700
+Subject: kvm: x86: Include CPUID leaf 0x8000001e in kvm's supported CPUID
+Git-commit: 382409b4c43e5b44ae4a869ff793d3cf01d12004
+Patch-mainline: v5.2-rc2
+References: bsc#1114279
+
+Kvm now supports extended CPUID functions through 0x8000001f. CPUID
+leaf 0x8000001e is AMD's Processor Topology Information leaf. This
+contains similar information to CPUID leaf 0xb (Intel's Extended
+Topology Enumeration leaf), and should be included in the output of
+KVM_GET_SUPPORTED_CPUID, even though userspace is likely to override
+some of this information based upon the configuration of the
+particular VM.
+
+Cc: Brijesh Singh <brijesh.singh@amd.com>
+Cc: Borislav Petkov <bp@suse.de>
+Fixes: 8765d75329a38 ("KVM: X86: Extend CPUID range to include new leaf")
+Signed-off-by: Jim Mattson <jmattson@google.com>
+Reviewed-by: Marc Orr <marcorr@google.com>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ arch/x86/kvm/cpuid.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
+index 3c96ce8fbb96..e18a9f9f65b5 100644
+--- a/arch/x86/kvm/cpuid.c
++++ b/arch/x86/kvm/cpuid.c
+@@ -702,6 +702,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ entry->ecx = entry->edx = 0;
+ break;
+ case 0x8000001a:
++ case 0x8000001e:
+ break;
+ /*Add support for Centaur's CPUID instruction*/
+ case 0xC0000000:
+
diff --git a/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch b/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch
new file mode 100644
index 0000000000..96647bad22
--- /dev/null
+++ b/patches.arch/kvm-x86-include-multiple-indices-with-cpuid-leaf-0x8000001d.patch
@@ -0,0 +1,57 @@
+From: Jim Mattson <jmattson@google.com>
+Date: Wed, 27 Mar 2019 13:15:36 -0700
+Subject: kvm: x86: Include multiple indices with CPUID leaf 0x8000001d
+Git-commit: 32a243df82c8dc04ccba7fc6c6564ae9261cb738
+Patch-mainline: v5.2-rc2
+References: bsc#1114279
+
+Per the APM, "CPUID Fn8000_001D_E[D,C,B,A]X reports cache topology
+information for the cache enumerated by the value passed to the
+instruction in ECX, referred to as Cache n in the following
+description. To gather information for all cache levels, software must
+repeatedly execute CPUID with 8000_001Dh in EAX and ECX set to
+increasing values beginning with 0 until a value of 00h is returned in
+the field CacheType (EAX[4:0]) indicating no more cache descriptions
+are available for this processor."
+
+The termination condition is the same as leaf 4, so we can reuse that
+code block for leaf 0x8000001d.
+
+Fixes: 8765d75329a38 ("KVM: X86: Extend CPUID range to include new leaf")
+Cc: Brijesh Singh <brijesh.singh@amd.com>
+Cc: Borislav Petkov <bp@suse.de>
+Signed-off-by: Jim Mattson <jmattson@google.com>
+Reviewed-by: Marc Orr <marcorr@google.com>
+Reviewed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ arch/x86/kvm/cpuid.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
+index 80a642a0143d..3c96ce8fbb96 100644
+--- a/arch/x86/kvm/cpuid.c
++++ b/arch/x86/kvm/cpuid.c
+@@ -456,8 +456,9 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ }
+ break;
+ }
+- /* function 4 has additional index. */
+- case 4: {
++ /* functions 4 and 0x8000001d have additional index. */
++ case 4:
++ case 0x8000001d: {
+ int i, cache_type;
+
+ entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+@@ -702,8 +703,6 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
+ break;
+ case 0x8000001a:
+ break;
+- case 0x8000001d:
+- break;
+ /*Add support for Centaur's CPUID instruction*/
+ case 0xC0000000:
+ /*Just support up to 0xC0000004 now*/
+
diff --git a/patches.arch/powerpc-pseries-dlpar-Fix-a-missing-check-in-dlpar_p.patch b/patches.arch/powerpc-pseries-dlpar-Fix-a-missing-check-in-dlpar_p.patch
new file mode 100644
index 0000000000..412f1cfa75
--- /dev/null
+++ b/patches.arch/powerpc-pseries-dlpar-Fix-a-missing-check-in-dlpar_p.patch
@@ -0,0 +1,40 @@
+From efa9ace68e487ddd29c2b4d6dd23242158f1f607 Mon Sep 17 00:00:00 2001
+From: Gen Zhang <blackgod016574@gmail.com>
+Date: Sun, 26 May 2019 10:42:40 +0800
+Subject: [PATCH] powerpc/pseries/dlpar: Fix a missing check in
+ dlpar_parse_cc_property()
+
+References: bsc#1137194, CVE-2019-12614
+Patch-mainline: queued
+Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
+Git-commit: efa9ace68e487ddd29c2b4d6dd23242158f1f607
+
+In dlpar_parse_cc_property(), 'prop->name' is allocated by kstrdup().
+kstrdup() may return NULL, so it should be checked and handle error.
+And prop should be freed if 'prop->name' is NULL.
+
+Signed-off-by: Gen Zhang <blackgod016574@gmail.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Acked-by: Michal Suchanek <msuchanek@suse.de>
+---
+ arch/powerpc/platforms/pseries/dlpar.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
+index 17958043e7f7..c852024044bb 100644
+--- a/arch/powerpc/platforms/pseries/dlpar.c
++++ b/arch/powerpc/platforms/pseries/dlpar.c
+@@ -61,6 +61,10 @@ static struct property *dlpar_parse_cc_property(struct cc_workarea *ccwa)
+
+ name = (char *)ccwa + be32_to_cpu(ccwa->name_offset);
+ prop->name = kstrdup(name, GFP_KERNEL);
++ if (!prop->name) {
++ dlpar_free_cc_property(prop);
++ return NULL;
++ }
+
+ prop->length = be32_to_cpu(ccwa->prop_length);
+ value = (char *)ccwa + be32_to_cpu(ccwa->prop_offset);
+--
+2.21.0
+
diff --git a/patches.arch/s390-jump_label-Use-jdd-constraint-on-gcc9.patch b/patches.arch/s390-jump_label-Use-jdd-constraint-on-gcc9.patch
new file mode 100644
index 0000000000..d6f09a9478
--- /dev/null
+++ b/patches.arch/s390-jump_label-Use-jdd-constraint-on-gcc9.patch
@@ -0,0 +1,72 @@
+From 146448524bddbf6dfc62de31957e428de001cbda Mon Sep 17 00:00:00 2001
+From: Ilya Leoshkevich <iii@linux.ibm.com>
+Date: Wed, 6 Feb 2019 12:35:58 +0100
+Subject: [PATCH] s390/jump_label: Use "jdd" constraint on gcc9
+
+References: bsc#1138589
+Patch-mainline: v5.1-rc1
+Git-commit: 146448524bddbf6dfc62de31957e428de001cbda
+
+[heiko.carstens@de.ibm.com]:
+-----
+Laura Abbott reported that the kernel doesn't build anymore with gcc 9,
+due to the "X" constraint. Ilya provided the gcc 9 patch "S/390:
+Introduce jdd constraint" which introduces the new "jdd" constraint
+which fixes this.
+-----
+
+The support for section anchors on S/390 introduced in gcc9 has changed
+the behavior of "X" constraint, which can now produce register
+references. Since existing constraints, in particular, "i", do not fit
+the intended use case on S/390, the new machine-specific "jdd"
+constraint was introduced. This patch makes jump labels use "jdd"
+constraint when building with gcc9.
+
+Reported-by: Laura Abbott <labbott@redhat.com>
+Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
+Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
+Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
+Acked-by: Michal Suchanek <msuchanek@suse.de>
+---
+ arch/s390/include/asm/jump_label.h | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/arch/s390/include/asm/jump_label.h
++++ b/arch/s390/include/asm/jump_label.h
+@@ -9,6 +9,12 @@
+ #define JUMP_LABEL_NOP_SIZE 6
+ #define JUMP_LABEL_NOP_OFFSET 2
+
++#if __GNUC__ < 9
++#define JUMP_LABEL_STATIC_KEY_CONSTRAINT "X"
++#else
++#define JUMP_LABEL_STATIC_KEY_CONSTRAINT "jdd"
++#endif
++
+ /*
+ * We use a brcl 0,2 instruction for jump labels at compile time so it
+ * can be easily distinguished from a hotpatch generated instruction.
+@@ -18,9 +24,9 @@ static __always_inline bool arch_static_
+ asm_volatile_goto("0: brcl 0,"__stringify(JUMP_LABEL_NOP_OFFSET)"\n"
+ ".pushsection __jump_table, \"aw\"\n"
+ ".balign 8\n"
+- ".quad 0b, %l[label], %0\n"
++ ".quad 0b, %l[label], %0+%1\n"
+ ".popsection\n"
+- : : "X" (&((char *)key)[branch]) : : label);
++ : : JUMP_LABEL_STATIC_KEY_CONSTRAINT (key), "i" (branch) : : label);
+
+ return false;
+ label:
+@@ -32,9 +38,9 @@ static __always_inline bool arch_static_
+ asm_volatile_goto("0: brcl 15, %l[label]\n"
+ ".pushsection __jump_table, \"aw\"\n"
+ ".balign 8\n"
+- ".quad 0b, %l[label], %0\n"
++ ".quad 0b, %l[label], %0+%1\n"
+ ".popsection\n"
+- : : "X" (&((char *)key)[branch]) : : label);
++ : : JUMP_LABEL_STATIC_KEY_CONSTRAINT (key), "i" (branch) : : label);
+
+ return false;
+ label:
diff --git a/patches.arch/s390-pci-improve-bar-check b/patches.arch/s390-pci-improve-bar-check
new file mode 100644
index 0000000000..0517719633
--- /dev/null
+++ b/patches.arch/s390-pci-improve-bar-check
@@ -0,0 +1,29 @@
+From: Sebastian Ott <sebott@linux.ibm.com>
+Date: Tue, 31 Jul 2018 09:59:09 -0400
+Subject: s390/pci: improve bar check
+Git-commit: e8e25a7718cf64701ddf7f7b2e31c79815b613f1
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-5803 FATE#327056
+
+Improve the bar check in pci_iomap_range to cover functions
+for which we recognize more bars than what we can access due
+to AR restrictions.
+
+Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ arch/s390/pci/pci.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/s390/pci/pci.c
++++ b/arch/s390/pci/pci.c
+@@ -288,7 +288,7 @@ void __iomem *pci_iomap_range(struct pci
+ struct zpci_dev *zdev = to_zpci(pdev);
+ int idx;
+
+- if (!pci_resource_len(pdev, bar))
++ if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
+ return NULL;
+
+ idx = zdev->bars[bar].map_idx;
diff --git a/patches.arch/s390-pci-map-iov-resources b/patches.arch/s390-pci-map-iov-resources
new file mode 100644
index 0000000000..ca0954b319
--- /dev/null
+++ b/patches.arch/s390-pci-map-iov-resources
@@ -0,0 +1,53 @@
+From: Sebastian Ott <sebott@linux.ibm.com>
+Date: Wed, 12 Sep 2018 12:47:37 +0200
+Subject: s390/pci: map IOV resources
+Git-commit: cfbb4a7ab6bd5df7aca826b92ebb3565efd3d801
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-5803 FATE#327056
+
+Map IOV resources such that pci common code recognizes the IOV
+capability of PFs.
+
+Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ arch/s390/pci/pci.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/s390/pci/pci.c
++++ b/arch/s390/pci/pci.c
+@@ -487,6 +487,15 @@ void arch_teardown_msi_irqs(struct pci_d
+ }
+ }
+
++#ifdef CONFIG_PCI_IOV
++static struct resource iov_res = {
++ .name = "PCI IOV res",
++ .start = 0,
++ .end = -1,
++ .flags = IORESOURCE_MEM,
++};
++#endif
++
+ static void zpci_map_resources(struct pci_dev *pdev)
+ {
+ resource_size_t len;
+@@ -500,6 +509,17 @@ static void zpci_map_resources(struct pc
+ (resource_size_t __force) pci_iomap(pdev, i, 0);
+ pdev->resource[i].end = pdev->resource[i].start + len - 1;
+ }
++
++#ifdef CONFIG_PCI_IOV
++ i = PCI_IOV_RESOURCES;
++
++ for (; i < PCI_SRIOV_NUM_BARS + PCI_IOV_RESOURCES; i++) {
++ len = pci_resource_len(pdev, i);
++ if (!len)
++ continue;
++ pdev->resource[i].parent = &iov_res;
++ }
++#endif
+ }
+
+ static void zpci_unmap_resources(struct pci_dev *pdev)
diff --git a/patches.arch/s390-pci-move-everything-irq-related-to-pci_irq-c b/patches.arch/s390-pci-move-everything-irq-related-to-pci_irq-c
index e5f70bc23b..e5d53bd030 100644
--- a/patches.arch/s390-pci-move-everything-irq-related-to-pci_irq-c
+++ b/patches.arch/s390-pci-move-everything-irq-related-to-pci_irq-c
@@ -263,9 +263,9 @@ Acked-by: Petr Tesarik <ptesarik@suse.com>
- }
-}
-
- static void zpci_map_resources(struct pci_dev *pdev)
- {
- resource_size_t len;
+ #ifdef CONFIG_PCI_IOV
+ static struct resource iov_res = {
+ .name = "PCI IOV res",
@@ -514,41 +333,6 @@ static void zpci_unmap_resources(struct
}
}
diff --git a/patches.arch/s390-pci-provide-support-for-mio-instructions b/patches.arch/s390-pci-provide-support-for-mio-instructions
index 6febf852fb..c2bae3c646 100644
--- a/patches.arch/s390-pci-provide-support-for-mio-instructions
+++ b/patches.arch/s390-pci-provide-support-for-mio-instructions
@@ -212,7 +212,7 @@ Acked-by: Petr Tesarik <ptesarik@suse.com>
struct zpci_dev *zdev = to_zpci(pdev);
int idx;
-- if (!pci_resource_len(pdev, bar))
+- if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
- return NULL;
-
idx = zdev->bars[bar].map_idx;
@@ -331,7 +331,7 @@ Acked-by: Petr Tesarik <ptesarik@suse.com>
+ (resource_size_t __force) pci_iomap(pdev, i, 0);
pdev->resource[i].end = pdev->resource[i].start + len - 1;
}
- }
+
@@ -325,6 +431,9 @@ static void zpci_unmap_resources(struct
resource_size_t len;
int i;
diff --git a/patches.arch/s390-pci-skip-vf-scanning b/patches.arch/s390-pci-skip-vf-scanning
new file mode 100644
index 0000000000..b01dde5dd5
--- /dev/null
+++ b/patches.arch/s390-pci-skip-vf-scanning
@@ -0,0 +1,30 @@
+From: Sebastian Ott <sebott@linux.ibm.com>
+Date: Fri, 21 Dec 2018 15:14:20 +0100
+Subject: s390/pci: skip VF scanning
+Git-commit: 7dc20ab1b9c431b792a6fe1e78baf36b63edc5e3
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-5803 FATE#327056
+
+Set the flag to skip scanning for VFs after SR-IOV enablement. VF creation
+will be triggered by the hotplug code.
+
+Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ arch/s390/pci/pci.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/s390/pci/pci.c
++++ b/arch/s390/pci/pci.c
+@@ -654,6 +654,9 @@ int pcibios_add_device(struct pci_dev *p
+ struct resource *res;
+ int i;
+
++ if (pdev->is_physfn)
++ pdev->no_vf_scan = 1;
++
+ pdev->dev.groups = zpci_attr_groups;
+ pdev->dev.dma_ops = &s390_pci_dma_ops;
+ zpci_map_resources(pdev);
diff --git a/patches.arch/x86-amd_nb-add-pci-device-ids-for-family-17h-model-30h.patch b/patches.arch/x86-amd_nb-add-pci-device-ids-for-family-17h-model-30h.patch
index 17c39d1ebd..f45d89847a 100644
--- a/patches.arch/x86-amd_nb-add-pci-device-ids-for-family-17h-model-30h.patch
+++ b/patches.arch/x86-amd_nb-add-pci-device-ids-for-family-17h-model-30h.patch
@@ -30,20 +30,21 @@ Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
-@@ -15,7 +15,9 @@
- #include <asm/amd_nb.h>
+@@ -16,8 +16,10 @@
#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
+ #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
+#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
/* Protect the PCI config register pairs used for SMN and DF indirect access. */
static DEFINE_MUTEX(smn_mutex);
-@@ -24,9 +26,11 @@ static u32 *flush_words;
-
+@@ -27,9 +29,11 @@ static u32 *flush_words;
static const struct pci_device_id amd_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
{}
};
@@ -52,25 +53,25 @@ Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com
#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
const struct pci_device_id amd_nb_misc_ids[] = {
-@@ -39,6 +43,7 @@ const struct pci_device_id amd_nb_misc_i
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+@@ -43,6 +47,7 @@ const struct pci_device_id amd_nb_misc_i
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{}
};
-@@ -51,6 +56,7 @@ static const struct pci_device_id amd_nb
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+@@ -56,6 +61,7 @@ static const struct pci_device_id amd_nb
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
{}
};
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
-@@ -539,6 +539,7 @@
+@@ -542,6 +542,7 @@
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
diff --git a/patches.arch/x86-amd_nb-add-support-for-raven-ridge-cpus.patch b/patches.arch/x86-amd_nb-add-support-for-raven-ridge-cpus.patch
new file mode 100644
index 0000000000..9da914c237
--- /dev/null
+++ b/patches.arch/x86-amd_nb-add-support-for-raven-ridge-cpus.patch
@@ -0,0 +1,56 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Fri, 4 May 2018 13:01:32 -0700
+Subject: x86/amd_nb: Add support for Raven Ridge CPUs
+Git-commit: f9bc6b2dd9cf025f827f471769e1d88b527bfb91
+Patch-mainline: v4.17
+References: FATE#327735
+
+Add Raven Ridge root bridge and data fabric PCI IDs.
+This is required for amd_pci_dev_to_node_id() and amd_smn_read().
+
+Cc: stable@vger.kernel.org # v4.16+
+Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index c88e0b127810..b481b95bd8f6 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -14,8 +14,11 @@
+ #include <asm/amd_nb.h>
+
+ #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
++#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
++#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
++#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+ static DEFINE_MUTEX(smn_mutex);
+@@ -24,6 +27,7 @@ static u32 *flush_words;
+
+ static const struct pci_device_id amd_root_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
+ {}
+ };
+
+@@ -39,6 +43,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
+ {}
+ };
+@@ -51,6 +56,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+ {}
+ };
diff --git a/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch b/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch
new file mode 100644
index 0000000000..41cd328937
--- /dev/null
+++ b/patches.arch/x86-cpu-amd-don-t-force-the-cpb-cap-when-running-under-a-hypervisor.patch
@@ -0,0 +1,65 @@
+From: Frank van der Linden <fllinden@amazon.com>
+Date: Wed, 22 May 2019 22:17:45 +0000
+Subject: x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor
+Git-commit: 2ac44ab608705948564791ce1d15d43ba81a1e38
+Patch-mainline: v5.2-rc3
+References: bsc#1114279
+
+For F17h AMD CPUs, the CPB capability ('Core Performance Boost') is forcibly set,
+because some versions of that chip incorrectly report that they do not have it.
+
+However, a hypervisor may filter out the CPB capability, for good
+reasons. For example, KVM currently does not emulate setting the CPB
+bit in MSR_K7_HWCR, and unchecked MSR access errors will be thrown
+when trying to set it as a guest:
+
+ unchecked MSR access error: WRMSR to 0xc0010015 (tried to write 0x0000000001000011) at rIP: 0xffffffff890638f4 (native_write_msr+0x4/0x20)
+
+ Call Trace:
+ boost_set_msr+0x50/0x80 [acpi_cpufreq]
+ cpuhp_invoke_callback+0x86/0x560
+ sort_range+0x20/0x20
+ cpuhp_thread_fun+0xb0/0x110
+ smpboot_thread_fn+0xef/0x160
+ kthread+0x113/0x130
+ kthread_create_worker_on_cpu+0x70/0x70
+ ret_from_fork+0x35/0x40
+
+To avoid this issue, don't forcibly set the CPB capability for a CPU
+when running under a hypervisor.
+
+Signed-off-by: Frank van der Linden <fllinden@amazon.com>
+Acked-by: Borislav Petkov <bp@suse.de>
+Cc: Andy Lutomirski <luto@kernel.org>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: bp@alien8.de
+Cc: jiaxun.yang@flygoat.com
+Fixes: 0237199186e7 ("x86/CPU/AMD: Set the CPB bit unconditionally on F17h")
+Link: http://lkml.kernel.org/r/20190522221745.GA15789@dev-dsk-fllinden-2c-c1893d73.us-west-2.amazon.com
+[ Minor edits to the changelog. ]
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+---
+ arch/x86/kernel/cpu/amd.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+index 80a405c2048a..8d4e50428b68 100644
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -824,8 +824,11 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
+ {
+ set_cpu_cap(c, X86_FEATURE_ZEN);
+
+- /* Fix erratum 1076: CPB feature bit not being set in CPUID. */
+- if (!cpu_has(c, X86_FEATURE_CPB))
++ /*
++ * Fix erratum 1076: CPB feature bit not being set in CPUID.
++ * Always set it, except when running under a hypervisor.
++ */
++ if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
+ set_cpu_cap(c, X86_FEATURE_CPB);
+ }
+
+
diff --git a/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch b/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
new file mode 100644
index 0000000000..ed550385fe
--- /dev/null
+++ b/patches.arch/x86-mce-fix-machine_check_poll-tests-for-error-types.patch
@@ -0,0 +1,103 @@
+From: Tony Luck <tony.luck@intel.com>
+Date: Tue, 12 Mar 2019 10:09:38 -0700
+Subject: x86/mce: Fix machine_check_poll() tests for error types
+Git-commit: f19501aa07f18268ab14f458b51c1c6b7f72a134
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+There has been a lurking "TBD" in the machine check poll routine ever
+since it was first split out from the machine check handler. The
+potential issue is that the poll routine may have just begun a read from
+the STATUS register in a machine check bank when the hardware logs an
+error in that bank and signals a machine check.
+
+That race used to be pretty small back when machine checks were
+broadcast, but the addition of local machine check means that the poll
+code could continue running and clear the error from the bank before the
+local machine check handler on another CPU gets around to reading it.
+
+Fix the code to be sure to only process errors that need to be processed
+in the poll code, leaving other logged errors alone for the machine
+check handler to find and process.
+
+ [ bp: Massage a bit and flip the "== 0" check to the usual !(..) test. ]
+
+Fixes: b79109c3bbcf ("x86, mce: separate correct machine check poller and fatal exception handler")
+Fixes: ed7290d0ee8f ("x86, mce: implement new status bits")
+Reported-by: Ashok Raj <ashok.raj@intel.com>
+Signed-off-by: Tony Luck <tony.luck@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: x86-ml <x86@kernel.org>
+Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
+Link: https://lkml.kernel.org/r/20190312170938.GA23035@agluck-desk
+---
+ arch/x86/kernel/cpu/mcheck/mce.c | 44 +++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 37 insertions(+), 7 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
+index b7fb541a4873..e558ca77cfe8 100644
+--- a/arch/x86/kernel/cpu/mcheck/mce.c
++++ b/arch/x86/kernel/cpu/mcheck/mce.c
+@@ -712,19 +712,49 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
+
+ barrier();
+ m.status = mce_rdmsrl(msr_ops.status(i));
++
++ /* If this entry is not valid, ignore it */
+ if (!(m.status & MCI_STATUS_VAL))
+ continue;
+
+ /*
+- * Uncorrected or signalled events are handled by the exception
+- * handler when it is enabled, so don't process those here.
+- *
+- * TBD do the same check for MCI_STATUS_EN here?
++ * If we are logging everything (at CPU online) or this
++ * is a corrected error, then we must log it.
+ */
+- if (!(flags & MCP_UC) &&
+- (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
+- continue;
++ if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
++ goto log_it;
++
++ /*
++ * Newer Intel systems that support software error
++ * recovery need to make additional checks. Other
++ * CPUs should skip over uncorrected errors, but log
++ * everything else.
++ */
++ if (!mca_cfg.ser) {
++ if (m.status & MCI_STATUS_UC)
++ continue;
++ goto log_it;
++ }
++
++ /* Log "not enabled" (speculative) errors */
++ if (!(m.status & MCI_STATUS_EN))
++ goto log_it;
++
++ /*
++ * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
++ * UC == 1 && PCC == 0 && S == 0
++ */
++ if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
++ goto log_it;
++
++ /*
++ * Skip anything else. Presumption is that our read of this
++ * bank is racing with a machine check. Leave the log alone
++ * for do_machine_check() to deal with it.
++ */
++ continue;
+
++log_it:
+ error_seen = true;
+
+ mce_read_aux(&m, i);
+
diff --git a/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch b/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch
new file mode 100644
index 0000000000..feaa22f1ea
--- /dev/null
+++ b/patches.arch/x86-microcode-cpuhotplug-add-a-microcode-loader-cpu-hotplug-callback.patch
@@ -0,0 +1,72 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Thu, 13 Jun 2019 15:49:02 +0200
+Subject: x86/microcode, cpuhotplug: Add a microcode loader CPU hotplug callback
+Git-commit: 78f4e932f7760d965fb1569025d1576ab77557c5
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+Adric Blake reported the following warning during suspend-resume:
+
+ Enabling non-boot CPUs ...
+ x86: Booting SMP configuration:
+ smpboot: Booting Node 0 Processor 1 APIC 0x2
+ unchecked MSR access error: WRMSR to 0x10f (tried to write 0x0000000000000000) \
+ at rIP: 0xffffffff8d267924 (native_write_msr+0x4/0x20)
+ Call Trace:
+ intel_set_tfa
+ intel_pmu_cpu_starting
+ ? x86_pmu_dead_cpu
+ x86_pmu_starting_cpu
+ cpuhp_invoke_callback
+ ? _raw_spin_lock_irqsave
+ notify_cpu_starting
+ start_secondary
+ secondary_startup_64
+ microcode: sig=0x806ea, pf=0x80, revision=0x96
+ microcode: updated to revision 0xb4, date = 2019-04-01
+ CPU1 is up
+
+The MSR in question is MSR_TFA_RTM_FORCE_ABORT and that MSR is emulated
+by microcode. The log above shows that the microcode loader callback
+happens after the PMU restoration, leading to the conjecture that
+because the microcode hasn't been updated yet, that MSR is not present
+yet, leading to the #GP.
+
+Add a microcode loader-specific hotplug vector which comes before
+the PERF vectors and thus executes earlier and makes sure the MSR is
+present.
+
+Fixes: 400816f60c54 ("perf/x86/intel: Implement support for TSX Force Abort")
+Reported-by: Adric Blake <promarbler14@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: <stable@vger.kernel.org>
+Cc: x86@kernel.org
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=203637
+---
+ arch/x86/kernel/cpu/microcode/core.c | 2 +-
+ include/linux/cpuhotplug.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/x86/kernel/cpu/microcode/core.c
++++ b/arch/x86/kernel/cpu/microcode/core.c
+@@ -853,7 +853,7 @@ int __init microcode_init(void)
+ goto out_ucode_group;
+
+ register_syscore_ops(&mc_syscore_ops);
+- cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
++ cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:online",
+ mc_cpu_online, mc_cpu_down_prep);
+
+ pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION);
+--- a/include/linux/cpuhotplug.h
++++ b/include/linux/cpuhotplug.h
+@@ -84,6 +84,7 @@ enum cpuhp_state {
+ CPUHP_AP_IRQ_ARMADA_XP_STARTING,
+ CPUHP_AP_IRQ_BCM2836_STARTING,
+ CPUHP_AP_ARM_MVEBU_COHERENCY,
++ CPUHP_AP_MICROCODE_LOADER,
+ CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
+ CPUHP_AP_PERF_X86_STARTING,
+ CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
diff --git a/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch b/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch
new file mode 100644
index 0000000000..09f5dbadd8
--- /dev/null
+++ b/patches.arch/x86-microcode-fix-the-ancient-deprecated-microcode-loading-method.patch
@@ -0,0 +1,42 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Thu, 4 Apr 2019 22:14:07 +0200
+Subject: x86/microcode: Fix the ancient deprecated microcode loading method
+Git-commit: 24613a04ad1c0588c10f4b5403ca60a73d164051
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+Commit
+
+ 2613f36ed965 ("x86/microcode: Attempt late loading only when new microcode is present")
+
+added the new define UCODE_NEW to denote that an update should happen
+only when newer microcode (than installed on the system) has been found.
+
+But it missed adjusting that for the old /dev/cpu/microcode loading
+interface. Fix it.
+
+Fixes: 2613f36ed965 ("x86/microcode: Attempt late loading only when new microcode is present")
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Jann Horn <jannh@google.com>
+Link: https://lkml.kernel.org/r/20190405133010.24249-3-bp@alien8.de
+---
+ arch/x86/kernel/cpu/microcode/core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
+index 5260185cbf7b..8a4a7823451a 100644
+--- a/arch/x86/kernel/cpu/microcode/core.c
++++ b/arch/x86/kernel/cpu/microcode/core.c
+@@ -418,8 +418,9 @@ static int do_microcode_update(const void __user *buf, size_t size)
+ if (ustate == UCODE_ERROR) {
+ error = -1;
+ break;
+- } else if (ustate == UCODE_OK)
++ } else if (ustate == UCODE_NEW) {
+ apply_microcode_on_target(cpu);
++ }
+ }
+
+ return error;
+
diff --git a/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch b/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch
new file mode 100644
index 0000000000..71866ad228
--- /dev/null
+++ b/patches.arch/x86-mm-mem_encrypt-disable-all-instrumentation-for-early-sme-setup.patch
@@ -0,0 +1,94 @@
+From: Gary Hook <Gary.Hook@amd.com>
+Date: Mon, 29 Apr 2019 22:22:58 +0000
+Subject: x86/mm/mem_encrypt: Disable all instrumentation for early SME setup
+Git-commit: b51ce3744f115850166f3d6c292b9c8cb849ad4f
+Patch-mainline: v5.1
+References: bsc#1114279
+
+Enablement of AMD's Secure Memory Encryption feature is determined very
+early after start_kernel() is entered. Part of this procedure involves
+scanning the command line for the parameter 'mem_encrypt'.
+
+To determine intended state, the function sme_enable() uses library
+functions cmdline_find_option() and strncmp(). Their use occurs early
+enough such that it cannot be assumed that any instrumentation subsystem
+is initialized.
+
+For example, making calls to a KASAN-instrumented function before KASAN
+is set up will result in the use of uninitialized memory and a boot
+failure.
+
+When AMD's SME support is enabled, conditionally disable instrumentation
+of these dependent functions in lib/string.c and arch/x86/lib/cmdline.c.
+
+ [ bp: Get rid of intermediary nostackp var and cleanup whitespace. ]
+
+Fixes: aca20d546214 ("x86/mm: Add support to make use of Secure Memory Encryption")
+Reported-by: Li RongQing <lirongqing@baidu.com>
+Signed-off-by: Gary R Hook <gary.hook@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Cc: Boris Brezillon <bbrezillon@kernel.org>
+Cc: Coly Li <colyli@suse.de>
+Cc: "dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Kees Cook <keescook@chromium.org>
+Cc: Kent Overstreet <kent.overstreet@gmail.com>
+Cc: "luto@kernel.org" <luto@kernel.org>
+Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
+Cc: Matthew Wilcox <willy@infradead.org>
+Cc: "mingo@redhat.com" <mingo@redhat.com>
+Cc: "peterz@infradead.org" <peterz@infradead.org>
+Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: x86-ml <x86@kernel.org>
+Link: https://lkml.kernel.org/r/155657657552.7116.18363762932464011367.stgit@sosrh3.amd.com
+---
+ arch/x86/lib/Makefile | 12 ++++++++++++
+ lib/Makefile | 11 +++++++++++
+ 2 files changed, 23 insertions(+)
+
+--- a/arch/x86/lib/Makefile
++++ b/arch/x86/lib/Makefile
+@@ -5,6 +5,18 @@
+ # Produces uninteresting flaky coverage.
+ KCOV_INSTRUMENT_delay.o := n
+
++# Early boot use of cmdline; don't instrument it
++ifdef CONFIG_AMD_MEM_ENCRYPT
++KCOV_INSTRUMENT_cmdline.o := n
++KASAN_SANITIZE_cmdline.o := n
++
++ifdef CONFIG_FUNCTION_TRACER
++CFLAGS_REMOVE_cmdline.o = -pg
++endif
++
++CFLAGS_cmdline.o := $(call cc-option, -fno-stack-protector)
++endif
++
+ inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk
+ inat_tables_maps = $(srctree)/arch/x86/lib/x86-opcode-map.txt
+ quiet_cmd_inat_tables = GEN $@
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -16,6 +16,17 @@ KCOV_INSTRUMENT_list_debug.o := n
+ KCOV_INSTRUMENT_debugobjects.o := n
+ KCOV_INSTRUMENT_dynamic_debug.o := n
+
++# Early boot use of cmdline, don't instrument it
++ifdef CONFIG_AMD_MEM_ENCRYPT
++KASAN_SANITIZE_string.o := n
++
++ifdef CONFIG_FUNCTION_TRACER
++CFLAGS_REMOVE_string.o = -pg
++endif
++
++CFLAGS_string.o := $(call cc-option, -fno-stack-protector)
++endif
++
+ lib-y := ctype.o string.o vsprintf.o cmdline.o \
+ rbtree.o radix-tree.o dump_stack.o timerqueue.o\
+ idr.o int_sqrt.o extable.o \
diff --git a/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch b/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch
new file mode 100644
index 0000000000..4e0b16cc72
--- /dev/null
+++ b/patches.arch/x86-speculation-mds-revert-cpu-buffer-clear-on-double-fault-exit.patch
@@ -0,0 +1,70 @@
+From: Andy Lutomirski <luto@kernel.org>
+Date: Tue, 14 May 2019 13:24:39 -0700
+Subject: x86/speculation/mds: Revert CPU buffer clear on double fault exit
+Git-commit: 88640e1dcd089879530a49a8d212d1814678dfe7
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+The double fault ESPFIX path doesn't return to user mode at all --
+it returns back to the kernel by simulating a #GP fault.
+prepare_exit_to_usermode() will run on the way out of
+general_protection before running user code.
+
+Signed-off-by: Andy Lutomirski <luto@kernel.org>
+Cc: Borislav Petkov <bp@suse.de>
+Cc: Frederic Weisbecker <frederic@kernel.org>
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: Jon Masters <jcm@redhat.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: stable@vger.kernel.org
+Fixes: 04dcbdb80578 ("x86/speculation/mds: Clear CPU buffers on exit to user")
+Link: http://lkml.kernel.org/r/ac97612445c0a44ee10374f6ea79c222fe22a5c4.1557865329.git.luto@kernel.org
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Borislav Petkov <bp@suse.de>
+---
+ Documentation/x86/mds.rst | 7 -------
+ arch/x86/kernel/traps.c | 8 --------
+ 2 files changed, 15 deletions(-)
+
+--- a/arch/x86/kernel/traps.c
++++ b/arch/x86/kernel/traps.c
+@@ -59,7 +59,6 @@
+ #include <asm/alternative.h>
+ #include <asm/fpu/xstate.h>
+ #include <asm/trace/mpx.h>
+-#include <asm/nospec-branch.h>
+ #include <asm/mpx.h>
+ #include <asm/vm86.h>
+ #include <asm/umip.h>
+@@ -394,13 +393,6 @@ dotraplinkage void do_double_fault(struc
+ regs->ip = (unsigned long)general_protection;
+ regs->sp = (unsigned long)&gpregs->orig_ax;
+
+- /*
+- * This situation can be triggered by userspace via
+- * modify_ldt(2) and the return does not take the regular
+- * user space exit, so a CPU buffer clear is required when
+- * MDS mitigation is enabled.
+- */
+- mds_user_clear_cpu_buffers();
+ return;
+ }
+ #endif
+--- a/Documentation/x86/mds.rst
++++ b/Documentation/x86/mds.rst
+@@ -157,13 +157,6 @@ Mitigation points
+ mitigated on the return from do_nmi() to provide almost complete
+ coverage.
+
+- - Double fault (#DF):
+-
+- A double fault is usually fatal, but the ESPFIX workaround, which can
+- be triggered from user space through modify_ldt(2) is a recoverable
+- double fault. #DF uses the paranoid exit path, so explicit mitigation
+- in the double fault handler is required.
+-
+ - Machine Check Exception (#MC):
+
+ Another corner case is a #MC which hits between the CPU buffer clear
diff --git a/patches.drivers/drivers-depend-on-has_iomem-for-devm_platform_ioremap_resource b/patches.drivers/drivers-depend-on-has_iomem-for-devm_platform_ioremap_resource
new file mode 100644
index 0000000000..e17aca8572
--- /dev/null
+++ b/patches.drivers/drivers-depend-on-has_iomem-for-devm_platform_ioremap_resource
@@ -0,0 +1,36 @@
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Thu, 21 Feb 2019 17:26:27 +0100
+Subject: drivers: depend on HAS_IOMEM for devm_platform_ioremap_resource()
+Git-commit: 837ccda3480d2861c09aabc5fa014be18df9dd3c
+Patch-mainline: v5.1-rc1
+References: bsc#1136333 jsc#SLE-4994
+
+We only build devm_ioremap_resource() if HAS_IOMEM is selected, so this
+dependency must cascade down to devm_platform_ioremap_resource().
+
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ drivers/base/platform.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -87,6 +87,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource)
+ * resource managemend
+ * @index: resource index
+ */
++#ifdef CONFIG_HAS_IOMEM
+ void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
+ unsigned int index)
+ {
+@@ -96,6 +97,7 @@ void __iomem *devm_platform_ioremap_reso
+ return devm_ioremap_resource(&pdev->dev, res);
+ }
+ EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
++#endif /* CONFIG_HAS_IOMEM */
+
+ /**
+ * platform_get_irq - get an IRQ for a device
diff --git a/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch b/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch
new file mode 100644
index 0000000000..e21b00dcd8
--- /dev/null
+++ b/patches.drivers/drivers-fix-a-typo-in-the-kernel-doc-for-devm_platfo.patch
@@ -0,0 +1,31 @@
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Mon, 1 Apr 2019 10:16:35 +0200
+Subject: drivers: fix a typo in the kernel doc for
+ devm_platform_ioremap_resource()
+Patch-mainline: v5.2-rc1
+Git-commit: 7067c96ee8d2d77039aeb49670acfe160f484ef9
+References: bsc#1136333 jsc#SLE-4994
+
+It should have been 'management' not 'managemend'.
+
+Fixes: 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()")
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
+Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/base/platform.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -84,7 +84,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource)
+ * device
+ *
+ * @pdev: platform device to use both for memory resource lookup as well as
+- * resource managemend
++ * resource management
+ * @index: resource index
+ */
+ #ifdef CONFIG_HAS_IOMEM
diff --git a/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch b/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch
new file mode 100644
index 0000000000..26051d1bab
--- /dev/null
+++ b/patches.drivers/drivers-provide-devm_platform_ioremap_resource.patch
@@ -0,0 +1,64 @@
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Wed, 20 Feb 2019 11:12:39 +0000
+Subject: drivers: provide devm_platform_ioremap_resource()
+Patch-mainline: v5.1-rc1
+Git-commit: 7945f929f1a77a1c8887a97ca07f87626858ff42
+References: bsc#1136333 jsc#SLE-4994
+
+There are currently 1200+ instances of using platform_get_resource()
+and devm_ioremap_resource() together in the kernel tree.
+
+This patch wraps these two calls in a single helper. Thanks to that
+we don't have to declare a local variable for struct resource * and can
+omit the redundant argument for resource type. We also have one
+function call less.
+
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/base/platform.c | 18 ++++++++++++++++++
+ include/linux/platform_device.h | 3 +++
+ 2 files changed, 21 insertions(+)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -80,6 +80,24 @@ struct resource *platform_get_resource(s
+ EXPORT_SYMBOL_GPL(platform_get_resource);
+
+ /**
++ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
++ * device
++ *
++ * @pdev: platform device to use both for memory resource lookup as well as
++ * resource managemend
++ * @index: resource index
++ */
++void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
++ unsigned int index)
++{
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
++ return devm_ioremap_resource(&pdev->dev, res);
++}
++EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
++
++/**
+ * platform_get_irq - get an IRQ for a device
+ * @dev: platform device
+ * @num: IRQ number index
+--- a/include/linux/platform_device.h
++++ b/include/linux/platform_device.h
+@@ -51,6 +51,9 @@ extern struct device platform_bus;
+ extern void arch_setup_pdev_archdata(struct platform_device *);
+ extern struct resource *platform_get_resource(struct platform_device *,
+ unsigned int, unsigned int);
++extern void __iomem *
++devm_platform_ioremap_resource(struct platform_device *pdev,
++ unsigned int index);
+ extern int platform_get_irq(struct platform_device *, unsigned int);
+ extern int platform_irq_count(struct platform_device *);
+ extern struct resource *platform_get_resource_byname(struct platform_device *,
diff --git a/patches.drivers/drivers-rapidio-devices-rio_mport_cdev.c-fix-resourc.patch b/patches.drivers/drivers-rapidio-devices-rio_mport_cdev.c-fix-resourc.patch
new file mode 100644
index 0000000000..5f2be1e44a
--- /dev/null
+++ b/patches.drivers/drivers-rapidio-devices-rio_mport_cdev.c-fix-resourc.patch
@@ -0,0 +1,44 @@
+From b1402dcb5643b7a27d46a05edd7491d49ba0e248 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Fri, 17 Nov 2017 15:37:57 -0800
+Subject: [PATCH] drivers/rapidio/devices/rio_mport_cdev.c: fix resource leak in error handling path in 'rio_dma_transfer()'
+Git-commit: b1402dcb5643b7a27d46a05edd7491d49ba0e248
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+If 'dma_map_sg()', we should branch to the existing error handling path
+to free some resources before returning.
+
+Link: http://lkml.kernel.org/r/61292a4f369229eee03394247385e955027283f8.1505687047.git.christophe.jaillet@wanadoo.fr
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Cc: Matt Porter <mporter@kernel.crashing.org>
+Cc: Alexandre Bounine <alexandre.bounine@idt.com>
+Cc: Lorenzo Stoakes <lstoakes@gmail.com>
+Cc: Jesper Nilsson <jesper.nilsson@axis.com>
+Cc: Christian K_nig <christian.koenig@amd.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/rapidio/devices/rio_mport_cdev.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rapidio/devices/rio_mport_cdev.c b/drivers/rapidio/devices/rio_mport_cdev.c
+index 5c1b6388122a..86805747a422 100644
+--- a/drivers/rapidio/devices/rio_mport_cdev.c
++++ b/drivers/rapidio/devices/rio_mport_cdev.c
+@@ -963,7 +963,8 @@ rio_dma_transfer(struct file *filp, u32 transfer_mode,
+ req->sgt.sgl, req->sgt.nents, dir);
+ if (nents == -EFAULT) {
+ rmcd_error("Failed to map SG list");
+- return -EFAULT;
++ ret = -EFAULT;
++ goto err_pg;
+ }
+
+ ret = do_dma_request(req, xfer, sync, nents);
+--
+2.16.4
+
diff --git a/patches.drivers/drivers-rapidio-rio_cm.c-fix-potential-oops-in-riocm.patch b/patches.drivers/drivers-rapidio-rio_cm.c-fix-potential-oops-in-riocm.patch
new file mode 100644
index 0000000000..41da0a0e02
--- /dev/null
+++ b/patches.drivers/drivers-rapidio-rio_cm.c-fix-potential-oops-in-riocm.patch
@@ -0,0 +1,44 @@
+From 5ac188b12e7cbdd92dee60877d1fac913fc1d074 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 7 Mar 2019 16:29:33 -0800
+Subject: [PATCH] drivers/rapidio/rio_cm.c: fix potential oops in riocm_ch_listen()
+Git-commit: 5ac188b12e7cbdd92dee60877d1fac913fc1d074
+Patch-mainline: v5.1-rc1
+References: bsc#1051510
+
+If riocm_get_channel() fails, then we should just return -EINVAL.
+Calling riocm_put_channel() will trigger a NULL dereference and
+generally we should call put() if the get() didn't succeed.
+
+Link: http://lkml.kernel.org/r/20190110130230.GB27017@kadam
+Fixes: b6e8d4aa1110 ("rapidio: add RapidIO channelized messaging driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
+Cc: Matt Porter <mporter@kernel.crashing.org>
+Cc: Alexandre Bounine <alexandre.bounine@idt.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/rapidio/rio_cm.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rapidio/rio_cm.c b/drivers/rapidio/rio_cm.c
+index bad0e0ea4f30..cf45829585cb 100644
+--- a/drivers/rapidio/rio_cm.c
++++ b/drivers/rapidio/rio_cm.c
+@@ -1215,7 +1215,9 @@ static int riocm_ch_listen(u16 ch_id)
+ riocm_debug(CHOP, "(ch_%d)", ch_id);
+
+ ch = riocm_get_channel(ch_id);
+- if (!ch || !riocm_cmp_exch(ch, RIO_CM_CHAN_BOUND, RIO_CM_LISTEN))
++ if (!ch)
++ return -EINVAL;
++ if (!riocm_cmp_exch(ch, RIO_CM_CHAN_BOUND, RIO_CM_LISTEN))
+ ret = -EINVAL;
+ riocm_put_channel(ch);
+ return ret;
+--
+2.16.4
+
diff --git a/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch b/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch
new file mode 100644
index 0000000000..947777dc21
--- /dev/null
+++ b/patches.drivers/edac-mc-fix-edac_mc_find-in-case-no-device-is-found.patch
@@ -0,0 +1,60 @@
+From: Robert Richter <rrichter@marvell.com>
+Date: Tue, 14 May 2019 10:49:09 +0000
+Subject: EDAC/mc: Fix edac_mc_find() in case no device is found
+Git-commit: 29a0c843973bc385918158c6976e4dbe891df969
+Patch-mainline: v5.2-rc1
+References: bsc#1114279
+
+The function should return NULL in case no device is found, but it
+always returns the last checked mc device from the list even if the
+index did not match. Fix that.
+
+I did some analysis why this did not raise any issues for about 3 years
+and the reason is that edac_mc_find() is mostly used to search for
+existing devices. Thus, the bug is not triggered.
+
+ [ bp: Drop the if (mci->mc_idx > idx) test in favor of readability. ]
+
+Fixes: c73e8833bec5 ("EDAC, mc: Fix locking around mc_devices list")
+Signed-off-by: Robert Richter <rrichter@marvell.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
+Cc: James Morse <james.morse@arm.com>
+Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
+Link: https://lkml.kernel.org/r/20190514104838.15065-1-rrichter@marvell.com
+---
+ drivers/edac/edac_mc.c | 12 ++++--------
+ 1 file changed, 4 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
+index 13594ffadcb3..64922c8fa7e3 100644
+--- a/drivers/edac/edac_mc.c
++++ b/drivers/edac/edac_mc.c
+@@ -679,22 +679,18 @@ static int del_mc_from_global_list(struct mem_ctl_info *mci)
+
+ struct mem_ctl_info *edac_mc_find(int idx)
+ {
+- struct mem_ctl_info *mci = NULL;
++ struct mem_ctl_info *mci;
+ struct list_head *item;
+
+ mutex_lock(&mem_ctls_mutex);
+
+ list_for_each(item, &mc_devices) {
+ mci = list_entry(item, struct mem_ctl_info, link);
+-
+- if (mci->mc_idx >= idx) {
+- if (mci->mc_idx == idx) {
+- goto unlock;
+- }
+- break;
+- }
++ if (mci->mc_idx == idx)
++ goto unlock;
+ }
+
++ mci = NULL;
+ unlock:
+ mutex_unlock(&mem_ctls_mutex);
+ return mci;
+
diff --git a/patches.drivers/hwmon-k10temp-27c-offset-needed-for-threadripper2.patch b/patches.drivers/hwmon-k10temp-27c-offset-needed-for-threadripper2.patch
new file mode 100644
index 0000000000..c3f0ba00b5
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-27c-offset-needed-for-threadripper2.patch
@@ -0,0 +1,28 @@
+From: Michael Larabel <michael@phoronix.com>
+Date: Tue, 7 Aug 2018 09:54:54 -0400
+Subject: hwmon: (k10temp) 27C Offset needed for Threadripper2
+Git-commit: 484a84f25ca7817c3662001316ba7d1e06b74ae2
+Patch-mainline: v4.19
+References: FATE#327735
+
+For at least the Threadripper 2950X and Threadripper 2990WX,
+it's confirmed a 27 degree offset is needed.
+
+Signed-off-by: Michael Larabel <michael@phoronix.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 17c6460ae351..577e2ede5a1a 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -105,6 +105,8 @@ static const struct tctl_offset tctl_offset_table[] = {
+ { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
+ { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
+ { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
++ { 0x17, "AMD Ryzen Threadripper 2950X", 27000 },
++ { 0x17, "AMD Ryzen Threadripper 2990WX", 27000 },
+ };
+
+ static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
diff --git a/patches.drivers/hwmon-k10temp-add-hygon-dhyana-support.patch b/patches.drivers/hwmon-k10temp-add-hygon-dhyana-support.patch
new file mode 100644
index 0000000000..c24a4b3373
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-hygon-dhyana-support.patch
@@ -0,0 +1,39 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Sat, 8 Dec 2018 14:33:28 +0800
+Subject: hwmon: (k10temp) Add Hygon Dhyana support
+Git-commit: d93217d84c6c7ef74bfeb606a1fb1ee28720646b
+Patch-mainline: v5.0
+References: FATE#327735
+
+Add support for Hygon Dhyana family 18h processor for k10temp to get the
+temperature. As Hygon Dhyana shares the same function interface with AMD
+family 17h, so add Hygon PCI Vendor ID and reuse the code path of AMD.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Acked-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+---
+ drivers/hwmon/k10temp.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -323,7 +323,7 @@ static int k10temp_probe(struct pci_dev
+ (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
+ data->read_htcreg = read_htcreg_nb_f15;
+ data->read_tempreg = read_tempreg_nb_f15;
+- } else if (boot_cpu_data.x86 == 0x17) {
++ } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+ data->temp_adjust_mask = 0x80000;
+ data->read_tempreg = read_tempreg_nb_f17;
+ data->show_tdie = true;
+@@ -360,6 +360,7 @@ static const struct pci_device_id k10tem
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
++ { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ {}
+ };
+ MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/patches.drivers/hwmon-k10temp-add-support-for-amd-family-17h-model-30h-cpus.patch b/patches.drivers/hwmon-k10temp-add-support-for-amd-family-17h-model-30h-cpus.patch
index 529de2ce30..ff0d2050cd 100644
--- a/patches.drivers/hwmon-k10temp-add-support-for-amd-family-17h-model-30h-cpus.patch
+++ b/patches.drivers/hwmon-k10temp-add-support-for-amd-family-17h-model-30h-cpus.patch
@@ -31,9 +31,9 @@ Link: http://lkml.kernel.org/r/20181106200754.60722-5-brian.woods@amd.com
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -215,6 +215,7 @@ static const struct pci_device_id k10tem
- { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
- { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{}
};
diff --git a/patches.drivers/hwmon-k10temp-add-support-for-amd-ryzen-w-vega-graphics.patch b/patches.drivers/hwmon-k10temp-add-support-for-amd-ryzen-w-vega-graphics.patch
new file mode 100644
index 0000000000..ea4a4ea221
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-support-for-amd-ryzen-w-vega-graphics.patch
@@ -0,0 +1,40 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Tue, 24 Apr 2018 08:59:45 -0700
+Subject: hwmon: (k10temp) Add support for AMD Ryzen w/ Vega graphics
+Git-commit: 877d8948d0aa402fbbede138fc73432bb335b65f
+Patch-mainline: v4.17
+References: FATE#327735
+
+Enable k10temp for AMD Ryzen APUs w/ Vega Mobile Gfx.
+
+Based on patch from René Rebe <rene@exactcode.de>. Dropped temperature
+offsets since those are not supposed to apply for the affected CPUs.
+
+Cc: stable@vger.kernel.org # v4.16+
+Cc: René Rebe <rene@exactcode.de>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index d19d08f81c6f..d2cc55e21374 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -40,6 +40,10 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #endif
+
++#ifndef PCI_DEVICE_ID_AMD_17H_RR_NB
++#define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0
++#endif
++
+ /* CPUID function 0x80000001, ebx */
+ #define CPUID_PKGTYPE_MASK 0xf0000000
+ #define CPUID_PKGTYPE_F 0x00000000
+@@ -298,6 +302,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) },
+ {}
+ };
+ MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/patches.drivers/hwmon-k10temp-add-support-for-family-17h.patch b/patches.drivers/hwmon-k10temp-add-support-for-family-17h.patch
new file mode 100644
index 0000000000..cc7b2e4997
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-support-for-family-17h.patch
@@ -0,0 +1,67 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Mon, 4 Sep 2017 18:33:53 -0700
+Subject: hwmon: (k10temp) Add support for family 17h
+Git-commit: 9af0a9aecdb945cd5513941ffdcbcc031009b402
+Patch-mainline: v4.15
+References: FATE#327735
+
+Add support for temperature sensors on Family 17h (Ryzen) processors.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index fc8076c7e1a1..c4dac53206c3 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -36,6 +36,10 @@ MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
+ /* Provide lock for writing to NB_SMU_IND_ADDR */
+ static DEFINE_MUTEX(nb_smu_ind_mutex);
+
++#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
++#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
++#endif
++
+ /* CPUID function 0x80000001, ebx */
+ #define CPUID_PKGTYPE_MASK 0xf0000000
+ #define CPUID_PKGTYPE_F 0x00000000
+@@ -61,6 +65,9 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ */
+ #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
+
++/* F17h M01h Access througn SMN */
++#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
++
+ struct k10temp_data {
+ struct pci_dev *pdev;
+ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
+@@ -88,6 +95,12 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
+ F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
+ }
+
++static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
++{
++ amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
++ F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
++}
++
+ static ssize_t temp1_input_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+ {
+@@ -224,6 +237,8 @@ static int k10temp_probe(struct pci_dev *pdev,
+ if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
+ boot_cpu_data.x86_model == 0x70))
+ data->read_tempreg = read_tempreg_nb_f15;
++ else if (boot_cpu_data.x86 == 0x17)
++ data->read_tempreg = read_tempreg_nb_f17;
+ else
+ data->read_tempreg = read_tempreg_pci;
+
+@@ -242,6 +257,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ {}
+ };
+ MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/patches.drivers/hwmon-k10temp-add-support-for-stoney-ridge-and-bristol.patch b/patches.drivers/hwmon-k10temp-add-support-for-stoney-ridge-and-bristol.patch
new file mode 100644
index 0000000000..cb9253540c
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-support-for-stoney-ridge-and-bristol.patch
@@ -0,0 +1,38 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Sun, 29 Apr 2018 09:16:45 -0700
+Subject: hwmon: (k10temp) Add support for Stoney Ridge and Bristol Ridge CPUs
+Git-commit: ccaf63b4d6eaf3447037cefbb0b1038fa80c6639
+Patch-mainline: v4.18
+References: FATE#327735
+
+Add support for Stoney Ridge and Bristol Ridge (Family 15h Model 0x70)
+CPUs. Registers match those of Family 15h Model 0x60.
+
+Cc: stable@vger.kernel.org # v4.16+
+Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 3b73dee6fdc6..e97105ae4158 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -37,6 +37,10 @@ MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
+ /* Provide lock for writing to NB_SMU_IND_ADDR */
+ static DEFINE_MUTEX(nb_smu_ind_mutex);
+
++#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
++#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
++#endif
++
+ #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #endif
+@@ -320,6 +324,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
diff --git a/patches.drivers/hwmon-k10temp-add-support-for-temperature-offsets.patch b/patches.drivers/hwmon-k10temp-add-support-for-temperature-offsets.patch
new file mode 100644
index 0000000000..3981e66da0
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-support-for-temperature-offsets.patch
@@ -0,0 +1,77 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Mon, 4 Sep 2017 18:33:53 -0700
+Subject: hwmon: (k10temp) Add support for temperature offsets
+Git-commit: 1b50b776355fa6c6d7b3281a63c275d5c18d629d
+Patch-mainline: v4.15
+References: FATE#327735
+
+Add support for handling temperature offset values for various AMD CPUs,
+similar to the code used in the coretemp driver for Intel CPUs. This is
+primarily for Ryzen CPUs (which has documented temperature offsets),
+but the code is kept generic to simplify adding additional CPUs.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index c4dac53206c3..46a54ed23410 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -71,6 +71,24 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ struct k10temp_data {
+ struct pci_dev *pdev;
+ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
++ int temp_offset;
++};
++
++struct tctl_offset {
++ u8 model;
++ char const *id;
++ int offset;
++};
++
++static const struct tctl_offset tctl_offset_table[] = {
++ { 0x17, "AMD Ryzen 7 1600X", 20000 },
++ { 0x17, "AMD Ryzen 7 1700X", 20000 },
++ { 0x17, "AMD Ryzen 7 1800X", 20000 },
++ { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
++ { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
++ { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
++ { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
++ { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
+ };
+
+ static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
+@@ -110,6 +128,7 @@ static ssize_t temp1_input_show(struct device *dev,
+
+ data->read_tempreg(data->pdev, &regval);
+ temp = (regval >> 21) * 125;
++ temp -= data->temp_offset;
+
+ return sprintf(buf, "%u\n", temp);
+ }
+@@ -217,6 +236,7 @@ static int k10temp_probe(struct pci_dev *pdev,
+ struct device *dev = &pdev->dev;
+ struct k10temp_data *data;
+ struct device *hwmon_dev;
++ int i;
+
+ if (unreliable) {
+ if (!force) {
+@@ -242,6 +262,16 @@ static int k10temp_probe(struct pci_dev *pdev,
+ else
+ data->read_tempreg = read_tempreg_pci;
+
++ for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
++ const struct tctl_offset *entry = &tctl_offset_table[i];
++
++ if (boot_cpu_data.x86 == entry->model &&
++ strstr(boot_cpu_data.x86_model_id, entry->id)) {
++ data->temp_offset = entry->offset;
++ break;
++ }
++ }
++
+ hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
+ k10temp_groups);
+ return PTR_ERR_OR_ZERO(hwmon_dev);
diff --git a/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-1900x.patch b/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-1900x.patch
new file mode 100644
index 0000000000..32b6594373
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-1900x.patch
@@ -0,0 +1,25 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Fri, 19 Jan 2018 06:38:03 -0800
+Subject: hwmon: (k10temp) Add temperature offset for Ryzen 1900X
+Git-commit: 6509614fdd2d05c6926d50901a45d5dfb852b715
+Patch-mainline: v4.16
+References: FATE#327735
+
+Like the other CPUs from the same series, the 1900X has a
+temperature offset of 27 degrees C.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 0721e175664a..06b4e1c78bd8 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -86,6 +86,7 @@ static const struct tctl_offset tctl_offset_table[] = {
+ { 0x17, "AMD Ryzen 7 1800X", 20000 },
+ { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
+ { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
++ { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
+ { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
+ { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
+ { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
diff --git a/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-2700x.patch b/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-2700x.patch
new file mode 100644
index 0000000000..d2a177033b
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-add-temperature-offset-for-ryzen-2700x.patch
@@ -0,0 +1,62 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Tue, 24 Apr 2018 06:55:55 -0700
+Subject: hwmon: (k10temp) Add temperature offset for Ryzen 2700X
+Git-commit: 1b59788979acd230b9627276c76f6e6ba2c4709c
+Patch-mainline: v4.17
+References: FATE#327735
+
+Ryzen 2700X has a temperature offset of 10 degrees C. If bit 19 of the
+Temperature Control register is set, there is an additional offset of
+49 degrees C. Take this into account as well.
+
+Cc: stable@vger.kernel.org # v4.16+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 051a72eecb24..d19d08f81c6f 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -72,6 +72,7 @@ struct k10temp_data {
+ struct pci_dev *pdev;
+ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
+ int temp_offset;
++ u32 temp_adjust_mask;
+ };
+
+ struct tctl_offset {
+@@ -84,6 +85,7 @@ static const struct tctl_offset tctl_offset_table[] = {
+ { 0x17, "AMD Ryzen 5 1600X", 20000 },
+ { 0x17, "AMD Ryzen 7 1700X", 20000 },
+ { 0x17, "AMD Ryzen 7 1800X", 20000 },
++ { 0x17, "AMD Ryzen 7 2700X", 10000 },
+ { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
+ { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
+ { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
+@@ -129,6 +131,8 @@ static ssize_t temp1_input_show(struct device *dev,
+
+ data->read_tempreg(data->pdev, &regval);
+ temp = (regval >> 21) * 125;
++ if (regval & data->temp_adjust_mask)
++ temp -= 49000;
+ if (temp > data->temp_offset)
+ temp -= data->temp_offset;
+ else
+@@ -259,12 +263,14 @@ static int k10temp_probe(struct pci_dev *pdev,
+ data->pdev = pdev;
+
+ if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
+- boot_cpu_data.x86_model == 0x70))
++ boot_cpu_data.x86_model == 0x70)) {
+ data->read_tempreg = read_tempreg_nb_f15;
+- else if (boot_cpu_data.x86 == 0x17)
++ } else if (boot_cpu_data.x86 == 0x17) {
++ data->temp_adjust_mask = 0x80000;
+ data->read_tempreg = read_tempreg_nb_f17;
+- else
++ } else {
+ data->read_tempreg = read_tempreg_pci;
++ }
+
+ for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
+ const struct tctl_offset *entry = &tctl_offset_table[i];
diff --git a/patches.drivers/hwmon-k10temp-correct-model-name-for-ryzen-1600x.patch b/patches.drivers/hwmon-k10temp-correct-model-name-for-ryzen-1600x.patch
new file mode 100644
index 0000000000..a9e79d94a3
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-correct-model-name-for-ryzen-1600x.patch
@@ -0,0 +1,25 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Mon, 13 Nov 2017 12:38:23 -0800
+Subject: hwmon: (k10temp) Correct model name for Ryzen 1600X
+Git-commit: ab5ee24615f9dd8b0cd199403959f8b13309e7b1
+Patch-mainline: v4.15
+References: FATE#327735
+
+Ryzen 1600X is a Ryzen 5 processor.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 46a54ed23410..0721e175664a 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -81,7 +81,7 @@ struct tctl_offset {
+ };
+
+ static const struct tctl_offset tctl_offset_table[] = {
+- { 0x17, "AMD Ryzen 7 1600X", 20000 },
++ { 0x17, "AMD Ryzen 5 1600X", 20000 },
+ { 0x17, "AMD Ryzen 7 1700X", 20000 },
+ { 0x17, "AMD Ryzen 7 1800X", 20000 },
+ { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
diff --git a/patches.drivers/hwmon-k10temp-display-both-tctl-and-tdie.patch b/patches.drivers/hwmon-k10temp-display-both-tctl-and-tdie.patch
new file mode 100644
index 0000000000..7bebab0460
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-display-both-tctl-and-tdie.patch
@@ -0,0 +1,138 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Thu, 26 Apr 2018 12:22:29 -0700
+Subject: hwmon: (k10temp) Display both Tctl and Tdie
+Git-commit: f934c0599ecab63ec9cca0000315240c1202d20c
+Patch-mainline: v4.18
+References: FATE#327735
+
+On some AMD CPUs, there is a different between the die temperature
+(Tdie) and the reported temperature (Tctl). Tdie is the real measured
+temperature, and Tctl is used for fan control. Lets report both for
+affected CPUs.
+
+Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index e97105ae4158..d3fae5a8e508 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -85,6 +85,7 @@ struct k10temp_data {
+ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
+ int temp_offset;
+ u32 temp_adjust_mask;
++ bool show_tdie;
+ };
+
+ struct tctl_offset {
+@@ -145,17 +146,24 @@ static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
+ F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
+ }
+
+-static ssize_t temp1_input_show(struct device *dev,
+- struct device_attribute *attr, char *buf)
++unsigned int get_raw_temp(struct k10temp_data *data)
+ {
+- struct k10temp_data *data = dev_get_drvdata(dev);
+- u32 regval;
+ unsigned int temp;
++ u32 regval;
+
+ data->read_tempreg(data->pdev, &regval);
+ temp = (regval >> 21) * 125;
+ if (regval & data->temp_adjust_mask)
+ temp -= 49000;
++ return temp;
++}
++
++static ssize_t temp1_input_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct k10temp_data *data = dev_get_drvdata(dev);
++ unsigned int temp = get_raw_temp(data);
++
+ if (temp > data->temp_offset)
+ temp -= data->temp_offset;
+ else
+@@ -164,6 +172,23 @@ static ssize_t temp1_input_show(struct device *dev,
+ return sprintf(buf, "%u\n", temp);
+ }
+
++static ssize_t temp2_input_show(struct device *dev,
++ struct device_attribute *devattr, char *buf)
++{
++ struct k10temp_data *data = dev_get_drvdata(dev);
++ unsigned int temp = get_raw_temp(data);
++
++ return sprintf(buf, "%u\n", temp);
++}
++
++static ssize_t temp_label_show(struct device *dev,
++ struct device_attribute *devattr, char *buf)
++{
++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
++
++ return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie");
++}
++
+ static ssize_t temp1_max_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+ {
+@@ -191,16 +216,23 @@ static DEVICE_ATTR_RO(temp1_max);
+ static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
+ static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
+
++static SENSOR_DEVICE_ATTR(temp1_label, 0444, temp_label_show, NULL, 0);
++static DEVICE_ATTR_RO(temp2_input);
++static SENSOR_DEVICE_ATTR(temp2_label, 0444, temp_label_show, NULL, 1);
++
+ static umode_t k10temp_is_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+ {
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct k10temp_data *data = dev_get_drvdata(dev);
+ struct pci_dev *pdev = data->pdev;
++ u32 reg;
+
+- if (index >= 2) {
+- u32 reg;
+-
++ switch (index) {
++ case 0 ... 1: /* temp1_input, temp1_max */
++ default:
++ break;
++ case 2 ... 3: /* temp1_crit, temp1_crit_hyst */
+ if (!data->read_htcreg)
+ return 0;
+
+@@ -212,6 +244,11 @@ static umode_t k10temp_is_visible(struct kobject *kobj,
+ data->read_htcreg(data->pdev, &reg);
+ if (!(reg & HTC_ENABLE))
+ return 0;
++ break;
++ case 4 ... 6: /* temp1_label, temp2_input, temp2_label */
++ if (!data->show_tdie)
++ return 0;
++ break;
+ }
+ return attr->mode;
+ }
+@@ -221,6 +258,9 @@ static struct attribute *k10temp_attrs[] = {
+ &dev_attr_temp1_max.attr,
+ &sensor_dev_attr_temp1_crit.dev_attr.attr,
+ &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
++ &sensor_dev_attr_temp1_label.dev_attr.attr,
++ &dev_attr_temp2_input.attr,
++ &sensor_dev_attr_temp2_label.dev_attr.attr,
+ NULL
+ };
+
+@@ -296,6 +336,7 @@ static int k10temp_probe(struct pci_dev *pdev,
+ } else if (boot_cpu_data.x86 == 0x17) {
+ data->temp_adjust_mask = 0x80000;
+ data->read_tempreg = read_tempreg_nb_f17;
++ data->show_tdie = true;
+ } else {
+ data->read_htcreg = read_htcreg_pci;
+ data->read_tempreg = read_tempreg_pci;
diff --git a/patches.drivers/hwmon-k10temp-fix-reading-critical-temperature-register.patch b/patches.drivers/hwmon-k10temp-fix-reading-critical-temperature-register.patch
new file mode 100644
index 0000000000..f01561de90
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-fix-reading-critical-temperature-register.patch
@@ -0,0 +1,116 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Sun, 29 Apr 2018 08:08:24 -0700
+Subject: hwmon: (k10temp) Fix reading critical temperature register
+Git-commit: 40626a1bf657eef557fcee9e1b8ef5b4f5b56dcd
+Patch-mainline: v4.17
+References: FATE#327735
+
+The HTC (Hardware Temperature Control) register has moved
+for recent chips.
+
+Cc: stable@vger.kernel.org # v4.16+
+Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index d2cc55e21374..34b5448b00be 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -63,10 +63,12 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ #define NB_CAP_HTC 0x00000400
+
+ /*
+- * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
+- * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
+- * Control]
++ * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
++ * and REG_REPORTED_TEMPERATURE have been moved to
++ * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
++ * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
+ */
++#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
+ #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
+
+ /* F17h M01h Access througn SMN */
+@@ -74,6 +76,7 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+
+ struct k10temp_data {
+ struct pci_dev *pdev;
++ void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
+ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
+ int temp_offset;
+ u32 temp_adjust_mask;
+@@ -98,6 +101,11 @@ static const struct tctl_offset tctl_offset_table[] = {
+ { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
+ };
+
++static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
++{
++ pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
++}
++
+ static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
+ {
+ pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
+@@ -114,6 +122,12 @@ static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
+ mutex_unlock(&nb_smu_ind_mutex);
+ }
+
++static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
++{
++ amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
++ F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
++}
++
+ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
+ {
+ amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
+@@ -160,8 +174,7 @@ static ssize_t show_temp_crit(struct device *dev,
+ u32 regval;
+ int value;
+
+- pci_read_config_dword(data->pdev,
+- REG_HARDWARE_THERMAL_CONTROL, &regval);
++ data->read_htcreg(data->pdev, &regval);
+ value = ((regval >> 16) & 0x7f) * 500 + 52000;
+ if (show_hyst)
+ value -= ((regval >> 24) & 0xf) * 500;
+@@ -181,13 +194,18 @@ static umode_t k10temp_is_visible(struct kobject *kobj,
+ struct pci_dev *pdev = data->pdev;
+
+ if (index >= 2) {
+- u32 reg_caps, reg_htc;
++ u32 reg;
++
++ if (!data->read_htcreg)
++ return 0;
+
+ pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
+- &reg_caps);
+- pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
+- &reg_htc);
+- if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
++ &reg);
++ if (!(reg & NB_CAP_HTC))
++ return 0;
++
++ data->read_htcreg(data->pdev, &reg);
++ if (!(reg & HTC_ENABLE))
+ return 0;
+ }
+ return attr->mode;
+@@ -268,11 +286,13 @@ static int k10temp_probe(struct pci_dev *pdev,
+
+ if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
+ boot_cpu_data.x86_model == 0x70)) {
++ data->read_htcreg = read_htcreg_nb_f15;
+ data->read_tempreg = read_tempreg_nb_f15;
+ } else if (boot_cpu_data.x86 == 0x17) {
+ data->temp_adjust_mask = 0x80000;
+ data->read_tempreg = read_tempreg_nb_f17;
+ } else {
++ data->read_htcreg = read_htcreg_pci;
+ data->read_tempreg = read_tempreg_pci;
+ }
+
diff --git a/patches.drivers/hwmon-k10temp-make-function-get_raw_temp-static.patch b/patches.drivers/hwmon-k10temp-make-function-get_raw_temp-static.patch
new file mode 100644
index 0000000000..a5d943e3b5
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-make-function-get_raw_temp-static.patch
@@ -0,0 +1,31 @@
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 1 Jun 2018 14:37:13 +0100
+Subject: hwmon: (k10temp) Make function get_raw_temp static
+Git-commit: fb8eefd3b4e6f79e0930fffff6640744699c6f1d
+Patch-mainline: v4.18
+References: FATE#327735
+
+The function get_raw_temp is local to the source and does not need to
+be in global scope, so make it static.
+
+Cleans up sparse warning:
+drivers/hwmon/k10temp.c:149:14: warning: symbol 'get_raw_temp' was not
+declared. Should it be static?
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index d3fae5a8e508..17c6460ae351 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -146,7 +146,7 @@ static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
+ F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
+ }
+
+-unsigned int get_raw_temp(struct k10temp_data *data)
++static unsigned int get_raw_temp(struct k10temp_data *data)
+ {
+ unsigned int temp;
+ u32 regval;
diff --git a/patches.drivers/hwmon-k10temp-move-chip-specific-code-into-probe-function.patch b/patches.drivers/hwmon-k10temp-move-chip-specific-code-into-probe-function.patch
new file mode 100644
index 0000000000..79c7ec76ca
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-move-chip-specific-code-into-probe-function.patch
@@ -0,0 +1,129 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Mon, 4 Sep 2017 18:33:53 -0700
+Subject: hwmon: (k10temp) Move chip specific code into probe function
+Git-commit: 68546abf7a3a63f199e53d6dcaa7375df37a6aaa
+Patch-mainline: v4.15
+References: FATE#327735
+
+Introduce a local data structure and determine the temperature read
+function at probe time to reduce runtime complexity.
+
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index ce3b91f22e30..fc8076c7e1a1 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -61,31 +61,44 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ */
+ #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
+
+-static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
+- int offset, u32 *val)
++struct k10temp_data {
++ struct pci_dev *pdev;
++ void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
++};
++
++static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
++{
++ pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
++}
++
++static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
++ unsigned int base, int offset, u32 *val)
+ {
+ mutex_lock(&nb_smu_ind_mutex);
+ pci_bus_write_config_dword(pdev->bus, devfn,
+- 0xb8, offset);
++ base, offset);
+ pci_bus_read_config_dword(pdev->bus, devfn,
+- 0xbc, val);
++ base + 4, val);
+ mutex_unlock(&nb_smu_ind_mutex);
+ }
+
++static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
++{
++ amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
++ F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
++}
++
+ static ssize_t temp1_input_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+ {
++ struct k10temp_data *data = dev_get_drvdata(dev);
+ u32 regval;
+- struct pci_dev *pdev = dev_get_drvdata(dev);
+-
+- if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
+- amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
+- F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
+- &regval);
+- } else {
+- pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
+- }
+- return sprintf(buf, "%u\n", (regval >> 21) * 125);
++ unsigned int temp;
++
++ data->read_tempreg(data->pdev, &regval);
++ temp = (regval >> 21) * 125;
++
++ return sprintf(buf, "%u\n", temp);
+ }
+
+ static ssize_t temp1_max_show(struct device *dev,
+@@ -98,11 +111,12 @@ static ssize_t show_temp_crit(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+ {
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
++ struct k10temp_data *data = dev_get_drvdata(dev);
+ int show_hyst = attr->index;
+ u32 regval;
+ int value;
+
+- pci_read_config_dword(dev_get_drvdata(dev),
++ pci_read_config_dword(data->pdev,
+ REG_HARDWARE_THERMAL_CONTROL, &regval);
+ value = ((regval >> 16) & 0x7f) * 500 + 52000;
+ if (show_hyst)
+@@ -119,7 +133,8 @@ static umode_t k10temp_is_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+ {
+ struct device *dev = container_of(kobj, struct device, kobj);
+- struct pci_dev *pdev = dev_get_drvdata(dev);
++ struct k10temp_data *data = dev_get_drvdata(dev);
++ struct pci_dev *pdev = data->pdev;
+
+ if (index >= 2) {
+ u32 reg_caps, reg_htc;
+@@ -187,6 +202,7 @@ static int k10temp_probe(struct pci_dev *pdev,
+ {
+ int unreliable = has_erratum_319(pdev);
+ struct device *dev = &pdev->dev;
++ struct k10temp_data *data;
+ struct device *hwmon_dev;
+
+ if (unreliable) {
+@@ -199,7 +215,19 @@ static int k10temp_probe(struct pci_dev *pdev,
+ "unreliable CPU thermal sensor; check erratum 319\n");
+ }
+
+- hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ data->pdev = pdev;
++
++ if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
++ boot_cpu_data.x86_model == 0x70))
++ data->read_tempreg = read_tempreg_nb_f15;
++ else
++ data->read_tempreg = read_tempreg_pci;
++
++ hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
+ k10temp_groups);
+ return PTR_ERR_OR_ZERO(hwmon_dev);
+ }
diff --git a/patches.drivers/hwmon-k10temp-only-apply-temperature-offset-if-result-is.patch b/patches.drivers/hwmon-k10temp-only-apply-temperature-offset-if-result-is.patch
new file mode 100644
index 0000000000..3fafff4be7
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-only-apply-temperature-offset-if-result-is.patch
@@ -0,0 +1,38 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Wed, 7 Feb 2018 17:49:39 -0800
+Subject: hwmon: (k10temp) Only apply temperature offset if result is positive
+Git-commit: aef17ca1271948ee57cc39b2493d31110cc42625
+Patch-mainline: v4.16
+References: FATE#327735
+
+A user reports a really bad temperature on Ryzen 1950X.
+
+k10temp-pci-00cb
+Adapter: PCI adapter
+temp1: +4294948.3°C (high = +70.0°C)
+
+This will happen if the temperature reported by the chip is lower than
+the offset temperature. This has been seen in the field if "Sense MI Skew"
+and/or "Sense MI Offset" BIOS parameters were set to unexpected values.
+Let's report a temperature of 0 degrees C in that case.
+
+Fixes: 1b50b776355f ("hwmon: (k10temp) Add support for temperature offsets")
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 06b4e1c78bd8..4c6594a4661d 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -129,7 +129,10 @@ static ssize_t temp1_input_show(struct device *dev,
+
+ data->read_tempreg(data->pdev, &regval);
+ temp = (regval >> 21) * 125;
+- temp -= data->temp_offset;
++ if (temp > data->temp_offset)
++ temp -= data->temp_offset;
++ else
++ temp = 0;
+
+ return sprintf(buf, "%u\n", temp);
+ }
diff --git a/patches.drivers/hwmon-k10temp-support-all-family-15h-model-6xh-and-model.patch b/patches.drivers/hwmon-k10temp-support-all-family-15h-model-6xh-and-model.patch
new file mode 100644
index 0000000000..e0241f3f34
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-support-all-family-15h-model-6xh-and-model.patch
@@ -0,0 +1,36 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Sun, 2 Sep 2018 12:02:53 -0700
+Subject: hwmon: (k10temp) Support all Family 15h Model 6xh and Model 7xh processors
+Git-commit: 53dfa0088edd2e2793afa21488532b12eb2dae48
+Patch-mainline: v4.20
+References: FATE#327735
+
+BIOS developer guides refer to Family 15h Models 60h-6fh and Family 15h
+Models 70h-7fh. So far the driver only checked for Models 60h and 70h.
+However, there are now processors with other model numbers in the same
+families. Example is A10-9620P family 15h model 65h. Follow the developer
+guides and mask the lower 4 bit of the model number to determine the
+registers to use for reading temperatures and temperature limits.
+
+Reported-by: Guglielmo Fanini <g.fanini@gmail.com>
+Cc: Guglielmo Fanini <g.fanini@gmail.com>
+Acked-by: Clemens Ladisch <clemens@ladisch.de>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index bb15d7816a29..2cef0c37ff6f 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -325,8 +325,9 @@ static int k10temp_probe(struct pci_dev *pdev,
+
+ data->pdev = pdev;
+
+- if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
+- boot_cpu_data.x86_model == 0x70)) {
++ if (boot_cpu_data.x86 == 0x15 &&
++ ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
++ (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
+ data->read_htcreg = read_htcreg_nb_f15;
+ data->read_tempreg = read_tempreg_nb_f15;
+ } else if (boot_cpu_data.x86 == 0x17) {
diff --git a/patches.drivers/hwmon-k10temp-support-threadripper-2920x-2970wx-simplify.patch b/patches.drivers/hwmon-k10temp-support-threadripper-2920x-2970wx-simplify.patch
new file mode 100644
index 0000000000..5335679822
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-support-threadripper-2920x-2970wx-simplify.patch
@@ -0,0 +1,39 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Thu, 9 Aug 2018 11:50:46 -0700
+Subject: hwmon: k10temp: Support Threadripper 2920X, 2970WX; simplify offset table
+Git-commit: cd6a2064dbf9e485b80c54687f0ce91cca91a6df
+Patch-mainline: v4.19
+References: FATE#327735
+
+All announced Threadripper 29xx models have a temperature offset of
+27 degrees C. Simplify temperature offset table to match all 29xx
+Threadripper models with a single entry. Also simplify the table to match
+all 19xx Threadripper models with a single entry. This effectively drops
+entries for Threadripper 1910/1920/1950 which never saw the light of day.
+
+Cc: Michael Larabel <Michael@phoronix.com>
+Cc: Clemens Ladisch <clemens@ladisch.de>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 577e2ede5a1a..bb15d7816a29 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -99,14 +99,8 @@ static const struct tctl_offset tctl_offset_table[] = {
+ { 0x17, "AMD Ryzen 7 1700X", 20000 },
+ { 0x17, "AMD Ryzen 7 1800X", 20000 },
+ { 0x17, "AMD Ryzen 7 2700X", 10000 },
+- { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
+- { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
+- { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
+- { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
+- { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
+- { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
+- { 0x17, "AMD Ryzen Threadripper 2950X", 27000 },
+- { 0x17, "AMD Ryzen Threadripper 2990WX", 27000 },
++ { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
++ { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
+ };
+
+ static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
diff --git a/patches.drivers/hwmon-k10temp-use-api-function-to-access-system-management.patch b/patches.drivers/hwmon-k10temp-use-api-function-to-access-system-management.patch
new file mode 100644
index 0000000000..418b823488
--- /dev/null
+++ b/patches.drivers/hwmon-k10temp-use-api-function-to-access-system-management.patch
@@ -0,0 +1,78 @@
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Fri, 4 May 2018 13:01:33 -0700
+Subject: hwmon: (k10temp) Use API function to access System Management Network
+Git-commit: 3b031622f598481970400519bd5abc2a16708282
+Patch-mainline: v4.17
+References: FATE#327735
+
+The SMN (System Management Network) on Family 17h AMD CPUs is also accessed
+from other drivers, specifically EDAC. Accessing it directly is racy.
+On top of that, accessing the SMN through root bridge 00:00 is wrong on
+multi-die CPUs and may result in reading the temperature from the wrong
+die. Use available API functions to fix the problem.
+
+For this to work, add dependency on AMD_NB. Also change the Raven Ridge
+PCI device ID to point to Data Fabric Function 3, since this ID is used
+by the API functions to find the CPU node.
+
+Cc: stable@vger.kernel.org # v4.16+
+Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+
+diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
+index f249a4428458..6ec307c93ece 100644
+--- a/drivers/hwmon/Kconfig
++++ b/drivers/hwmon/Kconfig
+@@ -272,7 +272,7 @@ config SENSORS_K8TEMP
+
+ config SENSORS_K10TEMP
+ tristate "AMD Family 10h+ temperature sensor"
+- depends on X86 && PCI
++ depends on X86 && PCI && AMD_NB
+ help
+ If you say yes here you get support for the temperature
+ sensor(s) inside your CPU. Supported are later revisions of
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 34b5448b00be..3b73dee6fdc6 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -23,6 +23,7 @@
+ #include <linux/init.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
++#include <asm/amd_nb.h>
+ #include <asm/processor.h>
+
+ MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
+@@ -40,8 +41,8 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #endif
+
+-#ifndef PCI_DEVICE_ID_AMD_17H_RR_NB
+-#define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0
++#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
++#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #endif
+
+ /* CPUID function 0x80000001, ebx */
+@@ -136,8 +137,8 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
+
+ static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
+ {
+- amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
+- F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
++ amd_smn_read(amd_pci_dev_to_node_id(pdev),
++ F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
+ }
+
+ static ssize_t temp1_input_show(struct device *dev,
+@@ -322,7 +323,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+- { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ {}
+ };
+ MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/patches.drivers/hwmon-k10temp-x86-amd_nb-consolidate-shared-device-ids.patch b/patches.drivers/hwmon-k10temp-x86-amd_nb-consolidate-shared-device-ids.patch
index 5ea776d679..0a1697b980 100644
--- a/patches.drivers/hwmon-k10temp-x86-amd_nb-consolidate-shared-device-ids.patch
+++ b/patches.drivers/hwmon-k10temp-x86-amd_nb-consolidate-shared-device-ids.patch
@@ -3,7 +3,7 @@ Date: Tue, 6 Nov 2018 20:08:14 +0000
Subject: hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs
Git-commit: dedf7dce4cec5c0abe69f4fa6938d5100398220b
Patch-mainline: v5.0-rc1
-References: fate#326884
+References: FATE#326884 FATE#327735
Consolidate shared PCI_DEVICE_IDs that were scattered through k10temp
and amd_nb, and move them into pci_ids.
@@ -24,14 +24,14 @@ CC: Thomas Gleixner <tglx@linutronix.de>
CC: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com
---
- arch/x86/kernel/amd_nb.c | 2 +-
- drivers/hwmon/k10temp.c | 1 +
+ arch/x86/kernel/amd_nb.c | 3 +--
+ drivers/hwmon/k10temp.c | 9 +--------
include/linux/pci_ids.h | 2 ++
- 3 files changed, 4 insertions(+), 1 deletion(-)
+ 3 files changed, 4 insertions(+), 10 deletions(-)
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
-@@ -11,10 +11,10 @@
+@@ -11,13 +11,12 @@
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/spinlock.h>
@@ -39,8 +39,11 @@ Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com
#include <asm/amd_nb.h>
#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
+ #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
-#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
+-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
/* Protect the PCI config register pairs used for SMN and DF indirect access. */
--- a/drivers/hwmon/k10temp.c
@@ -50,12 +53,27 @@ Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com
#include <linux/module.h>
#include <linux/pci.h>
+#include <linux/pci_ids.h>
+ #include <asm/amd_nb.h>
#include <asm/processor.h>
- MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
+@@ -41,14 +42,6 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
+ #endif
+
+-#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
+-#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+-#endif
+-
+-#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
+-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+-#endif
+-
+ /* CPUID function 0x80000001, ebx */
+ #define CPUID_PKGTYPE_MASK 0xf0000000
+ #define CPUID_PKGTYPE_F 0x00000000
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
-@@ -537,6 +537,8 @@
+@@ -540,6 +540,8 @@
#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
diff --git a/patches.drivers/i2c-piix4-add-hygon-dhyana-smbus-support.patch b/patches.drivers/i2c-piix4-add-hygon-dhyana-smbus-support.patch
new file mode 100644
index 0000000000..0857566a32
--- /dev/null
+++ b/patches.drivers/i2c-piix4-add-hygon-dhyana-smbus-support.patch
@@ -0,0 +1,91 @@
+From: Pu Wen <puwen@hygon.cn>
+Date: Tue, 30 Apr 2019 00:08:43 +0800
+Subject: i2c-piix4: Add Hygon Dhyana SMBus support
+Git-commit: 24beb83ad289c68bce7c01351cb90465bbb1940a
+Patch-mainline: v5.2
+References: FATE#327735
+
+The Hygon Dhyana CPU has the SMBus device with PCI device ID 0x790b,
+which is the same as AMD CZ SMBus device. So add Hygon Dhyana support
+to the i2c-piix4 driver by using the code path of AMD.
+
+Signed-off-by: Pu Wen <puwen@hygon.cn>
+Reviewed-by: Jean Delvare <jdelvare@suse.de>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Acked-by: Jean Delvare <jdelvare@suse.de>
+---
+ Documentation/i2c/busses/i2c-piix4 | 2 ++
+ drivers/i2c/busses/Kconfig | 1 +
+ drivers/i2c/busses/i2c-piix4.c | 12 +++++++++---
+ 3 files changed, 12 insertions(+), 3 deletions(-)
+
+--- a/Documentation/i2c/busses/i2c-piix4
++++ b/Documentation/i2c/busses/i2c-piix4
+@@ -15,6 +15,8 @@ Supported adapters:
+ http://support.amd.com/us/Embedded_TechDocs/44413.pdf
+ * AMD Hudson-2, ML, CZ
+ Datasheet: Not publicly available
++ * Hygon CZ
++ Datasheet: Not publicly available
+ * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
+ Datasheet: Publicly available at the SMSC website http://www.smsc.com
+
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -176,6 +176,7 @@ config I2C_PIIX4
+ AMD Hudson-2
+ AMD ML
+ AMD CZ
++ Hygon CZ
+ Serverworks OSB4
+ Serverworks CSB5
+ Serverworks CSB6
+--- a/drivers/i2c/busses/i2c-piix4.c
++++ b/drivers/i2c/busses/i2c-piix4.c
+@@ -19,6 +19,7 @@
+ Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
+ ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
+ AMD Hudson-2, ML, CZ
++ Hygon CZ
+ SMSC Victory66
+
+ Note: we assume there can only be one device, with one or more
+@@ -289,7 +290,9 @@ static int piix4_setup_sb800(struct pci_
+ PIIX4_dev->revision >= 0x41) ||
+ (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
+ PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
+- PIIX4_dev->revision >= 0x49))
++ PIIX4_dev->revision >= 0x49) ||
++ (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
++ PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
+ smb_en = 0x00;
+ else
+ smb_en = (aux) ? 0x28 : 0x2c;
+@@ -354,7 +357,8 @@ static int piix4_setup_sb800(struct pci_
+ piix4_smba, i2ccfg >> 4);
+
+ /* Find which register is used for port selection */
+- if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) {
++ if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
++ PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
+ switch (PIIX4_dev->device) {
+ case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
+ piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
+@@ -682,6 +686,7 @@ static const struct pci_device_id piix4_
+ { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
++ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
+ PCI_DEVICE_ID_SERVERWORKS_OSB4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
+@@ -790,7 +795,8 @@ static int piix4_probe(struct pci_dev *d
+ if ((dev->vendor == PCI_VENDOR_ID_ATI &&
+ dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
+ dev->revision >= 0x40) ||
+- dev->vendor == PCI_VENDOR_ID_AMD) {
++ dev->vendor == PCI_VENDOR_ID_AMD ||
++ dev->vendor == PCI_VENDOR_ID_HYGON) {
+ is_sb800 = true;
+
+ if (!request_region(SB800_PIIX4_SMB_IDX, 2, "smba_idx")) {
diff --git a/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch b/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch
new file mode 100644
index 0000000000..0d801ac374
--- /dev/null
+++ b/patches.drivers/ipv6-fib-Don-t-assume-only-nodes-hold-a-reference-on.patch
@@ -0,0 +1,41 @@
+From: Ido Schimmel <idosch@mellanox.com>
+Date: Thu, 3 Aug 2017 13:28:21 +0200
+Subject: ipv6: fib: Don't assume only nodes hold a reference on routes
+Patch-mainline: v4.14-rc1
+Git-commit: c5b12410fa591acb1d48e167b9bd0d2a7a38498d
+References: bsc#1138732
+
+The code currently assumes that only FIB nodes can hold a reference on
+routes. Therefore, after fib6_purge_rt() has run and the route is no
+longer present in any intermediate nodes, it's assumed that its
+reference count would be 1 - taken by the node where it's currently
+stored.
+
+However, we're going to allow users other than the FIB to take a
+reference on a route, so this assumption is no longer valid and the
+BUG_ON() needs to be removed.
+
+Note that purging only takes place if the initial reference count is
+different than 1. I've left that check intact, as in the majority of
+systems (where routes are only referenced by the FIB), it does actually
+mean the route is present in intermediate nodes.
+
+Signed-off-by: Ido Schimmel <idosch@mellanox.com>
+Signed-off-by: Jiri Pirko <jiri@mellanox.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ net/ipv6/ip6_fib.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/net/ipv6/ip6_fib.c
++++ b/net/ipv6/ip6_fib.c
+@@ -763,8 +763,6 @@ static void fib6_purge_rt(struct rt6_inf
+ }
+ fn = fn->parent;
+ }
+- /* No more references are possible at this point. */
+- BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
+ }
+ }
+
diff --git a/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch b/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch
new file mode 100644
index 0000000000..231a9e17a8
--- /dev/null
+++ b/patches.drivers/platform-mellanox-Add-TmFifo-driver-for-Mellanox-Blu.patch
@@ -0,0 +1,1410 @@
+From: Liming Sun <lsun@mellanox.com>
+Date: Fri, 3 May 2019 09:49:08 -0400
+Subject: platform/mellanox: Add TmFifo driver for Mellanox BlueField Soc
+Patch-mainline: v5.2-rc1
+Git-commit: 1357dfd7261fc2f625bf895f77bb57e8827b8f63
+References: bsc#1136333 jsc#SLE-4994
+
+This commit adds the TmFifo platform driver for Mellanox BlueField
+Soc. TmFifo is a shared FIFO which enables external host machine
+to exchange data with the SoC via USB or PCIe. The driver is based
+on virtio framework and has console and network access enabled.
+
+Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Liming Sun <lsun@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/mellanox/Kconfig | 12
+ drivers/platform/mellanox/Makefile | 1
+ drivers/platform/mellanox/mlxbf-tmfifo-regs.h | 63 +
+ drivers/platform/mellanox/mlxbf-tmfifo.c | 1281 ++++++++++++++++++++++++++
+ 4 files changed, 1356 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+ create mode 100644 drivers/platform/mellanox/mlxbf-tmfifo.c
+
+--- a/drivers/platform/mellanox/Kconfig
++++ b/drivers/platform/mellanox/Kconfig
+@@ -5,7 +5,7 @@
+
+ menuconfig MELLANOX_PLATFORM
+ bool "Platform support for Mellanox hardware"
+- depends on X86 || ARM || COMPILE_TEST
++ depends on X86 || ARM || ARM64 || COMPILE_TEST
+ ---help---
+ Say Y here to get to see options for platform support for
+ Mellanox systems. This option alone does not add any kernel code.
+@@ -34,4 +34,14 @@ config MLXREG_IO
+ to system resets operation, system reset causes monitoring and some
+ kinds of mux selection.
+
++config MLXBF_TMFIFO
++ tristate "Mellanox BlueField SoC TmFifo platform driver"
++ depends on ARM64
++ depends on ACPI
++ depends on VIRTIO_CONSOLE && VIRTIO_NET
++ help
++ Say y here to enable TmFifo support. The TmFifo driver provides
++ platform driver support for the TmFifo which supports console
++ and networking based on the virtio framework.
++
+ endif # MELLANOX_PLATFORM
+--- a/drivers/platform/mellanox/Makefile
++++ b/drivers/platform/mellanox/Makefile
+@@ -3,5 +3,6 @@
+ # Makefile for linux/drivers/platform/mellanox
+ # Mellanox Platform-Specific Drivers
+ #
++obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o
+ obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o
+ obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o
+--- /dev/null
++++ b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+@@ -0,0 +1,63 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
++ */
++
++#ifndef __MLXBF_TMFIFO_REGS_H__
++#define __MLXBF_TMFIFO_REGS_H__
++
++#include <linux/types.h>
++#include <linux/bits.h>
++
++#define MLXBF_TMFIFO_TX_DATA 0x00
++#define MLXBF_TMFIFO_TX_STS 0x08
++#define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001
++#define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0
++#define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9
++#define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0
++#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_CTL 0x10
++#define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001
++#define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0
++#define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8
++#define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128
++#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8
++#define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8
++#define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128
++#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
++#define MLXBF_TMFIFO_RX_DATA 0x00
++#define MLXBF_TMFIFO_RX_STS 0x08
++#define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001
++#define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0
++#define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9
++#define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0
++#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_CTL 0x10
++#define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001
++#define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0
++#define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8
++#define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128
++#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8
++#define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8
++#define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128
++#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
++#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
++#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
++
++#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
+--- /dev/null
++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c
+@@ -0,0 +1,1281 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Mellanox BlueField SoC TmFifo driver
++ *
++ * Copyright (C) 2019 Mellanox Technologies
++ */
++
++#include <linux/acpi.h>
++#include <linux/bitfield.h>
++#include <linux/circ_buf.h>
++#include <linux/efi.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/types.h>
++
++#include <linux/virtio_config.h>
++#include <linux/virtio_console.h>
++#include <linux/virtio_ids.h>
++#include <linux/virtio_net.h>
++#include <linux/virtio_ring.h>
++
++#include "mlxbf-tmfifo-regs.h"
++
++/* Vring size. */
++#define MLXBF_TMFIFO_VRING_SIZE SZ_1K
++
++/* Console Tx buffer size. */
++#define MLXBF_TMFIFO_CON_TX_BUF_SIZE SZ_32K
++
++/* Console Tx buffer reserved space. */
++#define MLXBF_TMFIFO_CON_TX_BUF_RSV_SIZE 8
++
++/* House-keeping timer interval. */
++#define MLXBF_TMFIFO_TIMER_INTERVAL (HZ / 10)
++
++/* Virtual devices sharing the TM FIFO. */
++#define MLXBF_TMFIFO_VDEV_MAX (VIRTIO_ID_CONSOLE + 1)
++
++/*
++ * Reserve 1/16 of TmFifo space, so console messages are not starved by
++ * the networking traffic.
++ */
++#define MLXBF_TMFIFO_RESERVE_RATIO 16
++
++/* Message with data needs at least two words (for header & data). */
++#define MLXBF_TMFIFO_DATA_MIN_WORDS 2
++
++struct mlxbf_tmfifo;
++
++/**
++ * mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
++ * @va: virtual address of the ring
++ * @dma: dma address of the ring
++ * @vq: pointer to the virtio virtqueue
++ * @desc: current descriptor of the pending packet
++ * @desc_head: head descriptor of the pending packet
++ * @cur_len: processed length of the current descriptor
++ * @rem_len: remaining length of the pending packet
++ * @pkt_len: total length of the pending packet
++ * @next_avail: next avail descriptor id
++ * @num: vring size (number of descriptors)
++ * @align: vring alignment size
++ * @index: vring index
++ * @vdev_id: vring virtio id (VIRTIO_ID_xxx)
++ * @fifo: pointer to the tmfifo structure
++ */
++struct mlxbf_tmfifo_vring {
++ void *va;
++ dma_addr_t dma;
++ struct virtqueue *vq;
++ struct vring_desc *desc;
++ struct vring_desc *desc_head;
++ int cur_len;
++ int rem_len;
++ u32 pkt_len;
++ u16 next_avail;
++ int num;
++ int align;
++ int index;
++ int vdev_id;
++ struct mlxbf_tmfifo *fifo;
++};
++
++/* Interrupt types. */
++enum {
++ MLXBF_TM_RX_LWM_IRQ,
++ MLXBF_TM_RX_HWM_IRQ,
++ MLXBF_TM_TX_LWM_IRQ,
++ MLXBF_TM_TX_HWM_IRQ,
++ MLXBF_TM_MAX_IRQ
++};
++
++/* Ring types (Rx & Tx). */
++enum {
++ MLXBF_TMFIFO_VRING_RX,
++ MLXBF_TMFIFO_VRING_TX,
++ MLXBF_TMFIFO_VRING_MAX
++};
++
++/**
++ * mlxbf_tmfifo_vdev - Structure of the TmFifo virtual device
++ * @vdev: virtio device, in which the vdev.id.device field has the
++ * VIRTIO_ID_xxx id to distinguish the virtual device.
++ * @status: status of the device
++ * @features: supported features of the device
++ * @vrings: array of tmfifo vrings of this device
++ * @config.cons: virtual console config -
++ * select if vdev.id.device is VIRTIO_ID_CONSOLE
++ * @config.net: virtual network config -
++ * select if vdev.id.device is VIRTIO_ID_NET
++ * @tx_buf: tx buffer used to buffer data before writing into the FIFO
++ */
++struct mlxbf_tmfifo_vdev {
++ struct virtio_device vdev;
++ u8 status;
++ u64 features;
++ struct mlxbf_tmfifo_vring vrings[MLXBF_TMFIFO_VRING_MAX];
++ union {
++ struct virtio_console_config cons;
++ struct virtio_net_config net;
++ } config;
++ struct circ_buf tx_buf;
++};
++
++/**
++ * mlxbf_tmfifo_irq_info - Structure of the interrupt information
++ * @fifo: pointer to the tmfifo structure
++ * @irq: interrupt number
++ * @index: index into the interrupt array
++ */
++struct mlxbf_tmfifo_irq_info {
++ struct mlxbf_tmfifo *fifo;
++ int irq;
++ int index;
++};
++
++/**
++ * mlxbf_tmfifo - Structure of the TmFifo
++ * @vdev: array of the virtual devices running over the TmFifo
++ * @lock: lock to protect the TmFifo access
++ * @rx_base: mapped register base address for the Rx FIFO
++ * @tx_base: mapped register base address for the Tx FIFO
++ * @rx_fifo_size: number of entries of the Rx FIFO
++ * @tx_fifo_size: number of entries of the Tx FIFO
++ * @pend_events: pending bits for deferred events
++ * @irq_info: interrupt information
++ * @work: work struct for deferred process
++ * @timer: background timer
++ * @vring: Tx/Rx ring
++ * @spin_lock: spin lock
++ * @is_ready: ready flag
++ */
++struct mlxbf_tmfifo {
++ struct mlxbf_tmfifo_vdev *vdev[MLXBF_TMFIFO_VDEV_MAX];
++ struct mutex lock; /* TmFifo lock */
++ void __iomem *rx_base;
++ void __iomem *tx_base;
++ int rx_fifo_size;
++ int tx_fifo_size;
++ unsigned long pend_events;
++ struct mlxbf_tmfifo_irq_info irq_info[MLXBF_TM_MAX_IRQ];
++ struct work_struct work;
++ struct timer_list timer;
++ struct mlxbf_tmfifo_vring *vring[2];
++ spinlock_t spin_lock; /* spin lock */
++ bool is_ready;
++};
++
++/**
++ * mlxbf_tmfifo_msg_hdr - Structure of the TmFifo message header
++ * @type: message type
++ * @len: payload length in network byte order. Messages sent into the FIFO
++ * will be read by the other side as data stream in the same byte order.
++ * The length needs to be encoded into network order so both sides
++ * could understand it.
++ */
++struct mlxbf_tmfifo_msg_hdr {
++ u8 type;
++ __be16 len;
++ u8 unused[5];
++} __packed __aligned(sizeof(u64));
++
++/*
++ * Default MAC.
++ * This MAC address will be read from EFI persistent variable if configured.
++ * It can also be reconfigured with standard Linux tools.
++ */
++static u8 mlxbf_tmfifo_net_default_mac[ETH_ALEN] = {
++ 0x00, 0x1A, 0xCA, 0xFF, 0xFF, 0x01
++};
++
++/* EFI variable name of the MAC address. */
++static efi_char16_t mlxbf_tmfifo_efi_name[] = L"RshimMacAddr";
++
++/* Maximum L2 header length. */
++#define MLXBF_TMFIFO_NET_L2_OVERHEAD 36
++
++/* Supported virtio-net features. */
++#define MLXBF_TMFIFO_NET_FEATURES \
++ (BIT_ULL(VIRTIO_NET_F_MTU) | BIT_ULL(VIRTIO_NET_F_STATUS) | \
++ BIT_ULL(VIRTIO_NET_F_MAC))
++
++#define mlxbf_vdev_to_tmfifo(d) container_of(d, struct mlxbf_tmfifo_vdev, vdev)
++
++/* Free vrings of the FIFO device. */
++static void mlxbf_tmfifo_free_vrings(struct mlxbf_tmfifo *fifo,
++ struct mlxbf_tmfifo_vdev *tm_vdev)
++{
++ struct mlxbf_tmfifo_vring *vring;
++ int i, size;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++ if (vring->va) {
++ size = vring_size(vring->num, vring->align);
++ dma_free_coherent(tm_vdev->vdev.dev.parent, size,
++ vring->va, vring->dma);
++ vring->va = NULL;
++ if (vring->vq) {
++ vring_del_virtqueue(vring->vq);
++ vring->vq = NULL;
++ }
++ }
++ }
++}
++
++/* Allocate vrings for the FIFO. */
++static int mlxbf_tmfifo_alloc_vrings(struct mlxbf_tmfifo *fifo,
++ struct mlxbf_tmfifo_vdev *tm_vdev)
++{
++ struct mlxbf_tmfifo_vring *vring;
++ struct device *dev;
++ dma_addr_t dma;
++ int i, size;
++ void *va;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++ vring->fifo = fifo;
++ vring->num = MLXBF_TMFIFO_VRING_SIZE;
++ vring->align = SMP_CACHE_BYTES;
++ vring->index = i;
++ vring->vdev_id = tm_vdev->vdev.id.device;
++ dev = &tm_vdev->vdev.dev;
++
++ size = vring_size(vring->num, vring->align);
++ va = dma_alloc_coherent(dev->parent, size, &dma, GFP_KERNEL);
++ if (!va) {
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ dev_err(dev->parent, "dma_alloc_coherent failed\n");
++ return -ENOMEM;
++ }
++
++ vring->va = va;
++ vring->dma = dma;
++ }
++
++ return 0;
++}
++
++/* Disable interrupts of the FIFO device. */
++static void mlxbf_tmfifo_disable_irqs(struct mlxbf_tmfifo *fifo)
++{
++ int i, irq;
++
++ for (i = 0; i < MLXBF_TM_MAX_IRQ; i++) {
++ irq = fifo->irq_info[i].irq;
++ fifo->irq_info[i].irq = 0;
++ disable_irq(irq);
++ }
++}
++
++/* Interrupt handler. */
++static irqreturn_t mlxbf_tmfifo_irq_handler(int irq, void *arg)
++{
++ struct mlxbf_tmfifo_irq_info *irq_info = arg;
++
++ if (!test_and_set_bit(irq_info->index, &irq_info->fifo->pend_events))
++ schedule_work(&irq_info->fifo->work);
++
++ return IRQ_HANDLED;
++}
++
++/* Get the next packet descriptor from the vring. */
++static struct vring_desc *
++mlxbf_tmfifo_get_next_desc(struct mlxbf_tmfifo_vring *vring)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ unsigned int idx, head;
++
++ if (vring->next_avail == virtio16_to_cpu(vdev, vr->avail->idx))
++ return NULL;
++
++ idx = vring->next_avail % vr->num;
++ head = virtio16_to_cpu(vdev, vr->avail->ring[idx]);
++ if (WARN_ON(head >= vr->num))
++ return NULL;
++
++ vring->next_avail++;
++
++ return &vr->desc[head];
++}
++
++/* Release virtio descriptor. */
++static void mlxbf_tmfifo_release_desc(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc, u32 len)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ u16 idx, vr_idx;
++
++ vr_idx = virtio16_to_cpu(vdev, vr->used->idx);
++ idx = vr_idx % vr->num;
++ vr->used->ring[idx].id = cpu_to_virtio32(vdev, desc - vr->desc);
++ vr->used->ring[idx].len = cpu_to_virtio32(vdev, len);
++
++ /*
++ * Virtio could poll and check the 'idx' to decide whether the desc is
++ * done or not. Add a memory barrier here to make sure the update above
++ * completes before updating the idx.
++ */
++ mb();
++ vr->used->idx = cpu_to_virtio16(vdev, vr_idx + 1);
++}
++
++/* Get the total length of the descriptor chain. */
++static u32 mlxbf_tmfifo_get_pkt_len(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = vring->vq->vdev;
++ u32 len = 0, idx;
++
++ while (desc) {
++ len += virtio32_to_cpu(vdev, desc->len);
++ if (!(virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT))
++ break;
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ }
++
++ return len;
++}
++
++static void mlxbf_tmfifo_release_pending_pkt(struct mlxbf_tmfifo_vring *vring)
++{
++ struct vring_desc *desc_head;
++ u32 len = 0;
++
++ if (vring->desc_head) {
++ desc_head = vring->desc_head;
++ len = vring->pkt_len;
++ } else {
++ desc_head = mlxbf_tmfifo_get_next_desc(vring);
++ len = mlxbf_tmfifo_get_pkt_len(vring, desc_head);
++ }
++
++ if (desc_head)
++ mlxbf_tmfifo_release_desc(vring, desc_head, len);
++
++ vring->pkt_len = 0;
++ vring->desc = NULL;
++ vring->desc_head = NULL;
++}
++
++static void mlxbf_tmfifo_init_net_desc(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc, bool is_rx)
++{
++ struct virtio_device *vdev = vring->vq->vdev;
++ struct virtio_net_hdr *net_hdr;
++
++ net_hdr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++ memset(net_hdr, 0, sizeof(*net_hdr));
++}
++
++/* Get and initialize the next packet. */
++static struct vring_desc *
++mlxbf_tmfifo_get_next_pkt(struct mlxbf_tmfifo_vring *vring, bool is_rx)
++{
++ struct vring_desc *desc;
++
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ if (desc && is_rx && vring->vdev_id == VIRTIO_ID_NET)
++ mlxbf_tmfifo_init_net_desc(vring, desc, is_rx);
++
++ vring->desc_head = desc;
++ vring->desc = desc;
++
++ return desc;
++}
++
++/* House-keeping timer. */
++static void mlxbf_tmfifo_timer(struct timer_list *t)
++{
++ struct mlxbf_tmfifo *fifo = container_of(t, struct mlxbf_tmfifo, timer);
++ int rx, tx;
++
++ rx = !test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events);
++ tx = !test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
++
++ if (rx || tx)
++ schedule_work(&fifo->work);
++
++ mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
++}
++
++/* Copy one console packet into the output buffer. */
++static void mlxbf_tmfifo_console_output_one(struct mlxbf_tmfifo_vdev *cons,
++ struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct virtio_device *vdev = &cons->vdev;
++ u32 len, idx, seg;
++ void *addr;
++
++ while (desc) {
++ addr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++ len = virtio32_to_cpu(vdev, desc->len);
++
++ seg = CIRC_SPACE_TO_END(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (len <= seg) {
++ memcpy(cons->tx_buf.buf + cons->tx_buf.head, addr, len);
++ } else {
++ memcpy(cons->tx_buf.buf + cons->tx_buf.head, addr, seg);
++ addr += seg;
++ memcpy(cons->tx_buf.buf, addr, len - seg);
++ }
++ cons->tx_buf.head = (cons->tx_buf.head + len) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++
++ if (!(virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT))
++ break;
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ }
++}
++
++/* Copy console data into the output buffer. */
++static void mlxbf_tmfifo_console_output(struct mlxbf_tmfifo_vdev *cons,
++ struct mlxbf_tmfifo_vring *vring)
++{
++ struct vring_desc *desc;
++ u32 len, avail;
++
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ while (desc) {
++ /* Release the packet if not enough space. */
++ len = mlxbf_tmfifo_get_pkt_len(vring, desc);
++ avail = CIRC_SPACE(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (len + MLXBF_TMFIFO_CON_TX_BUF_RSV_SIZE > avail) {
++ mlxbf_tmfifo_release_desc(vring, desc, len);
++ break;
++ }
++
++ mlxbf_tmfifo_console_output_one(cons, vring, desc);
++ mlxbf_tmfifo_release_desc(vring, desc, len);
++ desc = mlxbf_tmfifo_get_next_desc(vring);
++ }
++}
++
++/* Get the number of available words in Rx FIFO for receiving. */
++static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
++{
++ u64 sts;
++
++ sts = readq(fifo->rx_base + MLXBF_TMFIFO_RX_STS);
++ return FIELD_GET(MLXBF_TMFIFO_RX_STS__COUNT_MASK, sts);
++}
++
++/* Get the number of available words in the TmFifo for sending. */
++static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
++{
++ int tx_reserve;
++ u32 count;
++ u64 sts;
++
++ /* Reserve some room in FIFO for console messages. */
++ if (vdev_id == VIRTIO_ID_NET)
++ tx_reserve = fifo->tx_fifo_size / MLXBF_TMFIFO_RESERVE_RATIO;
++ else
++ tx_reserve = 1;
++
++ sts = readq(fifo->tx_base + MLXBF_TMFIFO_TX_STS);
++ count = FIELD_GET(MLXBF_TMFIFO_TX_STS__COUNT_MASK, sts);
++ return fifo->tx_fifo_size - tx_reserve - count;
++}
++
++/* Console Tx (move data from the output buffer into the TmFifo). */
++static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
++{
++ struct mlxbf_tmfifo_msg_hdr hdr;
++ struct mlxbf_tmfifo_vdev *cons;
++ unsigned long flags;
++ int size, seg;
++ void *addr;
++ u64 data;
++
++ /* Return if not enough space available. */
++ if (avail < MLXBF_TMFIFO_DATA_MIN_WORDS)
++ return;
++
++ cons = fifo->vdev[VIRTIO_ID_CONSOLE];
++ if (!cons || !cons->tx_buf.buf)
++ return;
++
++ /* Return if no data to send. */
++ size = CIRC_CNT(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (size == 0)
++ return;
++
++ /* Adjust the size to available space. */
++ if (size + sizeof(hdr) > avail * sizeof(u64))
++ size = avail * sizeof(u64) - sizeof(hdr);
++
++ /* Write header. */
++ hdr.type = VIRTIO_ID_CONSOLE;
++ hdr.len = htons(size);
++ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++
++ /* Use spin-lock to protect the 'cons->tx_buf'. */
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++
++ while (size > 0) {
++ addr = cons->tx_buf.buf + cons->tx_buf.tail;
++
++ seg = CIRC_CNT_TO_END(cons->tx_buf.head, cons->tx_buf.tail,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE);
++ if (seg >= sizeof(u64)) {
++ memcpy(&data, addr, sizeof(u64));
++ } else {
++ memcpy(&data, addr, seg);
++ memcpy((u8 *)&data + seg, cons->tx_buf.buf,
++ sizeof(u64) - seg);
++ }
++ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++
++ if (size >= sizeof(u64)) {
++ cons->tx_buf.tail = (cons->tx_buf.tail + sizeof(u64)) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++ size -= sizeof(u64);
++ } else {
++ cons->tx_buf.tail = (cons->tx_buf.tail + size) %
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE;
++ size = 0;
++ }
++ }
++
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++}
++
++/* Rx/Tx one word in the descriptor buffer. */
++static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc,
++ bool is_rx, int len)
++{
++ struct virtio_device *vdev = vring->vq->vdev;
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ void *addr;
++ u64 data;
++
++ /* Get the buffer address of this desc. */
++ addr = phys_to_virt(virtio64_to_cpu(vdev, desc->addr));
++
++ /* Read a word from FIFO for Rx. */
++ if (is_rx)
++ data = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
++
++ if (vring->cur_len + sizeof(u64) <= len) {
++ /* The whole word. */
++ if (is_rx)
++ memcpy(addr + vring->cur_len, &data, sizeof(u64));
++ else
++ memcpy(&data, addr + vring->cur_len, sizeof(u64));
++ vring->cur_len += sizeof(u64);
++ } else {
++ /* Leftover bytes. */
++ if (is_rx)
++ memcpy(addr + vring->cur_len, &data,
++ len - vring->cur_len);
++ else
++ memcpy(&data, addr + vring->cur_len,
++ len - vring->cur_len);
++ vring->cur_len = len;
++ }
++
++ /* Write the word into FIFO for Tx. */
++ if (!is_rx)
++ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++}
++
++/*
++ * Rx/Tx packet header.
++ *
++ * In Rx case, the packet might be found to belong to a different vring since
++ * the TmFifo is shared by different services. In such case, the 'vring_change'
++ * flag is set.
++ */
++static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
++ struct vring_desc *desc,
++ bool is_rx, bool *vring_change)
++{
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ struct virtio_net_config *config;
++ struct mlxbf_tmfifo_msg_hdr hdr;
++ int vdev_id, hdr_len;
++
++ /* Read/Write packet header. */
++ if (is_rx) {
++ /* Drain one word from the FIFO. */
++ *(u64 *)&hdr = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
++
++ /* Skip the length 0 packets (keepalive). */
++ if (hdr.len == 0)
++ return;
++
++ /* Check packet type. */
++ if (hdr.type == VIRTIO_ID_NET) {
++ vdev_id = VIRTIO_ID_NET;
++ hdr_len = sizeof(struct virtio_net_hdr);
++ config = &fifo->vdev[vdev_id]->config.net;
++ if (ntohs(hdr.len) > config->mtu +
++ MLXBF_TMFIFO_NET_L2_OVERHEAD)
++ return;
++ } else {
++ vdev_id = VIRTIO_ID_CONSOLE;
++ hdr_len = 0;
++ }
++
++ /*
++ * Check whether the new packet still belongs to this vring.
++ * If not, update the pkt_len of the new vring.
++ */
++ if (vdev_id != vring->vdev_id) {
++ struct mlxbf_tmfifo_vdev *tm_dev2 = fifo->vdev[vdev_id];
++
++ if (!tm_dev2)
++ return;
++ vring->desc = desc;
++ vring = &tm_dev2->vrings[MLXBF_TMFIFO_VRING_RX];
++ *vring_change = true;
++ }
++ vring->pkt_len = ntohs(hdr.len) + hdr_len;
++ } else {
++ /* Network virtio has an extra header. */
++ hdr_len = (vring->vdev_id == VIRTIO_ID_NET) ?
++ sizeof(struct virtio_net_hdr) : 0;
++ vring->pkt_len = mlxbf_tmfifo_get_pkt_len(vring, desc);
++ hdr.type = (vring->vdev_id == VIRTIO_ID_NET) ?
++ VIRTIO_ID_NET : VIRTIO_ID_CONSOLE;
++ hdr.len = htons(vring->pkt_len - hdr_len);
++ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
++ }
++
++ vring->cur_len = hdr_len;
++ vring->rem_len = vring->pkt_len;
++ fifo->vring[is_rx] = vring;
++}
++
++/*
++ * Rx/Tx one descriptor.
++ *
++ * Return true to indicate more data available.
++ */
++static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring,
++ bool is_rx, int *avail)
++{
++ const struct vring *vr = virtqueue_get_vring(vring->vq);
++ struct mlxbf_tmfifo *fifo = vring->fifo;
++ struct virtio_device *vdev;
++ bool vring_change = false;
++ struct vring_desc *desc;
++ unsigned long flags;
++ u32 len, idx;
++
++ vdev = &fifo->vdev[vring->vdev_id]->vdev;
++
++ /* Get the descriptor of the next packet. */
++ if (!vring->desc) {
++ desc = mlxbf_tmfifo_get_next_pkt(vring, is_rx);
++ if (!desc)
++ return false;
++ } else {
++ desc = vring->desc;
++ }
++
++ /* Beginning of a packet. Start to Rx/Tx packet header. */
++ if (vring->pkt_len == 0) {
++ mlxbf_tmfifo_rxtx_header(vring, desc, is_rx, &vring_change);
++ (*avail)--;
++
++ /* Return if new packet is for another ring. */
++ if (vring_change)
++ return false;
++ goto mlxbf_tmfifo_desc_done;
++ }
++
++ /* Get the length of this desc. */
++ len = virtio32_to_cpu(vdev, desc->len);
++ if (len > vring->rem_len)
++ len = vring->rem_len;
++
++ /* Rx/Tx one word (8 bytes) if not done. */
++ if (vring->cur_len < len) {
++ mlxbf_tmfifo_rxtx_word(vring, desc, is_rx, len);
++ (*avail)--;
++ }
++
++ /* Check again whether it's done. */
++ if (vring->cur_len == len) {
++ vring->cur_len = 0;
++ vring->rem_len -= len;
++
++ /* Get the next desc on the chain. */
++ if (vring->rem_len > 0 &&
++ (virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT)) {
++ idx = virtio16_to_cpu(vdev, desc->next);
++ desc = &vr->desc[idx];
++ goto mlxbf_tmfifo_desc_done;
++ }
++
++ /* Done and release the pending packet. */
++ mlxbf_tmfifo_release_pending_pkt(vring);
++ desc = NULL;
++ fifo->vring[is_rx] = NULL;
++
++ /* Notify upper layer that packet is done. */
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++ vring_interrupt(0, vring->vq);
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++ }
++
++mlxbf_tmfifo_desc_done:
++ /* Save the current desc. */
++ vring->desc = desc;
++
++ return true;
++}
++
++/* Rx & Tx processing of a queue. */
++static void mlxbf_tmfifo_rxtx(struct mlxbf_tmfifo_vring *vring, bool is_rx)
++{
++ int avail = 0, devid = vring->vdev_id;
++ struct mlxbf_tmfifo *fifo;
++ bool more;
++
++ fifo = vring->fifo;
++
++ /* Return if vdev is not ready. */
++ if (!fifo->vdev[devid])
++ return;
++
++ /* Return if another vring is running. */
++ if (fifo->vring[is_rx] && fifo->vring[is_rx] != vring)
++ return;
++
++ /* Only handle console and network for now. */
++ if (WARN_ON(devid != VIRTIO_ID_NET && devid != VIRTIO_ID_CONSOLE))
++ return;
++
++ do {
++ /* Get available FIFO space. */
++ if (avail == 0) {
++ if (is_rx)
++ avail = mlxbf_tmfifo_get_rx_avail(fifo);
++ else
++ avail = mlxbf_tmfifo_get_tx_avail(fifo, devid);
++ if (avail <= 0)
++ break;
++ }
++
++ /* Console output always comes from the Tx buffer. */
++ if (!is_rx && devid == VIRTIO_ID_CONSOLE) {
++ mlxbf_tmfifo_console_tx(fifo, avail);
++ break;
++ }
++
++ /* Handle one descriptor. */
++ more = mlxbf_tmfifo_rxtx_one_desc(vring, is_rx, &avail);
++ } while (more);
++}
++
++/* Handle Rx or Tx queues. */
++static void mlxbf_tmfifo_work_rxtx(struct mlxbf_tmfifo *fifo, int queue_id,
++ int irq_id, bool is_rx)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++ struct mlxbf_tmfifo_vring *vring;
++ int i;
++
++ if (!test_and_clear_bit(irq_id, &fifo->pend_events) ||
++ !fifo->irq_info[irq_id].irq)
++ return;
++
++ for (i = 0; i < MLXBF_TMFIFO_VDEV_MAX; i++) {
++ tm_vdev = fifo->vdev[i];
++ if (tm_vdev) {
++ vring = &tm_vdev->vrings[queue_id];
++ if (vring->vq)
++ mlxbf_tmfifo_rxtx(vring, is_rx);
++ }
++ }
++}
++
++/* Work handler for Rx and Tx case. */
++static void mlxbf_tmfifo_work_handler(struct work_struct *work)
++{
++ struct mlxbf_tmfifo *fifo;
++
++ fifo = container_of(work, struct mlxbf_tmfifo, work);
++ if (!fifo->is_ready)
++ return;
++
++ mutex_lock(&fifo->lock);
++
++ /* Tx (Send data to the TmFifo). */
++ mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_TX,
++ MLXBF_TM_TX_LWM_IRQ, false);
++
++ /* Rx (Receive data from the TmFifo). */
++ mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_RX,
++ MLXBF_TM_RX_HWM_IRQ, true);
++
++ mutex_unlock(&fifo->lock);
++}
++
++/* The notify function is called when new buffers are posted. */
++static bool mlxbf_tmfifo_virtio_notify(struct virtqueue *vq)
++{
++ struct mlxbf_tmfifo_vring *vring = vq->priv;
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++ struct mlxbf_tmfifo *fifo;
++ unsigned long flags;
++
++ fifo = vring->fifo;
++
++ /*
++ * Virtio maintains vrings in pairs, even number ring for Rx
++ * and odd number ring for Tx.
++ */
++ if (vring->index & BIT(0)) {
++ /*
++ * Console could make blocking call with interrupts disabled.
++ * In such case, the vring needs to be served right away. For
++ * other cases, just set the TX LWM bit to start Tx in the
++ * worker handler.
++ */
++ if (vring->vdev_id == VIRTIO_ID_CONSOLE) {
++ spin_lock_irqsave(&fifo->spin_lock, flags);
++ tm_vdev = fifo->vdev[VIRTIO_ID_CONSOLE];
++ mlxbf_tmfifo_console_output(tm_vdev, vring);
++ spin_unlock_irqrestore(&fifo->spin_lock, flags);
++ } else if (test_and_set_bit(MLXBF_TM_TX_LWM_IRQ,
++ &fifo->pend_events)) {
++ return true;
++ }
++ } else {
++ if (test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events))
++ return true;
++ }
++
++ schedule_work(&fifo->work);
++
++ return true;
++}
++
++/* Get the array of feature bits for this device. */
++static u64 mlxbf_tmfifo_virtio_get_features(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ return tm_vdev->features;
++}
++
++/* Confirm device features to use. */
++static int mlxbf_tmfifo_virtio_finalize_features(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->features = vdev->features;
++
++ return 0;
++}
++
++/* Free virtqueues found by find_vqs(). */
++static void mlxbf_tmfifo_virtio_del_vqs(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++ struct mlxbf_tmfifo_vring *vring;
++ struct virtqueue *vq;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(tm_vdev->vrings); i++) {
++ vring = &tm_vdev->vrings[i];
++
++ /* Release the pending packet. */
++ if (vring->desc)
++ mlxbf_tmfifo_release_pending_pkt(vring);
++ vq = vring->vq;
++ if (vq) {
++ vring->vq = NULL;
++ vring_del_virtqueue(vq);
++ }
++ }
++}
++
++/* Create and initialize the virtual queues. */
++static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev,
++ unsigned int nvqs,
++ struct virtqueue *vqs[],
++ vq_callback_t *callbacks[],
++ const char * const names[],
++ const bool *ctx,
++ struct irq_affinity *desc)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++ struct mlxbf_tmfifo_vring *vring;
++ struct virtqueue *vq;
++ int i, ret, size;
++
++ if (nvqs > ARRAY_SIZE(tm_vdev->vrings))
++ return -EINVAL;
++
++ for (i = 0; i < nvqs; ++i) {
++ if (!names[i]) {
++ ret = -EINVAL;
++ goto error;
++ }
++ vring = &tm_vdev->vrings[i];
++
++ /* zero vring */
++ size = vring_size(vring->num, vring->align);
++ memset(vring->va, 0, size);
++ vq = vring_new_virtqueue(i, vring->num, vring->align, vdev,
++ false, false, vring->va,
++ mlxbf_tmfifo_virtio_notify,
++ callbacks[i], names[i]);
++ if (!vq) {
++ dev_err(&vdev->dev, "vring_new_virtqueue failed\n");
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ vqs[i] = vq;
++ vring->vq = vq;
++ vq->priv = vring;
++ }
++
++ return 0;
++
++error:
++ mlxbf_tmfifo_virtio_del_vqs(vdev);
++ return ret;
++}
++
++/* Read the status byte. */
++static u8 mlxbf_tmfifo_virtio_get_status(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ return tm_vdev->status;
++}
++
++/* Write the status byte. */
++static void mlxbf_tmfifo_virtio_set_status(struct virtio_device *vdev,
++ u8 status)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->status = status;
++}
++
++/* Reset the device. Not much here for now. */
++static void mlxbf_tmfifo_virtio_reset(struct virtio_device *vdev)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ tm_vdev->status = 0;
++}
++
++/* Read the value of a configuration field. */
++static void mlxbf_tmfifo_virtio_get(struct virtio_device *vdev,
++ unsigned int offset,
++ void *buf,
++ unsigned int len)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ if ((u64)offset + len > sizeof(tm_vdev->config))
++ return;
++
++ memcpy(buf, (u8 *)&tm_vdev->config + offset, len);
++}
++
++/* Write the value of a configuration field. */
++static void mlxbf_tmfifo_virtio_set(struct virtio_device *vdev,
++ unsigned int offset,
++ const void *buf,
++ unsigned int len)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ if ((u64)offset + len > sizeof(tm_vdev->config))
++ return;
++
++ memcpy((u8 *)&tm_vdev->config + offset, buf, len);
++}
++
++static void tmfifo_virtio_dev_release(struct device *device)
++{
++ struct virtio_device *vdev =
++ container_of(device, struct virtio_device, dev);
++ struct mlxbf_tmfifo_vdev *tm_vdev = mlxbf_vdev_to_tmfifo(vdev);
++
++ kfree(tm_vdev);
++}
++
++/* Virtio config operations. */
++static const struct virtio_config_ops mlxbf_tmfifo_virtio_config_ops = {
++ .get_features = mlxbf_tmfifo_virtio_get_features,
++ .finalize_features = mlxbf_tmfifo_virtio_finalize_features,
++ .find_vqs = mlxbf_tmfifo_virtio_find_vqs,
++ .del_vqs = mlxbf_tmfifo_virtio_del_vqs,
++ .reset = mlxbf_tmfifo_virtio_reset,
++ .set_status = mlxbf_tmfifo_virtio_set_status,
++ .get_status = mlxbf_tmfifo_virtio_get_status,
++ .get = mlxbf_tmfifo_virtio_get,
++ .set = mlxbf_tmfifo_virtio_set,
++};
++
++/* Create vdev for the FIFO. */
++static int mlxbf_tmfifo_create_vdev(struct device *dev,
++ struct mlxbf_tmfifo *fifo,
++ int vdev_id, u64 features,
++ void *config, u32 size)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev, *reg_dev = NULL;
++ int ret;
++
++ mutex_lock(&fifo->lock);
++
++ tm_vdev = fifo->vdev[vdev_id];
++ if (tm_vdev) {
++ dev_err(dev, "vdev %d already exists\n", vdev_id);
++ ret = -EEXIST;
++ goto fail;
++ }
++
++ tm_vdev = kzalloc(sizeof(*tm_vdev), GFP_KERNEL);
++ if (!tm_vdev) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ tm_vdev->vdev.id.device = vdev_id;
++ tm_vdev->vdev.config = &mlxbf_tmfifo_virtio_config_ops;
++ tm_vdev->vdev.dev.parent = dev;
++ tm_vdev->vdev.dev.release = tmfifo_virtio_dev_release;
++ tm_vdev->features = features;
++ if (config)
++ memcpy(&tm_vdev->config, config, size);
++
++ if (mlxbf_tmfifo_alloc_vrings(fifo, tm_vdev)) {
++ dev_err(dev, "unable to allocate vring\n");
++ ret = -ENOMEM;
++ goto vdev_fail;
++ }
++
++ /* Allocate an output buffer for the console device. */
++ if (vdev_id == VIRTIO_ID_CONSOLE)
++ tm_vdev->tx_buf.buf = devm_kmalloc(dev,
++ MLXBF_TMFIFO_CON_TX_BUF_SIZE,
++ GFP_KERNEL);
++ fifo->vdev[vdev_id] = tm_vdev;
++
++ /* Register the virtio device. */
++ ret = register_virtio_device(&tm_vdev->vdev);
++ reg_dev = tm_vdev;
++ if (ret) {
++ dev_err(dev, "register_virtio_device failed\n");
++ goto vdev_fail;
++ }
++
++ mutex_unlock(&fifo->lock);
++ return 0;
++
++vdev_fail:
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ fifo->vdev[vdev_id] = NULL;
++ if (reg_dev)
++ put_device(&tm_vdev->vdev.dev);
++ else
++ kfree(tm_vdev);
++fail:
++ mutex_unlock(&fifo->lock);
++ return ret;
++}
++
++/* Delete vdev for the FIFO. */
++static int mlxbf_tmfifo_delete_vdev(struct mlxbf_tmfifo *fifo, int vdev_id)
++{
++ struct mlxbf_tmfifo_vdev *tm_vdev;
++
++ mutex_lock(&fifo->lock);
++
++ /* Unregister vdev. */
++ tm_vdev = fifo->vdev[vdev_id];
++ if (tm_vdev) {
++ unregister_virtio_device(&tm_vdev->vdev);
++ mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
++ fifo->vdev[vdev_id] = NULL;
++ }
++
++ mutex_unlock(&fifo->lock);
++
++ return 0;
++}
++
++/* Read the configured network MAC address from efi variable. */
++static void mlxbf_tmfifo_get_cfg_mac(u8 *mac)
++{
++ efi_guid_t guid = EFI_GLOBAL_VARIABLE_GUID;
++ unsigned long size = ETH_ALEN;
++ u8 buf[ETH_ALEN];
++ efi_status_t rc;
++
++ rc = efi.get_variable(mlxbf_tmfifo_efi_name, &guid, NULL, &size, buf);
++ if (rc == EFI_SUCCESS && size == ETH_ALEN)
++ ether_addr_copy(mac, buf);
++ else
++ ether_addr_copy(mac, mlxbf_tmfifo_net_default_mac);
++}
++
++/* Set TmFifo thresolds which is used to trigger interrupts. */
++static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
++{
++ u64 ctl;
++
++ /* Get Tx FIFO size and set the low/high watermark. */
++ ctl = readq(fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
++ fifo->tx_fifo_size =
++ FIELD_GET(MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK, ctl);
++ ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__LWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_TX_CTL__LWM_MASK,
++ fifo->tx_fifo_size / 2);
++ ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__HWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_TX_CTL__HWM_MASK,
++ fifo->tx_fifo_size - 1);
++ writeq(ctl, fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
++
++ /* Get Rx FIFO size and set the low/high watermark. */
++ ctl = readq(fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
++ fifo->rx_fifo_size =
++ FIELD_GET(MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK, ctl);
++ ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__LWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_RX_CTL__LWM_MASK, 0);
++ ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__HWM_MASK) |
++ FIELD_PREP(MLXBF_TMFIFO_RX_CTL__HWM_MASK, 1);
++ writeq(ctl, fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
++}
++
++static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
++{
++ int i;
++
++ fifo->is_ready = false;
++ del_timer_sync(&fifo->timer);
++ mlxbf_tmfifo_disable_irqs(fifo);
++ cancel_work_sync(&fifo->work);
++ for (i = 0; i < MLXBF_TMFIFO_VDEV_MAX; i++)
++ mlxbf_tmfifo_delete_vdev(fifo, i);
++}
++
++/* Probe the TMFIFO. */
++static int mlxbf_tmfifo_probe(struct platform_device *pdev)
++{
++ struct virtio_net_config net_config;
++ struct device *dev = &pdev->dev;
++ struct mlxbf_tmfifo *fifo;
++ int i, rc;
++
++ fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
++ if (!fifo)
++ return -ENOMEM;
++
++ spin_lock_init(&fifo->spin_lock);
++ INIT_WORK(&fifo->work, mlxbf_tmfifo_work_handler);
++ mutex_init(&fifo->lock);
++
++ /* Get the resource of the Rx FIFO. */
++ fifo->rx_base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(fifo->rx_base))
++ return PTR_ERR(fifo->rx_base);
++
++ /* Get the resource of the Tx FIFO. */
++ fifo->tx_base = devm_platform_ioremap_resource(pdev, 1);
++ if (IS_ERR(fifo->tx_base))
++ return PTR_ERR(fifo->tx_base);
++
++ platform_set_drvdata(pdev, fifo);
++
++ timer_setup(&fifo->timer, mlxbf_tmfifo_timer, 0);
++
++ for (i = 0; i < MLXBF_TM_MAX_IRQ; i++) {
++ fifo->irq_info[i].index = i;
++ fifo->irq_info[i].fifo = fifo;
++ fifo->irq_info[i].irq = platform_get_irq(pdev, i);
++ rc = devm_request_irq(dev, fifo->irq_info[i].irq,
++ mlxbf_tmfifo_irq_handler, 0,
++ "tmfifo", &fifo->irq_info[i]);
++ if (rc) {
++ dev_err(dev, "devm_request_irq failed\n");
++ fifo->irq_info[i].irq = 0;
++ return rc;
++ }
++ }
++
++ mlxbf_tmfifo_set_threshold(fifo);
++
++ /* Create the console vdev. */
++ rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_CONSOLE, 0, NULL, 0);
++ if (rc)
++ goto fail;
++
++ /* Create the network vdev. */
++ memset(&net_config, 0, sizeof(net_config));
++ net_config.mtu = ETH_DATA_LEN;
++ net_config.status = VIRTIO_NET_S_LINK_UP;
++ mlxbf_tmfifo_get_cfg_mac(net_config.mac);
++ rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_NET,
++ MLXBF_TMFIFO_NET_FEATURES, &net_config,
++ sizeof(net_config));
++ if (rc)
++ goto fail;
++
++ mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
++
++ fifo->is_ready = true;
++ return 0;
++
++fail:
++ mlxbf_tmfifo_cleanup(fifo);
++ return rc;
++}
++
++/* Device remove function. */
++static int mlxbf_tmfifo_remove(struct platform_device *pdev)
++{
++ struct mlxbf_tmfifo *fifo = platform_get_drvdata(pdev);
++
++ mlxbf_tmfifo_cleanup(fifo);
++
++ return 0;
++}
++
++static const struct acpi_device_id mlxbf_tmfifo_acpi_match[] = {
++ { "MLNXBF01", 0 },
++ {}
++};
++MODULE_DEVICE_TABLE(acpi, mlxbf_tmfifo_acpi_match);
++
++static struct platform_driver mlxbf_tmfifo_driver = {
++ .probe = mlxbf_tmfifo_probe,
++ .remove = mlxbf_tmfifo_remove,
++ .driver = {
++ .name = "bf-tmfifo",
++ .acpi_match_table = mlxbf_tmfifo_acpi_match,
++ },
++};
++
++module_platform_driver(mlxbf_tmfifo_driver);
++
++MODULE_DESCRIPTION("Mellanox BlueField SoC TmFifo Driver");
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Mellanox Technologies");
diff --git a/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch b/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch
new file mode 100644
index 0000000000..9ab2d9bb2d
--- /dev/null
+++ b/patches.drivers/platform-mellanox-Add-new-ODM-system-types-to-mlx-pl.patch
@@ -0,0 +1,59 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 7 May 2018 06:48:52 +0000
+Subject: platform/mellanox: Add new ODM system types to mlx-platform
+Patch-mainline: v4.18-rc1
+Git-commit: cbf7ff8cdb03a81ae81680ac133c7b1bf5194001
+References: bsc#1112374
+
+Add new ODM system types, matched according to DMI_BOARD_NAME. The
+supported ODM Ids are: VMOD0001, VMOD0002, VMOD0003, VMOD0004, VMOD0005.
+Patch does not introduce new systems, but allows to ODM companies to set
+DMI_BOARD_VENDOR and DMI_PRODUCT_NAME on their own. It assumes that ODM
+company can't change DMI_BOARD_NAME.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -844,6 +844,36 @@ static struct dmi_system_id mlxplat_dmi_
+ DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
+ },
+ },
++ {
++ .callback = mlxplat_dmi_default_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn21xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn274x_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_msn201x_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
++ },
++ },
++ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
++ },
++ },
+ { }
+ };
+
diff --git a/patches.drivers/platform-x86-asus-wmi-Only-Tell-EC-the-OS-will-handl.patch b/patches.drivers/platform-x86-asus-wmi-Only-Tell-EC-the-OS-will-handl.patch
new file mode 100644
index 0000000000..ec5feedfec
--- /dev/null
+++ b/patches.drivers/platform-x86-asus-wmi-Only-Tell-EC-the-OS-will-handl.patch
@@ -0,0 +1,102 @@
+From 401fee8195d401b2b94dee57383f627050724d5b Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Wed, 12 Jun 2019 09:02:02 +0200
+Subject: [PATCH] platform/x86: asus-wmi: Only Tell EC the OS will handle display hotkeys from asus_nb_wmi
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 401fee8195d401b2b94dee57383f627050724d5b
+Patch-mainline: v5.2-rc5
+References: bsc#1051510
+
+Commit 78f3ac76d9e5 ("platform/x86: asus-wmi: Tell the EC the OS will
+handle the display off hotkey") causes the backlight to be permanently off
+on various EeePC laptop models using the eeepc-wmi driver (Asus EeePC
+1015BX, Asus EeePC 1025C).
+
+The asus_wmi_set_devstate(ASUS_WMI_DEVID_BACKLIGHT, 2, NULL) call added
+by that commit is made conditional in this commit and only enabled in
+the quirk_entry structs in the asus-nb-wmi driver fixing the broken
+display / backlight on various EeePC laptop models.
+
+Cc: João Paulo Rechi Vita <jprvita@endlessm.com>
+Fixes: 78f3ac76d9e5 ("platform/x86: asus-wmi: Tell the EC the OS will handle the display off hotkey")
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/platform/x86/asus-nb-wmi.c | 8 ++++++++
+ drivers/platform/x86/asus-wmi.c | 2 +-
+ drivers/platform/x86/asus-wmi.h | 1 +
+ 3 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/asus-nb-wmi.c
++++ b/drivers/platform/x86/asus-nb-wmi.c
+@@ -78,10 +78,12 @@ static bool asus_q500a_i8042_filter(unsi
+
+ static struct quirk_entry quirk_asus_unknown = {
+ .wapf = 0,
++ .wmi_backlight_set_devstate = true,
+ };
+
+ static struct quirk_entry quirk_asus_q500a = {
+ .i8042_filter = asus_q500a_i8042_filter,
++ .wmi_backlight_set_devstate = true,
+ };
+
+ /*
+@@ -92,26 +94,32 @@ static struct quirk_entry quirk_asus_q50
+ static struct quirk_entry quirk_asus_x55u = {
+ .wapf = 4,
+ .wmi_backlight_power = true,
++ .wmi_backlight_set_devstate = true,
+ .no_display_toggle = true,
+ };
+
+ static struct quirk_entry quirk_asus_wapf4 = {
+ .wapf = 4,
++ .wmi_backlight_set_devstate = true,
+ };
+
+ static struct quirk_entry quirk_asus_x200ca = {
+ .wapf = 2,
++ .wmi_backlight_set_devstate = true,
+ };
+
+ static struct quirk_entry quirk_asus_ux303ub = {
+ .wmi_backlight_native = true,
++ .wmi_backlight_set_devstate = true,
+ };
+
+ static struct quirk_entry quirk_asus_x550lb = {
++ .wmi_backlight_set_devstate = true,
+ .xusb2pr = 0x01D9,
+ };
+
+ static struct quirk_entry quirk_asus_forceals = {
++ .wmi_backlight_set_devstate = true,
+ .wmi_force_als_set = true,
+ };
+
+--- a/drivers/platform/x86/asus-wmi.c
++++ b/drivers/platform/x86/asus-wmi.c
+@@ -2159,7 +2159,7 @@ static int asus_wmi_add(struct platform_
+ err = asus_wmi_backlight_init(asus);
+ if (err && err != -ENODEV)
+ goto fail_backlight;
+- } else
++ } else if (asus->driver->quirks->wmi_backlight_set_devstate)
+ err = asus_wmi_set_devstate(ASUS_WMI_DEVID_BACKLIGHT, 2, NULL);
+
+ status = wmi_install_notify_handler(asus->driver->event_guid,
+--- a/drivers/platform/x86/asus-wmi.h
++++ b/drivers/platform/x86/asus-wmi.h
+@@ -44,6 +44,7 @@ struct quirk_entry {
+ bool store_backlight_power;
+ bool wmi_backlight_power;
+ bool wmi_backlight_native;
++ bool wmi_backlight_set_devstate;
+ bool wmi_force_als_set;
+ int wapf;
+ /*
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch b/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
new file mode 100644
index 0000000000..5a77582824
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-ASIC-hotplug-device-co.patch
@@ -0,0 +1,196 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:00 +0000
+Subject: platform/x86: mlx-platform: Add ASIC hotplug device configuration
+Patch-mainline: v4.19-rc1
+Git-commit: 0404a0b2ca3b88eab1e44b7a1d80c2aeb37fb2f1
+References: bsc#1112374
+
+Add support for ASIC hotplug device events for the all system types. The
+ASIC hotplug event is sent in cases ASIC reaches the good health state or
+dropped to the bad health state. The health state is used to change, when
+device is reset or in case of some system failures. In such cases hwmon
+uevent notification will be sent.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 74 ++++++++++++++++++++++++++++++++++--
+ 1 file changed, 71 insertions(+), 3 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -65,6 +65,8 @@
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
+ #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
++#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
++#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
+ #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
+ #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
+@@ -100,17 +102,21 @@
+ MLXPLAT_CPLD_LPC_PIO_OFFSET)
+
+ /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
++#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
+ #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
+ #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
+ #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
+-#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
++#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
++ MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
+ MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
++#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
+ #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
+-#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc0
++#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
+ #define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
+ #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
++#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
+ #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
+ #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
+@@ -315,6 +321,15 @@ static struct mlxreg_core_data mlxplat_m
+ },
+ };
+
++static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
++ {
++ .label = "asic1",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
++ },
++};
++
+ static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
+ {
+ .data = mlxplat_mlxcpld_default_psu_items_data,
+@@ -343,6 +358,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -351,6 +375,8 @@ struct mlxreg_core_hotplug_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items),
+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+ .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+ };
+
+ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
+@@ -379,6 +405,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 0,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -481,6 +516,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -519,6 +563,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 0,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -616,6 +669,15 @@ static struct mlxreg_core_item mlxplat_m
+ .inversed = 1,
+ .health = false,
+ },
++ {
++ .data = mlxplat_mlxcpld_default_asic_items_data,
++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
++ .inversed = 0,
++ .health = true,
++ },
+ };
+
+ static
+@@ -935,7 +997,7 @@ static struct mlxreg_core_data mlxplat_m
+ {
+ .label = "asic_health",
+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
+- .mask = GENMASK(1, 0),
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
+ .bit = 1,
+ .mode = 0444,
+ },
+@@ -1033,6 +1095,8 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
+@@ -1066,6 +1130,8 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -1112,6 +1178,8 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch b/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch
new file mode 100644
index 0000000000..d51bd0618c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-LED-platform-driver-ac.patch
@@ -0,0 +1,396 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 7 May 2018 06:48:53 +0000
+Subject: platform/x86: mlx-platform: Add LED platform driver activation
+Patch-mainline: v4.18-rc1
+Git-commit: 1189456b1cce36f653622d15c0f38410bf6c37c5
+References: bsc#1112374
+
+Add LED platform driver activation from mlx-platform. This LED driver uses
+the same regmap infrastructure as others Mellanox platform drivers, so LED
+specific registers description is added.
+
+System LED configuration depends on system type. To support all the
+relevant types per system type LED descriptions are defined for passing
+to LED platform driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 259 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 258 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -47,6 +47,11 @@
+ /* LPC bus IO offsets */
+ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
++#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
++#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
++#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
++#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
++#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+@@ -84,6 +89,8 @@
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
+ #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0)
++#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
++#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
+
+ /* Default I2C parent bus number */
+ #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
+@@ -114,11 +121,13 @@
+ * @pdev_i2c - i2c controller platform device
+ * @pdev_mux - array of mux platform devices
+ * @pdev_hotplug - hotplug platform devices
++ * @pdev_led - led platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+ struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
+ struct platform_device *pdev_hotplug;
++ struct platform_device *pdev_led;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -592,9 +601,227 @@ struct mlxreg_core_hotplug_platform_data
+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+ };
+
++/* Platform led default data */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "psu:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_led_data = {
++ .data = mlxplat_mlxcpld_default_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
++};
++
++/* Platform led MSN21xx system family data */
++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "fan:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu1:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "psu2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu2:red",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "uid:blue",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {
++ .data = mlxplat_mlxcpld_msn21xx_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data),
++};
++
++/* Platform led for default data for 200GbE systems */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
++ {
++ .label = "status:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "status:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
++ },
++ {
++ .label = "psu:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "psu:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan1:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan2:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan3:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan4:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan5:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan5:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
++ {
++ .label = "fan6:green",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++ {
++ .label = "fan6:orange",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
++ .data = mlxplat_mlxcpld_default_ng_led_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
++};
++
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+@@ -611,6 +838,11 @@ static bool mlxplat_mlxcpld_writeable_re
+ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+@@ -632,6 +864,11 @@ static bool mlxplat_mlxcpld_readable_reg
+ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+@@ -692,6 +929,7 @@ static struct resource mlxplat_mlxcpld_r
+
+ static struct platform_device *mlxplat_dev;
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
++static struct mlxreg_core_platform_data *mlxplat_led;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -705,6 +943,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_led_data;
+
+ return 1;
+ };
+@@ -721,6 +960,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+
+ return 1;
+ };
+@@ -737,6 +977,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_led_data;
+
+ return 1;
+ };
+@@ -753,6 +994,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_default_ng_led_data;
+
+ return 1;
+ };
+@@ -769,6 +1011,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+
+ return 1;
+ };
+@@ -990,14 +1233,27 @@ static int __init mlxplat_init(void)
+ goto fail_platform_mux_register;
+ }
+
++ /* Add LED driver. */
++ mlxplat_led->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_led = platform_device_register_resndata(
++ &mlxplat_dev->dev, "leds-mlxreg",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_led, sizeof(*mlxplat_led));
++ if (IS_ERR(priv->pdev_led)) {
++ err = PTR_ERR(priv->pdev_led);
++ goto fail_platform_hotplug_register;
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_hotplug_register;
++ goto fail_platform_led_register;
+
+ return 0;
+
++fail_platform_led_register:
++ platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+ platform_device_unregister(priv->pdev_hotplug);
+ fail_platform_mux_register:
+@@ -1016,6 +1272,7 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ platform_device_unregister(priv->pdev_led);
+ platform_device_unregister(priv->pdev_hotplug);
+
+ for (i = ARRAY_SIZE(mlxplat_mux_data) - 1; i >= 0 ; i--)
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch b/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch
new file mode 100644
index 0000000000..1943ca9e9f
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-UID-LED-for-the-next-g.patch
@@ -0,0 +1,36 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:33 +0000
+Subject: platform/x86: mlx-platform: Add UID LED for the next generation
+ systems
+Patch-mainline: v5.1-rc1
+Git-commit: cc2597eb8eeb4634408e206a7374463868805d41
+References: bsc#1112374
+
+Add support for UID LED for the next generation systems MQMB7xx,
+MSN37xx, MSN34xx, MSN38xx.
+
+All these systems support UID LED control through the programmable
+device.
+The UID LED is to be exposed to leds-mlxreg driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -913,6 +913,11 @@ static struct mlxreg_core_data mlxplat_m
+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
+ .bit = BIT(5),
+ },
++ {
++ .label = "uid:blue",
++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
new file mode 100644
index 0000000000..c28060b3ee
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-definitions-for-new-re.patch
@@ -0,0 +1,54 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:54 +0000
+Subject: platform/x86: mlx-platform: Add definitions for new registers
+Patch-mainline: v5.0-rc1
+Git-commit: 59e96ec85e8e59170f6d5cba028e199a2e5dfe67
+References: bsc#1112374
+
+Add definitions for new registers:
+- CPLD3 version - next generation systems are equipped with three CPLD;
+- Two reset cause registers, which store the system reset reason (like
+ system failures, upgrade failures and so on;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -49,7 +49,10 @@
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
++#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+@@ -1208,7 +1211,10 @@ static bool mlxplat_mlxcpld_readable_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+@@ -1258,7 +1264,10 @@ static bool mlxplat_mlxcpld_volatile_reg
+ switch (reg) {
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
new file mode 100644
index 0000000000..624e97f80b
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-extra-CPLD-for-next-ge.patch
@@ -0,0 +1,61 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:32 +0000
+Subject: platform/x86: mlx-platform: Add extra CPLD for next generation
+ systems
+Patch-mainline: v5.1-rc1
+Git-commit: eb480b41f2c5eea72bf9a58dd166409e3b0731f3
+References: bsc#1112374
+
+Add support for CPLD4 for the next generation systems MQMB7xx, MSN37xx,
+MSN34xx, MSN38xx.
+
+All these systems are equipped with four programmable device.
+The version of this new device is to be exposed to sysfs through
+mlxreg-io register.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -25,6 +25,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
+ #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
+ #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
++#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
+ #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
+ #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
+@@ -1140,6 +1141,12 @@ static struct mlxreg_core_data mlxplat_m
+ .mode = 0444,
+ },
+ {
++ .label = "cpld4_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
+ .label = "reset_long_pb",
+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+@@ -1369,6 +1376,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
+@@ -1426,6 +1434,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch
new file mode 100644
index 0000000000..3f075acaf5
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlx-wdt-platform-drive.patch
@@ -0,0 +1,376 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 18 Mar 2019 10:58:23 +0000
+Subject: platform/x86: mlx-platform: Add mlx-wdt platform driver activation
+Patch-mainline: v5.2-rc1
+Git-commit: 9b9f2f5416ef24260c5a5c041ba15b67fd5889b7
+References: bsc#1112374
+
+Add mlx-wdt platform driver activation. Watchdog driver uses the same
+regmap infrastructure as others Mellanox platform drivers. Specific
+registers description for watchdog platform data configuration are
+added to mlx-platform. There are the registers for watchdog timer
+manipulation, and action setting on watchdog timer expiration.
+The watchdog action function could be configured to perform one of the
+following: system reset, setting PWM to full speed or counter
+increment.
+Two types of watchdog devices are supported main and auxiliary.
+These devices are co-exist and each of them could be configured to
+handle the specific action.
+
+Signed-off-by: Michael Shych <michealsh@mellanox.com>
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 221 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 219 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -56,6 +56,16 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
+ #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
+ #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
++#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
++#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
++#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
++#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
++#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
++#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
++#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
++#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
++#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
++#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
+ #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
+ #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
+ #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
+@@ -129,6 +139,18 @@
+ #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
+ #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
+
++/* Masks and default values for watchdogs */
++#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
++#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
++
++#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
++#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
++#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
++#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
++#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
++#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
++#define MLXPLAT_CPLD_WD_MAX_DEVS 2
++
+ /* mlxplat_priv - platform private data
+ * @pdev_i2c - i2c controller platform device
+ * @pdev_mux - array of mux platform devices
+@@ -136,6 +158,7 @@
+ * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
+ * @pdev_fan - FAN platform devices
++ * @pdev_wd - array of watchdog platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+@@ -144,6 +167,7 @@ struct mlxplat_priv {
+ struct platform_device *pdev_led;
+ struct platform_device *pdev_io_regs;
+ struct platform_device *pdev_fan;
++ struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -1351,6 +1375,148 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
+ };
+
++/* Watchdog type1: hardware implementation version1
++ * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
++ */
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .bit = 6,
++ },
++};
++
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
++ .bit = 1,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
++ {
++ .data = mlxplat_mlxcpld_wd_main_regs_type1,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
++ .version = MLX_WDT_TYPE1,
++ .identity = "mlx-wdt-main",
++ },
++ {
++ .data = mlxplat_mlxcpld_wd_aux_regs_type1,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
++ .version = MLX_WDT_TYPE1,
++ .identity = "mlx-wdt-aux",
++ },
++};
++
++/* Watchdog type2: hardware implementation version 2
++ * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
++ */
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "timeleft",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
++ .bit = 0,
++ },
++ {
++ .label = "reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .bit = 6,
++ },
++};
++
++static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
++ {
++ .label = "action",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++ {
++ .label = "timeout",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
++ },
++ {
++ .label = "timeleft",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
++ },
++ {
++ .label = "ping",
++ .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
++ .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
++ .bit = 4,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
++ {
++ .data = mlxplat_mlxcpld_wd_main_regs_type2,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
++ .version = MLX_WDT_TYPE2,
++ .identity = "mlx-wdt-main",
++ },
++ {
++ .data = mlxplat_mlxcpld_wd_aux_regs_type2,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
++ .version = MLX_WDT_TYPE2,
++ .identity = "mlx-wdt-aux",
++ },
++};
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -1373,6 +1539,14 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+@@ -1416,6 +1590,16 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
+@@ -1473,6 +1657,10 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
+@@ -1500,6 +1688,7 @@ static const struct reg_default mlxplat_
+ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
+ };
+
+ struct mlxplat_mlxcpld_regmap_context {
+@@ -1549,6 +1738,8 @@ static struct mlxreg_core_hotplug_platfo
+ static struct mlxreg_core_platform_data *mlxplat_led;
+ static struct mlxreg_core_platform_data *mlxplat_regs_io;
+ static struct mlxreg_core_platform_data *mlxplat_fan;
++static struct mlxreg_core_platform_data
++ *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -1564,6 +1755,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+ mlxplat_regs_io = &mlxplat_default_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1582,6 +1774,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1600,6 +1793,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1618,6 +1812,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
++ mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
+
+ return 1;
+ };
+@@ -1637,6 +1832,8 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_led = &mlxplat_default_ng_led_data;
+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
+
+ return 1;
+ };
+@@ -1919,15 +2116,33 @@ static int __init mlxplat_init(void)
+ }
+ }
+
++ /* Add WD drivers. */
++ for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
++ if (mlxplat_wd_data[j]) {
++ mlxplat_wd_data[j]->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_wd[j] = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlx-wdt",
++ j, NULL, 0,
++ mlxplat_wd_data[j],
++ sizeof(*mlxplat_wd_data[j]));
++ if (IS_ERR(priv->pdev_wd[j])) {
++ err = PTR_ERR(priv->pdev_wd[j]);
++ goto fail_platform_wd_register;
++ }
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_fan_register;
++ goto fail_platform_wd_register;
+
+ return 0;
+
+-fail_platform_fan_register:
++fail_platform_wd_register:
++ while (--j >= 0)
++ platform_device_unregister(priv->pdev_wd[j]);
+ if (mlxplat_fan)
+ platform_device_unregister(priv->pdev_fan);
+ fail_platform_io_regs_register:
+@@ -1953,6 +2168,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
++ platform_device_unregister(priv->pdev_wd[i]);
+ if (priv->pdev_fan)
+ platform_device_unregister(priv->pdev_fan);
+ if (priv->pdev_io_regs)
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch
new file mode 100644
index 0000000000..fdfb1f8187
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-fan-platform-dr.patch
@@ -0,0 +1,270 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:40:57 +0000
+Subject: platform/x86: mlx-platform: Add mlxreg-fan platform driver activation
+Patch-mainline: v4.19-rc1
+Git-commit: 0378123c580091b4c2972a6e4fcb3dcb4686667a
+References: bsc#1112374
+
+Add mlxreg-fan platform driver activation. FAN driver uses the same regmap
+infrastructure as others Mellanox platform drivers. Specific registers
+description for default FAN platform data configuration are added to
+mlx-platform. There are the registers for tachometers reading, PWM
+control and FAN ownership control. The last one has a default value,
+which is set at initialization time through the regmap infrastructure,
+which is necessary for moving FAN control ownership from hardware to
+software.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 144 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 143 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -59,6 +59,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
+ #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
+ #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
++#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+@@ -73,9 +74,23 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
+ #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
+ #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
++#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
++#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
++#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
++#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6
++#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
++#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
++#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
++#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xea
++#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xeb
++#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xec
++#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xed
++#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xee
++#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xef
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
++
+ #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
+ #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
+ MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
+@@ -131,6 +146,7 @@
+ * @pdev_hotplug - hotplug platform devices
+ * @pdev_led - led platform devices
+ * @pdev_io_regs - register access platform devices
++ * @pdev_fan - FAN platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+@@ -138,6 +154,7 @@ struct mlxplat_priv {
+ struct platform_device *pdev_hotplug;
+ struct platform_device *pdev_led;
+ struct platform_device *pdev_io_regs;
++ struct platform_device *pdev_fan;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -929,6 +946,79 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
++/* Platform FAN default */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
++ {
++ .label = "pwm1",
++ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
++ },
++ {
++ .label = "tacho1",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho2",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho3",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho4",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho5",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho6",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho7",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho8",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho9",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho10",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho11",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++ {
++ .label = "tacho12",
++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
++ .mask = GENMASK(7, 0),
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
++ .data = mlxplat_mlxcpld_default_fan_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
++};
++
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -949,6 +1039,8 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -983,6 +1075,20 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1015,6 +1121,20 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1023,6 +1143,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
+ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
+ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
+ };
+
+ struct mlxplat_mlxcpld_regmap_context {
+@@ -1071,6 +1192,7 @@ static struct platform_device *mlxplat_d
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
+ static struct mlxreg_core_platform_data *mlxplat_led;
+ static struct mlxreg_core_platform_data *mlxplat_regs_io;
++static struct mlxreg_core_platform_data *mlxplat_fan;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -1155,6 +1277,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
+ };
+@@ -1410,14 +1533,31 @@ static int __init mlxplat_init(void)
+ }
+ }
+
++ /* Add FAN driver. */
++ if (mlxplat_fan) {
++ mlxplat_fan->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_fan = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlxreg-fan",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_fan,
++ sizeof(*mlxplat_fan));
++ if (IS_ERR(priv->pdev_io_regs)) {
++ err = PTR_ERR(priv->pdev_io_regs);
++ goto fail_platform_io_regs_register;
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_io_regs_register;
++ goto fail_platform_fan_register;
+
+ return 0;
+
++fail_platform_fan_register:
++ if (mlxplat_fan)
++ platform_device_unregister(priv->pdev_fan);
+ fail_platform_io_regs_register:
+ if (mlxplat_regs_io)
+ platform_device_unregister(priv->pdev_io_regs);
+@@ -1441,6 +1581,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ if (priv->pdev_fan)
++ platform_device_unregister(priv->pdev_fan);
+ if (priv->pdev_io_regs)
+ platform_device_unregister(priv->pdev_io_regs);
+ platform_device_unregister(priv->pdev_led);
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
new file mode 100644
index 0000000000..f5ed364ac1
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-mlxreg-io-platform-dri.patch
@@ -0,0 +1,350 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Sun, 17 Jun 2018 16:56:54 +0000
+Subject: platform/x86: mlx-platform: Add mlxreg-io platform driver activation
+Patch-mainline: v4.19-rc1
+Git-commit: 8871f5e4234112f02b8afe1000c18f49827c8d01
+References: bsc#1112374
+
+Add mlxreg-io platform driver activation. Access driver uses the same
+regmap infrastructure as others Mellanox platform drivers.
+Specific registers description for default platform data configuration are
+added to mlx-platform. There are the registers for resets control, reset
+causes monitoring, programmable devices version reading and mux select
+control. This platform data is passed to mlxreg-io driver. Also some
+default values for the register are set at initialization time through
+the regmap infrastructure, which are necessary for moving write protection
+from the general purpose registers, which are used by mlxreg-io for
+write access.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+v4-v5:
+ Changes added by Vadim:
+ - Add two new attributes for ASIC health and main power domain shutdown.
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 175 +++++++++++++++++++++++++++++++++++-
+ 1 file changed, 173 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -47,15 +47,23 @@
+ /* LPC bus IO offsets */
+ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+ #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
++#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
++#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
++#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
+ #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
+ #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+ #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
+ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
++#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
++#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
++#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
++#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
+ #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
+ #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
++#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
+ #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
+ #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
+ #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
+@@ -122,12 +130,14 @@
+ * @pdev_mux - array of mux platform devices
+ * @pdev_hotplug - hotplug platform devices
+ * @pdev_led - led platform devices
++ * @pdev_io_regs - register access platform devices
+ */
+ struct mlxplat_priv {
+ struct platform_device *pdev_i2c;
+ struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
+ struct platform_device *pdev_hotplug;
+ struct platform_device *pdev_led;
++ struct platform_device *pdev_io_regs;
+ };
+
+ /* Regions for LPC I2C controller and LPC base register space */
+@@ -813,6 +823,111 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
+ };
+
++/* Platform register access default */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_fw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_wd",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "select_iio",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = GENMASK(1, 0),
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
++};
+
+ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
+ {
+@@ -822,6 +937,10 @@ static bool mlxplat_mlxcpld_writeable_re
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+@@ -838,15 +957,23 @@ static bool mlxplat_mlxcpld_writeable_re
+ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -864,15 +991,21 @@ static bool mlxplat_mlxcpld_readable_reg
+ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
+@@ -887,6 +1020,11 @@ static bool mlxplat_mlxcpld_volatile_reg
+ return false;
+ }
+
++static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
++ { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
++ { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
++};
++
+ struct mlxplat_mlxcpld_regmap_context {
+ void __iomem *base;
+ };
+@@ -919,6 +1057,8 @@ static const struct regmap_config mlxpla
+ .writeable_reg = mlxplat_mlxcpld_writeable_reg,
+ .readable_reg = mlxplat_mlxcpld_readable_reg,
+ .volatile_reg = mlxplat_mlxcpld_volatile_reg,
++ .reg_defaults = mlxplat_mlxcpld_regmap_default,
++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
+ .reg_read = mlxplat_mlxcpld_reg_read,
+ .reg_write = mlxplat_mlxcpld_reg_write,
+ };
+@@ -930,6 +1070,7 @@ static struct resource mlxplat_mlxcpld_r
+ static struct platform_device *mlxplat_dev;
+ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
+ static struct mlxreg_core_platform_data *mlxplat_led;
++static struct mlxreg_core_platform_data *mlxplat_regs_io;
+
+ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
+ {
+@@ -944,6 +1085,7 @@ static int __init mlxplat_dmi_default_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -978,6 +1120,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
++ mlxplat_regs_io = &mlxplat_default_regs_io_data;
+
+ return 1;
+ };
+@@ -1163,7 +1306,7 @@ static int mlxplat_mlxcpld_verify_bus_to
+ static int __init mlxplat_init(void)
+ {
+ struct mlxplat_priv *priv;
+- int i, nr, err;
++ int i, j, nr, err;
+
+ if (!dmi_check_system(mlxplat_dmi_table))
+ return -ENODEV;
+@@ -1233,6 +1376,15 @@ static int __init mlxplat_init(void)
+ goto fail_platform_mux_register;
+ }
+
++ /* Set default registers. */
++ for (j = 0; j < mlxplat_mlxcpld_regmap_config.num_reg_defaults; j++) {
++ err = regmap_write(mlxplat_hotplug->regmap,
++ mlxplat_mlxcpld_regmap_default[j].reg,
++ mlxplat_mlxcpld_regmap_default[j].def);
++ if (err)
++ goto fail_platform_mux_register;
++ }
++
+ /* Add LED driver. */
+ mlxplat_led->regmap = mlxplat_hotplug->regmap;
+ priv->pdev_led = platform_device_register_resndata(
+@@ -1244,14 +1396,31 @@ static int __init mlxplat_init(void)
+ goto fail_platform_hotplug_register;
+ }
+
++ /* Add registers io access driver. */
++ if (mlxplat_regs_io) {
++ mlxplat_regs_io->regmap = mlxplat_hotplug->regmap;
++ priv->pdev_io_regs = platform_device_register_resndata(
++ &mlxplat_dev->dev, "mlxreg-io",
++ PLATFORM_DEVID_NONE, NULL, 0,
++ mlxplat_regs_io,
++ sizeof(*mlxplat_regs_io));
++ if (IS_ERR(priv->pdev_io_regs)) {
++ err = PTR_ERR(priv->pdev_io_regs);
++ goto fail_platform_led_register;
++ }
++ }
++
+ /* Sync registers with hardware. */
+ regcache_mark_dirty(mlxplat_hotplug->regmap);
+ err = regcache_sync(mlxplat_hotplug->regmap);
+ if (err)
+- goto fail_platform_led_register;
++ goto fail_platform_io_regs_register;
+
+ return 0;
+
++fail_platform_io_regs_register:
++ if (mlxplat_regs_io)
++ platform_device_unregister(priv->pdev_io_regs);
+ fail_platform_led_register:
+ platform_device_unregister(priv->pdev_led);
+ fail_platform_hotplug_register:
+@@ -1272,6 +1441,8 @@ static void __exit mlxplat_exit(void)
+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
+ int i;
+
++ if (priv->pdev_io_regs)
++ platform_device_unregister(priv->pdev_io_regs);
+ platform_device_unregister(priv->pdev_led);
+ platform_device_unregister(priv->pdev_hotplug);
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
new file mode 100644
index 0000000000..7aed8cd9d0
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-capabi.patch
@@ -0,0 +1,315 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:15 +0000
+Subject: platform/x86: mlx-platform: Add support for fan capability registers
+Patch-mainline: v5.1-rc1
+Git-commit: 83cdb2c11173ee4aa621c8cce6e1c33fb564d2be
+References: bsc#1112374
+
+Provide support for the fan capability registers for the next generation
+systems of types MQM87xx, MSN34xx, MSN37xx. These new registers provide
+configuration for tachometers and fan drawers connectivity. Use these
+registers for next generation led, fan and hotplug structures in order
+to distinguish between the systems which have minor configuration
+differences. This reduces the amount of code used to describe such
+systems.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/mellanox/mlxreg-hotplug.c | 23 +++++++++
+ drivers/platform/x86/mlx-platform.c | 69 +++++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/mellanox/mlxreg-hotplug.c
++++ b/drivers/platform/mellanox/mlxreg-hotplug.c
+@@ -494,7 +494,9 @@ static int mlxreg_hotplug_set_irq(struct
+ {
+ struct mlxreg_core_hotplug_platform_data *pdata;
+ struct mlxreg_core_item *item;
+- int i, ret;
++ struct mlxreg_core_data *data;
++ u32 regval;
++ int i, j, ret;
+
+ pdata = dev_get_platdata(&priv->pdev->dev);
+ item = pdata->items;
+@@ -506,6 +508,25 @@ static int mlxreg_hotplug_set_irq(struct
+ if (ret)
+ goto out;
+
++ /*
++ * Verify if hardware configuration requires to disable
++ * interrupt capability for some of components.
++ */
++ data = item->data;
++ for (j = 0; j < item->count; j++, data++) {
++ /* Verify if the attribute has capability register. */
++ if (data->capability) {
++ /* Read capability register. */
++ ret = regmap_read(priv->regmap,
++ data->capability, &regval);
++ if (ret)
++ goto out;
++
++ if (!(regval & data->bit))
++ item->mask &= ~BIT(j);
++ }
++ }
++
+ /* Set group initial status as mask and unmask group event. */
+ if (item->inversed) {
+ item->cache = item->mask;
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -68,6 +68,9 @@
+ #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
+ #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
+ #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
++#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
++#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
+@@ -585,36 +588,48 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan2",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(1),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan3",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(2),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan4",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(3),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan5",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(4),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ {
+ .label = "fan6",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+ .mask = BIT(5),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+ },
+ };
+@@ -817,61 +832,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan1:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan1:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "fan2:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan2:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "fan3:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan3:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "fan4:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan4:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "fan5:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan5:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "fan6:green",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "fan6:orange",
+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
++ .bit = BIT(5),
+ },
+ };
+
+@@ -1208,61 +1247,85 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "tacho1",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho2",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho3",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho4",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(3),
+ },
+ {
+ .label = "tacho5",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(4),
+ },
+ {
+ .label = "tacho6",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(5),
+ },
+ {
+ .label = "tacho7",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(6),
+ },
+ {
+ .label = "tacho8",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
++ .bit = BIT(7),
+ },
+ {
+ .label = "tacho9",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(0),
+ },
+ {
+ .label = "tacho10",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(1),
+ },
+ {
+ .label = "tacho11",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(2),
+ },
+ {
+ .label = "tacho12",
+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
+ .mask = GENMASK(7, 0),
++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
++ .bit = BIT(3),
+ },
+ };
+
+@@ -1349,6 +1412,9 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1401,6 +1467,9 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
+ return true;
+ }
+ return false;
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
new file mode 100644
index 0000000000..67ee8f53f2
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-fan-direct.patch
@@ -0,0 +1,59 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:11 +0000
+Subject: platform/x86: mlx-platform: Add support for fan direction register
+Patch-mainline: v5.1-rc1
+Git-commit: aff475804f608c5375dc1c5df6f0fdeb63459ccb
+References: bsc#1112374
+
+Provide support for the fan direction register.
+This register shows configuration for system fans direction, which could
+be forward or reversed.
+For forward direction - relevant bit is set 0;
+For reversed direction - relevant bit is set 1.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -33,6 +33,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
+ #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
+ #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
++#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
+ #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
+ #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
+ #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
+@@ -1184,6 +1185,12 @@ static struct mlxreg_core_data mlxplat_m
+ .bit = 1,
+ .mode = 0444,
+ },
++ {
++ .label = "fan_dir",
++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
++ .bit = GENMASK(7, 0),
++ .mode = 0200,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
+@@ -1307,6 +1314,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
+ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+@@ -1360,6 +1368,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
+ case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch
new file mode 100644
index 0000000000..ccf1abfcf7
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-new-VMOD00.patch
@@ -0,0 +1,46 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:16 +0000
+Subject: platform/x86: mlx-platform: Add support for new VMOD0007 board name
+Patch-mainline: v5.1-rc1
+Git-commit: e7706a4359f0f172b5f2ab6807f421145041c393
+References: bsc#1112374
+
+Add support for new Mellanox system type MSN3700C, which is
+a cost reduced flavor of the MSN37 system class.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1692,6 +1692,13 @@ static struct dmi_system_id mlxplat_dmi_
+ },
+ },
+ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
++ },
++ },
++ {
+ .callback = mlxplat_dmi_default_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
+@@ -1721,6 +1728,12 @@ static struct dmi_system_id mlxplat_dmi_
+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
+ },
+ },
++ {
++ .callback = mlxplat_dmi_qmb7xx_matched,
++ .matches = {
++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
++ },
++ },
+ { }
+ };
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch b/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch
new file mode 100644
index 0000000000..21dfc3fb4d
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Add-support-for-tachometer.patch
@@ -0,0 +1,57 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Mon, 18 Mar 2019 10:58:22 +0000
+Subject: platform/x86: mlx-platform: Add support for tachometer speed register
+Patch-mainline: v5.2-rc1
+Git-commit: 584814af9f8ca07cd38e5c554ddd10e85c4e2053
+References: bsc#1112374
+
+Add support for tachometer speed register for the next generation
+systems MQMB7xx, MSN37xx, MSN34xx, MSN38xx.
+
+All these systems support tachometer speed capability register.
+This register is to be provided mlxreg-fan driver.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -72,6 +72,7 @@
+ #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
+ #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
+ #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
++#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
+@@ -1339,6 +1340,10 @@ static struct mlxreg_core_data mlxplat_m
+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
+ .bit = BIT(3),
+ },
++ {
++ .label = "conf",
++ .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
++ },
+ };
+
+ static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
+@@ -1428,6 +1433,7 @@ static bool mlxplat_mlxcpld_readable_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
+ return true;
+ }
+ return false;
+@@ -1484,6 +1490,7 @@ static bool mlxplat_mlxcpld_volatile_reg
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
+ case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
++ case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
+ return true;
+ }
+ return false;
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
new file mode 100644
index 0000000000..8b2d814b83
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act-e2883859.patch
@@ -0,0 +1,151 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:58 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for new
+ systems
+Patch-mainline: v5.0-rc1
+Git-commit: e2883859dd0b4ee6fc70151e417fed8680efaa4b
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for the next generation
+systems, in particular for MQM87xx, MSN34xx, MSN37xx types, which have:
+- extended reset causes bits related to ComEx reset, voltage devices
+ firmware upgrade, system platform reset;
+- additional CPLD device;
+- JTAG select capability;
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 113 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 113 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1104,6 +1104,118 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
+ };
+
++/* Platform register access for next generation systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld3_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_from_comex",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(7),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_comex_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_voltmon_upgrade_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_system",
++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "jtag_enable",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0644,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
++ .data = mlxplat_mlxcpld_default_ng_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1449,6 +1561,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
diff --git a/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
new file mode 100644
index 0000000000..5ce8b1dc81
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Allow-mlxreg-io-driver-act.patch
@@ -0,0 +1,138 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:01 +0000
+Subject: platform/x86: mlx-platform: Allow mlxreg-io driver activation for
+ more systems
+Patch-mainline: v4.19-rc1
+Git-commit: 2ac24d336c95fb2525574d4fd46f0673d27464e7
+References: bsc#1112374
+
+Allow mlxreg-io platform driver activation for more system types, in
+particular for MSN21xx, MSN201x types, which have reset causes bits
+slightly different from the default configuration.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 96 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1008,6 +1008,100 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
++/* Platform register access MSN21xx, MSN201x systems families data */
++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
++ {
++ .label = "cpld1_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "cpld2_version",
++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
++ .bit = GENMASK(7, 0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_long_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_short_pb",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_aux_pwr_or_ref",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_sw_reset",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_main_pwr_fail",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(4),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_asic_thermal",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(5),
++ .mode = 0444,
++ },
++ {
++ .label = "reset_hotswap_or_halt",
++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(6),
++ .mode = 0444,
++ },
++ {
++ .label = "psu1_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(0),
++ .mode = 0200,
++ },
++ {
++ .label = "psu2_on",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(1),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_cycle",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(2),
++ .mode = 0200,
++ },
++ {
++ .label = "pwr_down",
++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
++ .mask = GENMASK(7, 0) & ~BIT(3),
++ .mode = 0200,
++ },
++ {
++ .label = "asic_health",
++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
++ .mask = MLXPLAT_CPLD_ASIC_MASK,
++ .bit = 1,
++ .mode = 0444,
++ },
++};
++
++static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
++ .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
++};
++
+ /* Platform FAN default */
+ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
+ {
+@@ -1293,6 +1387,7 @@ static int __init mlxplat_dmi_msn21xx_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
+@@ -1328,6 +1423,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
diff --git a/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch b/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch
new file mode 100644
index 0000000000..45973731be
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Change-mlxreg-io-configura.patch
@@ -0,0 +1,38 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:03 +0000
+Subject: platform/x86: mlx-platform: Change mlxreg-io configuration for
+ MSN274x systems
+Patch-mainline: v4.19-rc1
+Git-commit: da80c7aece1619c2c299432d3d498885ca6d757b
+References: bsc#1112374
+
+Change mlxreg-io platform driver configuration for MSN274x system types
+from the default to MSN21xx.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1008,7 +1008,7 @@ static struct mlxreg_core_platform_data
+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
+ };
+
+-/* Platform register access MSN21xx, MSN201x systems families data */
++/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */
+ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
+ {
+ .label = "cpld1_version",
+@@ -1405,7 +1405,7 @@ static int __init mlxplat_dmi_msn274x_ma
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+ mlxplat_led = &mlxplat_default_led_data;
+- mlxplat_regs_io = &mlxplat_default_regs_io_data;
++ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+ };
diff --git a/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch b/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch
new file mode 100644
index 0000000000..77ea7f90d4
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Convert-to-use-SPDX-identi.patch
@@ -0,0 +1,57 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:27:00 +0000
+Subject: platform/x86: mlx-platform: Convert to use SPDX identifier
+Patch-mainline: v5.0-rc1
+Git-commit: fb7255a923115188ac134bb562d1c44f4f3a413b
+References: bsc#1112374
+
+Reduce size of duplicated comments by switching to use SPDX identifier.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 33 ++++-----------------------------
+ 1 file changed, 4 insertions(+), 29 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1,34 +1,9 @@
++// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+ /*
+- * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
+- * Copyright (c) 2016 Vadim Pasternak <vadimp@mellanox.com>
++ * Mellanox platform driver
+ *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *
+- * 1. Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * 2. Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * 3. Neither the names of the copyright holders nor the names of its
+- * contributors may be used to endorse or promote products derived from
+- * this software without specific prior written permission.
+- *
+- * Alternatively, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") version 2 as published by the Free
+- * Software Foundation.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
++ * Copyright (C) 2016-2018 Mellanox Technologies
++ * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
+ */
+
+ #include <linux/device.h>
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch b/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
new file mode 100644
index 0000000000..61ac2a89be
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-LED-configuration.patch
@@ -0,0 +1,43 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:57 +0000
+Subject: platform/x86: mlx-platform: Fix LED configuration
+Patch-mainline: v5.0-rc1
+Git-commit: 440f343df1996302d9a3904647ff11b689bf27bc
+References: bsc#1112374
+
+Exchange LED configuration between msn201x and next generation systems
+types.
+
+Bug was introduced when LED driver activation was added to mlx-platform.
+LED configuration for the three new system MQMB7, MSN37, MSN34 was
+assigned to MSN21 and vice versa. This bug affects MSN21 only and
+likely requires backport to v4.19.
+
+Fixes: 1189456b1cce ("platform/x86: mlx-platform: Add LED platform driver activation")
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1430,7 +1430,7 @@ static int __init mlxplat_dmi_msn201x_ma
+ mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+- mlxplat_led = &mlxplat_default_ng_led_data;
++ mlxplat_led = &mlxplat_msn21xx_led_data;
+ mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
+
+ return 1;
+@@ -1448,7 +1448,7 @@ static int __init mlxplat_dmi_qmb7xx_mat
+ mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
+ mlxplat_hotplug->deferred_nr =
+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
+- mlxplat_led = &mlxplat_msn21xx_led_data;
++ mlxplat_led = &mlxplat_default_ng_led_data;
+ mlxplat_fan = &mlxplat_default_fan_data;
+
+ return 1;
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch b/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch
new file mode 100644
index 0000000000..31a1e919bd
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-access-mode-for-fan_di.patch
@@ -0,0 +1,32 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Tue, 26 Feb 2019 08:20:34 +0000
+Subject: platform/x86: mlx-platform: Fix access mode for fan_dir attribute
+Patch-mainline: v5.1-rc1
+Git-commit: 3ba29326b894e512db9ea7aaa7cb17b235f75d1b
+References: bsc#1112374
+
+Fix access mode for "fan_dir" attribute from "write only" to
+"read only". This attribute is exposed to leds-mlxreg driver.
+The purpose of this attribute is to provide information about FAN
+direction setting on the system (forward or backward).
+It is relevant for the next generation systems MQMB7xx, MSN37xx,
+MSN34xx, MSN38xx.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1240,7 +1240,7 @@ static struct mlxreg_core_data mlxplat_m
+ .label = "fan_dir",
+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
+ .bit = GENMASK(7, 0),
+- .mode = 0200,
++ .mode = 0444,
+ },
+ };
+
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch b/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch
new file mode 100644
index 0000000000..ba9ff3ec8c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-copy-paste-error-in-ml.patch
@@ -0,0 +1,32 @@
+From: Wei Yongjun <weiyongjun1@huawei.com>
+Date: Wed, 8 Aug 2018 04:00:30 +0000
+Subject: platform/x86: mlx-platform: Fix copy-paste error in mlxplat_init()
+Patch-mainline: v4.19-rc1
+Git-commit: 207da7128a6d61a1ce3d052b3dfb10d237af6078
+References: bsc#1112374
+
+The return value from platform_device_register_resndata() is not checked
+correctly. The test is done against a wrong variable. This patch fix it.
+
+Fixes: 0378123c5800 ("platform/x86: mlx-platform: Add mlxreg-fan platform driver activation")
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Acked-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1704,8 +1704,8 @@ static int __init mlxplat_init(void)
+ PLATFORM_DEVID_NONE, NULL, 0,
+ mlxplat_fan,
+ sizeof(*mlxplat_fan));
+- if (IS_ERR(priv->pdev_io_regs)) {
+- err = PTR_ERR(priv->pdev_io_regs);
++ if (IS_ERR(priv->pdev_fan)) {
++ err = PTR_ERR(priv->pdev_fan);
+ goto fail_platform_io_regs_register;
+ }
+ }
diff --git a/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch b/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
new file mode 100644
index 0000000000..8a35b4721c
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Fix-tachometer-registers.patch
@@ -0,0 +1,47 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:56 +0000
+Subject: platform/x86: mlx-platform: Fix tachometer registers
+Patch-mainline: v5.0-rc1
+Git-commit: edd45cba5ed7f53974475ddc9a1453c2c87b3328
+References: bsc#1112374
+
+Shift by one the registers for tachometers (7 - 12).
+
+This fix is relevant for the same new systems MQMB7, MSN37, MSN34,
+which are about to be released to the customers.
+At the moment, none of them is at customers sites. The customers will
+not suffer from this change.
+This fix is necessary, because register used before for tachometer 7
+has been than reserved for the second PWM for newer systems, which are
+not supported yet in mlx-platform driver. So registers of tachometers
+7-12 have been shifted by one.
+
+Fixes: 0378123c5800 ("platform/x86: mlx-platform: Add mlxreg-fan platform driver activation")
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -86,12 +86,12 @@
+ #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
+ #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
+ #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
+-#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xea
+-#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xeb
+-#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xec
+-#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xed
+-#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xee
+-#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xef
++#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb
++#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec
++#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed
++#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
++#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
++#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
+ #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
+ #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
+ #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
diff --git a/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch b/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch
new file mode 100644
index 0000000000..ea1fbb6fb3
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Remove-unused-define.patch
@@ -0,0 +1,26 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 26 Jul 2018 22:41:04 +0000
+Subject: platform/x86: mlx-platform: Remove unused define
+Patch-mainline: v4.19-rc1
+Git-commit: 0b4e30f49aa44725cbaefa6e839bd82a768c385a
+References: bsc#1112374
+
+Remove unused define MLXPLAT_CPLD_AGGR_MASK_MSN21XX.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -112,7 +112,6 @@
+ #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
+ #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
+ #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
+-#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
+ #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
+ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
diff --git a/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch b/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
new file mode 100644
index 0000000000..926797f441
--- /dev/null
+++ b/patches.drivers/platform-x86-mlx-platform-Rename-new-systems-product.patch
@@ -0,0 +1,49 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Thu, 15 Nov 2018 17:26:55 +0000
+Subject: platform/x86: mlx-platform: Rename new systems product names
+Patch-mainline: v5.0-rc1
+Git-commit: 3752e5c764b4fb1abe43c78f635bf019c8e98db2
+References: bsc#1112374
+
+Rename product names for next generation systems QMB7, SN37, SN34 to
+respectively MQMB7, MSN37, MSN34.
+
+All these systems are about to be released to the customers.
+At the moment, none of them is at customers sites. The customers will
+not suffer from this change.
+The names have been changed due to marketing decision.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/platform/x86/mlx-platform.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/platform/x86/mlx-platform.c
++++ b/drivers/platform/x86/mlx-platform.c
+@@ -1508,21 +1508,21 @@ static struct dmi_system_id mlxplat_dmi_
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "QMB7"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
+ },
+ },
+ {
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "SN37"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
+ },
+ },
+ {
+ .callback = mlxplat_dmi_qmb7xx_matched,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+- DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
+ },
+ },
+ {
diff --git a/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch b/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
new file mode 100644
index 0000000000..585d85d1f3
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-Add-capability-field-to-core-pl.patch
@@ -0,0 +1,36 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:14 +0000
+Subject: platform_data/mlxreg: Add capability field to core platform data
+Patch-mainline: v5.1-rc1
+Git-commit: 946e4e02b11889cb161b15ff4712a8ba21a50eb6
+References: bsc#1112374
+
+Add capability field to "mlxreg_core_platform_data" structure.
+The purpose of this register is to provide additional info to platform
+driver through the atribute related capability register.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -61,6 +61,7 @@ struct mlxreg_hotplug_device {
+ * @reg: attribute register;
+ * @mask: attribute access mask;
+ * @bit: attribute effective bit;
++ * @capability: attribute capability register;
+ * @mode: access mode;
+ * @np - pointer to node platform associated with attribute;
+ * @hpdev - hotplug device data;
+@@ -72,6 +73,7 @@ struct mlxreg_core_data {
+ u32 reg;
+ u32 mask;
+ u32 bit;
++ u32 capability;
+ umode_t mode;
+ struct device_node *np;
+ struct mlxreg_hotplug_device hpdev;
diff --git a/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch b/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
new file mode 100644
index 0000000000..a69295d188
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-Document-fixes-for-core-platfor.patch
@@ -0,0 +1,31 @@
+From: Vadim Pasternak <vadimp@mellanox.com>
+Date: Wed, 12 Dec 2018 23:59:13 +0000
+Subject: platform_data/mlxreg: Document fixes for core platform data
+Patch-mainline: v5.1-rc1
+Git-commit: 9b28aa1d0eae1be1016c8f4ba504545caff01da3
+References: bsc#1112374
+
+Remove "led" from the description, since the structure
+"mlxreg_core_platform_data" is used not only for led data.
+
+Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
+Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -107,9 +107,9 @@ struct mlxreg_core_item {
+ /**
+ * struct mlxreg_core_platform_data - platform data:
+ *
+- * @led_data: led private data;
++ * @data: instance private data;
+ * @regmap: register map of parent device;
+- * @counter: number of led instances;
++ * @counter: number of instances;
+ */
+ struct mlxreg_core_platform_data {
+ struct mlxreg_core_data *data;
diff --git a/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch b/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch
new file mode 100644
index 0000000000..820917743e
--- /dev/null
+++ b/patches.drivers/platform_data-mlxreg-additions-for-Mellanox-watchdog.patch
@@ -0,0 +1,63 @@
+From: Michael Shych <michaelsh@mellanox.com>
+Date: Wed, 20 Feb 2019 09:34:22 +0000
+Subject: platform_data/mlxreg: additions for Mellanox watchdog driver.
+Patch-mainline: v5.1-rc1
+Git-commit: 9f03161a1bd8cd9ccf11533e52326718c656036e
+References: bsc#1112374
+
+There are two new fields added to mlxreg core structure:
+features - supported features of device and
+identity - device identity name.
+Add new defines for watchdog features.
+
+Signed-off-by: Michael Shych <michaelsh@mellanox.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ include/linux/platform_data/mlxreg.h | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+--- a/include/linux/platform_data/mlxreg.h
++++ b/include/linux/platform_data/mlxreg.h
+@@ -35,6 +35,19 @@
+ #define __LINUX_PLATFORM_DATA_MLXREG_H
+
+ #define MLXREG_CORE_LABEL_MAX_SIZE 32
++#define MLXREG_CORE_WD_FEATURE_NOWAYOUT BIT(0)
++#define MLXREG_CORE_WD_FEATURE_START_AT_BOOT BIT(1)
++
++/**
++ * enum mlxreg_wdt_type - type of HW watchdog
++ *
++ * TYPE1 HW watchdog implementation exist in old systems.
++ * All new systems have TYPE2 HW watchdog.
++ */
++enum mlxreg_wdt_type {
++ MLX_WDT_TYPE1,
++ MLX_WDT_TYPE2,
++};
+
+ /**
+ * struct mlxreg_hotplug_device - I2C device data:
+@@ -111,12 +124,18 @@ struct mlxreg_core_item {
+ *
+ * @data: instance private data;
+ * @regmap: register map of parent device;
+- * @counter: number of instances;
++ * @counter: number of led instances;
++ * @features: supported features of device;
++ * @version: implementation version;
++ * @identity: device identity name;
+ */
+ struct mlxreg_core_platform_data {
+ struct mlxreg_core_data *data;
+ void *regmap;
+ int counter;
++ u32 features;
++ u32 version;
++ char identity[MLXREG_CORE_LABEL_MAX_SIZE];
+ };
+
+ /**
diff --git a/patches.drivers/qmi_wwan-add-network-device-usage-statistics-for-qmi.patch b/patches.drivers/qmi_wwan-add-network-device-usage-statistics-for-qmi.patch
new file mode 100644
index 0000000000..cf1c813bef
--- /dev/null
+++ b/patches.drivers/qmi_wwan-add-network-device-usage-statistics-for-qmi.patch
@@ -0,0 +1,156 @@
+From 44f82312fe9113bab6642f4d0eab6b1b7902b6e1 Mon Sep 17 00:00:00 2001
+From: Reinhard Speyerer <rspmn@arcor.de>
+Date: Wed, 12 Jun 2019 19:02:46 +0200
+Subject: [PATCH] qmi_wwan: add network device usage statistics for qmimux devices
+Git-commit: 44f82312fe9113bab6642f4d0eab6b1b7902b6e1
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+Add proper network device usage statistics for qmimux devices
+instead of reporting all-zero values for them.
+
+Fixes: c6adf77953bc ("net: usb: qmi_wwan: add qmap mux protocol support")
+Cc: Daniele Palmas <dnlplm@gmail.com>
+Signed-off-by: Reinhard Speyerer <rspmn@arcor.de>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/usb/qmi_wwan.c | 76 +++++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 71 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
+index fd3d078a1923..b0a96459621f 100644
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -22,6 +22,7 @@
+ #include <linux/usb/cdc.h>
+ #include <linux/usb/usbnet.h>
+ #include <linux/usb/cdc-wdm.h>
++#include <linux/u64_stats_sync.h>
+
+ /* This driver supports wwan (3G/LTE/?) devices using a vendor
+ * specific management protocol called Qualcomm MSM Interface (QMI) -
+@@ -75,6 +76,7 @@ struct qmimux_hdr {
+ struct qmimux_priv {
+ struct net_device *real_dev;
+ u8 mux_id;
++ struct pcpu_sw_netstats __percpu *stats64;
+ };
+
+ static int qmimux_open(struct net_device *dev)
+@@ -101,19 +103,65 @@ static netdev_tx_t qmimux_start_xmit(struct sk_buff *skb, struct net_device *dev
+ struct qmimux_priv *priv = netdev_priv(dev);
+ unsigned int len = skb->len;
+ struct qmimux_hdr *hdr;
++ netdev_tx_t ret;
+
+ hdr = skb_push(skb, sizeof(struct qmimux_hdr));
+ hdr->pad = 0;
+ hdr->mux_id = priv->mux_id;
+ hdr->pkt_len = cpu_to_be16(len);
+ skb->dev = priv->real_dev;
+- return dev_queue_xmit(skb);
++ ret = dev_queue_xmit(skb);
++
++ if (likely(ret == NET_XMIT_SUCCESS || ret == NET_XMIT_CN)) {
++ struct pcpu_sw_netstats *stats64 = this_cpu_ptr(priv->stats64);
++
++ u64_stats_update_begin(&stats64->syncp);
++ stats64->tx_packets++;
++ stats64->tx_bytes += len;
++ u64_stats_update_end(&stats64->syncp);
++ } else {
++ dev->stats.tx_dropped++;
++ }
++
++ return ret;
++}
++
++static void qmimux_get_stats64(struct net_device *net,
++ struct rtnl_link_stats64 *stats)
++{
++ struct qmimux_priv *priv = netdev_priv(net);
++ unsigned int start;
++ int cpu;
++
++ netdev_stats_to_stats64(stats, &net->stats);
++
++ for_each_possible_cpu(cpu) {
++ struct pcpu_sw_netstats *stats64;
++ u64 rx_packets, rx_bytes;
++ u64 tx_packets, tx_bytes;
++
++ stats64 = per_cpu_ptr(priv->stats64, cpu);
++
++ do {
++ start = u64_stats_fetch_begin_irq(&stats64->syncp);
++ rx_packets = stats64->rx_packets;
++ rx_bytes = stats64->rx_bytes;
++ tx_packets = stats64->tx_packets;
++ tx_bytes = stats64->tx_bytes;
++ } while (u64_stats_fetch_retry_irq(&stats64->syncp, start));
++
++ stats->rx_packets += rx_packets;
++ stats->rx_bytes += rx_bytes;
++ stats->tx_packets += tx_packets;
++ stats->tx_bytes += tx_bytes;
++ }
+ }
+
+ static const struct net_device_ops qmimux_netdev_ops = {
+- .ndo_open = qmimux_open,
+- .ndo_stop = qmimux_stop,
+- .ndo_start_xmit = qmimux_start_xmit,
++ .ndo_open = qmimux_open,
++ .ndo_stop = qmimux_stop,
++ .ndo_start_xmit = qmimux_start_xmit,
++ .ndo_get_stats64 = qmimux_get_stats64,
+ };
+
+ static void qmimux_setup(struct net_device *dev)
+@@ -198,8 +246,19 @@ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
+ }
+
+ skb_put_data(skbn, skb->data + offset + qmimux_hdr_sz, pkt_len);
+- if (netif_rx(skbn) != NET_RX_SUCCESS)
++ if (netif_rx(skbn) != NET_RX_SUCCESS) {
++ net->stats.rx_errors++;
+ return 0;
++ } else {
++ struct pcpu_sw_netstats *stats64;
++ struct qmimux_priv *priv = netdev_priv(net);
++
++ stats64 = this_cpu_ptr(priv->stats64);
++ u64_stats_update_begin(&stats64->syncp);
++ stats64->rx_packets++;
++ stats64->rx_bytes += pkt_len;
++ u64_stats_update_end(&stats64->syncp);
++ }
+
+ skip:
+ offset += len + qmimux_hdr_sz;
+@@ -223,6 +282,12 @@ static int qmimux_register_device(struct net_device *real_dev, u8 mux_id)
+ priv->mux_id = mux_id;
+ priv->real_dev = real_dev;
+
++ priv->stats64 = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats);
++ if (!priv->stats64) {
++ err = -ENOBUFS;
++ goto out_free_newdev;
++ }
++
+ err = register_netdevice(new_dev);
+ if (err < 0)
+ goto out_free_newdev;
+@@ -252,6 +317,7 @@ static void qmimux_unregister_device(struct net_device *dev)
+ struct qmimux_priv *priv = netdev_priv(dev);
+ struct net_device *real_dev = priv->real_dev;
+
++ free_percpu(priv->stats64);
+ netdev_upper_dev_unlink(real_dev, dev);
+ unregister_netdevice(dev);
+
+--
+2.16.4
+
diff --git a/patches.drivers/qmi_wwan-add-support-for-QMAP-padding-in-the-RX-path.patch b/patches.drivers/qmi_wwan-add-support-for-QMAP-padding-in-the-RX-path.patch
new file mode 100644
index 0000000000..eb9c32520e
--- /dev/null
+++ b/patches.drivers/qmi_wwan-add-support-for-QMAP-padding-in-the-RX-path.patch
@@ -0,0 +1,66 @@
+From 61356088ace1866a847a727d4d40da7bf00b67fc Mon Sep 17 00:00:00 2001
+From: Reinhard Speyerer <rspmn@arcor.de>
+Date: Wed, 12 Jun 2019 19:02:13 +0200
+Subject: [PATCH] qmi_wwan: add support for QMAP padding in the RX path
+Git-commit: 61356088ace1866a847a727d4d40da7bf00b67fc
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+The QMAP code in the qmi_wwan driver is based on the CodeAurora GobiNet
+driver which does not process QMAP padding in the RX path correctly.
+Add support for QMAP padding to qmimux_rx_fixup() according to the
+description of the rmnet driver.
+
+Fixes: c6adf77953bc ("net: usb: qmi_wwan: add qmap mux protocol support")
+Cc: Daniele Palmas <dnlplm@gmail.com>
+Signed-off-by: Reinhard Speyerer <rspmn@arcor.de>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/usb/qmi_wwan.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
+index d9a6699abe59..fd3d078a1923 100644
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -153,7 +153,7 @@ static bool qmimux_has_slaves(struct usbnet *dev)
+
+ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
+ {
+- unsigned int len, offset = 0;
++ unsigned int len, offset = 0, pad_len, pkt_len;
+ struct qmimux_hdr *hdr;
+ struct net_device *net;
+ struct sk_buff *skbn;
+@@ -171,10 +171,16 @@ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
+ if (hdr->pad & 0x80)
+ goto skip;
+
++ /* extract padding length and check for valid length info */
++ pad_len = hdr->pad & 0x3f;
++ if (len == 0 || pad_len >= len)
++ goto skip;
++ pkt_len = len - pad_len;
++
+ net = qmimux_find_dev(dev, hdr->mux_id);
+ if (!net)
+ goto skip;
+- skbn = netdev_alloc_skb(net, len);
++ skbn = netdev_alloc_skb(net, pkt_len);
+ if (!skbn)
+ return 0;
+ skbn->dev = net;
+@@ -191,7 +197,7 @@ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
+ goto skip;
+ }
+
+- skb_put_data(skbn, skb->data + offset + qmimux_hdr_sz, len);
++ skb_put_data(skbn, skb->data + offset + qmimux_hdr_sz, pkt_len);
+ if (netif_rx(skbn) != NET_RX_SUCCESS)
+ return 0;
+
+--
+2.16.4
+
diff --git a/patches.drivers/qmi_wwan-avoid-RCU-stalls-on-device-disconnect-when-.patch b/patches.drivers/qmi_wwan-avoid-RCU-stalls-on-device-disconnect-when-.patch
new file mode 100644
index 0000000000..b2c402d76c
--- /dev/null
+++ b/patches.drivers/qmi_wwan-avoid-RCU-stalls-on-device-disconnect-when-.patch
@@ -0,0 +1,76 @@
+From a8fdde1cb830e560208af42b6c10750137f53eb3 Mon Sep 17 00:00:00 2001
+From: Reinhard Speyerer <rspmn@arcor.de>
+Date: Wed, 12 Jun 2019 19:03:15 +0200
+Subject: [PATCH] qmi_wwan: avoid RCU stalls on device disconnect when in QMAP mode
+Git-commit: a8fdde1cb830e560208af42b6c10750137f53eb3
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+Switch qmimux_unregister_device() and qmi_wwan_disconnect() to
+use unregister_netdevice_queue() and unregister_netdevice_many()
+instead of unregister_netdevice(). This avoids RCU stalls which
+have been observed on device disconnect in certain setups otherwise.
+
+Fixes: c6adf77953bc ("net: usb: qmi_wwan: add qmap mux protocol support")
+Cc: Daniele Palmas <dnlplm@gmail.com>
+Signed-off-by: Reinhard Speyerer <rspmn@arcor.de>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/usb/qmi_wwan.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
+index b0a96459621f..c6fbc2a2a785 100644
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -312,14 +312,15 @@ static int qmimux_register_device(struct net_device *real_dev, u8 mux_id)
+ return err;
+ }
+
+-static void qmimux_unregister_device(struct net_device *dev)
++static void qmimux_unregister_device(struct net_device *dev,
++ struct list_head *head)
+ {
+ struct qmimux_priv *priv = netdev_priv(dev);
+ struct net_device *real_dev = priv->real_dev;
+
+ free_percpu(priv->stats64);
+ netdev_upper_dev_unlink(real_dev, dev);
+- unregister_netdevice(dev);
++ unregister_netdevice_queue(dev, head);
+
+ /* Get rid of the reference to real_dev */
+ dev_put(real_dev);
+@@ -490,7 +491,7 @@ static ssize_t del_mux_store(struct device *d, struct device_attribute *attr, c
+ ret = -EINVAL;
+ goto err;
+ }
+- qmimux_unregister_device(del_dev);
++ qmimux_unregister_device(del_dev, NULL);
+
+ if (!qmimux_has_slaves(dev))
+ info->flags &= ~QMI_WWAN_FLAG_MUX;
+@@ -1500,6 +1501,7 @@ static void qmi_wwan_disconnect(struct usb_interface *intf)
+ struct qmi_wwan_state *info;
+ struct list_head *iter;
+ struct net_device *ldev;
++ LIST_HEAD(list);
+
+ /* called twice if separate control and data intf */
+ if (!dev)
+@@ -1512,8 +1514,9 @@ static void qmi_wwan_disconnect(struct usb_interface *intf)
+ }
+ rcu_read_lock();
+ netdev_for_each_upper_dev_rcu(dev->net, ldev, iter)
+- qmimux_unregister_device(ldev);
++ qmimux_unregister_device(ldev, &list);
+ rcu_read_unlock();
++ unregister_netdevice_many(&list);
+ rtnl_unlock();
+ info->flags &= ~QMI_WWAN_FLAG_MUX;
+ }
+--
+2.16.4
+
diff --git a/patches.drivers/qmi_wwan-extend-permitted-QMAP-mux_id-value-range.patch b/patches.drivers/qmi_wwan-extend-permitted-QMAP-mux_id-value-range.patch
new file mode 100644
index 0000000000..fb1b7ef206
--- /dev/null
+++ b/patches.drivers/qmi_wwan-extend-permitted-QMAP-mux_id-value-range.patch
@@ -0,0 +1,60 @@
+From 36815b416fa48766ac5a98e4b2dc3ebc5887222e Mon Sep 17 00:00:00 2001
+From: Reinhard Speyerer <rspmn@arcor.de>
+Date: Wed, 12 Jun 2019 19:03:50 +0200
+Subject: [PATCH] qmi_wwan: extend permitted QMAP mux_id value range
+Git-commit: 36815b416fa48766ac5a98e4b2dc3ebc5887222e
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+Permit mux_id values up to 254 to be used in qmimux_register_device()
+for compatibility with ip(8) and the rmnet driver.
+
+Fixes: c6adf77953bc ("net: usb: qmi_wwan: add qmap mux protocol support")
+Cc: Daniele Palmas <dnlplm@gmail.com>
+Signed-off-by: Reinhard Speyerer <rspmn@arcor.de>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ Documentation/ABI/testing/sysfs-class-net-qmi | 4 ++--
+ drivers/net/usb/qmi_wwan.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/Documentation/ABI/testing/sysfs-class-net-qmi b/Documentation/ABI/testing/sysfs-class-net-qmi
+index 7122d6264c49..c310db4ccbc2 100644
+--- a/Documentation/ABI/testing/sysfs-class-net-qmi
++++ b/Documentation/ABI/testing/sysfs-class-net-qmi
+@@ -29,7 +29,7 @@ Contact: Bjørn Mork <bjorn@mork.no>
+ Description:
+ Unsigned integer.
+
+- Write a number ranging from 1 to 127 to add a qmap mux
++ Write a number ranging from 1 to 254 to add a qmap mux
+ based network device, supported by recent Qualcomm based
+ modems.
+
+@@ -46,5 +46,5 @@ Contact: Bjørn Mork <bjorn@mork.no>
+ Description:
+ Unsigned integer.
+
+- Write a number ranging from 1 to 127 to delete a previously
++ Write a number ranging from 1 to 254 to delete a previously
+ created qmap mux based network device.
+diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
+index c6fbc2a2a785..780c10ee359b 100644
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -429,8 +429,8 @@ static ssize_t add_mux_store(struct device *d, struct device_attribute *attr, c
+ if (kstrtou8(buf, 0, &mux_id))
+ return -EINVAL;
+
+- /* mux_id [1 - 0x7f] range empirically found */
+- if (mux_id < 1 || mux_id > 0x7f)
++ /* mux_id [1 - 254] for compatibility with ip(8) and the rmnet driver */
++ if (mux_id < 1 || mux_id > 254)
+ return -EINVAL;
+
+ if (!rtnl_trylock())
+--
+2.16.4
+
diff --git a/patches.drivers/rapidio-fix-a-NULL-pointer-dereference-when-create_w.patch b/patches.drivers/rapidio-fix-a-NULL-pointer-dereference-when-create_w.patch
new file mode 100644
index 0000000000..5990ffd7ff
--- /dev/null
+++ b/patches.drivers/rapidio-fix-a-NULL-pointer-dereference-when-create_w.patch
@@ -0,0 +1,44 @@
+From 23015b22e47c5409620b1726a677d69e5cd032ba Mon Sep 17 00:00:00 2001
+From: Kangjie Lu <kjlu@umn.edu>
+Date: Tue, 14 May 2019 15:44:49 -0700
+Subject: [PATCH] rapidio: fix a NULL pointer dereference when create_workqueue() fails
+Git-commit: 23015b22e47c5409620b1726a677d69e5cd032ba
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+In case create_workqueue fails, the fix releases resources and returns
+-ENOMEM to avoid NULL pointer dereference.
+
+Signed-off-by: Kangjie Lu <kjlu@umn.edu>
+Acked-by: Alexandre Bounine <alex.bou9@gmail.com>
+Cc: Matt Porter <mporter@kernel.crashing.org>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/rapidio/rio_cm.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/rapidio/rio_cm.c b/drivers/rapidio/rio_cm.c
+index cf45829585cb..b29fc258eeba 100644
+--- a/drivers/rapidio/rio_cm.c
++++ b/drivers/rapidio/rio_cm.c
+@@ -2147,6 +2147,14 @@ static int riocm_add_mport(struct device *dev,
+ mutex_init(&cm->rx_lock);
+ riocm_rx_fill(cm, RIOCM_RX_RING_SIZE);
+ cm->rx_wq = create_workqueue(DRV_NAME "/rxq");
++ if (!cm->rx_wq) {
++ riocm_error("failed to allocate IBMBOX_%d on %s",
++ cmbox, mport->name);
++ rio_release_outb_mbox(mport, cmbox);
++ kfree(cm);
++ return -ENOMEM;
++ }
++
+ INIT_WORK(&cm->rx_work, rio_ibmsg_handler);
+
+ cm->tx_slot = 0;
+--
+2.16.4
+
diff --git a/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch b/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch
new file mode 100644
index 0000000000..dcfec72517
--- /dev/null
+++ b/patches.drivers/ras-cec-convert-the-timer-callback-to-a-workqueue.patch
@@ -0,0 +1,141 @@
+From: Cong Wang <xiyou.wangcong@gmail.com>
+Date: Tue, 16 Apr 2019 14:33:51 -0700
+Subject: RAS/CEC: Convert the timer callback to a workqueue
+Git-commit: 0ade0b6240c4853cf9725924c46c10f4251639d7
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+cec_timer_fn() is a timer callback which reads ce_arr.array[] and
+updates its decay values. However, it runs in interrupt context and the
+mutex protection the CEC uses for that array, is inadequate. Convert the
+used timer to a workqueue to keep the tasks the CEC performs preemptible
+and thus low-prio.
+
+ [ bp: Rewrite commit message.
+ s/timer/decay/gi to make it agnostic as to what facility is used. ]
+
+Fixes: 011d82611172 ("RAS: Add a Corrected Errors Collector")
+Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: <stable@vger.kernel.org>
+Link: https://lkml.kernel.org/r/20190416213351.28999-2-xiyou.wangcong@gmail.com
+---
+ drivers/ras/cec.c | 50 +++++++++++++++++++++++---------------------------
+ 1 file changed, 23 insertions(+), 27 deletions(-)
+
+--- a/drivers/ras/cec.c
++++ b/drivers/ras/cec.c
+@@ -1,6 +1,7 @@
+ #include <linux/mm.h>
+ #include <linux/gfp.h>
+ #include <linux/kernel.h>
++#include <linux/workqueue.h>
+
+ #include <asm/mce.h>
+
+@@ -122,16 +123,12 @@ static u64 dfs_pfn;
+ /* Amount of errors after which we offline */
+ static unsigned int count_threshold = COUNT_MASK;
+
+-/*
+- * The timer "decays" element count each timer_interval which is 24hrs by
+- * default.
+- */
+-
+-#define CEC_TIMER_DEFAULT_INTERVAL 24 * 60 * 60 /* 24 hrs */
+-#define CEC_TIMER_MIN_INTERVAL 1 * 60 * 60 /* 1h */
+-#define CEC_TIMER_MAX_INTERVAL 30 * 24 * 60 * 60 /* one month */
+-static struct timer_list cec_timer;
+-static u64 timer_interval = CEC_TIMER_DEFAULT_INTERVAL;
++/* Each element "decays" each decay_interval which is 24hrs by default. */
++#define CEC_DECAY_DEFAULT_INTERVAL 24 * 60 * 60 /* 24 hrs */
++#define CEC_DECAY_MIN_INTERVAL 1 * 60 * 60 /* 1h */
++#define CEC_DECAY_MAX_INTERVAL 30 * 24 * 60 * 60 /* one month */
++static struct delayed_work cec_work;
++static u64 decay_interval = CEC_DECAY_DEFAULT_INTERVAL;
+
+ /*
+ * Decrement decay value. We're using DECAY_BITS bits to denote decay of an
+@@ -159,22 +156,21 @@ static void do_spring_cleaning(struct ce
+ /*
+ * @interval in seconds
+ */
+-static void cec_mod_timer(struct timer_list *t, unsigned long interval)
++static void cec_mod_work(unsigned long interval)
+ {
+ unsigned long iv;
+
+- iv = interval * HZ + jiffies;
+-
+- mod_timer(t, round_jiffies(iv));
++ iv = interval * HZ;
++ mod_delayed_work(system_wq, &cec_work, round_jiffies(iv));
+ }
+
+-static void cec_timer_fn(unsigned long data)
++static void cec_work_fn(struct work_struct *work)
+ {
+- struct ce_array *ca = (struct ce_array *)data;
+-
+- do_spring_cleaning(ca);
++ mutex_lock(&ce_mutex);
++ do_spring_cleaning(&ce_arr);
++ mutex_unlock(&ce_mutex);
+
+- cec_mod_timer(&cec_timer, timer_interval);
++ cec_mod_work(decay_interval);
+ }
+
+ /*
+@@ -381,15 +377,15 @@ static int decay_interval_set(void *data
+ {
+ *(u64 *)data = val;
+
+- if (val < CEC_TIMER_MIN_INTERVAL)
++ if (val < CEC_DECAY_MIN_INTERVAL)
+ return -EINVAL;
+
+- if (val > CEC_TIMER_MAX_INTERVAL)
++ if (val > CEC_DECAY_MAX_INTERVAL)
+ return -EINVAL;
+
+- timer_interval = val;
++ decay_interval = val;
+
+- cec_mod_timer(&cec_timer, timer_interval);
++ cec_mod_work(decay_interval);
+ return 0;
+ }
+ DEFINE_DEBUGFS_ATTRIBUTE(decay_interval_ops, u64_get, decay_interval_set, "%lld\n");
+@@ -433,7 +429,7 @@ static int array_dump(struct seq_file *m
+
+ seq_printf(m, "Flags: 0x%x\n", ca->flags);
+
+- seq_printf(m, "Timer interval: %lld seconds\n", timer_interval);
++ seq_printf(m, "Decay interval: %lld seconds\n", decay_interval);
+ seq_printf(m, "Decays: %lld\n", ca->decays_done);
+
+ seq_printf(m, "Action threshold: %d\n", count_threshold);
+@@ -479,7 +475,7 @@ static int __init create_debugfs_nodes(v
+ }
+
+ decay = debugfs_create_file("decay_interval", S_IRUSR | S_IWUSR, d,
+- &timer_interval, &decay_interval_ops);
++ &decay_interval, &decay_interval_ops);
+ if (!decay) {
+ pr_warn("Error creating decay_interval debugfs node!\n");
+ goto err;
+@@ -515,8 +511,8 @@ void __init cec_init(void)
+ if (create_debugfs_nodes())
+ return;
+
+- setup_timer(&cec_timer, cec_timer_fn, (unsigned long)&ce_arr);
+- cec_mod_timer(&cec_timer, CEC_TIMER_DEFAULT_INTERVAL);
++ INIT_DELAYED_WORK(&cec_work, cec_work_fn);
++ schedule_delayed_work(&cec_work, CEC_DECAY_DEFAULT_INTERVAL);
+
+ pr_info("Correctable Errors collector initialized.\n");
+ }
diff --git a/patches.drivers/ras-cec-fix-binary-search-function.patch b/patches.drivers/ras-cec-fix-binary-search-function.patch
new file mode 100644
index 0000000000..ea4580d069
--- /dev/null
+++ b/patches.drivers/ras-cec-fix-binary-search-function.patch
@@ -0,0 +1,90 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Sat, 20 Apr 2019 13:27:51 +0200
+Subject: RAS/CEC: Fix binary search function
+Git-commit: f3c74b38a55aefe1004200d15a83f109b510068c
+Patch-mainline: v5.2-rc5
+References: bsc#1114279
+
+Switch to using Donald Knuth's binary search algorithm (The Art of
+Computer Programming, vol. 3, section 6.2.1). This should've been done
+from the very beginning but the author must've been smoking something
+very potent at the time.
+
+The problem with the current one was that it would return the wrong
+element index in certain situations:
+
+ https://lkml.kernel.org/r/CAM_iQpVd02zkVJ846cj-Fg1yUNuz6tY5q1Vpj4LrXmE06dPYYg@mail.gmail.com
+
+and the noodling code after the loop was fishy at best.
+
+So switch to using Knuth's binary search. The final result is much
+cleaner and straightforward.
+
+Fixes: 011d82611172 ("RAS: Add a Corrected Errors Collector")
+Reported-by: Cong Wang <xiyou.wangcong@gmail.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: linux-edac <linux-edac@vger.kernel.org>
+Cc: <stable@vger.kernel.org>
+---
+ drivers/ras/cec.c | 34 ++++++++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
+index 88e4f3ff0cb8..dbfe3e61d2c2 100644
+--- a/drivers/ras/cec.c
++++ b/drivers/ras/cec.c
+@@ -183,32 +183,38 @@ static void cec_timer_fn(struct timer_list *unused)
+ */
+ static int __find_elem(struct ce_array *ca, u64 pfn, unsigned int *to)
+ {
++ int min = 0, max = ca->n - 1;
+ u64 this_pfn;
+- int min = 0, max = ca->n;
+
+- while (min < max) {
+- int tmp = (max + min) >> 1;
++ while (min <= max) {
++ int i = (min + max) >> 1;
+
+- this_pfn = PFN(ca->array[tmp]);
++ this_pfn = PFN(ca->array[i]);
+
+ if (this_pfn < pfn)
+- min = tmp + 1;
++ min = i + 1;
+ else if (this_pfn > pfn)
+- max = tmp;
+- else {
+- min = tmp;
+- break;
++ max = i - 1;
++ else if (this_pfn == pfn) {
++ if (to)
++ *to = i;
++
++ return i;
+ }
+ }
+
++ /*
++ * When the loop terminates without finding @pfn, min has the index of
++ * the element slot where the new @pfn should be inserted. The loop
++ * terminates when min > max, which means the min index points to the
++ * bigger element while the max index to the smaller element, in-between
++ * which the new @pfn belongs to.
++ *
++ * For more details, see exercise 1, Section 6.2.1 in TAOCP, vol. 3.
++ */
+ if (to)
+ *to = min;
+
+- this_pfn = PFN(ca->array[min]);
+-
+- if (this_pfn == pfn)
+- return min;
+-
+ return -ENOKEY;
+ }
+
+
diff --git a/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main b/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
index 3bb9ba6856..1849004a8d 100644
--- a/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
+++ b/patches.drivers/scsi-mpt3sas_ctl-fix-double-fetch-bug-in-ctl_ioctl_main
@@ -2,7 +2,7 @@ From: Gen Zhang <blackgod016574@gmail.com>
Date: Thu, 30 May 2019 09:10:30 +0800
Subject: scsi: mpt3sas_ctl: fix double-fetch bug in _ctl_ioctl_main()
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git
-Git-commit: 86e5aca7fa2927060839f3e3b40c8bd65a7e8d1e
+Git-commit: f9e3ebeea4521652318af903cddeaf033527e93e
Patch-mainline: Queued in subsystem maintainer repo
References: bsc#1136922 CVE-2019-12456
diff --git a/patches.drivers/scsi-qla2xxx-Fix-FC-AL-connection-target-discovery.patch b/patches.drivers/scsi-qla2xxx-Fix-FC-AL-connection-target-discovery.patch
new file mode 100644
index 0000000000..6901738b6f
--- /dev/null
+++ b/patches.drivers/scsi-qla2xxx-Fix-FC-AL-connection-target-discovery.patch
@@ -0,0 +1,44 @@
+From: Quinn Tran <qtran@marvell.com>
+Date: Fri, 15 Mar 2019 15:04:18 -0700
+Subject: [PATCH] scsi: qla2xxx: Fix FC-AL connection target discovery
+Git-commit: 4705f10e82c63924bd84a9b31d15839ec9ba3d06
+Patch-Mainline: v5.1-rc2
+References: bsc#1094555
+
+Commit 7f147f9bfd44 ("scsi: qla2xxx: Fix N2N target discovery with Local
+loop") fixed N2N target discovery for local loop. However, same code is
+used for FC-AL discovery as well. Added check to make sure we are bypassing
+area and domain check only in N2N topology for target discovery.
+
+Fixes: 7f147f9bfd44 ("scsi: qla2xxx: Fix N2N target discovery with Local loop")
+Cc: stable@vger.kernel.org # 5.0+
+Signed-off-by: Quinn Tran <qtran@marvell.com>
+Signed-off-by: Himanshu Madhani <hmadhani@marvell.com>
+Reviewed-by: Ewan D. Milne <emilne@redhat.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Hannes Reinecke <hare@suse.com>
+---
+ drivers/scsi/qla2xxx/qla_init.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
+index 420045155ba0..0c700b140ce7 100644
+--- a/drivers/scsi/qla2xxx/qla_init.c
++++ b/drivers/scsi/qla2xxx/qla_init.c
+@@ -4991,6 +4991,13 @@ qla2x00_configure_local_loop(scsi_qla_host_t *vha)
+ if ((domain & 0xf0) == 0xf0)
+ continue;
+
++ /* Bypass if not same domain and area of adapter. */
++ if (area && domain && ((area != vha->d_id.b.area) ||
++ (domain != vha->d_id.b.domain)) &&
++ (ha->current_topology == ISP_CFG_NL))
++ continue;
++
++
+ /* Bypass invalid local loop ID. */
+ if (loop_id > LAST_LOCAL_LOOP_ID)
+ continue;
+--
+2.16.4
+
diff --git a/patches.drivers/scsi-qla2xxx-Fix-N2N-target-discovery-with-Local-loo.patch b/patches.drivers/scsi-qla2xxx-Fix-N2N-target-discovery-with-Local-loo.patch
index 21561e0107..9c48b8b90b 100644
--- a/patches.drivers/scsi-qla2xxx-Fix-N2N-target-discovery-with-Local-loo.patch
+++ b/patches.drivers/scsi-qla2xxx-Fix-N2N-target-discovery-with-Local-loo.patch
@@ -3,7 +3,7 @@ Date: Thu, 24 Jan 2019 23:23:39 -0800
Subject: [PATCH] scsi: qla2xxx: Fix N2N target discovery with Local loop
Git-commit: 7f147f9bfd44d048e22e8c65877d2b5590e6cf3d
Patch-mainline: v5.1-rc1
-References: bsc#1124541
+References: bsc#1094555 bsc#1124541
This patch fixes the issue where Dell-EMC Target will fail to discover LUNs
if domain and area of port ID is not same as adapter's.
diff --git a/patches.drivers/soc-mediatek-pwrap-Zero-initialize-rdata-in-pwrap_in.patch b/patches.drivers/soc-mediatek-pwrap-Zero-initialize-rdata-in-pwrap_in.patch
new file mode 100644
index 0000000000..1702aba2ed
--- /dev/null
+++ b/patches.drivers/soc-mediatek-pwrap-Zero-initialize-rdata-in-pwrap_in.patch
@@ -0,0 +1,46 @@
+From 89e28da82836530f1ac7a3a32fecc31f22d79b3e Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Thu, 7 Mar 2019 15:56:51 -0700
+Subject: [PATCH] soc: mediatek: pwrap: Zero initialize rdata in pwrap_init_cipher
+Git-commit: 89e28da82836530f1ac7a3a32fecc31f22d79b3e
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+When building with -Wsometimes-uninitialized, Clang warns:
+
+drivers/soc/mediatek/mtk-pmic-wrap.c:1358:6: error: variable 'rdata' is
+used uninitialized whenever '||' condition is true
+[-Werror,-Wsometimes-uninitialized]
+
+If pwrap_write returns non-zero, pwrap_read will not be called to
+initialize rdata, meaning that we will use some random uninitialized
+stack value in our print statement. Zero initialize rdata in case this
+happens.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/401
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/soc/mediatek/mtk-pmic-wrap.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 73f0be0567bd..c4449a163991 100644
+--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
+@@ -1371,7 +1371,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
+ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
+ {
+ int ret;
+- u32 rdata;
++ u32 rdata = 0;
+
+ pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
+ pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
+--
+2.16.4
+
diff --git a/patches.drivers/soc-rockchip-Set-the-proper-PWM-for-rk3288.patch b/patches.drivers/soc-rockchip-Set-the-proper-PWM-for-rk3288.patch
new file mode 100644
index 0000000000..a4a6078842
--- /dev/null
+++ b/patches.drivers/soc-rockchip-Set-the-proper-PWM-for-rk3288.patch
@@ -0,0 +1,57 @@
+From bbdc00a7de24cc90315b1775fb74841373fe12f7 Mon Sep 17 00:00:00 2001
+From: Douglas Anderson <dianders@chromium.org>
+Date: Tue, 9 Apr 2019 13:49:05 -0700
+Subject: [PATCH] soc: rockchip: Set the proper PWM for rk3288
+Git-commit: bbdc00a7de24cc90315b1775fb74841373fe12f7
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+The rk3288 SoC has two PWM implementations available, the "old"
+implementation and the "new" one. You can switch between the two of
+them by flipping a bit in the grf.
+
+The "old" implementation is the default at chip power up but isn't the
+one that's officially supposed to be used. ...and, in fact, the
+driver that gets selected in Linux using the rk3288 device tree only
+supports the "new" implementation.
+
+Long ago I tried to get a switch to the right IP block landed in the
+PWM driver (search for "rk3288: Switch to use the proper PWM IP") but
+that got rejected. In the mean time the grf has grown a full-fledged
+driver that already sets other random bits like this. That means we
+can now get the fix landed.
+
+For those wondering how things could have possibly worked for the last
+4.5 years, folks have mostly been relying on the bootloader to set
+this bit. ...but occasionally folks have pointed back to my old patch
+series [1] in downstream kernels.
+
+[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html
+
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/soc/rockchip/grf.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
+index 96882ffde67e..3b81e1d75a97 100644
+--- a/drivers/soc/rockchip/grf.c
++++ b/drivers/soc/rockchip/grf.c
+@@ -66,9 +66,11 @@ static const struct rockchip_grf_info rk3228_grf __initconst = {
+ };
+
+ #define RK3288_GRF_SOC_CON0 0x244
++#define RK3288_GRF_SOC_CON2 0x24c
+
+ static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
+ { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
++ { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
+ };
+
+ static const struct rockchip_grf_info rk3288_grf __initconst = {
+--
+2.16.4
+
diff --git a/patches.drivers/tty-max310x-Fix-external-crystal-register-setup.patch b/patches.drivers/tty-max310x-Fix-external-crystal-register-setup.patch
new file mode 100644
index 0000000000..367a6290e5
--- /dev/null
+++ b/patches.drivers/tty-max310x-Fix-external-crystal-register-setup.patch
@@ -0,0 +1,47 @@
+From 5d24f455c182d5116dd5db8e1dc501115ecc9c2c Mon Sep 17 00:00:00 2001
+From: Joe Burmeister <joe.burmeister@devtank.co.uk>
+Date: Mon, 13 May 2019 11:23:57 +0100
+Subject: [PATCH] tty: max310x: Fix external crystal register setup
+Git-commit: 5d24f455c182d5116dd5db8e1dc501115ecc9c2c
+Patch-mainline: v5.2-rc3
+References: bsc#1051510
+
+The datasheet states:
+
+ Bit 4: ClockEnSet the ClockEn bit high to enable an external clocking
+(crystal or clock generator at XIN). Set the ClockEn bit to 0 to disable
+clocking
+ Bit 1: CrystalEnSet the CrystalEn bit high to enable the crystal
+oscillator. When using an external clock source at XIN, CrystalEn must
+be set low.
+
+The bit 4, MAX310X_CLKSRC_EXTCLK_BIT, should be set and was not.
+
+This was required to make the MAX3107 with an external crystal on our
+board able to send or receive data.
+
+Signed-off-by: Joe Burmeister <joe.burmeister@devtank.co.uk>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/tty/serial/max310x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
+index 450ba6d7996c..e5aebbf5f302 100644
+--- a/drivers/tty/serial/max310x.c
++++ b/drivers/tty/serial/max310x.c
+@@ -581,7 +581,7 @@ static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
+ }
+
+ /* Configure clock source */
+- clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
++ clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
+
+ /* Configure PLL */
+ if (pllcfg) {
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-Add-new-AML_ULX-support-list.patch b/patches.drm/drm-i915-Add-new-AML_ULX-support-list.patch
new file mode 100644
index 0000000000..1986ec8b6c
--- /dev/null
+++ b/patches.drm/drm-i915-Add-new-AML_ULX-support-list.patch
@@ -0,0 +1,39 @@
+From ab2da3f8cd972d4813c7044bcb84a3271031e19a Mon Sep 17 00:00:00 2001
+From: "Lee, Shawn C" <shawn.c.lee@intel.com>
+Date: Thu, 27 Sep 2018 00:48:18 -0700
+Subject: [PATCH] drm/i915: Add new AML_ULX support list
+Git-commit: ab2da3f8cd972d4813c7044bcb84a3271031e19a
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-4986
+
+According to patch "drm/i915/aml: Introducing Amber Lake platform"
+(e364672477a1). Add a new marco for AML ULX GT2 devices.
+
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Jose Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Lee, Shawn C <shawn.c.lee@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/1538034499-31256-1-git-send-email-shawn.c.lee@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index 2264b30ce51a..b447acad850a 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2468,6 +2468,8 @@ intel_info(const struct drm_i915_private *dev_priv)
+ #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
+ INTEL_DEVID(dev_priv) == 0x5915 || \
+ INTEL_DEVID(dev_priv) == 0x591E)
++#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
++ INTEL_DEVID(dev_priv) == 0x87C0)
+ #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (dev_priv)->info.gt == 2)
+ #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-Add-new-ICL-PCI-ID.patch b/patches.drm/drm-i915-Add-new-ICL-PCI-ID.patch
new file mode 100644
index 0000000000..37abd619dd
--- /dev/null
+++ b/patches.drm/drm-i915-Add-new-ICL-PCI-ID.patch
@@ -0,0 +1,42 @@
+From 9a751b999d17a037d5562318d3a21dd5e5bd55eb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
+Date: Fri, 8 Mar 2019 13:56:46 -0800
+Subject: [PATCH] drm/i915: Add new ICL PCI ID
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 9a751b999d17a037d5562318d3a21dd5e5bd55eb
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+A new PCI ID for ICL was added to BSpec, lets keep it in tight sync
+as ICL is not protected by the alpha support flag anymore.
+
+V2: Keeping BSpec order(Rodrigo)
+
+Bsepc: 21141
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190308215646.30436-1-jose.souza@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ include/drm/i915_pciids.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+index d2fad7b0fcf6..d200000feeaa 100644
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -469,6 +469,7 @@
+ INTEL_VGA_DEVICE(0x8A57, info), \
+ INTEL_VGA_DEVICE(0x8A56, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+- INTEL_VGA_DEVICE(0x8A70, info)
++ INTEL_VGA_DEVICE(0x8A70, info), \
++ INTEL_VGA_DEVICE(0x8A53, info)
+
+ #endif /* _I915_PCIIDS_H */
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-Apply-correct-ddi-translation-table-for-AML.patch b/patches.drm/drm-i915-Apply-correct-ddi-translation-table-for-AML.patch
new file mode 100644
index 0000000000..d8fff17120
--- /dev/null
+++ b/patches.drm/drm-i915-Apply-correct-ddi-translation-table-for-AML.patch
@@ -0,0 +1,66 @@
+From dfdaa566b7d4ecbfcabbb624bc45c5221f142039 Mon Sep 17 00:00:00 2001
+From: "Lee, Shawn C" <shawn.c.lee@intel.com>
+Date: Thu, 27 Sep 2018 00:48:19 -0700
+Subject: [PATCH] drm/i915: Apply correct ddi translation table for AML device
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: dfdaa566b7d4ecbfcabbb624bc45c5221f142039
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-4986
+
+Amber Lake used the same gen graphics as Kaby Lake. Kernel driver
+should configure KBL's DDI buffer setting for AML ULX as well.
+
+So far, driver would load DDI translation table that used for
+KBL H/S platform and apply it on AML devices. But AML is belong to
+ULX series. This change will lead driver to apply KBL-Y's DDI table
+for AML devices to avoid unexpected eDP/DP signal quality issue.
+
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Jose Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Lee, Shawn C <shawn.c.lee@intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/1538034499-31256-2-git-send-email-shawn.c.lee@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
+index 9e82281b4fdf..47960c92cbbf 100644
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -642,7 +642,7 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+ static const struct ddi_buf_trans *
+ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
+ {
+- if (IS_KBL_ULX(dev_priv)) {
++ if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+ *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
+ return kbl_y_ddi_translations_dp;
+ } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
+@@ -658,7 +658,7 @@ static const struct ddi_buf_trans *
+ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+ {
+ if (dev_priv->vbt.edp.low_vswing) {
+- if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
++ if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+ *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
+ return skl_y_ddi_translations_edp;
+ } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
+@@ -680,7 +680,7 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
+ static const struct ddi_buf_trans *
+ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
+ {
+- if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
++ if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+ *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
+ return skl_y_ddi_translations_hdmi;
+ } else {
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-Attach-the-pci-match-data-to-the-device-upo.patch b/patches.drm/drm-i915-Attach-the-pci-match-data-to-the-device-upo.patch
new file mode 100644
index 0000000000..7df08b2fb4
--- /dev/null
+++ b/patches.drm/drm-i915-Attach-the-pci-match-data-to-the-device-upo.patch
@@ -0,0 +1,141 @@
+From 55ac5a1614f99816ed367a9ded5f5d65321b522f Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 5 Sep 2018 15:09:20 +0100
+Subject: [PATCH] drm/i915: Attach the pci match data to the device upon creation
+Git-commit: 55ac5a1614f99816ed367a9ded5f5d65321b522f
+Patch-mainline: v4.20-rc1
+References: jsc#SLE-4986
+
+Attach our device_info to the our i915 private on creation so that it is
+always available for inspection.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180905140921.17467-1-chris@chris-wilson.co.uk
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 66 +++++++++++++++++++++++-----------------
+ 1 file changed, 38 insertions(+), 28 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -867,7 +867,6 @@ static void intel_detect_preproduction_h
+ /**
+ * i915_driver_init_early - setup state not requiring device access
+ * @dev_priv: device private
+- * @ent: the matching pci_device_id
+ *
+ * Initialize everything that is a "SW-only" state, that is state not
+ * requiring accessing the device or exposing the driver via kernel internal
+@@ -875,25 +874,13 @@ static void intel_detect_preproduction_h
+ * system memory allocation, setting up device specific attributes and
+ * function hooks not requiring accessing the device.
+ */
+-static int i915_driver_init_early(struct drm_i915_private *dev_priv,
+- const struct pci_device_id *ent)
++static int i915_driver_init_early(struct drm_i915_private *dev_priv)
+ {
+- const struct intel_device_info *match_info =
+- (struct intel_device_info *)ent->driver_data;
+- struct intel_device_info *device_info;
+ int ret = 0;
+
+ if (i915_inject_load_failure())
+ return -ENODEV;
+
+- /* Setup the write-once "constant" device info */
+- device_info = mkwrite_device_info(dev_priv);
+- memcpy(device_info, match_info, sizeof(*device_info));
+- device_info->device_id = dev_priv->drm.pdev->device;
+-
+- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+- sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+- BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
+ spin_lock_init(&dev_priv->irq_lock);
+ spin_lock_init(&dev_priv->gpu_error.lock);
+ mutex_init(&dev_priv->backlight_lock);
+@@ -1333,6 +1320,39 @@ static void i915_welcome_messages(struct
+ DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
+ }
+
++static struct drm_i915_private *
++i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++ const struct intel_device_info *match_info =
++ (struct intel_device_info *)ent->driver_data;
++ struct intel_device_info *device_info;
++ struct drm_i915_private *i915;
++
++ i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
++ if (!i915)
++ return NULL;
++
++ if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
++ kfree(i915);
++ return NULL;
++ }
++
++ i915->drm.pdev = pdev;
++ i915->drm.dev_private = i915;
++ pci_set_drvdata(pdev, &i915->drm);
++
++ /* Setup the write-once "constant" device info */
++ device_info = mkwrite_device_info(i915);
++ memcpy(device_info, match_info, sizeof(*device_info));
++ device_info->device_id = pdev->device;
++
++ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
++ sizeof(device_info->platform_mask) * BITS_PER_BYTE);
++ BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
++
++ return i915;
++}
++
+ /**
+ * i915_driver_load - setup chip and create an initial config
+ * @pdev: PCI device
+@@ -1355,23 +1375,14 @@ int i915_driver_load(struct pci_dev *pde
+ if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
+ driver.driver_features &= ~DRIVER_ATOMIC;
+
+- ret = -ENOMEM;
+- dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
+- if (dev_priv)
+- ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
+- if (ret) {
+- DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
+- goto out_free;
+- }
+-
+- dev_priv->drm.pdev = pdev;
+- dev_priv->drm.dev_private = dev_priv;
++ dev_priv = i915_driver_create(pdev, ent);
++ if (!dev_priv)
++ return -ENOMEM;
+
+ ret = pci_enable_device(pdev);
+ if (ret)
+ goto out_fini;
+
+- pci_set_drvdata(pdev, &dev_priv->drm);
+ /*
+ * Disable the system suspend direct complete optimization, which can
+ * leave the device suspended skipping the driver's suspend handlers
+@@ -1382,7 +1393,7 @@ int i915_driver_load(struct pci_dev *pde
+ */
+ dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
+
+- ret = i915_driver_init_early(dev_priv, ent);
++ ret = i915_driver_init_early(dev_priv);
+ if (ret < 0)
+ goto out_pci_disable;
+
+@@ -1436,7 +1447,6 @@ out_pci_disable:
+ out_fini:
+ i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
+ drm_dev_fini(&dev_priv->drm);
+-out_free:
+ kfree(dev_priv);
+ pci_set_drvdata(pdev, NULL);
+ return ret;
diff --git a/patches.drm/drm-i915-Fix-uninitialized-mask-in-intel_device_info.patch b/patches.drm/drm-i915-Fix-uninitialized-mask-in-intel_device_info.patch
new file mode 100644
index 0000000000..3c29316c5c
--- /dev/null
+++ b/patches.drm/drm-i915-Fix-uninitialized-mask-in-intel_device_info.patch
@@ -0,0 +1,51 @@
+From 640cde65b48ae6c773f00cbbdece7e67945b3f34 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Wed, 3 Apr 2019 07:44:07 +0100
+Subject: [PATCH] drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 640cde65b48ae6c773f00cbbdece7e67945b3f34
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+Mask need to be initialized to zero since device id checks may not match.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Fixes: 805446c8347c ("drm/i915: Introduce concept of a sub-platform")
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Cc: Jose Souza <jose.souza@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190403064407.25646-1-tvrtko.ursulin@linux.intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_device_info.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
+index 0ed49d032c00..6af480b95bc6 100644
+--- a/drivers/gpu/drm/i915/intel_device_info.c
++++ b/drivers/gpu/drm/i915/intel_device_info.c
+@@ -778,7 +778,7 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+ const unsigned int pi = __platform_mask_index(rinfo, info->platform);
+ const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
+ u16 devid = INTEL_DEVID(i915);
+- u32 mask;
++ u32 mask = 0;
+
+ /* Make sure IS_<platform> checks are working. */
+ RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-Introduce-concept-of-a-sub-platform.patch b/patches.drm/drm-i915-Introduce-concept-of-a-sub-platform.patch
new file mode 100644
index 0000000000..d3cf9db89e
--- /dev/null
+++ b/patches.drm/drm-i915-Introduce-concept-of-a-sub-platform.patch
@@ -0,0 +1,416 @@
+From 805446c8347c9e743912cb7acf795683d9af7972 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Wed, 27 Mar 2019 14:23:28 +0000
+Subject: [PATCH] drm/i915: Introduce concept of a sub-platform
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 805446c8347c9e743912cb7acf795683d9af7972
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+Concept of a sub-platform already exist in our code (like ULX and ULT
+platform variants and similar),implemented via the macros which check a
+list of device ids to determine a match.
+
+With this patch we consolidate device ids checking into a single function
+called during early driver load.
+
+A few low bits in the platform mask are reserved for sub-platform
+identification and defined as a per-platform namespace.
+
+At the same time it future proofs the platform_mask handling by preparing
+the code for easy extending, and tidies the very verbose WARN strings
+generated when IS_PLATFORM macros are embedded into a WARN type
+statements.
+
+V2: Fixed IS_SUBPLATFORM. Updated commit msg.
+V3: Chris was right, there is an ordering problem.
+
+V4: * Catch-up with new sub-platforms. * Rebase for RUNTIME_INFO. * Drop subplatform mask union tricks and convert platform_mask to an array for extensibility.
+
+V5: * Fix subplatform check. * Protect against forgetting to expand subplatform bits. * Remove platform enum tallying. * Add subplatform to error state. (Chris) * Drop macros and just use static inlines. * Remove redundant IRONLAKE_M. (Ville)
+
+V6: * Split out Ironlake change. * Optimize subplatform check. * Use __always_inline. (Lucas) * Add platform_mask comment. (Paulo) * Pass stored runtime info in error capture. (Chris)
+
+V7: * Rebased for new AML ULX device id. * Bump platform mask array size for EHL. * Stop mentioning device ids in intel_device_subplatform_init by using the trick of splitting macros i915_pciids.h. (Jani) * AML seems to be either a subplatform of KBL or CFL so express it like that.
+
+V8: * Use one device id table per subplatform. (Jani)
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Cc: Jose Souza <jose.souza@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Acked-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190327142328.31780-1-tvrtko.ursulin@linux.intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 4 -
+ drivers/gpu/drm/i915/i915_drv.h | 121 ++++++++++++++++++++++---------
+ drivers/gpu/drm/i915/i915_gpu_error.c | 3
+ drivers/gpu/drm/i915/i915_pci.c | 2
+ drivers/gpu/drm/i915/intel_device_info.c | 93 +++++++++++++++++++++++
+ drivers/gpu/drm/i915/intel_device_info.h | 27 ++++++
+ 6 files changed, 211 insertions(+), 39 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -881,6 +881,8 @@ static int i915_driver_init_early(struct
+ if (i915_inject_load_failure())
+ return -ENODEV;
+
++ intel_device_info_subplatform_init(dev_priv);
++
+ spin_lock_init(&dev_priv->irq_lock);
+ spin_lock_init(&dev_priv->gpu_error.lock);
+ mutex_init(&dev_priv->backlight_lock);
+@@ -1346,8 +1348,6 @@ i915_driver_create(struct pci_dev *pdev,
+ memcpy(device_info, match_info, sizeof(*device_info));
+ RUNTIME_INFO(i915)->device_id = pdev->device;
+
+- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+- sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+ BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
+
+ return i915;
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2370,7 +2370,67 @@ intel_info(const struct drm_i915_private
+ #define IS_REVID(p, since, until) \
+ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
+
+-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
++static __always_inline unsigned int
++__platform_mask_index(const struct intel_runtime_info *info,
++ enum intel_platform p)
++{
++ const unsigned int pbits =
++ BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
++
++ /* Expand the platform_mask array if this fails. */
++ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
++ pbits * ARRAY_SIZE(info->platform_mask));
++
++ return p / pbits;
++}
++
++static __always_inline unsigned int
++__platform_mask_bit(const struct intel_runtime_info *info,
++ enum intel_platform p)
++{
++ const unsigned int pbits =
++ BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
++
++ return p % pbits + INTEL_SUBPLATFORM_BITS;
++}
++
++static inline u32
++intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
++{
++ const unsigned int pi = __platform_mask_index(info, p);
++
++ return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
++}
++
++static __always_inline bool
++IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
++{
++ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
++ const unsigned int pi = __platform_mask_index(info, p);
++ const unsigned int pb = __platform_mask_bit(info, p);
++
++ BUILD_BUG_ON(!__builtin_constant_p(p));
++
++ return info->platform_mask[pi] & BIT(pb);
++}
++
++static __always_inline bool
++IS_SUBPLATFORM(const struct drm_i915_private *i915,
++ enum intel_platform p, unsigned int s)
++{
++ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
++ const unsigned int pi = __platform_mask_index(info, p);
++ const unsigned int pb = __platform_mask_bit(info, p);
++ const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
++ const u32 mask = info->platform_mask[pi];
++
++ BUILD_BUG_ON(!__builtin_constant_p(p));
++ BUILD_BUG_ON(!__builtin_constant_p(s));
++ BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
++
++ /* Shift and test on the MSB position so sign flag can be used. */
++ return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
++}
+
+ #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
+
+@@ -2408,41 +2468,30 @@ intel_info(const struct drm_i915_private
+ #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+ #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
+-#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
+- ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
+- (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
+- (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
+-/* ULX machines are also considered ULT. */
+-#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
+- (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
++#define IS_BDW_ULT(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
++#define IS_BDW_ULX(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
+ #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
+ (dev_priv)->info.gt == 3)
+-#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
+- (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
++#define IS_HSW_ULT(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
+ #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
+ (dev_priv)->info.gt == 3)
+ /* ULX machines are also considered ULT. */
+-#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
+- INTEL_DEVID(dev_priv) == 0x0A1E)
+-#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
+- INTEL_DEVID(dev_priv) == 0x1913 || \
+- INTEL_DEVID(dev_priv) == 0x1916 || \
+- INTEL_DEVID(dev_priv) == 0x1921 || \
+- INTEL_DEVID(dev_priv) == 0x1926)
+-#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
+- INTEL_DEVID(dev_priv) == 0x1915 || \
+- INTEL_DEVID(dev_priv) == 0x191E)
+-#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
+- INTEL_DEVID(dev_priv) == 0x5913 || \
+- INTEL_DEVID(dev_priv) == 0x5916 || \
+- INTEL_DEVID(dev_priv) == 0x5921 || \
+- INTEL_DEVID(dev_priv) == 0x5926)
+-#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
+- INTEL_DEVID(dev_priv) == 0x5915 || \
+- INTEL_DEVID(dev_priv) == 0x591E)
+-#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
+- INTEL_DEVID(dev_priv) == 0x87C0 || \
+- INTEL_DEVID(dev_priv) == 0x87CA)
++#define IS_HSW_ULX(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
++#define IS_SKL_ULT(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
++#define IS_SKL_ULX(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
++#define IS_KBL_ULT(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
++#define IS_KBL_ULX(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
++#define IS_AML_ULX(dev_priv) \
++ (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
++ IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
+ #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (dev_priv)->info.gt == 2)
+ #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
+@@ -2453,14 +2502,16 @@ intel_info(const struct drm_i915_private
+ (dev_priv)->info.gt == 2)
+ #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
+ (dev_priv)->info.gt == 3)
+-#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
+- (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
++#define IS_CFL_ULT(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
+ #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
+ (dev_priv)->info.gt == 2)
+ #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
+ (dev_priv)->info.gt == 3)
+-#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
+- (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
++#define IS_CNL_WITH_PORT_F(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
++#define IS_ICL_WITH_PORT_F(dev_priv) \
++ IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
+
+ #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
+
+--- a/drivers/gpu/drm/i915/i915_gpu_error.c
++++ b/drivers/gpu/drm/i915/i915_gpu_error.c
+@@ -681,6 +681,9 @@ int i915_error_state_to_str(struct drm_i
+ err_printf(m, "Reset count: %u\n", error->reset_count);
+ err_printf(m, "Suspend count: %u\n", error->suspend_count);
+ err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
++ err_printf(m, "Subplatform: 0x%x\n",
++ intel_subplatform(&error->runtime_info,
++ error->device_info.platform));
+ err_print_pciid(m, error->i915);
+
+ err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -29,7 +29,7 @@
+ #include "i915_drv.h"
+ #include "i915_selftest.h"
+
+-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
++#define PLATFORM(x) .platform = (x)
+ #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
+
+ #define GEN_DEFAULT_PIPEOFFSETS \
+--- a/drivers/gpu/drm/i915/intel_device_info.c
++++ b/drivers/gpu/drm/i915/intel_device_info.c
+@@ -718,6 +718,99 @@ static u32 read_timestamp_frequency(stru
+ return 0;
+ }
+
++#undef INTEL_VGA_DEVICE
++#define INTEL_VGA_DEVICE(id, info) (id)
++
++static const u16 subplatform_ult_ids[] = {
++ INTEL_HSW_ULT_GT1_IDS(0),
++ INTEL_HSW_ULT_GT2_IDS(0),
++ INTEL_HSW_ULT_GT3_IDS(0),
++ INTEL_BDW_ULT_GT1_IDS(0),
++ INTEL_BDW_ULT_GT2_IDS(0),
++ INTEL_BDW_ULT_GT3_IDS(0),
++ INTEL_BDW_ULT_RSVD_IDS(0),
++ INTEL_SKL_ULT_GT1_IDS(0),
++ INTEL_SKL_ULT_GT2_IDS(0),
++ INTEL_SKL_ULT_GT3_IDS(0),
++ INTEL_KBL_ULT_GT1_IDS(0),
++ INTEL_KBL_ULT_GT2_IDS(0),
++ INTEL_KBL_ULT_GT3_IDS(0),
++ INTEL_CFL_U_GT2_IDS(0),
++ INTEL_CFL_U_GT3_IDS(0),
++ INTEL_WHL_U_GT1_IDS(0),
++ INTEL_WHL_U_GT2_IDS(0),
++ INTEL_WHL_U_GT3_IDS(0)
++};
++
++static const u16 subplatform_ulx_ids[] = {
++ INTEL_HSW_ULX_GT1_IDS(0),
++ INTEL_HSW_ULX_GT2_IDS(0),
++ INTEL_BDW_ULX_GT1_IDS(0),
++ INTEL_BDW_ULX_GT2_IDS(0),
++ INTEL_BDW_ULX_GT3_IDS(0),
++ INTEL_BDW_ULX_RSVD_IDS(0),
++ INTEL_SKL_ULX_GT1_IDS(0),
++ INTEL_SKL_ULX_GT2_IDS(0),
++ INTEL_KBL_ULX_GT1_IDS(0),
++ INTEL_KBL_ULX_GT2_IDS(0)
++};
++
++static const u16 subplatform_aml_ids[] = {
++ INTEL_AML_KBL_GT2_IDS(0),
++ INTEL_AML_CFL_GT2_IDS(0)
++};
++
++static const u16 subplatform_portf_ids[] = {
++ INTEL_CNL_PORT_F_IDS(0),
++ INTEL_ICL_PORT_F_IDS(0)
++};
++
++static bool find_devid(u16 id, const u16 *p, unsigned int num)
++{
++ for (; num; num--, p++) {
++ if (*p == id)
++ return true;
++ }
++
++ return false;
++}
++
++void intel_device_info_subplatform_init(struct drm_i915_private *i915)
++{
++ const struct intel_device_info *info = INTEL_INFO(i915);
++ const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
++ const unsigned int pi = __platform_mask_index(rinfo, info->platform);
++ const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
++ u16 devid = INTEL_DEVID(i915);
++ u32 mask;
++
++ /* Make sure IS_<platform> checks are working. */
++ RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
++
++ /* Find and mark subplatform bits based on the PCI device id. */
++ if (find_devid(devid, subplatform_ult_ids,
++ ARRAY_SIZE(subplatform_ult_ids))) {
++ mask = BIT(INTEL_SUBPLATFORM_ULT);
++ } else if (find_devid(devid, subplatform_ulx_ids,
++ ARRAY_SIZE(subplatform_ulx_ids))) {
++ mask = BIT(INTEL_SUBPLATFORM_ULX);
++ if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
++ /* ULX machines are also considered ULT. */
++ mask |= BIT(INTEL_SUBPLATFORM_ULT);
++ }
++ } else if (find_devid(devid, subplatform_aml_ids,
++ ARRAY_SIZE(subplatform_aml_ids))) {
++ mask = BIT(INTEL_SUBPLATFORM_AML);
++ } else if (find_devid(devid, subplatform_portf_ids,
++ ARRAY_SIZE(subplatform_portf_ids))) {
++ mask = BIT(INTEL_SUBPLATFORM_PORTF);
++ }
++
++ GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
++
++ RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
++}
++
+ /**
+ * intel_device_info_runtime_init - initialize runtime info
+ * @info: intel device info struct
+--- a/drivers/gpu/drm/i915/intel_device_info.h
++++ b/drivers/gpu/drm/i915/intel_device_info.h
+@@ -74,6 +74,21 @@ enum intel_platform {
+ INTEL_MAX_PLATFORMS
+ };
+
++/*
++ * Subplatform bits share the same namespace per parent platform. In other words
++ * it is fine for the same bit to be used on multiple parent platforms.
++ */
++
++#define INTEL_SUBPLATFORM_BITS (3)
++
++/* HSW/BDW/SKL/KBL/CFL */
++#define INTEL_SUBPLATFORM_ULT (0)
++#define INTEL_SUBPLATFORM_ULX (1)
++#define INTEL_SUBPLATFORM_AML (2)
++
++/* CNL/ICL */
++#define INTEL_SUBPLATFORM_PORTF (0)
++
+ #define DEV_INFO_FOR_EACH_FLAG(func) \
+ func(is_mobile); \
+ func(is_lp); \
+@@ -150,7 +165,6 @@ struct intel_device_info {
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+
+ enum intel_platform platform;
+- u32 platform_mask;
+
+ unsigned int page_sizes; /* page sizes supported by the HW */
+
+@@ -176,6 +190,16 @@ struct intel_device_info {
+ };
+
+ struct intel_runtime_info {
++ /*
++ * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
++ * into single runtime conditionals, and also to provide groundwork
++ * for future per platform, or per SKU build optimizations.
++ *
++ * Array can be extended when necessary if the corresponding
++ * BUILD_BUG_ON is hit.
++ */
++ u32 platform_mask[2];
++
+ u16 device_id;
+
+ u8 num_sprites[I915_MAX_PIPES];
+@@ -247,6 +271,7 @@ static inline void sseu_set_eus(struct s
+
+ const char *intel_platform_name(enum intel_platform platform);
+
++void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
+ void intel_device_info_runtime_init(struct intel_device_info *info);
+ void intel_device_info_dump(const struct intel_device_info *info,
+ struct drm_printer *p);
diff --git a/patches.drm/drm-i915-Mark-AML-0x87CA-as-ULX.patch b/patches.drm/drm-i915-Mark-AML-0x87CA-as-ULX.patch
new file mode 100644
index 0000000000..ab57d27fb2
--- /dev/null
+++ b/patches.drm/drm-i915-Mark-AML-0x87CA-as-ULX.patch
@@ -0,0 +1,44 @@
+From 4b9a3932e7ba929baa231231e61874c7a56f8959 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Fri, 22 Mar 2019 22:49:44 +0200
+Subject: [PATCH] drm/i915: Mark AML 0x87CA as ULX
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 4b9a3932e7ba929baa231231e61874c7a56f8959
+Patch-mainline: v5.1-rc3
+No-fix: 57b1c4460dc46a00f6ec439f3f11d670736b0209
+References: jsc#SLE-4986
+
+If I'm reading the spec right AML 0x87CA is a Y SKU, so it
+should be marked as ULX in our old style terminology.
+
+Cc: stable@vger.kernel.org
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Fixes: c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190322204944.23613-1-ville.syrjala@linux.intel.com
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+(cherry picked from commit 57b1c4460dc46a00f6ec439f3f11d670736b0209)
+
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2438,7 +2438,8 @@ intel_info(const struct drm_i915_private
+ INTEL_DEVID(dev_priv) == 0x5915 || \
+ INTEL_DEVID(dev_priv) == 0x591E)
+ #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
+- INTEL_DEVID(dev_priv) == 0x87C0)
++ INTEL_DEVID(dev_priv) == 0x87C0 || \
++ INTEL_DEVID(dev_priv) == 0x87CA)
+ #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (dev_priv)->info.gt == 2)
+ #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
diff --git a/patches.drm/drm-i915-Move-final-cleanup-of-drm_i915_private-to-i.patch b/patches.drm/drm-i915-Move-final-cleanup-of-drm_i915_private-to-i.patch
new file mode 100644
index 0000000000..eff7326818
--- /dev/null
+++ b/patches.drm/drm-i915-Move-final-cleanup-of-drm_i915_private-to-i.patch
@@ -0,0 +1,64 @@
+From 31962ca6a26087eea255c000ea9fa4ffbdad697b Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 5 Sep 2018 15:09:21 +0100
+Subject: [PATCH] drm/i915: Move final cleanup of drm_i915_private to i915_driver_destroy
+Git-commit: 31962ca6a26087eea255c000ea9fa4ffbdad697b
+Patch-mainline: v4.20-rc1
+References: jsc#SLE-4986
+
+Introduce a complementary function to i915_driver_create() to undo all
+that is created.
+
+Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180905140921.17467-2-chris@chris-wilson.co.uk
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -1353,6 +1353,17 @@ i915_driver_create(struct pci_dev *pdev,
+ return i915;
+ }
+
++static void i915_driver_destroy(struct drm_i915_private *i915)
++{
++ struct pci_dev *pdev = i915->drm.pdev;
++
++ drm_dev_fini(&i915->drm);
++ kfree(i915);
++
++ /* And make sure we never chase our dangling pointer from pci_dev */
++ pci_set_drvdata(pdev, NULL);
++}
++
+ /**
+ * i915_driver_load - setup chip and create an initial config
+ * @pdev: PCI device
+@@ -1446,9 +1457,7 @@ out_pci_disable:
+ pci_disable_device(pdev);
+ out_fini:
+ i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
+- drm_dev_fini(&dev_priv->drm);
+- kfree(dev_priv);
+- pci_set_drvdata(pdev, NULL);
++ i915_driver_destroy(dev_priv);
+ return ret;
+ }
+
+@@ -1497,9 +1506,7 @@ static void i915_driver_release(struct d
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ i915_driver_cleanup_early(dev_priv);
+- drm_dev_fini(&dev_priv->drm);
+-
+- kfree(dev_priv);
++ i915_driver_destroy(dev_priv);
+ }
+
+ static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
diff --git a/patches.drm/drm-i915-Remove-redundant-device-id-from-IS_IRONLAKE.patch b/patches.drm/drm-i915-Remove-redundant-device-id-from-IS_IRONLAKE.patch
new file mode 100644
index 0000000000..977c646223
--- /dev/null
+++ b/patches.drm/drm-i915-Remove-redundant-device-id-from-IS_IRONLAKE.patch
@@ -0,0 +1,61 @@
+From e08891a5b7e6d8b66c09bd6b0a1d3544083461c4 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Tue, 26 Mar 2019 07:40:55 +0000
+Subject: [PATCH] drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: e08891a5b7e6d8b66c09bd6b0a1d3544083461c4
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+IS_IRONLAKE_M can use the already defined intel_device_info.is_mobile for
+this platform, so remove the instance of Ironlake's mobile device id from
+the header file and replace it with an IS_MOBILE check.
+
+V2: * Improved commit text. (Chris)
+
+V3: * Rebased for EHL.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-3-tvrtko.ursulin@linux.intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2370,6 +2370,8 @@ intel_info(const struct drm_i915_private
+
+ #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+
++#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
++
+ #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
+ #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
+ #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
+@@ -2385,7 +2387,9 @@ intel_info(const struct drm_i915_private
+ #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
+ #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
+ #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
+-#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
++#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
++#define IS_IRONLAKE_M(dev_priv) \
++ (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
+ #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+ #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
+ (dev_priv)->info.gt == 1)
+@@ -2400,7 +2404,6 @@ intel_info(const struct drm_i915_private
+ #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
+ #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+ #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+-#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
+ #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
+ #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
diff --git a/patches.drm/drm-i915-Split-Pineview-device-info-into-desktop-and.patch b/patches.drm/drm-i915-Split-Pineview-device-info-into-desktop-and.patch
new file mode 100644
index 0000000000..bd50eaddbd
--- /dev/null
+++ b/patches.drm/drm-i915-Split-Pineview-device-info-into-desktop-and.patch
@@ -0,0 +1,119 @@
+From 86d35d4e7625f7c056d81316da107bd3a7564fb3 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Tue, 26 Mar 2019 07:40:54 +0000
+Subject: [PATCH] drm/i915: Split Pineview device info into desktop and mobile
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 86d35d4e7625f7c056d81316da107bd3a7564fb3
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+This allows the IS_PINEVIEW_<G|M> macros to be removed and avoid
+duplication of device ids already defined in i915_pciids.h.
+
+!IS_MOBILE check can be used in place of existing IS_PINEVIEW_G call
+sites.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-2-tvrtko.ursulin@linux.intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ arch/x86/kernel/early-quirks.c | 3 ++-
+ drivers/gpu/drm/i915/i915_drv.h | 2 --
+ drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++--
+ drivers/gpu/drm/i915/intel_pm.c | 4 ++--
+ include/drm/i915_pciids.h | 6 ++++--
+ 5 files changed, 18 insertions(+), 9 deletions(-)
+
+--- a/arch/x86/kernel/early-quirks.c
++++ b/arch/x86/kernel/early-quirks.c
+@@ -525,7 +525,8 @@ static const struct pci_device_id intel_
+ INTEL_I945G_IDS(&gen3_early_ops),
+ INTEL_I945GM_IDS(&gen3_early_ops),
+ INTEL_VLV_IDS(&gen6_early_ops),
+- INTEL_PINEVIEW_IDS(&gen3_early_ops),
++ INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
++ INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
+ INTEL_I965G_IDS(&gen3_early_ops),
+ INTEL_G33_IDS(&gen3_early_ops),
+ INTEL_I965GM_IDS(&gen3_early_ops),
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -2383,8 +2383,6 @@ intel_info(const struct drm_i915_private
+ #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
+ #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
+ #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
+-#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
+-#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
+ #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
+ #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
+ #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -163,7 +163,14 @@ static const struct intel_device_info in
+ .has_overlay = 1,
+ };
+
+-static const struct intel_device_info intel_pineview_info = {
++static const struct intel_device_info intel_pineview_g_info = {
++ GEN3_FEATURES,
++ PLATFORM(INTEL_PINEVIEW),
++ .has_hotplug = 1,
++ .has_overlay = 1,
++};
++
++static const struct intel_device_info intel_pineview_m_info = {
+ GEN3_FEATURES,
+ PLATFORM(INTEL_PINEVIEW),
+ .is_mobile = 1,
+@@ -625,7 +632,8 @@ static const struct pci_device_id pciidl
+ INTEL_I965GM_IDS(&intel_i965gm_info),
+ INTEL_GM45_IDS(&intel_gm45_info),
+ INTEL_G45_IDS(&intel_g45_info),
+- INTEL_PINEVIEW_IDS(&intel_pineview_info),
++ INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
++ INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
+ INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
+ INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+ INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
+--- a/drivers/gpu/drm/i915/intel_pm.c
++++ b/drivers/gpu/drm/i915/intel_pm.c
+@@ -846,7 +846,7 @@ static void pineview_update_wm(struct in
+ u32 reg;
+ unsigned int wm;
+
+- latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
++ latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
+ dev_priv->is_ddr3,
+ dev_priv->fsb_freq,
+ dev_priv->mem_freq);
+@@ -9372,7 +9372,7 @@ void intel_init_pm(struct drm_i915_priva
+ dev_priv->display.initial_watermarks = g4x_initial_watermarks;
+ dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
+ } else if (IS_PINEVIEW(dev_priv)) {
+- if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
++ if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
+ dev_priv->is_ddr3,
+ dev_priv->fsb_freq,
+ dev_priv->mem_freq)) {
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -108,8 +108,10 @@
+ INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
+ INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
+
+-#define INTEL_PINEVIEW_IDS(info) \
+- INTEL_VGA_DEVICE(0xa001, info), \
++#define INTEL_PINEVIEW_G_IDS(info) \
++ INTEL_VGA_DEVICE(0xa001, info)
++
++#define INTEL_PINEVIEW_M_IDS(info) \
+ INTEL_VGA_DEVICE(0xa011, info)
+
+ #define INTEL_IRONLAKE_D_IDS(info) \
diff --git a/patches.drm/drm-i915-Split-some-PCI-ids-into-separate-groups.patch b/patches.drm/drm-i915-Split-some-PCI-ids-into-separate-groups.patch
new file mode 100644
index 0000000000..f9ca73b49a
--- /dev/null
+++ b/patches.drm/drm-i915-Split-some-PCI-ids-into-separate-groups.patch
@@ -0,0 +1,351 @@
+From 4ae61358cc1ad537973b242cf390163a2f7b15b2 Mon Sep 17 00:00:00 2001
+From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Date: Tue, 26 Mar 2019 07:40:56 +0000
+Subject: [PATCH] drm/i915: Split some PCI ids into separate groups
+Git-commit: 4ae61358cc1ad537973b242cf390163a2f7b15b2
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+This will enable the following patch to consolidate most device ids into
+i915_pciids.h.
+
+While cross-referencing the ids listed in i915_drv.h, with the ones listed
+in i915_pciids.h, and also the comments in the latter, a bug for bug
+approach was used. This means two things:
+
+1.
+Some ids are only present in i915_drv.h - obviously this means those parts
+would not have been probed at all so they were not added to i915_pciids.h
+
+2.
+Some part type comments in i915_pciids.h were in disagreement with
+i915_drv.h. For instance parts labeled as ULT or ULX were not considered
+as such in i915_drv.h. The existing behaviour takes precedence here.
+
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Suggested-by: Jani Nikula <jani.nikula@intel.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-4-tvrtko.ursulin@linux.intel.com
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ include/drm/i915_pciids.h | 173 ++++++++++++++++++++++++++++++++--------------
+ 1 file changed, 124 insertions(+), 49 deletions(-)
+
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -168,7 +168,18 @@
+ #define INTEL_IVB_Q_IDS(info) \
+ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
+
++#define INTEL_HSW_ULT_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
++ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
++ INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
++ INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
++
++#define INTEL_HSW_ULX_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
++
+ #define INTEL_HSW_GT1_IDS(info) \
++ INTEL_HSW_ULT_GT1_IDS(info), \
++ INTEL_HSW_ULX_GT1_IDS(info), \
+ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
+@@ -177,20 +188,26 @@
+ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
+ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
+- INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+- INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+- INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
+ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
+- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
+- INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
+
++#define INTEL_HSW_ULT_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
++ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
++ INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
++ INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
++
++#define INTEL_HSW_ULX_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
++
+ #define INTEL_HSW_GT2_IDS(info) \
++ INTEL_HSW_ULT_GT2_IDS(info), \
++ INTEL_HSW_ULX_GT2_IDS(info), \
+ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+ INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
+@@ -199,9 +216,6 @@
+ INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
+ INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
+- INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+- INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
+ INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
+@@ -209,11 +223,17 @@
+ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
+- INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
+- INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
+
++#define INTEL_HSW_ULT_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
++ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
++ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
++ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
++ INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
++
+ #define INTEL_HSW_GT3_IDS(info) \
++ INTEL_HSW_ULT_GT3_IDS(info), \
+ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+ INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
+@@ -222,16 +242,11 @@
+ INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
+ INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
+- INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+- INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+- INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
+ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
+- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+- INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
+
+ #define INTEL_HSW_IDS(info) \
+@@ -247,35 +262,59 @@
+ INTEL_VGA_DEVICE(0x0157, info), \
+ INTEL_VGA_DEVICE(0x0155, info)
+
+-#define INTEL_BDW_GT1_IDS(info) \
+- INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
++#define INTEL_BDW_ULT_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+- INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+- INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
++ INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
++
++#define INTEL_BDW_ULX_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
++
++#define INTEL_BDW_GT1_IDS(info) \
++ INTEL_BDW_ULT_GT1_IDS(info), \
++ INTEL_BDW_ULX_GT1_IDS(info), \
++ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+ INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
+
+-#define INTEL_BDW_GT2_IDS(info) \
+- INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
++#define INTEL_BDW_ULT_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+- INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+- INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
++ INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
++
++#define INTEL_BDW_ULX_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
++
++#define INTEL_BDW_GT2_IDS(info) \
++ INTEL_BDW_ULT_GT2_IDS(info), \
++ INTEL_BDW_ULX_GT2_IDS(info), \
++ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+
++#define INTEL_BDW_ULT_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
++ INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
++
++#define INTEL_BDW_ULX_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x162E, info) /* ULX */
++
+ #define INTEL_BDW_GT3_IDS(info) \
++ INTEL_BDW_ULT_GT3_IDS(info), \
++ INTEL_BDW_ULX_GT3_IDS(info), \
+ INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+- INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+- INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+- INTEL_VGA_DEVICE(0x162E, info), /* ULX */\
+ INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
+
++#define INTEL_BDW_ULT_RSVD_IDS(info) \
++ INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
++ INTEL_VGA_DEVICE(0x163B, info) /* Iris */
++
++#define INTEL_BDW_ULX_RSVD_IDS(info) \
++ INTEL_VGA_DEVICE(0x163E, info) /* ULX */
++
+ #define INTEL_BDW_RSVD_IDS(info) \
++ INTEL_BDW_ULT_RSVD_IDS(info), \
++ INTEL_BDW_ULX_RSVD_IDS(info), \
+ INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+- INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+- INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+- INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
+ INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
+
+@@ -291,25 +330,40 @@
+ INTEL_VGA_DEVICE(0x22b2, info), \
+ INTEL_VGA_DEVICE(0x22b3, info)
+
++#define INTEL_SKL_ULT_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
++
++#define INTEL_SKL_ULX_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
++
+ #define INTEL_SKL_GT1_IDS(info) \
+- INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+- INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
++ INTEL_SKL_ULT_GT1_IDS(info), \
++ INTEL_SKL_ULX_GT1_IDS(info), \
+ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+-#define INTEL_SKL_GT2_IDS(info) \
++#define INTEL_SKL_ULT_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+- INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+- INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
++ INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
++
++#define INTEL_SKL_ULX_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
++
++#define INTEL_SKL_GT2_IDS(info) \
++ INTEL_SKL_ULT_GT2_IDS(info), \
++ INTEL_SKL_ULX_GT2_IDS(info), \
+ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+
++#define INTEL_SKL_ULT_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
++
+ #define INTEL_SKL_GT3_IDS(info) \
++ INTEL_SKL_ULT_GT3_IDS(info), \
+ INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+- INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
+@@ -338,29 +392,44 @@
+ INTEL_VGA_DEVICE(0x3184, info), \
+ INTEL_VGA_DEVICE(0x3185, info)
+
+-#define INTEL_KBL_GT1_IDS(info) \
+- INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+- INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
++#define INTEL_KBL_ULT_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
++ INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
++
++#define INTEL_KBL_ULX_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
++ INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
++
++#define INTEL_KBL_GT1_IDS(info) \
++ INTEL_KBL_ULT_GT1_IDS(info), \
++ INTEL_KBL_ULX_GT1_IDS(info), \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+-#define INTEL_KBL_GT2_IDS(info) \
++#define INTEL_KBL_ULT_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
++ INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
++
++#define INTEL_KBL_ULX_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
++
++#define INTEL_KBL_GT2_IDS(info) \
++ INTEL_KBL_ULT_GT2_IDS(info), \
++ INTEL_KBL_ULX_GT2_IDS(info), \
+ INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
+- INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+- INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
++#define INTEL_KBL_ULT_GT3_IDS(info) \
++ INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
++
+ #define INTEL_KBL_GT3_IDS(info) \
++ INTEL_KBL_ULT_GT3_IDS(info), \
+ INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
+- INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
+
+ #define INTEL_KBL_GT4_IDS(info) \
+@@ -467,7 +536,14 @@
+ INTEL_CML_GT2_IDS(info)
+
+ /* CNL */
++#define INTEL_CNL_PORT_F_IDS(info) \
++ INTEL_VGA_DEVICE(0x5A54, info), \
++ INTEL_VGA_DEVICE(0x5A5C, info), \
++ INTEL_VGA_DEVICE(0x5A44, info), \
++ INTEL_VGA_DEVICE(0x5A4C, info)
++
+ #define INTEL_CNL_IDS(info) \
++ INTEL_CNL_PORT_F_IDS(info), \
+ INTEL_VGA_DEVICE(0x5A51, info), \
+ INTEL_VGA_DEVICE(0x5A59, info), \
+ INTEL_VGA_DEVICE(0x5A41, info), \
+@@ -477,16 +553,11 @@
+ INTEL_VGA_DEVICE(0x5A42, info), \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
+ INTEL_VGA_DEVICE(0x5A50, info), \
+- INTEL_VGA_DEVICE(0x5A40, info), \
+- INTEL_VGA_DEVICE(0x5A54, info), \
+- INTEL_VGA_DEVICE(0x5A5C, info), \
+- INTEL_VGA_DEVICE(0x5A44, info), \
+- INTEL_VGA_DEVICE(0x5A4C, info)
++ INTEL_VGA_DEVICE(0x5A40, info)
+
+ /* ICL */
+-#define INTEL_ICL_11_IDS(info) \
++#define INTEL_ICL_PORT_F_IDS(info) \
+ INTEL_VGA_DEVICE(0x8A50, info), \
+- INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A59, info), \
+@@ -500,4 +571,8 @@
+ INTEL_VGA_DEVICE(0x8A70, info), \
+ INTEL_VGA_DEVICE(0x8A53, info)
+
++#define INTEL_ICL_11_IDS(info) \
++ INTEL_ICL_PORT_F_IDS(info), \
++ INTEL_VGA_DEVICE(0x8A51, info)
++
+ #endif /* _I915_PCIIDS_H */
diff --git a/patches.drm/drm-i915-aml-Add-new-Amber-Lake-PCI-ID.patch b/patches.drm/drm-i915-aml-Add-new-Amber-Lake-PCI-ID.patch
new file mode 100644
index 0000000000..2deff0edb1
--- /dev/null
+++ b/patches.drm/drm-i915-aml-Add-new-Amber-Lake-PCI-ID.patch
@@ -0,0 +1,93 @@
+From c0c46ca461f136a0ae1ed69da6c874e850aeeb53 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
+Date: Wed, 26 Sep 2018 18:06:50 -0700
+Subject: [PATCH] drm/i915/aml: Add new Amber Lake PCI ID
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: c0c46ca461f136a0ae1ed69da6c874e850aeeb53
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-4986
+
+This new AML PCI ID uses the same gen graphics as Coffe Lake not a
+Kaby Lake one like the other AMLs.
+
+So to make it more explicit renaming INTEL_AML_GT2_IDS to
+INTEL_AML_KBL_GT2_IDS and naming this id as INTEL_AML_CFL_GT2_IDS.
+
+V2:
+- missed add new AML macro to INTEL_CFL_IDS()
+- added derivated platform initials to AML macros
+
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180927010650.22731-1-jose.souza@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_pci.c | 3 ++-
+ include/drm/i915_pciids.h | 11 ++++++++---
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
+index 9ddd2db906ce..0a05cc7ace14 100644
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -660,7 +660,7 @@ static const struct pci_device_id pciidlist[] = {
+ INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
+ INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
+ INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
+- INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info),
++ INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
+ INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
+@@ -668,6 +668,7 @@ static const struct pci_device_id pciidlist[] = {
+ INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+ INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
++ INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+ INTEL_CNL_IDS(&intel_cannonlake_info),
+ INTEL_ICL_11_IDS(&intel_icelake_11_info),
+diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+index c8d3d541ad01..192667144693 100644
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -365,16 +365,20 @@
+ INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
+
+ /* AML/KBL Y GT2 */
+-#define INTEL_AML_GT2_IDS(info) \
++#define INTEL_AML_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
+
++/* AML/CFL Y GT2 */
++#define INTEL_AML_CFL_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x87CA, info)
++
+ #define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info), \
+- INTEL_AML_GT2_IDS(info)
++ INTEL_AML_KBL_GT2_IDS(info)
+
+ /* CFL S */
+ #define INTEL_CFL_S_GT1_IDS(info) \
+@@ -427,7 +431,8 @@
+ INTEL_CFL_U_GT3_IDS(info), \
+ INTEL_WHL_U_GT1_IDS(info), \
+ INTEL_WHL_U_GT2_IDS(info), \
+- INTEL_WHL_U_GT3_IDS(info)
++ INTEL_WHL_U_GT3_IDS(info), \
++ INTEL_AML_CFL_GT2_IDS(info)
+
+ /* CNL */
+ #define INTEL_CNL_IDS(info) \
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-cfl-Adding-another-PCI-Device-ID.patch b/patches.drm/drm-i915-cfl-Adding-another-PCI-Device-ID.patch
new file mode 100644
index 0000000000..79a1e43494
--- /dev/null
+++ b/patches.drm/drm-i915-cfl-Adding-another-PCI-Device-ID.patch
@@ -0,0 +1,67 @@
+From 5e0f5a58b167fc2c8352d90c0faa8c0c9ca75c26 Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Fri, 1 Feb 2019 15:50:49 -0800
+Subject: [PATCH] drm/i915/cfl: Adding another PCI Device ID.
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 5e0f5a58b167fc2c8352d90c0faa8c0c9ca75c26
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-4986
+
+While cross checking PCI IDs from Intel Media SDK
+and kernel Dmitry noticed this gap. So we checked the
+spec and this new ID had been recently added.
+
+V2: Adding new H_GT1 entry to i915_pci.c (Jose)
+
+Reported-by: Dmitry Rogozhkin<dmitry.v.rogozhkin@intel.com>
+Cc: Dmitry Rogozhkin<dmitry.v.rogozhkin@intel.com>
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190201235049.27206-1-rodrigo.vivi@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_pci.c | 1 +
+ include/drm/i915_pciids.h | 4 ++++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
+index 6f7ad10f34b8..55c9058e91a8 100644
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -711,6 +711,7 @@ static const struct pci_device_id pciidlist[] = {
+ INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
+ INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
++ INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+index df72be7e8b88..d2fad7b0fcf6 100644
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -394,6 +394,9 @@
+ INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
+
+ /* CFL H */
++#define INTEL_CFL_H_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x3E9C, info)
++
+ #define INTEL_CFL_H_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+@@ -426,6 +429,7 @@
+ #define INTEL_CFL_IDS(info) \
+ INTEL_CFL_S_GT1_IDS(info), \
+ INTEL_CFL_S_GT2_IDS(info), \
++ INTEL_CFL_H_GT1_IDS(info), \
+ INTEL_CFL_H_GT2_IDS(info), \
+ INTEL_CFL_U_GT2_IDS(info), \
+ INTEL_CFL_U_GT3_IDS(info), \
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-cml-Add-CML-PCI-IDS.patch b/patches.drm/drm-i915-cml-Add-CML-PCI-IDS.patch
new file mode 100644
index 0000000000..c02b53ae64
--- /dev/null
+++ b/patches.drm/drm-i915-cml-Add-CML-PCI-IDS.patch
@@ -0,0 +1,93 @@
+From a7b4deeb02b978bc59808cb13c93ba84f01023a4 Mon Sep 17 00:00:00 2001
+From: Anusha Srivatsa <anusha.srivatsa@intel.com>
+Date: Mon, 18 Mar 2019 13:01:32 -0700
+Subject: [PATCH] drm/i915/cml: Add CML PCI IDS
+Git-commit: a7b4deeb02b978bc59808cb13c93ba84f01023a4
+Patch-mainline: v5.2-rc1
+References: jsc#SLE-4986
+
+Comet Lake is a Intel Processor containing Gen9
+Intel HD Graphics. This patch adds the initial set of
+PCI IDs. Comet Lake comes off of Coffee Lake - adding
+the IDs to Coffee Lake ID list.
+
+More support and features will be in the patches that follow.
+
+V2: Split IDs according to GT. (Rodrigo)
+
+V3: Update IDs.
+
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
+Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190318200133.9666-1-anusha.srivatsa@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_pci.c | 2 ++
+ include/drm/i915_pciids.h | 28 +++++++++++++++++++++++++++-
+ 2 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
+index ef7410c492fd..7a6054eadb8e 100644
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -795,6 +795,8 @@ static const struct pci_device_id pciidlist[] = {
+ INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
++ INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
++ INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CNL_IDS(&intel_cannonlake_info),
+ INTEL_ICL_11_IDS(&intel_icelake_11_info),
+ {0, 0, 0}
+diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+index d200000feeaa..291b5e3fa59c 100644
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -373,6 +373,30 @@
+ #define INTEL_AML_CFL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x87CA, info)
+
++/* CML GT1 */
++#define INTEL_CML_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x9B21, info), \
++ INTEL_VGA_DEVICE(0x9BAA, info), \
++ INTEL_VGA_DEVICE(0x9BAB, info), \
++ INTEL_VGA_DEVICE(0x9BAC, info), \
++ INTEL_VGA_DEVICE(0x9BA0, info), \
++ INTEL_VGA_DEVICE(0x9BA5, info), \
++ INTEL_VGA_DEVICE(0x9BA8, info), \
++ INTEL_VGA_DEVICE(0x9BA4, info), \
++ INTEL_VGA_DEVICE(0x9BA2, info)
++
++/* CML GT2 */
++#define INTEL_CML_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x9B41, info), \
++ INTEL_VGA_DEVICE(0x9BCA, info), \
++ INTEL_VGA_DEVICE(0x9BCB, info), \
++ INTEL_VGA_DEVICE(0x9BCC, info), \
++ INTEL_VGA_DEVICE(0x9BC0, info), \
++ INTEL_VGA_DEVICE(0x9BC5, info), \
++ INTEL_VGA_DEVICE(0x9BC8, info), \
++ INTEL_VGA_DEVICE(0x9BC4, info), \
++ INTEL_VGA_DEVICE(0x9BC2, info)
++
+ #define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+@@ -436,7 +460,9 @@
+ INTEL_WHL_U_GT1_IDS(info), \
+ INTEL_WHL_U_GT2_IDS(info), \
+ INTEL_WHL_U_GT3_IDS(info), \
+- INTEL_AML_CFL_GT2_IDS(info)
++ INTEL_AML_CFL_GT2_IDS(info), \
++ INTEL_CML_GT1_IDS(info), \
++ INTEL_CML_GT2_IDS(info)
+
+ /* CNL */
+ #define INTEL_CNL_IDS(info) \
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-icl-Adding-few-more-device-IDs-for-Ice-Lake.patch b/patches.drm/drm-i915-icl-Adding-few-more-device-IDs-for-Ice-Lake.patch
new file mode 100644
index 0000000000..303efcbe08
--- /dev/null
+++ b/patches.drm/drm-i915-icl-Adding-few-more-device-IDs-for-Ice-Lake.patch
@@ -0,0 +1,48 @@
+From 03ca3cf8e9aa7549e6c398462af0f68bdd43e7fe Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Thu, 17 Jan 2019 21:59:43 -0800
+Subject: [PATCH] drm/i915/icl: Adding few more device IDs for Ice Lake
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 03ca3cf8e9aa7549e6c398462af0f68bdd43e7fe
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-4986
+
+We just got aware that there was more IDs available
+at spec, so let's add them already.
+
+Cc: James Ausmus <james.ausmus@intel.com>
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190118055943.10252-1-rodrigo.vivi@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ include/drm/i915_pciids.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+index 192667144693..df72be7e8b88 100644
+--- a/include/drm/i915_pciids.h
++++ b/include/drm/i915_pciids.h
+@@ -457,9 +457,13 @@
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
++ INTEL_VGA_DEVICE(0x8A59, info), \
++ INTEL_VGA_DEVICE(0x8A58, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
++ INTEL_VGA_DEVICE(0x8A57, info), \
++ INTEL_VGA_DEVICE(0x8A56, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
+
+--
+2.16.4
+
diff --git a/patches.drm/drm-i915-start-moving-runtime-device-info-to-a-separ.patch b/patches.drm/drm-i915-start-moving-runtime-device-info-to-a-separ.patch
new file mode 100644
index 0000000000..95f8a1911c
--- /dev/null
+++ b/patches.drm/drm-i915-start-moving-runtime-device-info-to-a-separ.patch
@@ -0,0 +1,734 @@
+From 0258404f9d3859b89f7b816f0549dd7d4357de01 Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Mon, 31 Dec 2018 16:56:41 +0200
+Subject: [PATCH] drm/i915: start moving runtime device info to a separate struct
+Git-commit: 0258404f9d3859b89f7b816f0549dd7d4357de01
+Patch-mainline: v5.1-rc1
+References: jsc#SLE-4986
+
+First move the low hanging fruit, the fields that are only initialized
+runtime. Use RUNTIME_INFO() exclusively to access the fields.
+
+Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/c24fe7a4b0492a888690c46814c0ff21ce2f12b1.1546267488.git.jani.nikula@intel.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++-----
+ drivers/gpu/drm/i915/i915_drv.c | 16 +++---
+ drivers/gpu/drm/i915/i915_drv.h | 4 +
+ drivers/gpu/drm/i915/i915_gpu_error.c | 9 ++-
+ drivers/gpu/drm/i915/i915_gpu_error.h | 1
+ drivers/gpu/drm/i915/i915_perf.c | 4 -
+ drivers/gpu/drm/i915/i915_query.c | 2
+ drivers/gpu/drm/i915/intel_device_info.c | 56 +++++++++++-----------
+ drivers/gpu/drm/i915/intel_device_info.h | 25 +++++----
+ drivers/gpu/drm/i915/intel_display.c | 2
+ drivers/gpu/drm/i915/intel_display.h | 6 +-
+ drivers/gpu/drm/i915/intel_engine_cs.c | 4 -
+ drivers/gpu/drm/i915/intel_lrc.c | 14 ++---
+ drivers/gpu/drm/i915/intel_pm.c | 2
+ drivers/gpu/drm/i915/intel_ringbuffer.c | 4 -
+ drivers/gpu/drm/i915/intel_ringbuffer.h | 4 -
+ drivers/gpu/drm/i915/intel_workarounds.c | 6 +-
+ drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 -
+ 18 files changed, 101 insertions(+), 88 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_debugfs.c
++++ b/drivers/gpu/drm/i915/i915_debugfs.c
+@@ -47,7 +47,7 @@ static int i915_capabilities(struct seq_
+ seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
+
+ intel_device_info_dump_flags(info, &p);
+- intel_device_info_dump_runtime(info, &p);
++ intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
+ intel_driver_caps_print(&dev_priv->caps, &p);
+
+ kernel_param_lock(THIS_MODULE);
+@@ -3255,7 +3255,7 @@ static int i915_engine_info(struct seq_f
+ seq_printf(m, "Global active requests: %d\n",
+ dev_priv->gt.active_requests);
+ seq_printf(m, "CS timestamp frequency: %u kHz\n",
+- dev_priv->info.cs_timestamp_frequency_khz);
++ RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
+
+ p = drm_seq_file_printer(m);
+ for_each_engine(engine, dev_priv, id)
+@@ -3271,7 +3271,7 @@ static int i915_rcs_topology(struct seq_
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct drm_printer p = drm_seq_file_printer(m);
+
+- intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
++ intel_device_info_dump_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
+
+ return 0;
+ }
+@@ -4275,7 +4275,7 @@ static void gen10_sseu_device_status(str
+ struct sseu_dev_info *sseu)
+ {
+ #define SS_MAX 6
+- const struct intel_device_info *info = INTEL_INFO(dev_priv);
++ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
+ int s, ss;
+
+@@ -4331,7 +4331,7 @@ static void gen9_sseu_device_status(stru
+ struct sseu_dev_info *sseu)
+ {
+ #define SS_MAX 3
+- const struct intel_device_info *info = INTEL_INFO(dev_priv);
++ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
+ int s, ss;
+
+@@ -4359,7 +4359,7 @@ static void gen9_sseu_device_status(stru
+
+ if (IS_GEN9_BC(dev_priv))
+ sseu->subslice_mask[s] =
+- INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
++ RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+
+ for (ss = 0; ss < info->sseu.max_subslices; ss++) {
+ unsigned int eu_cnt;
+@@ -4393,10 +4393,10 @@ static void broadwell_sseu_device_status
+
+ if (sseu->slice_mask) {
+ sseu->eu_per_subslice =
+- INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
++ RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++) {
+ sseu->subslice_mask[s] =
+- INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
++ RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ }
+ sseu->eu_total = sseu->eu_per_subslice *
+ sseu_subslice_total(sseu);
+@@ -4404,7 +4404,7 @@ static void broadwell_sseu_device_status
+ /* subtract fused off EU(s) from enabled slice(s) */
+ for (s = 0; s < fls(sseu->slice_mask); s++) {
+ u8 subslice_7eu =
+- INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
++ RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+
+ sseu->eu_total -= hweight8(subslice_7eu);
+ }
+@@ -4457,14 +4457,14 @@ static int i915_sseu_status(struct seq_f
+ return -ENODEV;
+
+ seq_puts(m, "SSEU Device Info\n");
+- i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
++ i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+
+ seq_puts(m, "SSEU Device Status\n");
+ memset(&sseu, 0, sizeof(sseu));
+- sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
+- sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
++ sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
++ sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
+ sseu.max_eus_per_subslice =
+- INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
++ RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+
+ intel_runtime_pm_get(dev_priv);
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -357,12 +357,12 @@ static int i915_getparam_ioctl(struct dr
+ value = i915_cmd_parser_get_version(dev_priv);
+ break;
+ case I915_PARAM_SUBSLICE_TOTAL:
+- value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
++ value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
+ if (!value)
+ return -ENODEV;
+ break;
+ case I915_PARAM_EU_TOTAL:
+- value = INTEL_INFO(dev_priv)->sseu.eu_total;
++ value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ if (!value)
+ return -ENODEV;
+ break;
+@@ -379,7 +379,7 @@ static int i915_getparam_ioctl(struct dr
+ value = HAS_POOLED_EU(dev_priv);
+ break;
+ case I915_PARAM_MIN_EU_IN_POOL:
+- value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
++ value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ break;
+ case I915_PARAM_HUC_STATUS:
+ value = intel_huc_check_status(&dev_priv->huc);
+@@ -429,17 +429,17 @@ static int i915_getparam_ioctl(struct dr
+ value = intel_engines_has_context_isolation(dev_priv);
+ break;
+ case I915_PARAM_SLICE_MASK:
+- value = INTEL_INFO(dev_priv)->sseu.slice_mask;
++ value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ if (!value)
+ return -ENODEV;
+ break;
+ case I915_PARAM_SUBSLICE_MASK:
+- value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
++ value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ if (!value)
+ return -ENODEV;
+ break;
+ case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
+- value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
++ value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
+ break;
+ default:
+ DRM_DEBUG("Unknown parameter %d\n", param->param);
+@@ -1311,7 +1311,7 @@ static void i915_welcome_messages(struct
+ struct drm_printer p = drm_debug_printer("i915 device info:");
+
+ intel_device_info_dump(&dev_priv->info, &p);
+- intel_device_info_dump_runtime(&dev_priv->info, &p);
++ intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
+ }
+
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
+@@ -1344,7 +1344,7 @@ i915_driver_create(struct pci_dev *pdev,
+ /* Setup the write-once "constant" device info */
+ device_info = mkwrite_device_info(i915);
+ memcpy(device_info, match_info, sizeof(*device_info));
+- device_info->device_id = pdev->device;
++ RUNTIME_INFO(i915)->device_id = pdev->device;
+
+ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+ sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -1587,6 +1587,7 @@ struct drm_i915_private {
+ struct kmem_cache *priorities;
+
+ const struct intel_device_info info;
++ struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
+ struct intel_driver_caps caps;
+
+ /**
+@@ -2335,10 +2336,11 @@ intel_info(const struct drm_i915_private
+ }
+
+ #define INTEL_INFO(dev_priv) intel_info((dev_priv))
++#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
+ #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
+
+ #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
+-#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
++#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
+
+ #define REVID_FOREVER 0xff
+ #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
+--- a/drivers/gpu/drm/i915/i915_gpu_error.c
++++ b/drivers/gpu/drm/i915/i915_gpu_error.c
+@@ -591,13 +591,14 @@ static void print_error_obj(struct drm_i
+
+ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
+ const struct intel_device_info *info,
++ const struct intel_runtime_info *runtime,
+ const struct intel_driver_caps *caps)
+ {
+ struct drm_printer p = i915_error_printer(m);
+
+ intel_device_info_dump_flags(info, &p);
+ intel_driver_caps_print(caps, &p);
+- intel_device_info_dump_topology(&info->sseu, &p);
++ intel_device_info_dump_topology(&runtime->sseu, &p);
+ }
+
+ static void err_print_params(struct drm_i915_error_state_buf *m,
+@@ -829,7 +830,8 @@ int i915_error_state_to_str(struct drm_i
+ if (error->display)
+ intel_display_print_error_state(m, error->display);
+
+- err_print_capabilities(m, &error->device_info, &error->driver_caps);
++ err_print_capabilities(m, &error->device_info, &error->runtime_info,
++ &error->driver_caps);
+ err_print_params(m, &error->params);
+ err_print_uc(m, &error->uc);
+
+@@ -1746,6 +1748,9 @@ static void capture_gen_state(struct i91
+ memcpy(&error->device_info,
+ INTEL_INFO(i915),
+ sizeof(error->device_info));
++ memcpy(&error->runtime_info,
++ RUNTIME_INFO(i915),
++ sizeof(error->runtime_info));
+ error->driver_caps = i915->caps;
+ }
+
+--- a/drivers/gpu/drm/i915/i915_gpu_error.h
++++ b/drivers/gpu/drm/i915/i915_gpu_error.h
+@@ -45,6 +45,7 @@ struct i915_gpu_state {
+ u32 reset_count;
+ u32 suspend_count;
+ struct intel_device_info device_info;
++ struct intel_runtime_info runtime_info;
+ struct intel_driver_caps driver_caps;
+ struct i915_params params;
+
+--- a/drivers/gpu/drm/i915/i915_perf.c
++++ b/drivers/gpu/drm/i915/i915_perf.c
+@@ -2743,7 +2743,7 @@ err:
+ static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
+ {
+ return div64_u64(1000000000ULL * (2ULL << exponent),
+- 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
++ 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
+ }
+
+ /**
+@@ -3571,7 +3571,7 @@ void i915_perf_init(struct drm_i915_priv
+ spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
+
+ oa_sample_rate_hard_limit = 1000 *
+- (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
++ (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
+ dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
+
+ mutex_init(&dev_priv->perf.metrics_lock);
+--- a/drivers/gpu/drm/i915/i915_query.c
++++ b/drivers/gpu/drm/i915/i915_query.c
+@@ -13,7 +13,7 @@
+ static int query_topology_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+ {
+- const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
++ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct drm_i915_query_topology_info topo;
+ u32 slice_length, subslice_length, eu_length, total_length;
+
+--- a/drivers/gpu/drm/i915/intel_device_info.c
++++ b/drivers/gpu/drm/i915/intel_device_info.c
+@@ -100,7 +100,7 @@ static void sseu_dump(const struct sseu_
+ drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
+ }
+
+-void intel_device_info_dump_runtime(const struct intel_device_info *info,
++void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
+ struct drm_printer *p)
+ {
+ sseu_dump(&info->sseu, p);
+@@ -160,7 +160,7 @@ static u16 compute_eu_total(const struct
+
+ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ u8 s_en;
+ u32 ss_en, ss_en_mask;
+ u8 eu_en;
+@@ -199,7 +199,7 @@ static void gen11_sseu_info_init(struct
+
+ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ const u32 fuse2 = I915_READ(GEN8_FUSE2);
+ int s, ss;
+ const int eu_mask = 0xff;
+@@ -276,7 +276,7 @@ static void gen10_sseu_info_init(struct
+
+ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ u32 fuse;
+
+ fuse = I915_READ(CHV_FUSE_GT);
+@@ -330,7 +330,7 @@ static void cherryview_sseu_info_init(st
+ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+ struct intel_device_info *info = mkwrite_device_info(dev_priv);
+- struct sseu_dev_info *sseu = &info->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ int s, ss;
+ u32 fuse2, eu_disable, subslice_mask;
+ const u8 eu_mask = 0xff;
+@@ -433,7 +433,7 @@ static void gen9_sseu_info_init(struct d
+
+ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ int s, ss;
+ u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
+
+@@ -515,8 +515,7 @@ static void broadwell_sseu_info_init(str
+
+ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
+ {
+- struct intel_device_info *info = mkwrite_device_info(dev_priv);
+- struct sseu_dev_info *sseu = &info->sseu;
++ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ u32 fuse1;
+ int s, ss;
+
+@@ -524,9 +523,9 @@ static void haswell_sseu_info_init(struc
+ * There isn't a register to tell us how many slices/subslices. We
+ * work off the PCI-ids here.
+ */
+- switch (info->gt) {
++ switch (INTEL_INFO(dev_priv)->gt) {
+ default:
+- MISSING_CASE(info->gt);
++ MISSING_CASE(INTEL_INFO(dev_priv)->gt);
+ /* fall through */
+ case 1:
+ sseu->slice_mask = BIT(0);
+@@ -739,15 +738,16 @@ void intel_device_info_runtime_init(stru
+ {
+ struct drm_i915_private *dev_priv =
+ container_of(info, struct drm_i915_private, info);
++ struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
+ enum pipe pipe;
+
+ if (INTEL_GEN(dev_priv) >= 10) {
+ for_each_pipe(dev_priv, pipe)
+- info->num_scalers[pipe] = 2;
++ runtime->num_scalers[pipe] = 2;
+ } else if (INTEL_GEN(dev_priv) == 9) {
+- info->num_scalers[PIPE_A] = 2;
+- info->num_scalers[PIPE_B] = 2;
+- info->num_scalers[PIPE_C] = 1;
++ runtime->num_scalers[PIPE_A] = 2;
++ runtime->num_scalers[PIPE_B] = 2;
++ runtime->num_scalers[PIPE_C] = 1;
+ }
+
+ BUILD_BUG_ON(I915_NUM_ENGINES >
+@@ -763,17 +763,17 @@ void intel_device_info_runtime_init(stru
+ */
+ if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
+ for_each_pipe(dev_priv, pipe)
+- info->num_sprites[pipe] = 3;
++ runtime->num_sprites[pipe] = 3;
+ else if (IS_BROXTON(dev_priv)) {
+- info->num_sprites[PIPE_A] = 2;
+- info->num_sprites[PIPE_B] = 2;
+- info->num_sprites[PIPE_C] = 1;
++ runtime->num_sprites[PIPE_A] = 2;
++ runtime->num_sprites[PIPE_B] = 2;
++ runtime->num_sprites[PIPE_C] = 1;
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ for_each_pipe(dev_priv, pipe)
+- info->num_sprites[pipe] = 2;
++ runtime->num_sprites[pipe] = 2;
+ } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+ for_each_pipe(dev_priv, pipe)
+- info->num_sprites[pipe] = 1;
++ runtime->num_sprites[pipe] = 1;
+ }
+
+ if (i915_modparams.disable_display) {
+@@ -852,7 +852,7 @@ void intel_device_info_runtime_init(stru
+ gen11_sseu_info_init(dev_priv);
+
+ /* Initialize command stream timestamp frequency */
+- info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
++ runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
+ }
+
+ void intel_driver_caps_print(const struct intel_driver_caps *caps,
+@@ -880,27 +880,27 @@ void intel_device_info_init_mmio(struct
+
+ media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
+
+- info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+- info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+- GEN11_GT_VEBOX_DISABLE_SHIFT;
++ RUNTIME_INFO(dev_priv)->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
++ RUNTIME_INFO(dev_priv)->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
++ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+- DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
++ DRM_DEBUG_DRIVER("vdbox enable: %04x\n", RUNTIME_INFO(dev_priv)->vdbox_enable);
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(dev_priv, _VCS(i)))
+ continue;
+
+- if (!(BIT(i) & info->vdbox_enable)) {
++ if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vdbox_enable)) {
+ info->ring_mask &= ~ENGINE_MASK(_VCS(i));
+ DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
+ }
+ }
+
+- DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
++ DRM_DEBUG_DRIVER("vebox enable: %04x\n", RUNTIME_INFO(dev_priv)->vebox_enable);
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(dev_priv, _VECS(i)))
+ continue;
+
+- if (!(BIT(i) & info->vebox_enable)) {
++ if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vebox_enable)) {
+ info->ring_mask &= ~ENGINE_MASK(_VECS(i));
+ DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
+ }
+--- a/drivers/gpu/drm/i915/intel_device_info.h
++++ b/drivers/gpu/drm/i915/intel_device_info.h
+@@ -143,12 +143,10 @@ struct sseu_dev_info {
+ typedef u8 intel_ring_mask_t;
+
+ struct intel_device_info {
+- u16 device_id;
+ u16 gen_mask;
+
+ u8 gen;
+ u8 gt; /* GT number, 0 if undefined */
+- u8 num_rings;
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+
+ enum intel_platform platform;
+@@ -159,8 +157,6 @@ struct intel_device_info {
+ u32 display_mmio_offset;
+
+ u8 num_pipes;
+- u8 num_sprites[I915_MAX_PIPES];
+- u8 num_scalers[I915_MAX_PIPES];
+
+ #define DEFINE_FLAG(name) u8 name:1
+ DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
+@@ -173,6 +169,20 @@ struct intel_device_info {
+ int palette_offsets[I915_MAX_PIPES];
+ int cursor_offsets[I915_MAX_PIPES];
+
++ struct color_luts {
++ u16 degamma_lut_size;
++ u16 gamma_lut_size;
++ } color;
++};
++
++struct intel_runtime_info {
++ u16 device_id;
++
++ u8 num_sprites[I915_MAX_PIPES];
++ u8 num_scalers[I915_MAX_PIPES];
++
++ u8 num_rings;
++
+ /* Slice/subslice/EU info */
+ struct sseu_dev_info sseu;
+
+@@ -181,11 +191,6 @@ struct intel_device_info {
+ /* Enabled (not fused off) media engine bitmasks. */
+ u8 vdbox_enable;
+ u8 vebox_enable;
+-
+- struct color_luts {
+- u16 degamma_lut_size;
+- u16 gamma_lut_size;
+- } color;
+ };
+
+ struct intel_driver_caps {
+@@ -247,7 +252,7 @@ void intel_device_info_dump(const struct
+ struct drm_printer *p);
+ void intel_device_info_dump_flags(const struct intel_device_info *info,
+ struct drm_printer *p);
+-void intel_device_info_dump_runtime(const struct intel_device_info *info,
++void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
+ struct drm_printer *p);
+ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+ struct drm_printer *p);
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -13993,7 +13993,7 @@ static void intel_crtc_init_scalers(stru
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int i;
+
+- crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
++ crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
+ if (!crtc->num_scalers)
+ return;
+
+--- a/drivers/gpu/drm/i915/intel_display.h
++++ b/drivers/gpu/drm/i915/intel_display.h
+@@ -85,7 +85,7 @@ enum i9xx_plane_id {
+ };
+
+ #define plane_name(p) ((p) + 'A')
+-#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
++#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+
+ /*
+ * Per-pipe plane identifier.
+@@ -271,12 +271,12 @@ struct intel_link_m_n {
+
+ #define for_each_universal_plane(__dev_priv, __pipe, __p) \
+ for ((__p) = 0; \
+- (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
++ (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
+ (__p)++)
+
+ #define for_each_sprite(__dev_priv, __p, __s) \
+ for ((__s) = 0; \
+- (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
++ (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
+ (__s)++)
+
+ #define for_each_port_masked(__port, __ports_mask) \
+--- a/drivers/gpu/drm/i915/intel_engine_cs.c
++++ b/drivers/gpu/drm/i915/intel_engine_cs.c
+@@ -362,7 +362,7 @@ int intel_engines_init_mmio(struct drm_i
+ goto cleanup;
+ }
+
+- device_info->num_rings = hweight32(mask);
++ RUNTIME_INFO(dev_priv)->num_rings = hweight32(mask);
+
+ i915_check_and_clear_faults(dev_priv);
+
+@@ -815,7 +815,7 @@ const char *i915_cache_level_str(struct
+
+ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
+ {
+- const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
++ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ u32 mcr_s_ss_select;
+ u32 slice = fls(sseu->slice_mask);
+ u32 subslice = fls(sseu->subslice_mask[slice]);
+--- a/drivers/gpu/drm/i915/intel_lrc.c
++++ b/drivers/gpu/drm/i915/intel_lrc.c
+@@ -2502,9 +2502,9 @@ int logical_xcs_ring_init(struct intel_e
+ static u32
+ make_rpcs(struct drm_i915_private *dev_priv)
+ {
+- bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
+- u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+- u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
++ bool subslice_pg = RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg;
++ u8 slices = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
++ u8 subslices = hweight8(RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]);
+ u32 rpcs = 0;
+
+ /*
+@@ -2552,7 +2552,7 @@ make_rpcs(struct drm_i915_private *dev_p
+ * must make an explicit request through RPCS for full
+ * enablement.
+ */
+- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
++ if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
+ u32 mask, val = slices;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+@@ -2580,17 +2580,17 @@ make_rpcs(struct drm_i915_private *dev_p
+ rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
+ }
+
+- if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
++ if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
+ u32 val;
+
+- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
++ val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice <<
+ GEN8_RPCS_EU_MIN_SHIFT;
+ GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
+ val &= GEN8_RPCS_EU_MIN_MASK;
+
+ rpcs |= val;
+
+- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
++ val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice <<
+ GEN8_RPCS_EU_MAX_SHIFT;
+ GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
+ val &= GEN8_RPCS_EU_MAX_MASK;
+--- a/drivers/gpu/drm/i915/intel_pm.c
++++ b/drivers/gpu/drm/i915/intel_pm.c
+@@ -7233,7 +7233,7 @@ static int cherryview_rps_max_freq(struc
+
+ val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+
+- switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
++ switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) {
+ case 8:
+ /* (2 * 4) config */
+ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
+@@ -1573,7 +1573,7 @@ static inline int mi_set_context(struct
+ const int num_rings =
+ /* Use an extended w/a on gen7 if signalling from other rings */
+ (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
+- INTEL_INFO(i915)->num_rings - 1 :
++ RUNTIME_INFO(i915)->num_rings - 1 :
+ 0;
+ bool force_restore = false;
+ int len;
+@@ -2220,7 +2220,7 @@ static void intel_ring_default_vfuncs(st
+
+ engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
+
+- num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
++ num_rings = RUNTIME_INFO(dev_priv)->num_rings - 1;
+ engine->emit_breadcrumb_sz += num_rings * 3;
+ if (num_rings & 1)
+ engine->emit_breadcrumb_sz++;
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
+@@ -92,11 +92,11 @@ hangcheck_action_to_str(const enum intel
+
+ #define instdone_slice_mask(dev_priv__) \
+ (INTEL_GEN(dev_priv__) == 7 ? \
+- 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
++ 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
+
+ #define instdone_subslice_mask(dev_priv__) \
+ (INTEL_GEN(dev_priv__) == 7 ? \
+- 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
++ 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
+
+ #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
+ for ((slice__) = 0, (subslice__) = 0; \
+--- a/drivers/gpu/drm/i915/intel_workarounds.c
++++ b/drivers/gpu/drm/i915/intel_workarounds.c
+@@ -332,7 +332,7 @@ static int skl_tune_iz_hashing(struct dr
+ * Only consider slices where one, and only one, subslice has 7
+ * EUs
+ */
+- if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
++ if (!is_power_of_2(RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[i]))
+ continue;
+
+ /*
+@@ -341,7 +341,7 @@ static int skl_tune_iz_hashing(struct dr
+ *
+ * -> 0 <= ss <= 3;
+ */
+- ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
++ ss = ffs(RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
+ vals[i] = 3 - ss;
+ }
+
+@@ -757,7 +757,7 @@ static void cfl_gt_workarounds_init(stru
+
+ static void wa_init_mcr(struct drm_i915_private *dev_priv)
+ {
+- const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
++ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ struct i915_wa_list *wal = &dev_priv->gt_wa_list;
+ u32 mcr_slice_subslice_mask;
+
+--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
++++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+@@ -410,7 +410,7 @@ static int igt_ctx_exec(void *arg)
+ ncontexts++;
+ }
+ pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
+- ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
++ ncontexts, RUNTIME_INFO(i915)->num_rings, ndwords);
+
+ dw = 0;
+ list_for_each_entry(obj, &objects, st_link) {
+@@ -510,7 +510,7 @@ static int igt_ctx_readonly(void *arg)
+ }
+ }
+ pr_info("Submitted %lu dwords (across %u engines)\n",
+- ndwords, INTEL_INFO(i915)->num_rings);
++ ndwords, RUNTIME_INFO(i915)->num_rings);
+
+ dw = 0;
+ list_for_each_entry(obj, &objects, st_link) {
diff --git a/patches.fixes/0001-USB-serial-pl2303-fix-tranceiver-suspend-mode.patch b/patches.fixes/0001-USB-serial-pl2303-fix-tranceiver-suspend-mode.patch
new file mode 100644
index 0000000000..416506349f
--- /dev/null
+++ b/patches.fixes/0001-USB-serial-pl2303-fix-tranceiver-suspend-mode.patch
@@ -0,0 +1,83 @@
+From f64c3ab230682e8395a7fbd01f3eb5140c837d4e Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Tue, 2 Apr 2019 10:19:31 +0200
+Subject: [PATCH] USB: serial: pl2303: fix tranceiver suspend mode
+Git-commit: f64c3ab230682e8395a7fbd01f3eb5140c837d4e
+Patch-mainline: v5.2-rc1
+References: bsc#1135642
+
+Add helper function to update register bits instead of overwriting the
+entire control register when updating the flow-control settings.
+
+This specifically avoids having the tranceiver suspend mode (bit 0)
+depend on the flow control setting.
+
+The tranceiver is currently configured at probe to be disabled during
+suspend, but this was overridden when disabling flow control or enabling
+xon/xoff.
+
+Fixes: 715f9527c1c1 ("USB: flow control fix for pl2303")
+Fixes: 7041d9c3f01b ("USB: serial: pl2303: add support for tx xon/xoff flow control")
+Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/serial/pl2303.c | 31 ++++++++++++++++++++++++++++---
+ 1 file changed, 28 insertions(+), 3 deletions(-)
+
+--- a/drivers/usb/serial/pl2303.c
++++ b/drivers/usb/serial/pl2303.c
+@@ -148,6 +148,8 @@ MODULE_DEVICE_TABLE(usb, id_table);
+ #define UART_OVERRUN_ERROR 0x40
+ #define UART_CTS 0x80
+
++#define PL2303_FLOWCTRL_MASK 0xf0
++
+ static void pl2303_set_break(struct usb_serial_port *port, bool enable);
+
+ enum pl2303_type {
+@@ -226,6 +228,29 @@ static int pl2303_vendor_write(struct us
+ return 0;
+ }
+
++static int pl2303_update_reg(struct usb_serial *serial, u8 reg, u8 mask, u8 val)
++{
++ int ret = 0;
++ u8 *buf;
++
++ buf = kmalloc(1, GFP_KERNEL);
++ if (!buf)
++ return -ENOMEM;
++
++ ret = pl2303_vendor_read(serial, reg | 0x80, buf);
++ if (ret)
++ goto out_free;
++
++ *buf &= ~mask;
++ *buf |= val & mask;
++
++ ret = pl2303_vendor_write(serial, reg, *buf);
++out_free:
++ kfree(buf);
++
++ return ret;
++}
++
+ static int pl2303_probe(struct usb_serial *serial,
+ const struct usb_device_id *id)
+ {
+@@ -670,11 +695,11 @@ static void pl2303_set_termios(struct tt
+
+ if (C_CRTSCTS(tty)) {
+ if (spriv->quirks & PL2303_QUIRK_LEGACY)
+- pl2303_vendor_write(serial, 0x0, 0x41);
++ pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x40);
+ else
+- pl2303_vendor_write(serial, 0x0, 0x61);
++ pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x60);
+ } else {
+- pl2303_vendor_write(serial, 0x0, 0x0);
++ pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0);
+ }
+
+ kfree(buf);
diff --git a/patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch b/patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch
index 62221e8979..245da31cdd 100644
--- a/patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch
+++ b/patches.fixes/0001-mwifiex-Abort-at-too-short-BSS-descriptor-element.patch
@@ -2,8 +2,9 @@ From 685c9b7750bfacd6fc1db50d86579980593b7869 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Wed, 29 May 2019 14:52:20 +0200
Subject: [PATCH] mwifiex: Abort at too short BSS descriptor element
-Patch-mainline: Submitted, https://lore.kernel.org/linux-wireless/20190529125220.17066-3-tiwai@suse.de/
References: bsc#1136424 CVE-2019-3846
+Git-commit: 685c9b7750bfacd6fc1db50d86579980593b7869
+Patch-mainline: v5.2-rc5
Currently mwifiex_update_bss_desc_with_ie() implicitly assumes that
the source descriptor entries contain the enough size for each type
diff --git a/patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch b/patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch
index 8b2f4d2d0e..bfb3f90103 100644
--- a/patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch
+++ b/patches.fixes/0001-mwifiex-Fix-heap-overflow-in-mwifiex_uap_parse_tail_.patch
@@ -2,8 +2,9 @@ From 69ae4f6aac1578575126319d3f55550e7e440449 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Fri, 31 May 2019 15:18:41 +0200
Subject: [PATCH] mwifiex: Fix heap overflow in mwifiex_uap_parse_tail_ies()
-Patch-mainline: Submitted, https://www.spinics.net/lists/linux-wireless/msg186667.html
References: bsc#1136935
+Patch-mainline: v5.2-rc5
+Git-commit: 69ae4f6aac1578575126319d3f55550e7e440449
A few places in mwifiex_uap_parse_tail_ies() perform memcpy()
unconditionally, which may lead to either buffer overflow or read over
diff --git a/patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch b/patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch
index 0bbe3b355d..c1375d52a3 100644
--- a/patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch
+++ b/patches.fixes/0001-mwifiex-Fix-possible-buffer-overflows-at-parsing-bss.patch
@@ -3,8 +3,9 @@ From: Takashi Iwai <tiwai@suse.de>
Date: Wed, 29 May 2019 14:52:19 +0200
Subject: [PATCH] mwifiex: Fix possible buffer overflows at parsing bss
descriptor
-Patch-mainline: Submitted, https://lore.kernel.org/linux-wireless/20190529125220.17066-1-tiwai@suse.de/
References: bsc#1136424 CVE-2019-3846
+Patch-mainline: v5.2-rc5
+Git-commit: 13ec7f10b87f5fc04c4ccbd491c94c7980236a74
mwifiex_update_bss_desc_with_ie() calls memcpy() unconditionally in
a couple places without checking the destination size. Since the
diff --git a/patches.fixes/0001-usb-xhci-avoid-null-pointer-deref-when-bos-field-is-.patch b/patches.fixes/0001-usb-xhci-avoid-null-pointer-deref-when-bos-field-is-.patch
new file mode 100644
index 0000000000..ffe54af93e
--- /dev/null
+++ b/patches.fixes/0001-usb-xhci-avoid-null-pointer-deref-when-bos-field-is-.patch
@@ -0,0 +1,105 @@
+From 7aa1bb2ffd84d6b9b5f546b079bb15cd0ab6e76e Mon Sep 17 00:00:00 2001
+From: Carsten Schmid <carsten_schmid@mentor.com>
+Date: Wed, 22 May 2019 14:33:59 +0300
+Subject: [PATCH] usb: xhci: avoid null pointer deref when bos field is NULL
+Git-commit: 7aa1bb2ffd84d6b9b5f546b079bb15cd0ab6e76e
+Patch-mainline: v5.2-rc3
+References: bsc#1135642
+
+With defective USB sticks we see the following error happen:
+usb 1-3: new high-speed USB device number 6 using xhci_hcd
+usb 1-3: device descriptor read/64, error -71
+usb 1-3: device descriptor read/64, error -71
+usb 1-3: new high-speed USB device number 7 using xhci_hcd
+usb 1-3: device descriptor read/64, error -71
+usb 1-3: unable to get BOS descriptor set
+usb 1-3: New USB device found, idVendor=0781, idProduct=5581
+usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+...
+BUG: unable to handle kernel NULL pointer dereference at 0000000000000008
+
+This comes from the following place:
+[ 1660.215380] IP: xhci_set_usb2_hardware_lpm+0xdf/0x3d0 [xhci_hcd]
+[ 1660.222092] PGD 0 P4D 0
+[ 1660.224918] Oops: 0000 [#1] PREEMPT SMP NOPTI
+[ 1660.425520] CPU: 1 PID: 38 Comm: kworker/1:1 Tainted: P U W O 4.14.67-apl #1
+[ 1660.434277] Workqueue: usb_hub_wq hub_event [usbcore]
+[ 1660.439918] task: ffffa295b6ae4c80 task.stack: ffffad4580150000
+[ 1660.446532] RIP: 0010:xhci_set_usb2_hardware_lpm+0xdf/0x3d0 [xhci_hcd]
+[ 1660.453821] RSP: 0018:ffffad4580153c70 EFLAGS: 00010046
+[ 1660.459655] RAX: 0000000000000000 RBX: ffffa295b4d7c000 RCX: 0000000000000002
+[ 1660.467625] RDX: 0000000000000002 RSI: ffffffff984a55b2 RDI: ffffffff984a55b2
+[ 1660.475586] RBP: ffffad4580153cc8 R08: 0000000000d6520a R09: 0000000000000001
+[ 1660.483556] R10: ffffad4580a004a0 R11: 0000000000000286 R12: ffffa295b4d7c000
+[ 1660.491525] R13: 0000000000010648 R14: ffffa295a84e1800 R15: 0000000000000000
+[ 1660.499494] FS: 0000000000000000(0000) GS:ffffa295bfc80000(0000) knlGS:0000000000000000
+[ 1660.508530] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[ 1660.514947] CR2: 0000000000000008 CR3: 000000025a114000 CR4: 00000000003406a0
+[ 1660.522917] Call Trace:
+[ 1660.525657] usb_set_usb2_hardware_lpm+0x3d/0x70 [usbcore]
+[ 1660.531792] usb_disable_device+0x242/0x260 [usbcore]
+[ 1660.537439] usb_disconnect+0xc1/0x2b0 [usbcore]
+[ 1660.542600] hub_event+0x596/0x18f0 [usbcore]
+[ 1660.547467] ? trace_preempt_on+0xdf/0x100
+[ 1660.552040] ? process_one_work+0x1c1/0x410
+[ 1660.556708] process_one_work+0x1d2/0x410
+[ 1660.561184] ? preempt_count_add.part.3+0x21/0x60
+[ 1660.566436] worker_thread+0x2d/0x3f0
+[ 1660.570522] kthread+0x122/0x140
+[ 1660.574123] ? process_one_work+0x410/0x410
+[ 1660.578792] ? kthread_create_on_node+0x60/0x60
+[ 1660.583849] ret_from_fork+0x3a/0x50
+[ 1660.587839] Code: 00 49 89 c3 49 8b 84 24 50 16 00 00 8d 4a ff 48 8d 04 c8 48 89 ca 4c 8b 10 45 8b 6a 04 48 8b 00 48 89 45 c0 49 8b 86 80 03 00 00 <48> 8b 40 08 8b 40 03 0f 1f 44 00 00 45 85 ff 0f 84 81 01 00 00
+[ 1660.608980] RIP: xhci_set_usb2_hardware_lpm+0xdf/0x3d0 [xhci_hcd] RSP: ffffad4580153c70
+[ 1660.617921] CR2: 0000000000000008
+
+Tracking this down shows that udev->bos is NULL in the following code:
+(xhci.c, in xhci_set_usb2_hardware_lpm)
+ field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); <<<<<<< here
+
+ xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
+ enable ? "enable" : "disable", port_num + 1);
+
+ if (enable) {
+ /* Host supports BESL timeout instead of HIRD */
+ if (udev->usb2_hw_lpm_besl_capable) {
+ /* if device doesn't have a preferred BESL value use a
+ * default one which works with mixed HIRD and BESL
+ * systems. See XHCI_DEFAULT_BESL definition in xhci.h
+ */
+ if ((field & USB_BESL_SUPPORT) &&
+ (field & USB_BESL_BASELINE_VALID))
+ hird = USB_GET_BESL_BASELINE(field);
+ else
+ hird = udev->l1_params.besl;
+
+The failing case is when disabling LPM. So it is sufficient to avoid
+access to udev->bos by moving the instruction into the "enable" clause.
+
+Cc: Stable <stable@vger.kernel.org>
+Signed-off-by: Carsten Schmid <carsten_schmid@mentor.com>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/host/xhci.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -4218,7 +4218,6 @@ static int xhci_set_usb2_hardware_lpm(st
+ pm_addr = port_array[port_num] + PORTPMSC;
+ pm_val = readl(pm_addr);
+ hlpm_addr = port_array[port_num] + PORTHLPMC;
+- field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
+
+ xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
+ enable ? "enable" : "disable", port_num + 1);
+@@ -4230,6 +4229,7 @@ static int xhci_set_usb2_hardware_lpm(st
+ * default one which works with mixed HIRD and BESL
+ * systems. See XHCI_DEFAULT_BESL definition in xhci.h
+ */
++ field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
+ if ((field & USB_BESL_SUPPORT) &&
+ (field & USB_BESL_BASELINE_VALID))
+ hird = USB_GET_BESL_BASELINE(field);
diff --git a/patches.fixes/6lowpan-Off-by-one-handling-nexthdr.patch b/patches.fixes/6lowpan-Off-by-one-handling-nexthdr.patch
new file mode 100644
index 0000000000..48413b0321
--- /dev/null
+++ b/patches.fixes/6lowpan-Off-by-one-handling-nexthdr.patch
@@ -0,0 +1,41 @@
+From f57c4bbf34439531adccd7d3a4ecc14f409c1399 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Wed, 3 Apr 2019 08:34:16 +0300
+Subject: [PATCH] 6lowpan: Off by one handling ->nexthdr
+Git-commit: f57c4bbf34439531adccd7d3a4ecc14f409c1399
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+NEXTHDR_MAX is 255. What happens here is that we take a u8 value
+"hdr->nexthdr" from the network and then look it up in
+lowpan_nexthdr_nhcs[]. The problem is that if hdr->nexthdr is 0xff then
+we read one element beyond the end of the array so the array needs to
+be one element larger.
+
+Fixes: 92aa7c65d295 ("6lowpan: add generic nhc layer interface")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
+Acked-by: Alexander Aring <aring@mojatatu.com>
+Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/6lowpan/nhc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/6lowpan/nhc.c b/net/6lowpan/nhc.c
+index 4fa2fdda174d..9e56fb98f33c 100644
+--- a/net/6lowpan/nhc.c
++++ b/net/6lowpan/nhc.c
+@@ -18,7 +18,7 @@
+ #include "nhc.h"
+
+ static struct rb_root rb_root = RB_ROOT;
+-static struct lowpan_nhc *lowpan_nexthdr_nhcs[NEXTHDR_MAX];
++static struct lowpan_nhc *lowpan_nexthdr_nhcs[NEXTHDR_MAX + 1];
+ static DEFINE_SPINLOCK(lowpan_nhc_lock);
+
+ static int lowpan_nhc_insert(struct lowpan_nhc *nhc)
+--
+2.16.4
+
diff --git a/patches.fixes/SMB3-Fix-endian-warning.patch b/patches.fixes/SMB3-Fix-endian-warning.patch
new file mode 100644
index 0000000000..23ad8ba478
--- /dev/null
+++ b/patches.fixes/SMB3-Fix-endian-warning.patch
@@ -0,0 +1,40 @@
+From: Steve French <smfrench@gmail.com>
+Date: Tue, 19 Sep 2017 11:43:47 -0500
+Subject: [PATCH] SMB3: Fix endian warning
+References: bsc#1137884
+Patch-mainline: v4.14-rc2
+Git-commit: 590d08d3da45e9fed423b08ab38d71886c07abc8
+
+Multi-dialect negotiate patch had a minor endian error.
+
+Signed-off-by: Steve French <smfrench@gmail.com>
+Reviewed-by: Ronnie Sahlberg <lsahlber@redhat.com>
+Cc: Stable <stable@vger.kernel.org> # 4.13+
+Acked-by: Aurelien Aptel <aaptel@suse.com>
+
+---
+ fs/cifs/smb2pdu.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
+index b0eaebe627e9..b4c58a1db1ae 100644
+--- a/fs/cifs/smb2pdu.c
++++ b/fs/cifs/smb2pdu.c
+@@ -570,10 +570,11 @@ SMB2_negotiate(const unsigned int xid, struct cifs_ses *ses)
+ /* ops set to 3.0 by default for default so update */
+ ses->server->ops = &smb21_operations;
+ }
+- } else if (rsp->DialectRevision != ses->server->vals->protocol_id) {
++ } else if (le16_to_cpu(rsp->DialectRevision) !=
++ ses->server->vals->protocol_id) {
+ /* if requested single dialect ensure returned dialect matched */
+ cifs_dbg(VFS, "Illegal 0x%x dialect returned: not requested\n",
+- cpu_to_le16(rsp->DialectRevision));
++ le16_to_cpu(rsp->DialectRevision));
+ return -EIO;
+ }
+
+--
+2.16.4
+
+
diff --git a/patches.fixes/af_key-unconditionally-clone-on-broadcast.patch b/patches.fixes/af_key-unconditionally-clone-on-broadcast.patch
new file mode 100644
index 0000000000..518434a9b2
--- /dev/null
+++ b/patches.fixes/af_key-unconditionally-clone-on-broadcast.patch
@@ -0,0 +1,132 @@
+From fc2d5cfdcfe2ab76b263d91429caa22451123085 Mon Sep 17 00:00:00 2001
+From: Sean Tranchetti <stranche@codeaurora.org>
+Date: Thu, 7 Feb 2019 13:33:21 -0700
+Subject: [PATCH] af_key: unconditionally clone on broadcast
+Git-commit: fc2d5cfdcfe2ab76b263d91429caa22451123085
+Patch-mainline: v5.0-rc8
+References: bsc#1051510
+
+Attempting to avoid cloning the skb when broadcasting by inflating
+the refcount with sock_hold/sock_put while under RCU lock is dangerous
+and violates RCU principles. It leads to subtle race conditions when
+attempting to free the SKB, as we may reference sockets that have
+already been freed by the stack.
+
+Unable to handle kernel paging request at virtual address 6b6b6b6b6b6c4b
+[006b6b6b6b6b6c4b] address between user and kernel address ranges
+Internal error: Oops: 96000004 [#1] PREEMPT SMP
+Task: fffffff78f65b380 task.stack: ffffff8049a88000
+pc : sock_rfree+0x38/0x6c
+lr : skb_release_head_state+0x6c/0xcc
+Process repro (pid: 7117, stack limit = 0xffffff8049a88000)
+Call trace:
+ sock_rfree+0x38/0x6c
+ skb_release_head_state+0x6c/0xcc
+ skb_release_all+0x1c/0x38
+ __kfree_skb+0x1c/0x30
+ kfree_skb+0xd0/0xf4
+ pfkey_broadcast+0x14c/0x18c
+ pfkey_sendmsg+0x1d8/0x408
+ sock_sendmsg+0x44/0x60
+ ___sys_sendmsg+0x1d0/0x2a8
+ __sys_sendmsg+0x64/0xb4
+ SyS_sendmsg+0x34/0x4c
+ el0_svc_naked+0x34/0x38
+Kernel panic - not syncing: Fatal exception
+
+Suggested-by: Eric Dumazet <eric.dumazet@gmail.com>
+Signed-off-by: Sean Tranchetti <stranche@codeaurora.org>
+Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/key/af_key.c | 40 +++++++++++++++-------------------------
+ 1 file changed, 15 insertions(+), 25 deletions(-)
+
+diff --git a/net/key/af_key.c b/net/key/af_key.c
+index 637030f43b67..5651c29cb5bd 100644
+--- a/net/key/af_key.c
++++ b/net/key/af_key.c
+@@ -196,30 +196,22 @@ static int pfkey_release(struct socket *sock)
+ return 0;
+ }
+
+-static int pfkey_broadcast_one(struct sk_buff *skb, struct sk_buff **skb2,
+- gfp_t allocation, struct sock *sk)
++static int pfkey_broadcast_one(struct sk_buff *skb, gfp_t allocation,
++ struct sock *sk)
+ {
+ int err = -ENOBUFS;
+
+- sock_hold(sk);
+- if (*skb2 == NULL) {
+- if (refcount_read(&skb->users) != 1) {
+- *skb2 = skb_clone(skb, allocation);
+- } else {
+- *skb2 = skb;
+- refcount_inc(&skb->users);
+- }
+- }
+- if (*skb2 != NULL) {
+- if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) {
+- skb_set_owner_r(*skb2, sk);
+- skb_queue_tail(&sk->sk_receive_queue, *skb2);
+- sk->sk_data_ready(sk);
+- *skb2 = NULL;
+- err = 0;
+- }
++ if (atomic_read(&sk->sk_rmem_alloc) > sk->sk_rcvbuf)
++ return err;
++
++ skb = skb_clone(skb, allocation);
++
++ if (skb) {
++ skb_set_owner_r(skb, sk);
++ skb_queue_tail(&sk->sk_receive_queue, skb);
++ sk->sk_data_ready(sk);
++ err = 0;
+ }
+- sock_put(sk);
+ return err;
+ }
+
+@@ -234,7 +226,6 @@ static int pfkey_broadcast(struct sk_buff *skb, gfp_t allocation,
+ {
+ struct netns_pfkey *net_pfkey = net_generic(net, pfkey_net_id);
+ struct sock *sk;
+- struct sk_buff *skb2 = NULL;
+ int err = -ESRCH;
+
+ /* XXX Do we need something like netlink_overrun? I think
+@@ -253,7 +244,7 @@ static int pfkey_broadcast(struct sk_buff *skb, gfp_t allocation,
+ * socket.
+ */
+ if (pfk->promisc)
+- pfkey_broadcast_one(skb, &skb2, GFP_ATOMIC, sk);
++ pfkey_broadcast_one(skb, GFP_ATOMIC, sk);
+
+ /* the exact target will be processed later */
+ if (sk == one_sk)
+@@ -268,7 +259,7 @@ static int pfkey_broadcast(struct sk_buff *skb, gfp_t allocation,
+ continue;
+ }
+
+- err2 = pfkey_broadcast_one(skb, &skb2, GFP_ATOMIC, sk);
++ err2 = pfkey_broadcast_one(skb, GFP_ATOMIC, sk);
+
+ /* Error is cleared after successful sending to at least one
+ * registered KM */
+@@ -278,9 +269,8 @@ static int pfkey_broadcast(struct sk_buff *skb, gfp_t allocation,
+ rcu_read_unlock();
+
+ if (one_sk != NULL)
+- err = pfkey_broadcast_one(skb, &skb2, allocation, one_sk);
++ err = pfkey_broadcast_one(skb, allocation, one_sk);
+
+- kfree_skb(skb2);
+ kfree_skb(skb);
+ return err;
+ }
+--
+2.16.4
+
diff --git a/patches.fixes/audit-fix-a-memory-leak-bug.patch b/patches.fixes/audit-fix-a-memory-leak-bug.patch
new file mode 100644
index 0000000000..a17fe82c98
--- /dev/null
+++ b/patches.fixes/audit-fix-a-memory-leak-bug.patch
@@ -0,0 +1,68 @@
+From 70c4cf17e445264453bc5323db3e50aa0ac9e81f Mon Sep 17 00:00:00 2001
+From: Wenwen Wang <wang6495@umn.edu>
+Date: Fri, 19 Apr 2019 20:49:29 -0500
+Subject: [PATCH] audit: fix a memory leak bug
+Git-commit: 70c4cf17e445264453bc5323db3e50aa0ac9e81f
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+In audit_rule_change(), audit_data_to_entry() is firstly invoked to
+translate the payload data to the kernel's rule representation. In
+audit_data_to_entry(), depending on the audit field type, an audit tree may
+be created in audit_make_tree(), which eventually invokes kmalloc() to
+allocate the tree. Since this tree is a temporary tree, it will be then
+freed in the following execution, e.g., audit_add_rule() if the message
+type is AUDIT_ADD_RULE or audit_del_rule() if the message type is
+AUDIT_DEL_RULE. However, if the message type is neither AUDIT_ADD_RULE nor
+AUDIT_DEL_RULE, i.e., the default case of the switch statement, this
+temporary tree is not freed.
+
+To fix this issue, only allocate the tree when the type is AUDIT_ADD_RULE
+or AUDIT_DEL_RULE.
+
+Signed-off-by: Wenwen Wang <wang6495@umn.edu>
+Reviewed-by: Richard Guy Briggs <rgb@redhat.com>
+Signed-off-by: Paul Moore <paul@paul-moore.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ kernel/auditfilter.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/auditfilter.c b/kernel/auditfilter.c
+index 2c3c2f349b23..1bc6410413e6 100644
+--- a/kernel/auditfilter.c
++++ b/kernel/auditfilter.c
+@@ -1114,22 +1114,24 @@ int audit_rule_change(int type, int seq, void *data, size_t datasz)
+ int err = 0;
+ struct audit_entry *entry;
+
+- entry = audit_data_to_entry(data, datasz);
+- if (IS_ERR(entry))
+- return PTR_ERR(entry);
+-
+ switch (type) {
+ case AUDIT_ADD_RULE:
++ entry = audit_data_to_entry(data, datasz);
++ if (IS_ERR(entry))
++ return PTR_ERR(entry);
+ err = audit_add_rule(entry);
+ audit_log_rule_change("add_rule", &entry->rule, !err);
+ break;
+ case AUDIT_DEL_RULE:
++ entry = audit_data_to_entry(data, datasz);
++ if (IS_ERR(entry))
++ return PTR_ERR(entry);
+ err = audit_del_rule(entry);
+ audit_log_rule_change("remove_rule", &entry->rule, !err);
+ break;
+ default:
+- err = -EINVAL;
+ WARN_ON(1);
++ return -EINVAL;
+ }
+
+ if (err || type == AUDIT_DEL_RULE) {
+--
+2.16.4
+
diff --git a/patches.fixes/ceph-factor-out-ceph_lookup_inode.patch b/patches.fixes/ceph-factor-out-ceph_lookup_inode.patch
new file mode 100644
index 0000000000..54ce69dae3
--- /dev/null
+++ b/patches.fixes/ceph-factor-out-ceph_lookup_inode.patch
@@ -0,0 +1,64 @@
+From: Luis Henriques <lhenriques@suse.com>
+Date: Thu, 21 Mar 2019 10:20:09 +0000
+Subject: ceph: factor out ceph_lookup_inode()
+Git-commit: 3886274adf34a4e38417772e3d1c0b213380004e
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+This function will be used by __fh_to_dentry and by the quotas code, to
+find quota realm inodes that are not visible in the mountpoint.
+
+Signed-off-by: Luis Henriques <lhenriques@suse.com>
+Reviewed-by: "Yan, Zheng" <zyan@redhat.com>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+---
+ fs/ceph/export.c | 14 ++++++++++++--
+ fs/ceph/super.h | 1 +
+ 2 files changed, 13 insertions(+), 2 deletions(-)
+
+--- a/fs/ceph/export.c
++++ b/fs/ceph/export.c
+@@ -58,7 +58,7 @@ static int ceph_encode_fh(struct inode *
+ return type;
+ }
+
+-static struct dentry *__fh_to_dentry(struct super_block *sb, u64 ino)
++struct inode *ceph_lookup_inode(struct super_block *sb, u64 ino)
+ {
+ struct ceph_mds_client *mdsc = ceph_sb_to_client(sb)->mdsc;
+ struct inode *inode;
+@@ -90,13 +90,23 @@ static struct dentry *__fh_to_dentry(str
+ ihold(inode);
+ ceph_mdsc_put_request(req);
+ if (!inode)
+- return ERR_PTR(-ESTALE);
++ return err < 0 ? ERR_PTR(err) : ERR_PTR(-ESTALE);
+ if (inode->i_nlink == 0) {
+ iput(inode);
+ return ERR_PTR(-ESTALE);
+ }
+ }
+
++ return inode;
++}
++
++static struct dentry *__fh_to_dentry(struct super_block *sb, u64 ino)
++{
++ struct inode *inode = ceph_lookup_inode(sb, ino);
++
++ if (IS_ERR(inode))
++ return ERR_CAST(inode);
++
+ return d_obtain_alias(inode);
+ }
+
+--- a/fs/ceph/super.h
++++ b/fs/ceph/super.h
+@@ -1057,6 +1057,7 @@ extern long ceph_ioctl(struct file *file
+
+ /* export.c */
+ extern const struct export_operations ceph_export_ops;
++struct inode *ceph_lookup_inode(struct super_block *sb, u64 ino);
+
+ /* locks.c */
+ extern __init void ceph_flock_init(void);
diff --git a/patches.fixes/ceph-fix-null-pointer-deref-when-debugging-is-enabled.patch b/patches.fixes/ceph-fix-null-pointer-deref-when-debugging-is-enabled.patch
new file mode 100644
index 0000000000..1a4080a69f
--- /dev/null
+++ b/patches.fixes/ceph-fix-null-pointer-deref-when-debugging-is-enabled.patch
@@ -0,0 +1,25 @@
+From: Jeff Layton <jlayton@kernel.org>
+Date: Tue, 23 Apr 2019 14:18:45 -0400
+Subject: ceph: fix NULL pointer deref when debugging is enabled
+Git-commit: 40e7e2c0e86464bca839cdf891bd58a6d41b60b4
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+Signed-off-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ fs/ceph/file.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/fs/ceph/file.c
++++ b/fs/ceph/file.c
+@@ -926,7 +926,7 @@ ceph_direct_read_write(struct kiocb *ioc
+
+ dout("sync_direct_%s on file %p %lld~%u snapc %p seq %lld\n",
+ (write ? "write" : "read"), file, pos, (unsigned)count,
+- snapc, snapc->seq);
++ snapc, snapc ? snapc->seq : 0);
+
+ ret = filemap_write_and_wait_range(inode->i_mapping, pos, pos + count);
+ if (ret < 0)
diff --git a/patches.fixes/ceph-fix-potential-use-after-free-in-ceph_mdsc_build_path.patch b/patches.fixes/ceph-fix-potential-use-after-free-in-ceph_mdsc_build_path.patch
new file mode 100644
index 0000000000..338983cd8e
--- /dev/null
+++ b/patches.fixes/ceph-fix-potential-use-after-free-in-ceph_mdsc_build_path.patch
@@ -0,0 +1,57 @@
+From: Jeff Layton <jlayton@kernel.org>
+Date: Fri, 26 Apr 2019 13:33:39 -0400
+Subject: ceph: fix potential use-after-free in ceph_mdsc_build_path
+Git-commit: 69a10fb3f4b8769ffd44e4eaa662ab691fa61f4c
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+temp is not defined outside of the RCU critical section here. Ensure
+we grab that value before we drop the rcu_read_lock.
+
+Reported-by: Al Viro <viro@zeniv.linux.org.uk>
+Signed-off-by: Jeff Layton <jlayton@kernel.org>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ fs/ceph/mds_client.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/fs/ceph/mds_client.c
++++ b/fs/ceph/mds_client.c
+@@ -1883,13 +1883,14 @@ static inline u64 __get_oldest_tid(stru
+ * Encode hidden .snap dirs as a double /, i.e.
+ * foo/.snap/bar -> foo//bar
+ */
+-char *ceph_mdsc_build_path(struct dentry *dentry, int *plen, u64 *base,
++char *ceph_mdsc_build_path(struct dentry *dentry, int *plen, u64 *pbase,
+ int stop_on_nosnap)
+ {
+ struct dentry *temp;
+ char *path;
+ int len, pos;
+ unsigned seq;
++ u64 base;
+
+ if (!dentry)
+ return ERR_PTR(-EINVAL);
+@@ -1945,6 +1946,7 @@ retry:
+ path[--pos] = '/';
+ temp = temp->d_parent;
+ }
++ base = ceph_ino(d_inode(temp));
+ rcu_read_unlock();
+ if (pos != 0 || read_seqretry(&rename_lock, seq)) {
+ pr_err("build_path did not end path lookup where "
+@@ -1957,10 +1959,10 @@ retry:
+ goto retry;
+ }
+
+- *base = ceph_ino(d_inode(temp));
++ *pbase = base;
+ *plen = len;
+ dout("build_path on %p %d built %llx '%.*s'\n",
+- dentry, d_count(dentry), *base, len, path);
++ dentry, d_count(dentry), base, len, path);
+ return path;
+ }
+
diff --git a/patches.fixes/ceph-flush-dirty-inodes-before-proceeding-with-remount.patch b/patches.fixes/ceph-flush-dirty-inodes-before-proceeding-with-remount.patch
new file mode 100644
index 0000000000..5614ca34ae
--- /dev/null
+++ b/patches.fixes/ceph-flush-dirty-inodes-before-proceeding-with-remount.patch
@@ -0,0 +1,48 @@
+From: Jeff Layton <jlayton@kernel.org>
+Date: Tue, 7 May 2019 09:20:54 -0400
+Subject: ceph: flush dirty inodes before proceeding with remount
+Git-commit: 00abf69dd24f4444d185982379c5cc3bb7b6d1fc
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+xfstest generic/452 was triggering a "Busy inodes after umount" warning.
+ceph was allowing the mount to go read-only without first flushing out
+dirty inodes in the cache. Ensure we sync out the filesystem before
+allowing a remount to proceed.
+
+Cc: stable@vger.kernel.org
+Link: http://tracker.ceph.com/issues/39571
+Signed-off-by: Jeff Layton <jlayton@kernel.org>
+Reviewed-by: "Yan, Zheng" <zyan@redhat.com>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ fs/ceph/super.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/fs/ceph/super.c b/fs/ceph/super.c
+index 6d5bb2f74612..01113c86e469 100644
+--- a/fs/ceph/super.c
++++ b/fs/ceph/super.c
+@@ -845,6 +845,12 @@ static void ceph_umount_begin(struct super_block *sb)
+ return;
+ }
+
++static int ceph_remount(struct super_block *sb, int *flags, char *data)
++{
++ sync_filesystem(sb);
++ return 0;
++}
++
+ static const struct super_operations ceph_super_ops = {
+ .alloc_inode = ceph_alloc_inode,
+ .destroy_inode = ceph_destroy_inode,
+@@ -852,6 +858,7 @@ static const struct super_operations ceph_super_ops = {
+ .drop_inode = ceph_drop_inode,
+ .sync_fs = ceph_sync_fs,
+ .put_super = ceph_put_super,
++ .remount_fs = ceph_remount,
+ .show_options = ceph_show_options,
+ .statfs = ceph_statfs,
+ .umount_begin = ceph_umount_begin,
+
diff --git a/patches.fixes/ceph-print-inode-number-in-_caps_issued_mask-debugging-messages.patch b/patches.fixes/ceph-print-inode-number-in-_caps_issued_mask-debugging-messages.patch
new file mode 100644
index 0000000000..a822ab0883
--- /dev/null
+++ b/patches.fixes/ceph-print-inode-number-in-_caps_issued_mask-debugging-messages.patch
@@ -0,0 +1,55 @@
+From: Jeff Layton <jlayton@kernel.org>
+Date: Tue, 23 Apr 2019 13:40:02 -0400
+Subject: ceph: print inode number in __caps_issued_mask debugging messages
+Git-commit: 5ddc61fc145861e4e542c9273a4088b627ba9b8d
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+To make it easier to correlate with MDS logs.
+
+Signed-off-by: Jeff Layton <jlayton@kernel.org>
+Reviewed-by: "Yan, Zheng" <zyan@redhat.com>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ fs/ceph/caps.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
+index 9e0b464d374f..72f8e1311392 100644
+--- a/fs/ceph/caps.c
++++ b/fs/ceph/caps.c
+@@ -892,8 +892,8 @@ int __ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, int touch)
+ int have = ci->i_snap_caps;
+
+ if ((have & mask) == mask) {
+- dout("__ceph_caps_issued_mask %p snap issued %s"
+- " (mask %s)\n", &ci->vfs_inode,
++ dout("__ceph_caps_issued_mask ino 0x%lx snap issued %s"
++ " (mask %s)\n", ci->vfs_inode.i_ino,
+ ceph_cap_string(have),
+ ceph_cap_string(mask));
+ return 1;
+@@ -904,8 +904,8 @@ int __ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, int touch)
+ if (!__cap_is_valid(cap))
+ continue;
+ if ((cap->issued & mask) == mask) {
+- dout("__ceph_caps_issued_mask %p cap %p issued %s"
+- " (mask %s)\n", &ci->vfs_inode, cap,
++ dout("__ceph_caps_issued_mask ino 0x%lx cap %p issued %s"
++ " (mask %s)\n", ci->vfs_inode.i_ino, cap,
+ ceph_cap_string(cap->issued),
+ ceph_cap_string(mask));
+ if (touch)
+@@ -916,8 +916,8 @@ int __ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, int touch)
+ /* does a combination of caps satisfy mask? */
+ have |= cap->issued;
+ if ((have & mask) == mask) {
+- dout("__ceph_caps_issued_mask %p combo issued %s"
+- " (mask %s)\n", &ci->vfs_inode,
++ dout("__ceph_caps_issued_mask ino 0x%lx combo issued %s"
++ " (mask %s)\n", ci->vfs_inode.i_ino,
+ ceph_cap_string(cap->issued),
+ ceph_cap_string(mask));
+ if (touch) {
+
diff --git a/patches.fixes/ceph-quota-fix-quota-subdir-mounts.patch b/patches.fixes/ceph-quota-fix-quota-subdir-mounts.patch
new file mode 100644
index 0000000000..afd66f82cd
--- /dev/null
+++ b/patches.fixes/ceph-quota-fix-quota-subdir-mounts.patch
@@ -0,0 +1,347 @@
+From: Luis Henriques <lhenriques@suse.com>
+Date: Thu, 21 Mar 2019 10:20:10 +0000
+Subject: ceph: quota: fix quota subdir mounts
+Git-commit: 0c44a8e0fc55f56a70f72e67d7cc5b9341dae7d1
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+The CephFS kernel client does not enforce quotas set in a directory that
+isn't visible from the mount point. For example, given the path
+'/dir1/dir2', if quotas are set in 'dir1' and the filesystem is mounted with
+
+ mount -t ceph <server>:<port>:/dir1/ /mnt
+
+then the client won't be able to access 'dir1' inode, even if 'dir2' belongs
+to a quota realm that points to it.
+
+This patch fixes this issue by simply doing an MDS LOOKUPINO operation for
+unknown inodes. Any inode reference obtained this way will be added to a
+list in ceph_mds_client, and will only be released when the filesystem is
+umounted.
+
+Link: https://tracker.ceph.com/issues/38482
+Reported-by: Hendrik Peyerl <hpeyerl@plusline.net>
+Signed-off-by: Luis Henriques <lhenriques@suse.com>
+Reviewed-by: "Yan, Zheng" <zyan@redhat.com>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+---
+ fs/ceph/mds_client.c | 4 +
+ fs/ceph/mds_client.h | 18 +++++
+ fs/ceph/quota.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++---
+ fs/ceph/super.h | 1
+ 4 files changed, 190 insertions(+), 10 deletions(-)
+
+--- a/fs/ceph/mds_client.c
++++ b/fs/ceph/mds_client.c
+@@ -3701,6 +3701,8 @@ int ceph_mdsc_init(struct ceph_fs_client
+ mdsc->max_sessions = 0;
+ mdsc->stopping = 0;
+ atomic64_set(&mdsc->quotarealms_count, 0);
++ mdsc->quotarealms_inodes = RB_ROOT;
++ mutex_init(&mdsc->quotarealms_inodes_mutex);
+ mdsc->last_snap_seq = 0;
+ init_rwsem(&mdsc->snap_rwsem);
+ mdsc->snap_realms = RB_ROOT;
+@@ -3783,6 +3785,8 @@ void ceph_mdsc_pre_umount(struct ceph_md
+ * their inode/dcache refs
+ */
+ ceph_msgr_flush();
++
++ ceph_cleanup_quotarealms_inodes(mdsc);
+ }
+
+ /*
+--- a/fs/ceph/mds_client.h
++++ b/fs/ceph/mds_client.h
+@@ -310,6 +310,18 @@ struct ceph_pool_perm {
+ };
+
+ /*
++ * node for list of quotarealm inodes that are not visible from the filesystem
++ * mountpoint, but required to handle, e.g. quotas.
++ */
++struct ceph_quotarealm_inode {
++ struct rb_node node;
++ u64 ino;
++ unsigned long timeout; /* last time a lookup failed for this inode */
++ struct mutex mutex;
++ struct inode *inode;
++};
++
++/*
+ * mds client state
+ */
+ struct ceph_mds_client {
+@@ -328,6 +340,12 @@ struct ceph_mds_client {
+ int stopping; /* true if shutting down */
+
+ atomic64_t quotarealms_count; /* # realms with quota */
++ /*
++ * We keep a list of inodes we don't see in the mountpoint but that we
++ * need to track quota realms.
++ */
++ struct rb_root quotarealms_inodes;
++ struct mutex quotarealms_inodes_mutex;
+
+ /*
+ * snap_rwsem will cover cap linkage into snaprealms, and
+--- a/fs/ceph/quota.c
++++ b/fs/ceph/quota.c
+@@ -35,7 +35,16 @@ void ceph_adjust_quota_realms_count(stru
+ static inline bool ceph_has_realms_with_quotas(struct inode *inode)
+ {
+ struct ceph_mds_client *mdsc = ceph_inode_to_client(inode)->mdsc;
+- return atomic64_read(&mdsc->quotarealms_count) > 0;
++ struct super_block *sb = mdsc->fsc->sb;
++
++ if (atomic64_read(&mdsc->quotarealms_count) > 0)
++ return true;
++ /* if root is the real CephFS root, we don't have quota realms */
++ if (sb->s_root->d_inode &&
++ (sb->s_root->d_inode->i_ino == CEPH_INO_ROOT))
++ return false;
++ /* otherwise, we can't know for sure */
++ return true;
+ }
+
+ void ceph_handle_quota(struct ceph_mds_client *mdsc,
+@@ -81,6 +90,108 @@ void ceph_handle_quota(struct ceph_mds_c
+ iput(inode);
+ }
+
++static struct ceph_quotarealm_inode *
++find_quotarealm_inode(struct ceph_mds_client *mdsc, u64 ino)
++{
++ struct ceph_quotarealm_inode *qri = NULL;
++ struct rb_node **node, *parent = NULL;
++
++ mutex_lock(&mdsc->quotarealms_inodes_mutex);
++ node = &(mdsc->quotarealms_inodes.rb_node);
++ while (*node) {
++ parent = *node;
++ qri = container_of(*node, struct ceph_quotarealm_inode, node);
++
++ if (ino < qri->ino)
++ node = &((*node)->rb_left);
++ else if (ino > qri->ino)
++ node = &((*node)->rb_right);
++ else
++ break;
++ }
++ if (!qri || (qri->ino != ino)) {
++ /* Not found, create a new one and insert it */
++ qri = kmalloc(sizeof(*qri), GFP_KERNEL);
++ if (qri) {
++ qri->ino = ino;
++ qri->inode = NULL;
++ qri->timeout = 0;
++ mutex_init(&qri->mutex);
++ rb_link_node(&qri->node, parent, node);
++ rb_insert_color(&qri->node, &mdsc->quotarealms_inodes);
++ } else
++ pr_warn("Failed to alloc quotarealms_inode\n");
++ }
++ mutex_unlock(&mdsc->quotarealms_inodes_mutex);
++
++ return qri;
++}
++
++/*
++ * This function will try to lookup a realm inode which isn't visible in the
++ * filesystem mountpoint. A list of these kind of inodes (not visible) is
++ * maintained in the mdsc and freed only when the filesystem is umounted.
++ *
++ * Note that these inodes are kept in this list even if the lookup fails, which
++ * allows to prevent useless lookup requests.
++ */
++static struct inode *lookup_quotarealm_inode(struct ceph_mds_client *mdsc,
++ struct super_block *sb,
++ struct ceph_snap_realm *realm)
++{
++ struct ceph_quotarealm_inode *qri;
++ struct inode *in;
++
++ qri = find_quotarealm_inode(mdsc, realm->ino);
++ if (!qri)
++ return NULL;
++
++ mutex_lock(&qri->mutex);
++ if (qri->inode) {
++ /* A request has already returned the inode */
++ mutex_unlock(&qri->mutex);
++ return qri->inode;
++ }
++ /* Check if this inode lookup has failed recently */
++ if (qri->timeout &&
++ time_before_eq(jiffies, qri->timeout)) {
++ mutex_unlock(&qri->mutex);
++ return NULL;
++ }
++ in = ceph_lookup_inode(sb, realm->ino);
++ if (IS_ERR(in)) {
++ pr_warn("Can't lookup inode %llx (err: %ld)\n",
++ realm->ino, PTR_ERR(in));
++ qri->timeout = jiffies + msecs_to_jiffies(60 * 1000); /* XXX */
++ } else {
++ qri->timeout = 0;
++ qri->inode = in;
++ }
++ mutex_unlock(&qri->mutex);
++
++ return in;
++}
++
++void ceph_cleanup_quotarealms_inodes(struct ceph_mds_client *mdsc)
++{
++ struct ceph_quotarealm_inode *qri;
++ struct rb_node *node;
++
++ /*
++ * It should now be safe to clean quotarealms_inode tree without holding
++ * mdsc->quotarealms_inodes_mutex...
++ */
++ mutex_lock(&mdsc->quotarealms_inodes_mutex);
++ while (!RB_EMPTY_ROOT(&mdsc->quotarealms_inodes)) {
++ node = rb_first(&mdsc->quotarealms_inodes);
++ qri = rb_entry(node, struct ceph_quotarealm_inode, node);
++ rb_erase(node, &mdsc->quotarealms_inodes);
++ iput(qri->inode);
++ kfree(qri);
++ }
++ mutex_unlock(&mdsc->quotarealms_inodes_mutex);
++}
++
+ /*
+ * This function walks through the snaprealm for an inode and returns the
+ * ceph_snap_realm for the first snaprealm that has quotas set (either max_files
+@@ -89,9 +200,15 @@ void ceph_handle_quota(struct ceph_mds_c
+ *
+ * Note that the caller is responsible for calling ceph_put_snap_realm() on the
+ * returned realm.
++ *
++ * Callers of this function need to hold mdsc->snap_rwsem. However, if there's
++ * a need to do an inode lookup, this rwsem will be temporarily dropped. Hence
++ * the 'retry' argument: if rwsem needs to be dropped and 'retry' is 'false'
++ * this function will return -EAGAIN; otherwise, the snaprealms walk-through
++ * will be restarted.
+ */
+ static struct ceph_snap_realm *get_quota_realm(struct ceph_mds_client *mdsc,
+- struct inode *inode)
++ struct inode *inode, bool retry)
+ {
+ struct ceph_inode_info *ci = NULL;
+ struct ceph_snap_realm *realm, *next;
+@@ -101,6 +218,7 @@ static struct ceph_snap_realm *get_quota
+ if (ceph_snap(inode) != CEPH_NOSNAP)
+ return NULL;
+
++restart:
+ realm = ceph_inode(inode)->i_snap_realm;
+ if (realm)
+ ceph_get_snap_realm(mdsc, realm);
+@@ -108,11 +226,25 @@ static struct ceph_snap_realm *get_quota
+ pr_err_ratelimited("get_quota_realm: ino (%llx.%llx) "
+ "null i_snap_realm\n", ceph_vinop(inode));
+ while (realm) {
++ bool has_inode;
++
+ spin_lock(&realm->inodes_with_caps_lock);
+- in = realm->inode ? igrab(realm->inode) : NULL;
++ has_inode = realm->inode;
++ in = has_inode ? igrab(realm->inode) : NULL;
+ spin_unlock(&realm->inodes_with_caps_lock);
+- if (!in)
++ if (has_inode && !in)
+ break;
++ if (!in) {
++ up_read(&mdsc->snap_rwsem);
++ in = lookup_quotarealm_inode(mdsc, inode->i_sb, realm);
++ down_read(&mdsc->snap_rwsem);
++ if (IS_ERR_OR_NULL(in))
++ break;
++ ceph_put_snap_realm(mdsc, realm);
++ if (!retry)
++ return ERR_PTR(-EAGAIN);
++ goto restart;
++ }
+
+ ci = ceph_inode(in);
+ has_quota = __ceph_has_any_quota(ci);
+@@ -138,9 +270,22 @@ bool ceph_quota_is_same_realm(struct ino
+ struct ceph_snap_realm *old_realm, *new_realm;
+ bool is_same;
+
++restart:
++ /*
++ * We need to lookup 2 quota realms atomically, i.e. with snap_rwsem.
++ * However, get_quota_realm may drop it temporarily. By setting the
++ * 'retry' parameter to 'false', we'll get -EAGAIN if the rwsem was
++ * dropped and we can then restart the whole operation.
++ */
+ down_read(&mdsc->snap_rwsem);
+- old_realm = get_quota_realm(mdsc, old);
+- new_realm = get_quota_realm(mdsc, new);
++ old_realm = get_quota_realm(mdsc, old, true);
++ new_realm = get_quota_realm(mdsc, new, false);
++ if (PTR_ERR(new_realm) == -EAGAIN) {
++ up_read(&mdsc->snap_rwsem);
++ if (old_realm)
++ ceph_put_snap_realm(mdsc, old_realm);
++ goto restart;
++ }
+ is_same = (old_realm == new_realm);
+ up_read(&mdsc->snap_rwsem);
+
+@@ -179,6 +324,7 @@ static bool check_quota_exceeded(struct
+ return false;
+
+ down_read(&mdsc->snap_rwsem);
++restart:
+ realm = ceph_inode(inode)->i_snap_realm;
+ if (realm)
+ ceph_get_snap_realm(mdsc, realm);
+@@ -186,12 +332,23 @@ static bool check_quota_exceeded(struct
+ pr_err_ratelimited("check_quota_exceeded: ino (%llx.%llx) "
+ "null i_snap_realm\n", ceph_vinop(inode));
+ while (realm) {
++ bool has_inode;
++
+ spin_lock(&realm->inodes_with_caps_lock);
+- in = realm->inode ? igrab(realm->inode) : NULL;
++ has_inode = realm->inode;
++ in = has_inode ? igrab(realm->inode) : NULL;
+ spin_unlock(&realm->inodes_with_caps_lock);
+- if (!in)
++ if (has_inode && !in)
+ break;
+-
++ if (!in) {
++ up_read(&mdsc->snap_rwsem);
++ in = lookup_quotarealm_inode(mdsc, inode->i_sb, realm);
++ down_read(&mdsc->snap_rwsem);
++ if (IS_ERR_OR_NULL(in))
++ break;
++ ceph_put_snap_realm(mdsc, realm);
++ goto restart;
++ }
+ ci = ceph_inode(in);
+ spin_lock(&ci->i_ceph_lock);
+ if (op == QUOTA_CHECK_MAX_FILES_OP) {
+@@ -327,7 +484,7 @@ bool ceph_quota_update_statfs(struct cep
+ bool is_updated = false;
+
+ down_read(&mdsc->snap_rwsem);
+- realm = get_quota_realm(mdsc, d_inode(fsc->sb->s_root));
++ realm = get_quota_realm(mdsc, d_inode(fsc->sb->s_root), true);
+ up_read(&mdsc->snap_rwsem);
+ if (!realm)
+ return false;
+--- a/fs/ceph/super.h
++++ b/fs/ceph/super.h
+@@ -1108,5 +1108,6 @@ extern bool ceph_quota_is_max_bytes_appr
+ loff_t newlen);
+ extern bool ceph_quota_update_statfs(struct ceph_fs_client *fsc,
+ struct kstatfs *buf);
++extern void ceph_cleanup_quotarealms_inodes(struct ceph_mds_client *mdsc);
+
+ #endif /* _FS_CEPH_SUPER_H */
diff --git a/patches.fixes/ceph-remove-duplicated-filelock-ref-increase.patch b/patches.fixes/ceph-remove-duplicated-filelock-ref-increase.patch
new file mode 100644
index 0000000000..055628bcc5
--- /dev/null
+++ b/patches.fixes/ceph-remove-duplicated-filelock-ref-increase.patch
@@ -0,0 +1,53 @@
+From: Zhi Zhang <willzzhang@tencent.com>
+Date: Fri, 22 Mar 2019 14:16:33 +0800
+Subject: ceph: remove duplicated filelock ref increase
+Git-commit: 1b52931ca9b5b87e237c591f99201b6254c00809
+Patch-mainline: v5.2-rc1
+References: bsc#1138681
+
+Inode i_filelock_ref is increased in ceph_lock or ceph_flock, but it is
+increased again in ceph_lock_message. This results in this ref won't
+become zero. If CEPH_I_ERROR_FILELOCK flag is set in
+remove_session_caps once, this flag can't be cleared even if client is
+back to normal. So further file lock will return EIO.
+
+Signed-off-by: Zhi Zhang <zhang.david2011@gmail.com>
+Reviewed-by: "Yan, Zheng" <zyan@redhat.com>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ fs/ceph/locks.c | 13 -------------
+ 1 file changed, 13 deletions(-)
+
+diff --git a/fs/ceph/locks.c b/fs/ceph/locks.c
+index 9dae2ec7e1fa..ac9b53b89365 100644
+--- a/fs/ceph/locks.c
++++ b/fs/ceph/locks.c
+@@ -237,15 +237,6 @@ int ceph_lock(struct file *file, int cmd, struct file_lock *fl)
+ spin_lock(&ci->i_ceph_lock);
+ if (ci->i_ceph_flags & CEPH_I_ERROR_FILELOCK) {
+ err = -EIO;
+- } else if (op == CEPH_MDS_OP_SETFILELOCK) {
+- /*
+- * increasing i_filelock_ref closes race window between
+- * handling request reply and adding file_lock struct to
+- * inode. Otherwise, i_auth_cap may get trimmed in the
+- * window. Caller function will decrease the counter.
+- */
+- fl->fl_ops = &ceph_fl_lock_ops;
+- atomic_inc(&ci->i_filelock_ref);
+ }
+ spin_unlock(&ci->i_ceph_lock);
+ if (err < 0) {
+@@ -299,10 +290,6 @@ int ceph_flock(struct file *file, int cmd, struct file_lock *fl)
+ spin_lock(&ci->i_ceph_lock);
+ if (ci->i_ceph_flags & CEPH_I_ERROR_FILELOCK) {
+ err = -EIO;
+- } else {
+- /* see comment in ceph_lock */
+- fl->fl_ops = &ceph_fl_lock_ops;
+- atomic_inc(&ci->i_filelock_ref);
+ }
+ spin_unlock(&ci->i_ceph_lock);
+ if (err < 0) {
+
diff --git a/patches.fixes/cfg80211-fix-memory-leak-of-wiphy-device-name.patch b/patches.fixes/cfg80211-fix-memory-leak-of-wiphy-device-name.patch
new file mode 100644
index 0000000000..485204fd15
--- /dev/null
+++ b/patches.fixes/cfg80211-fix-memory-leak-of-wiphy-device-name.patch
@@ -0,0 +1,39 @@
+From 4f488fbca2a86cc7714a128952eead92cac279ab Mon Sep 17 00:00:00 2001
+From: Eric Biggers <ebiggers@google.com>
+Date: Mon, 10 Jun 2019 13:02:19 -0700
+Subject: [PATCH] cfg80211: fix memory leak of wiphy device name
+Git-commit: 4f488fbca2a86cc7714a128952eead92cac279ab
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+In wiphy_new_nm(), if an error occurs after dev_set_name() and
+device_initialize() have already been called, it's necessary to call
+put_device() (via wiphy_free()) to avoid a memory leak.
+
+Reported-by: syzbot+7fddca22578bc67c3fe4@syzkaller.appspotmail.com
+Fixes: 1f87f7d3a3b4 ("cfg80211: add rfkill support")
+Cc: stable@vger.kernel.org
+Signed-off-by: Eric Biggers <ebiggers@google.com>
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/wireless/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/wireless/core.c b/net/wireless/core.c
+index 4e83892f1ac2..c58acca09301 100644
+--- a/net/wireless/core.c
++++ b/net/wireless/core.c
+@@ -513,7 +513,7 @@ struct wiphy *wiphy_new_nm(const struct cfg80211_ops *ops, int sizeof_priv,
+ &rdev->rfkill_ops, rdev);
+
+ if (!rdev->rfkill) {
+- kfree(rdev);
++ wiphy_free(&rdev->wiphy);
+ return NULL;
+ }
+
+--
+2.16.4
+
diff --git a/patches.fixes/drivers-thermal-tsens-Don-t-print-error-message-on-E.patch b/patches.fixes/drivers-thermal-tsens-Don-t-print-error-message-on-E.patch
new file mode 100644
index 0000000000..d7f310ec64
--- /dev/null
+++ b/patches.fixes/drivers-thermal-tsens-Don-t-print-error-message-on-E.patch
@@ -0,0 +1,38 @@
+From fc7d18cf6a923cde7f5e7ba2c1105bb106d3e29a Mon Sep 17 00:00:00 2001
+From: Amit Kucheria <amit.kucheria@linaro.org>
+Date: Wed, 20 Mar 2019 18:47:52 +0530
+Subject: [PATCH] drivers: thermal: tsens: Don't print error message on -EPROBE_DEFER
+Git-commit: fc7d18cf6a923cde7f5e7ba2c1105bb106d3e29a
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+We print a calibration failure message on -EPROBE_DEFER from
+nvmem/qfprom as follows:
+[ 3.003090] qcom-tsens 4a9000.thermal-sensor: version: 1.4
+[ 3.005376] qcom-tsens 4a9000.thermal-sensor: tsens calibration failed
+[ 3.113248] qcom-tsens 4a9000.thermal-sensor: version: 1.4
+
+This confuses people when, in fact, calibration succeeds later when
+nvmem/qfprom device is available. Don't print this message on a
+-EPROBE_DEFER.
+
+Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/qcom/tsens.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -162,7 +162,8 @@ static int tsens_probe(struct platform_d
+ if (tmdev->ops->calibrate) {
+ ret = tmdev->ops->calibrate(tmdev);
+ if (ret < 0) {
+- dev_err(dev, "tsens calibration failed\n");
++ if (ret != -EPROBE_DEFER)
++ dev_err(dev, "tsens calibration failed\n");
+ return ret;
+ }
+ }
diff --git a/patches.fixes/nfsd-COPY-and-CLONE-operations-require-the-saved-fil.patch b/patches.fixes/nfsd-COPY-and-CLONE-operations-require-the-saved-fil.patch
index 9a15e68ae5..e384d991e4 100644
--- a/patches.fixes/nfsd-COPY-and-CLONE-operations-require-the-saved-fil.patch
+++ b/patches.fixes/nfsd-COPY-and-CLONE-operations-require-the-saved-fil.patch
@@ -4,7 +4,7 @@ Subject: [PATCH] nfsd: COPY and CLONE operations require the saved filehandle
to be set
Git-commit: 01310bb7c9c98752cc763b36532fab028e0f8f81
Patch-mainline: v4.20
-References: git-fixes
+References: git-fixes, bsc#1137103, CVE-2018-16871
Make sure we have a saved filehandle, otherwise we'll oops with a null
pointer dereference in nfs4_preprocess_stateid_op().
diff --git a/patches.fixes/nl-mac-80211-allow-4addr-AP-operation-on-crypto-cont.patch b/patches.fixes/nl-mac-80211-allow-4addr-AP-operation-on-crypto-cont.patch
new file mode 100644
index 0000000000..37da0fb654
--- /dev/null
+++ b/patches.fixes/nl-mac-80211-allow-4addr-AP-operation-on-crypto-cont.patch
@@ -0,0 +1,107 @@
+From 33d915d9e8ce811d8958915ccd18d71a66c7c495 Mon Sep 17 00:00:00 2001
+From: Manikanta Pubbisetty <mpubbise@codeaurora.org>
+Date: Wed, 8 May 2019 14:55:33 +0530
+Subject: [PATCH] {nl,mac}80211: allow 4addr AP operation on crypto controlled devices
+Git-commit: 33d915d9e8ce811d8958915ccd18d71a66c7c495
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+As per the current design, in the case of sw crypto controlled devices,
+it is the device which advertises the support for AP/VLAN iftype based
+on it's ability to tranmsit packets encrypted in software
+(In VLAN functionality, group traffic generated for a specific
+VLAN group is always encrypted in software). Commit db3bdcb9c3ff
+("mac80211: allow AP_VLAN operation on crypto controlled devices")
+has introduced this change.
+
+Since 4addr AP operation also uses AP/VLAN iftype, this conditional
+way of advertising AP/VLAN support has broken 4addr AP mode operation on
+crypto controlled devices which do not support VLAN functionality.
+
+In the case of ath10k driver, not all firmwares have support for VLAN
+functionality but all can support 4addr AP operation. Because AP/VLAN
+support is not advertised for these devices, 4addr AP operations are
+also blocked.
+
+Fix this by allowing 4addr operation on devices which do not support
+AP/VLAN iftype but can support 4addr AP operation (decision is based on
+the wiphy flag WIPHY_FLAG_4ADDR_AP).
+
+Cc: stable@vger.kernel.org
+Fixes: db3bdcb9c3ff ("mac80211: allow AP_VLAN operation on crypto controlled devices")
+Signed-off-by: Manikanta Pubbisetty <mpubbise@codeaurora.org>
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ include/net/cfg80211.h | 3 ++-
+ net/mac80211/util.c | 4 +++-
+ net/wireless/core.c | 6 +++++-
+ net/wireless/nl80211.c | 8 ++++++--
+ 4 files changed, 16 insertions(+), 5 deletions(-)
+
+--- a/include/net/cfg80211.h
++++ b/include/net/cfg80211.h
+@@ -3448,7 +3448,8 @@ struct cfg80211_ops {
+ * on wiphy_new(), but can be changed by the driver if it has a good
+ * reason to override the default
+ * @WIPHY_FLAG_4ADDR_AP: supports 4addr mode even on AP (with a single station
+- * on a VLAN interface)
++ * on a VLAN interface). This flag also serves an extra purpose of
++ * supporting 4ADDR AP mode on devices which do not support AP/VLAN iftype.
+ * @WIPHY_FLAG_4ADDR_STATION: supports 4addr mode even as a station
+ * @WIPHY_FLAG_CONTROL_PORT_PROTOCOL: This device supports setting the
+ * control port protocol ethertype. The device also honours the
+--- a/net/mac80211/util.c
++++ b/net/mac80211/util.c
+@@ -3522,7 +3522,9 @@ int ieee80211_check_combinations(struct
+ }
+
+ /* Always allow software iftypes */
+- if (local->hw.wiphy->software_iftypes & BIT(iftype)) {
++ if (local->hw.wiphy->software_iftypes & BIT(iftype) ||
++ (iftype == NL80211_IFTYPE_AP_VLAN &&
++ local->hw.wiphy->flags & WIPHY_FLAG_4ADDR_AP)) {
+ if (radar_detect)
+ return -EINVAL;
+ return 0;
+--- a/net/wireless/core.c
++++ b/net/wireless/core.c
+@@ -1335,8 +1335,12 @@ static int cfg80211_netdev_notifier_call
+ }
+ break;
+ case NETDEV_PRE_UP:
+- if (!(wdev->wiphy->interface_modes & BIT(wdev->iftype)))
++ if (!(wdev->wiphy->interface_modes & BIT(wdev->iftype)) &&
++ !(wdev->iftype == NL80211_IFTYPE_AP_VLAN &&
++ rdev->wiphy.flags & WIPHY_FLAG_4ADDR_AP &&
++ wdev->use_4addr))
+ return notifier_from_errno(-EOPNOTSUPP);
++
+ if (rfkill_blocked(rdev->rfkill))
+ return notifier_from_errno(-ERFKILL);
+ break;
+--- a/net/wireless/nl80211.c
++++ b/net/wireless/nl80211.c
+@@ -3191,8 +3191,7 @@ static int nl80211_new_interface(struct
+ return -EINVAL;
+ }
+
+- if (!rdev->ops->add_virtual_intf ||
+- !(rdev->wiphy.interface_modes & (1 << type)))
++ if (!rdev->ops->add_virtual_intf)
+ return -EOPNOTSUPP;
+
+ if ((type == NL80211_IFTYPE_P2P_DEVICE || type == NL80211_IFTYPE_NAN ||
+@@ -3211,6 +3210,11 @@ static int nl80211_new_interface(struct
+ return err;
+ }
+
++ if (!(rdev->wiphy.interface_modes & (1 << type)) &&
++ !(type == NL80211_IFTYPE_AP_VLAN && params.use_4addr &&
++ rdev->wiphy.flags & WIPHY_FLAG_4ADDR_AP))
++ return -EOPNOTSUPP;
++
+ err = nl80211_parse_mon_options(rdev, type, info, &params);
+ if (err < 0)
+ return err;
diff --git a/patches.fixes/nl80211-fix-station_info-pertid-memory-leak.patch b/patches.fixes/nl80211-fix-station_info-pertid-memory-leak.patch
new file mode 100644
index 0000000000..f06d8ef2b4
--- /dev/null
+++ b/patches.fixes/nl80211-fix-station_info-pertid-memory-leak.patch
@@ -0,0 +1,43 @@
+From f77bf4863dc2218362f4227d56af4a5f3f08830c Mon Sep 17 00:00:00 2001
+From: Andy Strohman <andrew@andrewstrohman.com>
+Date: Fri, 24 May 2019 23:27:29 -0700
+Subject: [PATCH] nl80211: fix station_info pertid memory leak
+Git-commit: f77bf4863dc2218362f4227d56af4a5f3f08830c
+Patch-mainline: v5.2-rc6
+References: bsc#1051510
+
+When dumping stations, memory allocated for station_info's
+pertid member will leak if the nl80211 header cannot be added to
+the sk_buff due to insufficient tail room.
+
+I noticed this leak in the kmalloc-2048 cache.
+
+Cc: stable@vger.kernel.org
+Fixes: 8689c051a201 ("cfg80211: dynamically allocate per-tid stats for station info")
+Signed-off-by: Andy Strohman <andy@uplevelsystems.com>
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/wireless/nl80211.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
+index 4b3c5281ca14..140d24e5718f 100644
+--- a/net/wireless/nl80211.c
++++ b/net/wireless/nl80211.c
+@@ -4859,8 +4859,10 @@ static int nl80211_send_station(struct sk_buff *msg, u32 cmd, u32 portid,
+ struct nlattr *sinfoattr, *bss_param;
+
+ hdr = nl80211hdr_put(msg, portid, seq, flags, cmd);
+- if (!hdr)
++ if (!hdr) {
++ cfg80211_sinfo_release_content(sinfo);
+ return -1;
++ }
+
+ if (nla_put_u32(msg, NL80211_ATTR_IFINDEX, dev->ifindex) ||
+ nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, mac_addr) ||
+--
+2.16.4
+
diff --git a/patches.fixes/pci-disable-vf-decoding-before-pcibios_sriov_disable-updates-resources b/patches.fixes/pci-disable-vf-decoding-before-pcibios_sriov_disable-updates-resources
new file mode 100644
index 0000000000..b1fd50a10a
--- /dev/null
+++ b/patches.fixes/pci-disable-vf-decoding-before-pcibios_sriov_disable-updates-resources
@@ -0,0 +1,72 @@
+From: Gavin Shan <gwshan@linux.vnet.ibm.com>
+Date: Fri, 11 Aug 2017 18:19:33 +1000
+Subject: PCI: Disable VF decoding before pcibios_sriov_disable() updates
+ resources
+Git-commit: 0fc690a7c3f7053613dcbab6a7613bb6586d8ee2
+Patch-mainline: v4.14-rc1
+References: jsc#SLE-5803 FATE#327056
+
+A struct resource represents the address space consumed by a device. We
+should not modify that resource while the device is actively using the
+address space. For VFs, pci_iov_update_resource() enforces this by
+printing a warning and doing nothing if the VFE (VF Enable) and MSE (VF
+Memory Space Enable) bits are set.
+
+Previously, both sriov_enable() and sriov_disable() called the
+pcibios_sriov_disable() arch hook, which may update the struct resource,
+while VFE and MSE were enabled. This effectively dropped the resource
+update pcibios_sriov_disable() intended to do.
+
+Disable VF memory decoding before calling pcibios_sriov_disable().
+
+Reported-by: Carol L Soto <clsoto@us.ibm.com>
+Tested-by: Carol L Soto <clsoto@us.ibm.com>
+Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
+Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
+[bhelgaas: changelog]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: shan.gavin@gmail.com
+Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Cc: Paul Mackerras <paulus@samba.org>
+
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ drivers/pci/iov.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/pci/iov.c
++++ b/drivers/pci/iov.c
+@@ -331,7 +331,6 @@ failed:
+ while (i--)
+ pci_iov_remove_virtfn(dev, i, 0);
+
+- pcibios_sriov_disable(dev);
+ err_pcibios:
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ pci_cfg_access_lock(dev);
+@@ -339,6 +338,8 @@ err_pcibios:
+ ssleep(1);
+ pci_cfg_access_unlock(dev);
+
++ pcibios_sriov_disable(dev);
++
+ if (iov->link != dev->devfn)
+ sysfs_remove_link(&dev->dev.kobj, "dep_link");
+
+@@ -357,14 +358,14 @@ static void sriov_disable(struct pci_dev
+ for (i = 0; i < iov->num_VFs; i++)
+ pci_iov_remove_virtfn(dev, i, 0);
+
+- pcibios_sriov_disable(dev);
+-
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ pci_cfg_access_lock(dev);
+ pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
+ ssleep(1);
+ pci_cfg_access_unlock(dev);
+
++ pcibios_sriov_disable(dev);
++
+ if (iov->link != dev->devfn)
+ sysfs_remove_link(&dev->dev.kobj, "dep_link");
+
diff --git a/patches.fixes/rbd-don-t-assert-on-writes-to-snapshots.patch b/patches.fixes/rbd-don-t-assert-on-writes-to-snapshots.patch
new file mode 100644
index 0000000000..401ea8ea6f
--- /dev/null
+++ b/patches.fixes/rbd-don-t-assert-on-writes-to-snapshots.patch
@@ -0,0 +1,44 @@
+From: Ilya Dryomov <idryomov@gmail.com>
+Date: Fri, 3 May 2019 17:27:03 +0200
+Subject: rbd: don't assert on writes to snapshots
+Git-commit: b91a7bdca4439e286f26cdd6c15ed338e6a9fda2
+Patch-mainline: v5.2-rc1
+References: bsc#1137985 bsc#1138681
+
+The check added in commit 721c7fc701c7 ("block: fail op_is_write()
+requests to read-only partitions") was lifted in commit a32e236eb93e
+("Partially revert "block: fail op_is_write() requests to read-only
+partitions""). Basic things like user triggered writes and discards
+are still caught, but internal kernel users can submit anything. In
+particular, ext4 will attempt to write to the superblock if it detects
+errors in the filesystem, even if the filesystem is mounted read-only
+on a read-only partition.
+
+The assert is overkill regardless.
+
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Acked-by: Luis Henriques <lhenriques@suse.com>
+---
+ drivers/block/rbd.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
+index 99de7166bf89..e5009a34f9c2 100644
+--- a/drivers/block/rbd.c
++++ b/drivers/block/rbd.c
+@@ -3842,8 +3842,12 @@ static void rbd_queue_workfn(struct work_struct *work)
+ goto err_rq;
+ }
+
+- rbd_assert(op_type == OBJ_OP_READ ||
+- rbd_dev->spec->snap_id == CEPH_NOSNAP);
++ if (op_type != OBJ_OP_READ && rbd_dev->spec->snap_id != CEPH_NOSNAP) {
++ rbd_warn(rbd_dev, "%s on read-only snapshot",
++ obj_op_name(op_type));
++ result = -EIO;
++ goto err;
++ }
+
+ /*
+ * Quit early if the mapped snapshot no longer exists. It's
+
diff --git a/patches.fixes/sched-topology-Improve-load-balancing-on-AMD-EPYC.patch b/patches.fixes/sched-topology-Improve-load-balancing-on-AMD-EPYC.patch
new file mode 100644
index 0000000000..14284cb082
--- /dev/null
+++ b/patches.fixes/sched-topology-Improve-load-balancing-on-AMD-EPYC.patch
@@ -0,0 +1,144 @@
+From 75e83ec36bfc93bdafaf9dda2262b7ff006781cf Mon Sep 17 00:00:00 2001
+From: Matt Fleming <mfleming@suse.de>
+Date: Fri, 24 May 2019 22:11:42 +0100
+Subject: [PATCH] sched/topology: Improve load balancing on AMD EPYC
+Patch-mainline: Not yet, under discussion on LKML
+References: bsc#1137366
+
+SD_BALANCE_{FORK,EXEC} and SD_WAKE_AFFINE are stripped in sd_init()
+for any sched domains with a NUMA distance greater than 2 hops
+(RECLAIM_DISTANCE). The idea being that it's expensive to balance
+across domains that far apart.
+
+However, as is rather unfortunately explained in
+
+ commit 32e45ff43eaf ("mm: increase RECLAIM_DISTANCE to 30")
+
+the value for RECLAIM_DISTANCE is based on node distance tables from
+2011-era hardware.
+
+Current AMD EPYC machines have the following NUMA node distances:
+
+node distances:
+node 0 1 2 3 4 5 6 7
+ 0: 10 16 16 16 32 32 32 32
+ 1: 16 10 16 16 32 32 32 32
+ 2: 16 16 10 16 32 32 32 32
+ 3: 16 16 16 10 32 32 32 32
+ 4: 32 32 32 32 10 16 16 16
+ 5: 32 32 32 32 16 10 16 16
+ 6: 32 32 32 32 16 16 10 16
+ 7: 32 32 32 32 16 16 16 10
+
+where 2 hops is 32.
+
+The result is that the scheduler fails to load balance properly across
+NUMA nodes on different sockets -- 2 hops apart.
+
+For example, pinning 16 busy threads to NUMA nodes 0 (CPUs 0-7) and 4
+(CPUs 32-39) like so,
+
+ $ numactl -C 0-7,32-39 ./spinner 16
+
+causes all threads to fork and remain on node 0 until the active
+balancer kicks in after a few seconds and forcibly moves some threads
+to node 4.
+
+Override node_reclaim_distance for AMD Zen.
+
+Signed-off-by: Matt Fleming <mfleming@suse.de>
+---
+ arch/x86/kernel/cpu/amd.c | 5 +++++
+ include/linux/topology.h | 3 +++
+ kernel/sched/topology.c | 3 ++-
+ mm/khugepaged.c | 2 +-
+ mm/page_alloc.c | 2 +-
+ 5 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+index 57bb2100e05b..bb2f3e98efbf 100644
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -7,6 +7,7 @@
+ #include <linux/sched.h>
+ #include <linux/sched/clock.h>
+ #include <linux/random.h>
++#include <linux/topology.h>
+ #include <asm/processor.h>
+ #include <asm/apic.h>
+ #include <asm/cacheinfo.h>
+@@ -812,6 +813,10 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
+ {
+ set_cpu_cap(c, X86_FEATURE_ZEN);
+
++#ifdef CONFIG_NUMA
++ node_reclaim_distance = 32;
++#endif
++
+ /*
+ * Fix erratum 1076: CPB feature bit not being set in CPUID.
+ * Always set it, except when running under a hypervisor.
+diff --git a/include/linux/topology.h b/include/linux/topology.h
+index cb0775e1ee4b..74b484354ac9 100644
+--- a/include/linux/topology.h
++++ b/include/linux/topology.h
+@@ -59,6 +59,9 @@ int arch_update_cpu_topology(void);
+ */
+ #define RECLAIM_DISTANCE 30
+ #endif
++
++extern int __read_mostly node_reclaim_distance;
++
+ #ifndef PENALTY_FOR_NODE_WITH_CPUS
+ #define PENALTY_FOR_NODE_WITH_CPUS (1)
+ #endif
+diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c
+index 8b646058fb57..57b4afe6387a 100644
+--- a/kernel/sched/topology.c
++++ b/kernel/sched/topology.c
+@@ -1070,6 +1070,7 @@ static int *sched_domains_numa_distance;
+ int sched_max_numa_distance;
+ static struct cpumask ***sched_domains_numa_masks;
+ static int sched_domains_curr_level;
++int __read_mostly node_reclaim_distance = RECLAIM_DISTANCE;
+ #endif
+
+ /*
+@@ -1191,7 +1192,7 @@ sd_init(struct sched_domain_topology_level *tl,
+ sd->idle_idx = 2;
+
+ sd->flags |= SD_SERIALIZE;
+- if (sched_domains_numa_distance[tl->numa_level] > RECLAIM_DISTANCE) {
++ if (sched_domains_numa_distance[tl->numa_level] > node_reclaim_distance) {
+ sd->flags &= ~(SD_BALANCE_EXEC |
+ SD_BALANCE_FORK |
+ SD_WAKE_AFFINE);
+diff --git a/mm/khugepaged.c b/mm/khugepaged.c
+index 2c2813d90cb2..859f6fd0cb84 100644
+--- a/mm/khugepaged.c
++++ b/mm/khugepaged.c
+@@ -690,7 +690,7 @@ static bool khugepaged_scan_abort(int nid)
+ for (i = 0; i < MAX_NUMNODES; i++) {
+ if (!khugepaged_node_load[i])
+ continue;
+- if (node_distance(nid, i) > RECLAIM_DISTANCE)
++ if (node_distance(nid, i) > node_reclaim_distance)
+ return true;
+ }
+ return false;
+diff --git a/mm/page_alloc.c b/mm/page_alloc.c
+index b8ba38dc77f4..0c8b489c0f0c 100644
+--- a/mm/page_alloc.c
++++ b/mm/page_alloc.c
+@@ -3191,7 +3191,7 @@ bool zone_watermark_ok_safe(struct zone *z, unsigned int order,
+ static bool zone_allows_reclaim(struct zone *local_zone, struct zone *zone)
+ {
+ return node_distance(zone_to_nid(local_zone), zone_to_nid(zone)) <=
+- RECLAIM_DISTANCE;
++ node_reclaim_distance;
+ }
+ #else /* CONFIG_NUMA */
+ static bool zone_allows_reclaim(struct zone *local_zone, struct zone *zone)
+--
+2.13.7
+
diff --git a/patches.fixes/scsi-vmw_pscsi-Fix-use-after-free-in-pvscsi_queue_lc.patch b/patches.fixes/scsi-vmw_pscsi-Fix-use-after-free-in-pvscsi_queue_lc.patch
new file mode 100644
index 0000000000..96bb5c711f
--- /dev/null
+++ b/patches.fixes/scsi-vmw_pscsi-Fix-use-after-free-in-pvscsi_queue_lc.patch
@@ -0,0 +1,51 @@
+From 973ce39b8aebfe71d1fcae17ff1dc450699979d5 Mon Sep 17 00:00:00 2001
+From: Jan Kara <jack@suse.cz>
+Date: Tue, 11 Jun 2019 14:33:38 +0200
+Subject: [PATCH] scsi: vmw_pscsi: Fix use-after-free in pvscsi_queue_lck()
+References: bsc#1135296
+Patch-mainline: Submitted 18/06/2019
+
+Once we unlock adapter->hw_lock in pvscsi_queue_lck() nothing prevents just
+queued scsi_cmnd from completing and freeing the request. Thus cmd->cmnd[0]
+dereference can dereference already freed request leading to kernel crashes or
+other issues (which one of our customers observed). Store cmd->cmnd[0] in a
+local variable before unlocking adapter->hw_lock to fix the issue.
+
+CC: stable@vger.kernel.org
+Signed-off-by: Jan Kara <jack@suse.cz>
+---
+ drivers/scsi/vmw_pvscsi.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/scsi/vmw_pvscsi.c b/drivers/scsi/vmw_pvscsi.c
+index ecee4b3ff073..377b07b2feeb 100644
+--- a/drivers/scsi/vmw_pvscsi.c
++++ b/drivers/scsi/vmw_pvscsi.c
+@@ -763,6 +763,7 @@ static int pvscsi_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd
+ struct pvscsi_adapter *adapter = shost_priv(host);
+ struct pvscsi_ctx *ctx;
+ unsigned long flags;
++ unsigned char op;
+
+ spin_lock_irqsave(&adapter->hw_lock, flags);
+
+@@ -775,13 +776,14 @@ static int pvscsi_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd
+ }
+
+ cmd->scsi_done = done;
++ op = cmd->cmnd[0];
+
+ dev_dbg(&cmd->device->sdev_gendev,
+- "queued cmd %p, ctx %p, op=%x\n", cmd, ctx, cmd->cmnd[0]);
++ "queued cmd %p, ctx %p, op=%x\n", cmd, ctx, op);
+
+ spin_unlock_irqrestore(&adapter->hw_lock, flags);
+
+- pvscsi_kick_io(adapter, cmd->cmnd[0]);
++ pvscsi_kick_io(adapter, op);
+
+ return 0;
+ }
+--
+2.16.4
+
diff --git a/patches.fixes/tcp-add-tcp_min_snd_mss-sysctl.patch b/patches.fixes/tcp-add-tcp_min_snd_mss-sysctl.patch
index 1993376b4e..00896db48c 100644
--- a/patches.fixes/tcp-add-tcp_min_snd_mss-sysctl.patch
+++ b/patches.fixes/tcp-add-tcp_min_snd_mss-sysctl.patch
@@ -1,7 +1,8 @@
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 6 Jun 2019 09:38:47 -0700
Subject: tcp: add tcp_min_snd_mss sysctl
-Patch-mainline: Not yet, embargo
+Patch-mainline: v5.2-rc6
+Git-commit: 5f3e2bf008c2221478101ee72f5cb4654b9fc363
References: bsc#1137586 CVE-2019-11479
Some TCP peers announce a very small MSS option in their SYN and/or
diff --git a/patches.fixes/tcp-enforce-tcp_min_snd_mss-in-tcp_mtu_probing.patch b/patches.fixes/tcp-enforce-tcp_min_snd_mss-in-tcp_mtu_probing.patch
index 1a82b48a16..b6e8c3a336 100644
--- a/patches.fixes/tcp-enforce-tcp_min_snd_mss-in-tcp_mtu_probing.patch
+++ b/patches.fixes/tcp-enforce-tcp_min_snd_mss-in-tcp_mtu_probing.patch
@@ -1,7 +1,8 @@
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 8 Jun 2019 10:38:08 -0700
Subject: tcp: enforce tcp_min_snd_mss in tcp_mtu_probing()
-Patch-mainline: Not yet, embargo
+Patch-mainline: v5.2-rc6
+Git-commit: 967c05aee439e6e5d7d805e195b3a20ef5c433d6
References: bsc#1137586 CVE-2019-11479
If mtu probing is enabled tcp_mtu_probing() could very well end up
@@ -18,6 +19,7 @@ Cc: Yuchung Cheng <ycheng@google.com>
Cc: Tyler Hicks <tyhicks@canonical.com>
Cc: Bruce Curtis <brucec@netflix.com>
Acked-by: Michal Kubecek <mkubecek@suse.cz>
+
---
net/ipv4/tcp_timer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/patches.fixes/tcp-fix-fack_count-accounting-on-tcp_shift_skb_data.patch b/patches.fixes/tcp-fix-fack_count-accounting-on-tcp_shift_skb_data.patch
deleted file mode 100644
index 2ac827286f..0000000000
--- a/patches.fixes/tcp-fix-fack_count-accounting-on-tcp_shift_skb_data.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From: Joao Martins <joao.m.martins@oracle.com>
-Date: Mon, 10 Jun 2019 10:13:23 -0400
-Subject: tcp: fix fack_count accounting on tcp_shift_skb_data()
-Patch-mainline: Not yet, embargo
-References: CVE-2019-11477 bsc#1137586
-
-v4.15 or since commit 737ff314563 ("tcp: use sequence distance to
-detect reordering") had switched from the packet-based FACK tracking and
-switched to sequence-based.
-
-v4.14 and older still have the old logic and hence on
-tcp_skb_shift_data() needs to retain its original logic and have
-@fack_count in sync. In other words, we keep the increment of pcount with
-tcp_skb_pcount(skb) to later used that to update fack_count. To make it
-more explicit we track the new skb that gets incremented to pcount in
-@next_pcount, and we get to avoid the constant invocation of
-tcp_skb_pcount(skb) all together.
-
-Reported-by: Alexey Kodanev <alexey.kodanev@oracle.com>
-Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
-Acked-by: Michal Kubecek <mkubecek@suse.cz>
----
- net/ipv4/tcp_input.c | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
---- a/net/ipv4/tcp_input.c
-+++ b/net/ipv4/tcp_input.c
-@@ -1419,6 +1419,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
- struct tcp_sock *tp = tcp_sk(sk);
- struct sk_buff *prev;
- int mss;
-+ int next_pcount;
- int pcount = 0;
- int len;
- int in_sack;
-@@ -1535,9 +1536,11 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
- goto out;
-
- len = skb->len;
-- pcount = tcp_skb_pcount(skb);
-- if (tcp_skb_shift(prev, skb, pcount, len))
-- tcp_shifted_skb(sk, skb, state, pcount, len, mss, 0);
-+ next_pcount = tcp_skb_pcount(skb);
-+ if (tcp_skb_shift(prev, skb, next_pcount, len)) {
-+ pcount += next_pcount;
-+ tcp_shifted_skb(sk, skb, state, next_pcount, len, mss, 0);
-+ }
-
- out:
- state->fack_count += pcount;
diff --git a/patches.fixes/tcp-limit-payload-size-of-sacked-skbs.patch b/patches.fixes/tcp-limit-payload-size-of-sacked-skbs.patch
index 51e93d80af..dc0601ca36 100644
--- a/patches.fixes/tcp-limit-payload-size-of-sacked-skbs.patch
+++ b/patches.fixes/tcp-limit-payload-size-of-sacked-skbs.patch
@@ -1,7 +1,8 @@
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 6 Jun 2019 09:38:45 -0700
Subject: tcp: limit payload size of sacked skbs
-Patch-mainline: Not yet, embargo
+Patch-mainline: v5.2-rc6
+Git-commit: 3b4929f65b0d8249f19a50245cd88ed1a2f78cff
References: bsc#1137586 CVE-2019-11477
Jonathan Looney reported that TCP can trigger the following crash
@@ -36,9 +37,9 @@ Acked-by: Michal Kubecek <mkubecek@suse.cz>
include/linux/tcp.h | 4 ++++
include/net/tcp.h | 2 ++
net/ipv4/tcp.c | 1 +
- net/ipv4/tcp_input.c | 26 ++++++++++++++++++++------
+ net/ipv4/tcp_input.c | 27 ++++++++++++++++++++++-----
net/ipv4/tcp_output.c | 6 +++---
- 5 files changed, 30 insertions(+), 9 deletions(-)
+ 5 files changed, 32 insertions(+), 8 deletions(-)
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -105,7 +106,15 @@ Acked-by: Michal Kubecek <mkubecek@suse.cz>
/* Try collapsing SACK blocks spanning across multiple skbs to a single
* skb.
*/
-@@ -1501,7 +1516,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
+@@ -1404,6 +1419,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
+ struct tcp_sock *tp = tcp_sk(sk);
+ struct sk_buff *prev;
+ int mss;
++ int next_pcount;
+ int pcount = 0;
+ int len;
+ int in_sack;
+@@ -1501,7 +1517,7 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
if (!after(TCP_SKB_CB(skb)->seq + len, tp->snd_una))
goto fallback;
@@ -114,20 +123,20 @@ Acked-by: Michal Kubecek <mkubecek@suse.cz>
goto fallback;
if (!tcp_shifted_skb(sk, skb, state, pcount, len, mss, dup_sack))
goto out;
-@@ -1520,10 +1535,9 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
+@@ -1520,9 +1536,10 @@ static struct sk_buff *tcp_shift_skb_data(struct sock *sk, struct sk_buff *skb,
goto out;
len = skb->len;
- if (skb_shift(prev, skb, len)) {
- pcount += tcp_skb_pcount(skb);
- tcp_shifted_skb(sk, skb, state, tcp_skb_pcount(skb), len, mss, 0);
-- }
-+ pcount = tcp_skb_pcount(skb);
-+ if (tcp_skb_shift(prev, skb, pcount, len))
-+ tcp_shifted_skb(sk, skb, state, pcount, len, mss, 0);
++ next_pcount = tcp_skb_pcount(skb);
++ if (tcp_skb_shift(prev, skb, next_pcount, len)) {
++ pcount += next_pcount;
++ tcp_shifted_skb(sk, skb, state, next_pcount, len, mss, 0);
+ }
out:
- state->fack_count += pcount;
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -1443,8 +1443,8 @@ static inline int __tcp_mtu_to_mss(struct sock *sk, int pmtu)
diff --git a/patches.fixes/tcp-tcp_fragment-should-apply-sane-memory-limits.patch b/patches.fixes/tcp-tcp_fragment-should-apply-sane-memory-limits.patch
index 46fa950840..cee78584d6 100644
--- a/patches.fixes/tcp-tcp_fragment-should-apply-sane-memory-limits.patch
+++ b/patches.fixes/tcp-tcp_fragment-should-apply-sane-memory-limits.patch
@@ -1,7 +1,8 @@
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 6 Jun 2019 09:38:46 -0700
Subject: tcp: tcp_fragment() should apply sane memory limits
-Patch-mainline: Not yet, embargo
+Patch-mainline: v5.2-rc6
+Git-commit: f070ef2ac66716357066b683fb0baf55f8191a2e
References: bsc#1137586 CVE-2019-11478
Jonathan Looney reported that a malicious peer can force a sender
diff --git a/patches.fixes/thermal-rcar_gen3_thermal-disable-interrupt-in-.remo.patch b/patches.fixes/thermal-rcar_gen3_thermal-disable-interrupt-in-.remo.patch
new file mode 100644
index 0000000000..d10e892240
--- /dev/null
+++ b/patches.fixes/thermal-rcar_gen3_thermal-disable-interrupt-in-.remo.patch
@@ -0,0 +1,42 @@
+From 63f55fcea50c25ae5ad45af92d08dae3b84534c2 Mon Sep 17 00:00:00 2001
+From: Jiada Wang <jiada_wang@mentor.com>
+Date: Wed, 24 Apr 2019 14:11:45 +0900
+Subject: [PATCH] thermal: rcar_gen3_thermal: disable interrupt in .remove
+Git-commit: 63f55fcea50c25ae5ad45af92d08dae3b84534c2
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+Currently IRQ remains enabled after .remove, later if device is probed,
+IRQ is requested before .thermal_init, this may cause IRQ function be
+called before device is initialized.
+
+this patch disables interrupt in .remove, to ensure irq function
+only be called after device is fully initialized.
+
+Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/rcar_gen3_thermal.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
+index cf5ae8f6e8ed..e6727bd09f86 100644
+--- a/drivers/thermal/rcar_gen3_thermal.c
++++ b/drivers/thermal/rcar_gen3_thermal.c
+@@ -307,6 +307,9 @@ MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids);
+ static int rcar_gen3_thermal_remove(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
++ struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
++
++ rcar_thermal_irq_set(priv, false);
+
+ pm_runtime_put(dev);
+ pm_runtime_disable(dev);
+--
+2.16.4
+
diff --git a/patches.fixes/tmpfs-fix-link-accounting-when-a-tmpfile-is-linked-i.patch b/patches.fixes/tmpfs-fix-link-accounting-when-a-tmpfile-is-linked-i.patch
new file mode 100644
index 0000000000..13f7743b9a
--- /dev/null
+++ b/patches.fixes/tmpfs-fix-link-accounting-when-a-tmpfile-is-linked-i.patch
@@ -0,0 +1,64 @@
+From 1062af920c07f5b54cf5060fde3339da6df0cf6b Mon Sep 17 00:00:00 2001
+From: "Darrick J. Wong" <darrick.wong@oracle.com>
+Date: Thu, 21 Feb 2019 08:48:09 -0800
+Subject: [PATCH] tmpfs: fix link accounting when a tmpfile is linked in
+Git-commit: 1062af920c07f5b54cf5060fde3339da6df0cf6b
+Patch-mainline: v5.0-rc8
+References: bsc#1051510
+
+tmpfs has a peculiarity of accounting hard links as if they were
+separate inodes: so that when the number of inodes is limited, as it is
+by default, a user cannot soak up an unlimited amount of unreclaimable
+dcache memory just by repeatedly linking a file.
+
+But when v3.11 added O_TMPFILE, and the ability to use linkat() on the
+fd, we missed accommodating this new case in tmpfs: "df -i" shows that
+an extra "inode" remains accounted after the file is unlinked and the fd
+closed and the actual inode evicted. If a user repeatedly links
+tmpfiles into a tmpfs, the limit will be hit (ENOSPC) even after they
+are deleted.
+
+Just skip the extra reservation from shmem_link() in this case: there's
+a sense in which this first link of a tmpfile is then cheaper than a
+hard link of another file, but the accounting works out, and there's
+still good limiting, so no need to do anything more complicated.
+
+Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1902182134370.7035@eggly.anvils
+Fixes: f4e0c30c191 ("allow the temp files created by open() to be linked to")
+Signed-off-by: Darrick J. Wong <darrick.wong@oracle.com>
+Signed-off-by: Hugh Dickins <hughd@google.com>
+Reported-by: Matej Kupljen <matej.kupljen@gmail.com>
+Acked-by: Al Viro <viro@zeniv.linux.org.uk>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ mm/shmem.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/mm/shmem.c b/mm/shmem.c
+index 6ece1e2fe76e..0905215fb016 100644
+--- a/mm/shmem.c
++++ b/mm/shmem.c
+@@ -2854,10 +2854,14 @@ static int shmem_link(struct dentry *old_dentry, struct inode *dir, struct dentr
+ * No ordinary (disk based) filesystem counts links as inodes;
+ * but each new link needs a new dentry, pinning lowmem, and
+ * tmpfs dentries cannot be pruned until they are unlinked.
++ * But if an O_TMPFILE file is linked into the tmpfs, the
++ * first link must skip that, to get the accounting right.
+ */
+- ret = shmem_reserve_inode(inode->i_sb);
+- if (ret)
+- goto out;
++ if (inode->i_nlink) {
++ ret = shmem_reserve_inode(inode->i_sb);
++ if (ret)
++ goto out;
++ }
+
+ dir->i_size += BOGO_DIRENT_SIZE;
+ inode->i_ctime = dir->i_ctime = dir->i_mtime = current_time(inode);
+--
+2.16.4
+
diff --git a/patches.fixes/tmpfs-fix-uninitialized-return-value-in-shmem_link.patch b/patches.fixes/tmpfs-fix-uninitialized-return-value-in-shmem_link.patch
new file mode 100644
index 0000000000..a04de9ba19
--- /dev/null
+++ b/patches.fixes/tmpfs-fix-uninitialized-return-value-in-shmem_link.patch
@@ -0,0 +1,42 @@
+From 29b00e609960ae0fcff382f4c7079dd0874a5311 Mon Sep 17 00:00:00 2001
+From: "Darrick J. Wong" <darrick.wong@oracle.com>
+Date: Fri, 22 Feb 2019 22:35:32 -0800
+Subject: [PATCH] tmpfs: fix uninitialized return value in shmem_link
+Git-commit: 29b00e609960ae0fcff382f4c7079dd0874a5311
+Patch-mainline: v5.0
+References: bsc#1051510
+
+When we made the shmem_reserve_inode call in shmem_link conditional, we
+forgot to update the declaration for ret so that it always has a known
+value. Dan Carpenter pointed out this deficiency in the original patch.
+
+Fixes: 1062af920c07 ("tmpfs: fix link accounting when a tmpfile is linked in")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Darrick J. Wong <darrick.wong@oracle.com>
+Signed-off-by: Hugh Dickins <hughd@google.com>
+Cc: Matej Kupljen <matej.kupljen@gmail.com>
+Cc: Al Viro <viro@zeniv.linux.org.uk>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ mm/shmem.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/mm/shmem.c b/mm/shmem.c
+index 0905215fb016..2c012eee133d 100644
+--- a/mm/shmem.c
++++ b/mm/shmem.c
+@@ -2848,7 +2848,7 @@ static int shmem_create(struct inode *dir, struct dentry *dentry, umode_t mode,
+ static int shmem_link(struct dentry *old_dentry, struct inode *dir, struct dentry *dentry)
+ {
+ struct inode *inode = d_inode(old_dentry);
+- int ret;
++ int ret = 0;
+
+ /*
+ * No ordinary (disk based) filesystem counts links as inodes;
+--
+2.16.4
+
diff --git a/patches.fixes/vlan-disable-SIOCSHWTSTAMP-in-container.patch b/patches.fixes/vlan-disable-SIOCSHWTSTAMP-in-container.patch
new file mode 100644
index 0000000000..5436a3754d
--- /dev/null
+++ b/patches.fixes/vlan-disable-SIOCSHWTSTAMP-in-container.patch
@@ -0,0 +1,44 @@
+From 873017af778439f2f8e3d87f28ddb1fcaf244a76 Mon Sep 17 00:00:00 2001
+From: Hangbin Liu <liuhangbin@gmail.com>
+Date: Thu, 9 May 2019 14:55:07 +0800
+Subject: [PATCH] vlan: disable SIOCSHWTSTAMP in container
+Git-commit: 873017af778439f2f8e3d87f28ddb1fcaf244a76
+Patch-mainline: v5.2-rc1
+References: bsc#1051510
+
+With NET_ADMIN enabled in container, a normal user could be mapped to
+root and is able to change the real device's rx filter via ioctl on
+vlan, which would affect the other ptp process on host. Fix it by
+disabling SIOCSHWTSTAMP in container.
+
+Fixes: a6111d3c93d0 ("vlan: Pass SIOC[SG]HWTSTAMP ioctls to real device")
+Signed-off-by: Hangbin Liu <liuhangbin@gmail.com>
+Acked-by: Richard Cochran <richardcochran@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/8021q/vlan_dev.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c
+index f044ae56a313..2a9a60733594 100644
+--- a/net/8021q/vlan_dev.c
++++ b/net/8021q/vlan_dev.c
+@@ -370,10 +370,12 @@ static int vlan_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+ ifrr.ifr_ifru = ifr->ifr_ifru;
+
+ switch (cmd) {
++ case SIOCSHWTSTAMP:
++ if (!net_eq(dev_net(dev), &init_net))
++ break;
+ case SIOCGMIIPHY:
+ case SIOCGMIIREG:
+ case SIOCSMIIREG:
+- case SIOCSHWTSTAMP:
+ case SIOCGHWTSTAMP:
+ if (netif_device_present(real_dev) && ops->ndo_do_ioctl)
+ err = ops->ndo_do_ioctl(real_dev, &ifrr, cmd);
+--
+2.16.4
+
diff --git a/patches.kabi/asus-wmi-kabi-workaround.patch b/patches.kabi/asus-wmi-kabi-workaround.patch
new file mode 100644
index 0000000000..21f5330f3d
--- /dev/null
+++ b/patches.kabi/asus-wmi-kabi-workaround.patch
@@ -0,0 +1,27 @@
+From: Takashi Iwai <tiwai@suse.de>
+Subject: kABI workaround for asus-wmi changes
+Patch-mainline: Never, kABI workaround
+References: bsc#1051510
+
+Move the newly added bool flag to a padding hole with ifdef.
+
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/platform/x86/asus-wmi.h | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/asus-wmi.h
++++ b/drivers/platform/x86/asus-wmi.h
+@@ -44,8 +44,10 @@ struct quirk_entry {
+ bool store_backlight_power;
+ bool wmi_backlight_power;
+ bool wmi_backlight_native;
+- bool wmi_backlight_set_devstate;
+ bool wmi_force_als_set;
++#ifndef __GENKSYMS__
++ bool wmi_backlight_set_devstate;
++#endif
+ int wapf;
+ /*
+ * For machines with AMD graphic chips, it will send out WMI event
diff --git a/patches.kabi/kabi-x86-microcode-hotplug-state-fix.patch b/patches.kabi/kabi-x86-microcode-hotplug-state-fix.patch
new file mode 100644
index 0000000000..e180f9a6e5
--- /dev/null
+++ b/patches.kabi/kabi-x86-microcode-hotplug-state-fix.patch
@@ -0,0 +1,40 @@
+From: Borislav Petkov <bp@suse.de>
+Date: Wed Jun 19 10:19:19 CEST 2019
+Subject: x86/microcode: Fix microcode hotplug state
+References: bsc#1114279
+Patch-mainline: never, kabi
+
+Make the new hotplug state alias to an already existing one so that KABI doesn't
+complain.
+
+Signed-off-by: Borislav Petkov <bp@suse.de>
+--
+---
+ arch/x86/kernel/cpu/microcode/core.c | 3 +++
+ include/linux/cpuhotplug.h | 3 +--
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/microcode/core.c
++++ b/arch/x86/kernel/cpu/microcode/core.c
+@@ -853,6 +853,9 @@ int __init microcode_init(void)
+ goto out_ucode_group;
+
+ register_syscore_ops(&mc_syscore_ops);
++
++#define CPUHP_AP_MICROCODE_LOADER CPUHP_AP_ARM_MVEBU_COHERENCY
++
+ cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:online",
+ mc_cpu_online, mc_cpu_down_prep);
+
+--- a/include/linux/cpuhotplug.h
++++ b/include/linux/cpuhotplug.h
+@@ -83,8 +83,7 @@ enum cpuhp_state {
+ CPUHP_AP_IRQ_HIP04_STARTING,
+ CPUHP_AP_IRQ_ARMADA_XP_STARTING,
+ CPUHP_AP_IRQ_BCM2836_STARTING,
+- CPUHP_AP_ARM_MVEBU_COHERENCY,
+- CPUHP_AP_MICROCODE_LOADER,
++ CPUHP_AP_ARM_MVEBU_COHERENCY, /* == CPUHP_AP_MICROCODE_LOADER, for KABI */
+ CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,
+ CPUHP_AP_PERF_X86_STARTING,
+ CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
diff --git a/patches.kabi/pci-iov-add-flag-so-platforms-can-skip-vf-scanning b/patches.kabi/pci-iov-add-flag-so-platforms-can-skip-vf-scanning
new file mode 100644
index 0000000000..650cc57650
--- /dev/null
+++ b/patches.kabi/pci-iov-add-flag-so-platforms-can-skip-vf-scanning
@@ -0,0 +1,25 @@
+From: Petr Tesarik <ptesarik@suse.com>
+Subject: kabi: Mask no_vf_scan in struct pci_dev
+Patch-mainline: never, kabi
+References: jsc#SLE-5803 FATE#327056
+
+There is a 10-bit hole after non_compliant_bars, so this field can be
+simply masked for genksyms.
+
+Signed-off-by: Petr Tesarik <ptesarik@suse.com>
+---
+ include/linux/pci.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -410,7 +410,9 @@ struct pci_dev {
+ unsigned int irq_managed:1;
+ unsigned int has_secondary_link:1;
+ unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
++#ifndef __GENKSYMS__
+ unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
++#endif
+ pci_dev_flags_t dev_flags;
+ atomic_t enable_cnt; /* pci_enable_device has been called */
+
diff --git a/patches.kabi/x86-topology-Add-CPUID.1F-multi-die-package-support.patch b/patches.kabi/x86-topology-Add-CPUID.1F-multi-die-package-support.patch
new file mode 100644
index 0000000000..e2cdc000d7
--- /dev/null
+++ b/patches.kabi/x86-topology-Add-CPUID.1F-multi-die-package-support.patch
@@ -0,0 +1,36 @@
+From: Jiri Slaby <jslaby@suse.cz>
+Subject: kabi: x86/topology: Add CPUID.1F multi-die/package support
+Patch-mainline: never, kabi
+References: jsc#SLE-5454
+
+This is a fix for patch:
+patches.suse/x86-topology-Add-CPUID.1F-multi-die-package-support.patch
+
+It added a member to struct cpuinfo_x86. Move it to the end along with
+other kabi fixups.
+
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/include/asm/processor.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/x86/include/asm/processor.h
++++ b/arch/x86/include/asm/processor.h
+@@ -128,7 +128,6 @@ struct cpuinfo_x86 {
+ u16 logical_proc_id;
+ /* Core id: */
+ u16 cpu_core_id;
+- u16 cpu_die_id;
+ u16 logical_die_id;
+ /* Index into per_cpu list: */
+ u16 cpu_index;
+@@ -140,6 +139,9 @@ struct cpuinfo_x86 {
+ */
+ u8 x86_cache_bits;
+ unsigned initialized : 1;
++#ifndef __GENKSYMS__
++ u16 cpu_die_id;
++#endif
+ };
+
+ struct cpuid_regs {
diff --git a/patches.kabi/x86-topology-Define-topology_logical_die_id.patch b/patches.kabi/x86-topology-Define-topology_logical_die_id.patch
new file mode 100644
index 0000000000..182e7574df
--- /dev/null
+++ b/patches.kabi/x86-topology-Define-topology_logical_die_id.patch
@@ -0,0 +1,34 @@
+From: Jiri Slaby <jslaby@suse.cz>
+Subject: kabi: x86/topology: Define topology_logical_die_id()
+Patch-mainline: never, kabi
+References: jsc#SLE-5454
+
+This is a fix for patch:
+patches.suse/x86-topology-Define-topology_logical_die_id.patch
+
+It added a member to struct cpuinfo_x86. Move it to the end along with
+other kabi fixups.
+
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/include/asm/processor.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/x86/include/asm/processor.h
++++ b/arch/x86/include/asm/processor.h
+@@ -128,7 +128,6 @@ struct cpuinfo_x86 {
+ u16 logical_proc_id;
+ /* Core id: */
+ u16 cpu_core_id;
+- u16 logical_die_id;
+ /* Index into per_cpu list: */
+ u16 cpu_index;
+ u32 microcode;
+@@ -140,6 +139,7 @@ struct cpuinfo_x86 {
+ unsigned initialized : 1;
+ #ifndef __GENKSYMS__
+ u16 cpu_die_id;
++ u16 logical_die_id;
+ #endif
+ };
+
diff --git a/patches.suse/NFS-optional-NFSv4_2-fix.patch b/patches.suse/NFS-optional-NFSv4_2-fix.patch
new file mode 100644
index 0000000000..a7c0760075
--- /dev/null
+++ b/patches.suse/NFS-optional-NFSv4_2-fix.patch
@@ -0,0 +1,30 @@
+From: NeilBrown <neilb@suse.com>
+Subject: Don't restrict NFSv4.2 on openSUSE
+Patch-mainline: Never, suse specific
+References: bsc#1138719
+
+We default the nfs.max_minor_version to 1 on some SLE kernels,
+but don't need to do that for openSUSE - Leap or Tumbleweed
+
+---
+ fs/nfs/super.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/fs/nfs/super.c
++++ b/fs/nfs/super.c
+@@ -76,11 +76,15 @@
+ #define NFS_DEFAULT_VERSION 2
+ #endif
+
++#ifdef CONFIG_SUSE_PRODUCT_SLE
+ #if CONFIG_SUSE_VERSION < 15 || (CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 0)
+ static int max_minor_version = 1;
+ #else
+ static int max_minor_version = 2;
+ #endif
++#else
++static int max_minor_version = 2;
++#endif
+
+ #define NFS_MAX_CONNECTIONS 16
+
diff --git a/patches.suse/cpu-topology-Export-die_id.patch b/patches.suse/cpu-topology-Export-die_id.patch
new file mode 100644
index 0000000000..ad1c92a26b
--- /dev/null
+++ b/patches.suse/cpu-topology-Export-die_id.patch
@@ -0,0 +1,94 @@
+From: Len Brown <len.brown@intel.com>
+Date: Mon, 13 May 2019 13:58:47 -0400
+Subject: cpu/topology: Export die_id
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 0e344d8c709fe01d882fc0fb5452bedfe5eba67a
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Export die_id in cpu topology, for the benefit of hardware that has
+multiple-die/package.
+
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: linux-doc@vger.kernel.org
+Link: https://lkml.kernel.org/r/e7d1caaf4fbd24ee40db6d557ab28d7d83298900.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ Documentation/cputopology.txt | 15 ++++++++++++---
+ drivers/base/topology.c | 4 ++++
+ include/linux/topology.h | 3 +++
+ 3 files changed, 19 insertions(+), 3 deletions(-)
+
+--- a/Documentation/cputopology.txt
++++ b/Documentation/cputopology.txt
+@@ -8,6 +8,12 @@ to /proc/cpuinfo output of some architec
+ socket number, but the actual value is architecture and platform
+ dependent.
+
++die_id:
++
++ the CPU die ID of cpuX. Typically it is the hardware platform's
++ identifier (rather than the kernel's). The actual value is
++ architecture and platform dependent.
++
+ 2) /sys/devices/system/cpu/cpuX/topology/core_id:
+
+ the CPU core ID of cpuX. Typically it is the hardware platform's
+@@ -77,6 +83,7 @@ they reflect the cpu and cache hierarchy
+ For an architecture to support this feature, it must define some of
+ these macros in include/asm-XXX/topology.h:
+ #define topology_physical_package_id(cpu)
++#define topology_die_id(cpu)
+ #define topology_core_id(cpu)
+ #define topology_book_id(cpu)
+ #define topology_drawer_id(cpu)
+@@ -94,9 +101,11 @@ To be consistent on all architectures, i
+ provides default definitions for any of the above macros that are
+ not defined by include/asm-XXX/topology.h:
+ 1) physical_package_id: -1
+-2) core_id: 0
+-3) sibling_cpumask: just the given CPU
+-4) core_cpumask: just the given CPU
++2) die_id: -1
++3) core_id: 0
++4) sibling_cpumask: just the given CPU
++5) core_cpumask: just the given CPU
++6) die_cpumask: just the given CPU
+
+ For architectures that don't support books (CONFIG_SCHED_BOOK) there are no
+ default definitions for topology_book_id() and topology_book_cpumask().
+--- a/drivers/base/topology.c
++++ b/drivers/base/topology.c
+@@ -58,6 +58,9 @@ static ssize_t name##_list_show(struct d
+ define_id_show_func(physical_package_id);
+ static DEVICE_ATTR_RO(physical_package_id);
+
++define_id_show_func(die_id);
++static DEVICE_ATTR_RO(die_id);
++
+ define_id_show_func(core_id);
+ static DEVICE_ATTR_RO(core_id);
+
+@@ -87,6 +90,7 @@ static DEVICE_ATTR_RO(drawer_siblings_li
+
+ static struct attribute *default_attrs[] = {
+ &dev_attr_physical_package_id.attr,
++ &dev_attr_die_id.attr,
+ &dev_attr_core_id.attr,
+ &dev_attr_thread_siblings.attr,
+ &dev_attr_thread_siblings_list.attr,
+--- a/include/linux/topology.h
++++ b/include/linux/topology.h
+@@ -184,6 +184,9 @@ static inline int cpu_to_mem(int cpu)
+ #ifndef topology_physical_package_id
+ #define topology_physical_package_id(cpu) ((void)(cpu), -1)
+ #endif
++#ifndef topology_die_id
++#define topology_die_id(cpu) ((void)(cpu), -1)
++#endif
+ #ifndef topology_core_id
+ #define topology_core_id(cpu) ((void)(cpu), 0)
+ #endif
diff --git a/patches.suse/hwmon-coretemp-Cosmetic-Rename-internal-variables-to.patch b/patches.suse/hwmon-coretemp-Cosmetic-Rename-internal-variables-to.patch
new file mode 100644
index 0000000000..6ce07122c5
--- /dev/null
+++ b/patches.suse/hwmon-coretemp-Cosmetic-Rename-internal-variables-to.patch
@@ -0,0 +1,133 @@
+From: Len Brown <len.brown@intel.com>
+Date: Mon, 13 May 2019 13:59:01 -0400
+Subject: hwmon/coretemp: Cosmetic: Rename internal variables to zones from
+ packages
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 835896a59b9577d0bc2131e027c37bdde5b979af
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Syntax update only -- no logical or functional change.
+
+In response to the new multi-die/package changes, update variable names to
+use the more generic thermal "zone" terminology, instead of "package", as
+the zones can refer to either packages or die.
+
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: Zhang Rui <rui.zhang@intel.com>
+Link: https://lkml.kernel.org/r/facecfd3525d55c2051f63a7ec709aeb03cc1dc1.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/hwmon/coretemp.c | 36 ++++++++++++++++++------------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+--- a/drivers/hwmon/coretemp.c
++++ b/drivers/hwmon/coretemp.c
+@@ -109,10 +109,10 @@ struct platform_data {
+ struct device_attribute name_attr;
+ };
+
+-/* Keep track of how many package pointers we allocated in init() */
+-static int max_packages __read_mostly;
+-/* Array of package pointers. Serialized by cpu hotplug lock */
+-static struct platform_device **pkg_devices;
++/* Keep track of how many zone pointers we allocated in init() */
++static int max_zones __read_mostly;
++/* Array of zone pointers. Serialized by cpu hotplug lock */
++static struct platform_device **zone_devices;
+
+ static ssize_t show_label(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+@@ -434,10 +434,10 @@ static int chk_ucode_version(unsigned in
+
+ static struct platform_device *coretemp_get_pdev(unsigned int cpu)
+ {
+- int pkgid = topology_logical_die_id(cpu);
++ int id = topology_logical_die_id(cpu);
+
+- if (pkgid >= 0 && pkgid < max_packages)
+- return pkg_devices[pkgid];
++ if (id >= 0 && id < max_zones)
++ return zone_devices[id];
+ return NULL;
+ }
+
+@@ -543,7 +543,7 @@ static int coretemp_probe(struct platfor
+ struct device *dev = &pdev->dev;
+ struct platform_data *pdata;
+
+- /* Initialize the per-package data structures */
++ /* Initialize the per-zone data structures */
+ pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+@@ -578,13 +578,13 @@ static struct platform_driver coretemp_d
+
+ static struct platform_device *coretemp_device_add(unsigned int cpu)
+ {
+- int err, pkgid = topology_logical_die_id(cpu);
++ int err, zoneid = topology_logical_die_id(cpu);
+ struct platform_device *pdev;
+
+- if (pkgid < 0)
++ if (zoneid < 0)
+ return ERR_PTR(-ENOMEM);
+
+- pdev = platform_device_alloc(DRVNAME, pkgid);
++ pdev = platform_device_alloc(DRVNAME, zoneid);
+ if (!pdev)
+ return ERR_PTR(-ENOMEM);
+
+@@ -594,7 +594,7 @@ static struct platform_device *coretemp_
+ return ERR_PTR(err);
+ }
+
+- pkg_devices[pkgid] = pdev;
++ zone_devices[zoneid] = pdev;
+ return pdev;
+ }
+
+@@ -702,7 +702,7 @@ static int coretemp_cpu_offline(unsigned
+ * the rest.
+ */
+ if (cpumask_empty(&pd->cpumask)) {
+- pkg_devices[topology_logical_die_id(cpu)] = NULL;
++ zone_devices[topology_logical_die_id(cpu)] = NULL;
+ platform_device_unregister(pdev);
+ return 0;
+ }
+@@ -740,10 +740,10 @@ static int __init coretemp_init(void)
+ if (!x86_match_cpu(coretemp_ids))
+ return -ENODEV;
+
+- max_packages = topology_max_packages() * topology_max_die_per_package();
+- pkg_devices = kzalloc(max_packages * sizeof(struct platform_device *),
++ max_zones = topology_max_packages() * topology_max_die_per_package();
++ zone_devices = kcalloc(max_zones, sizeof(struct platform_device *),
+ GFP_KERNEL);
+- if (!pkg_devices)
++ if (!zone_devices)
+ return -ENOMEM;
+
+ err = platform_driver_register(&coretemp_driver);
+@@ -759,7 +759,7 @@ static int __init coretemp_init(void)
+
+ outdrv:
+ platform_driver_unregister(&coretemp_driver);
+- kfree(pkg_devices);
++ kfree(zone_devices);
+ return err;
+ }
+ module_init(coretemp_init)
+@@ -768,7 +768,7 @@ static void __exit coretemp_exit(void)
+ {
+ cpuhp_remove_state(coretemp_hp_online);
+ platform_driver_unregister(&coretemp_driver);
+- kfree(pkg_devices);
++ kfree(zone_devices);
+ }
+ module_exit(coretemp_exit)
+
diff --git a/patches.suse/hwmon-coretemp-Support-multi-die-package.patch b/patches.suse/hwmon-coretemp-Support-multi-die-package.patch
new file mode 100644
index 0000000000..15882a891d
--- /dev/null
+++ b/patches.suse/hwmon-coretemp-Support-multi-die-package.patch
@@ -0,0 +1,65 @@
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 13 May 2019 13:58:54 -0400
+Subject: hwmon/coretemp: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: cfcd82e632882372db960b50782a439a8ba56c09
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Package temperature sensors are actually implemented in hardware per-die.
+
+Update coretemp to be "die-aware", so it can expose mulitple sensors per
+package, instead of just one. No change to single-die/package systems.
+
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Guenter Roeck <linux@roeck-us.net>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: linux-pm@vger.kernel.org
+Cc: linux-hwmon@vger.kernel.org
+Link: https://lkml.kernel.org/r/ec2868f35113a01ff72d9041e0b97fc6a1c7df84.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/hwmon/coretemp.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/hwmon/coretemp.c
++++ b/drivers/hwmon/coretemp.c
+@@ -434,7 +434,7 @@ static int chk_ucode_version(unsigned in
+
+ static struct platform_device *coretemp_get_pdev(unsigned int cpu)
+ {
+- int pkgid = topology_logical_package_id(cpu);
++ int pkgid = topology_logical_die_id(cpu);
+
+ if (pkgid >= 0 && pkgid < max_packages)
+ return pkg_devices[pkgid];
+@@ -578,7 +578,7 @@ static struct platform_driver coretemp_d
+
+ static struct platform_device *coretemp_device_add(unsigned int cpu)
+ {
+- int err, pkgid = topology_logical_package_id(cpu);
++ int err, pkgid = topology_logical_die_id(cpu);
+ struct platform_device *pdev;
+
+ if (pkgid < 0)
+@@ -702,7 +702,7 @@ static int coretemp_cpu_offline(unsigned
+ * the rest.
+ */
+ if (cpumask_empty(&pd->cpumask)) {
+- pkg_devices[topology_logical_package_id(cpu)] = NULL;
++ pkg_devices[topology_logical_die_id(cpu)] = NULL;
+ platform_device_unregister(pdev);
+ return 0;
+ }
+@@ -740,7 +740,7 @@ static int __init coretemp_init(void)
+ if (!x86_match_cpu(coretemp_ids))
+ return -ENODEV;
+
+- max_packages = topology_max_packages();
++ max_packages = topology_max_packages() * topology_max_die_per_package();
+ pkg_devices = kzalloc(max_packages * sizeof(struct platform_device *),
+ GFP_KERNEL);
+ if (!pkg_devices)
diff --git a/patches.suse/ibmveth-Update-ethtool-settings-to-reflect-virtual-p.patch b/patches.suse/ibmveth-Update-ethtool-settings-to-reflect-virtual-p.patch
new file mode 100644
index 0000000000..6327bb002a
--- /dev/null
+++ b/patches.suse/ibmveth-Update-ethtool-settings-to-reflect-virtual-p.patch
@@ -0,0 +1,162 @@
+From 3417314b96d0a872057942f928e08a35460f0153 Mon Sep 17 00:00:00 2001
+From: Thomas Falcon <tlfalcon@linux.ibm.com>
+Date: Fri, 3 May 2019 09:28:33 -0500
+Subject: [PATCH net-next] ibmveth: Update ethtool settings to reflect virtual
+ properties
+
+References: bsc#1136157, LTC#177197
+Patch-mainline: no, tbd
+
+As a paravirtual ethernet adapter, the current hardcoded ethtool
+link settings no longer reflect the actual capable speed of the
+interface. There is no way for the virtual adapter to determine
+the true speed, duplex, and other backing hardware specifications
+at this time.
+
+To avoid confusion, initially define them as unknown or other.
+Finally allow the user to alter speed and duplex settings to match
+the capabilities of underlying hardware and to allow some features
+that rely on certain ethtool reporting, such as LACP. This is based
+on the implementation in virtio_net.
+
+Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
+Acked-by: Michal Suchanek <msuchanek@suse.de>
+---
+ drivers/net/ethernet/ibm/ibmveth.c | 83 ++++++++++++++++++++++++++++----------
+ drivers/net/ethernet/ibm/ibmveth.h | 3 ++
+ 2 files changed, 64 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c
+index d654c234aaf7..77af9c2c0571 100644
+--- a/drivers/net/ethernet/ibm/ibmveth.c
++++ b/drivers/net/ethernet/ibm/ibmveth.c
+@@ -712,31 +712,68 @@ static int ibmveth_close(struct net_device *netdev)
+ return 0;
+ }
+
+-static int netdev_get_link_ksettings(struct net_device *dev,
+- struct ethtool_link_ksettings *cmd)
++static bool
++ibmveth_validate_ethtool_cmd(const struct ethtool_link_ksettings *cmd)
+ {
+- u32 supported, advertising;
+-
+- supported = (SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
+- SUPPORTED_FIBRE);
+- advertising = (ADVERTISED_1000baseT_Full | ADVERTISED_Autoneg |
+- ADVERTISED_FIBRE);
+- cmd->base.speed = SPEED_1000;
+- cmd->base.duplex = DUPLEX_FULL;
+- cmd->base.port = PORT_FIBRE;
+- cmd->base.phy_address = 0;
+- cmd->base.autoneg = AUTONEG_ENABLE;
+-
+- ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
+- supported);
+- ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
+- advertising);
++ struct ethtool_link_ksettings diff1 = *cmd;
++ struct ethtool_link_ksettings diff2 = {};
++
++ diff2.base.port = PORT_OTHER;
++ diff1.base.speed = 0;
++ diff1.base.duplex = 0;
++ diff1.base.cmd = 0;
++ diff1.base.link_mode_masks_nwords = 0;
++ ethtool_link_ksettings_zero_link_mode(&diff1, advertising);
++
++ return !memcmp(&diff1.base, &diff2.base, sizeof(diff1.base)) &&
++ bitmap_empty(diff1.link_modes.supported,
++ __ETHTOOL_LINK_MODE_MASK_NBITS) &&
++ bitmap_empty(diff1.link_modes.advertising,
++ __ETHTOOL_LINK_MODE_MASK_NBITS) &&
++ bitmap_empty(diff1.link_modes.lp_advertising,
++ __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static int ibmveth_set_link_ksettings(struct net_device *dev,
++ const struct ethtool_link_ksettings *cmd)
++{
++ struct ibmveth_adapter *adapter = netdev_priv(dev);
++ u32 speed;
++ u8 duplex;
++
++ speed = cmd->base.speed;
++ duplex = cmd->base.duplex;
++ /* don't allow custom speed and duplex */
++ if (!ethtool_validate_speed(speed) ||
++ !ethtool_validate_duplex(duplex) ||
++ !ibmveth_validate_ethtool_cmd(cmd))
++ return -EINVAL;
++ adapter->speed = speed;
++ adapter->duplex = duplex;
+
+ return 0;
+ }
+
+-static void netdev_get_drvinfo(struct net_device *dev,
+- struct ethtool_drvinfo *info)
++static int ibmveth_get_link_ksettings(struct net_device *dev,
++ struct ethtool_link_ksettings *cmd)
++{
++ struct ibmveth_adapter *adapter = netdev_priv(dev);
++
++ cmd->base.speed = adapter->speed;
++ cmd->base.duplex = adapter->duplex;
++ cmd->base.port = PORT_OTHER;
++
++ return 0;
++}
++
++static void ibmveth_init_link_settings(struct ibmveth_adapter *adapter)
++{
++ adapter->duplex = DUPLEX_UNKNOWN;
++ adapter->speed = SPEED_UNKNOWN;
++}
++
++static void ibmveth_get_drvinfo(struct net_device *dev,
++ struct ethtool_drvinfo *info)
+ {
+ strlcpy(info->driver, ibmveth_driver_name, sizeof(info->driver));
+ strlcpy(info->version, ibmveth_driver_version, sizeof(info->version));
+@@ -965,12 +1002,13 @@ static void ibmveth_get_ethtool_stats(struct net_device *dev,
+ }
+
+ static const struct ethtool_ops netdev_ethtool_ops = {
+- .get_drvinfo = netdev_get_drvinfo,
++ .get_drvinfo = ibmveth_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+ .get_strings = ibmveth_get_strings,
+ .get_sset_count = ibmveth_get_sset_count,
+ .get_ethtool_stats = ibmveth_get_ethtool_stats,
+- .get_link_ksettings = netdev_get_link_ksettings,
++ .get_link_ksettings = ibmveth_get_link_ksettings,
++ .set_link_ksettings = ibmveth_set_link_ksettings
+ };
+
+ static int ibmveth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+@@ -1647,6 +1685,7 @@ static int ibmveth_probe(struct vio_dev *dev, const struct vio_device_id *id)
+ adapter->netdev = netdev;
+ adapter->mcastFilterSize = *mcastFilterSize_p;
+ adapter->pool_config = 0;
++ ibmveth_init_link_settings(adapter);
+
+ netif_napi_add(netdev, &adapter->napi, ibmveth_poll, 16);
+
+diff --git a/drivers/net/ethernet/ibm/ibmveth.h b/drivers/net/ethernet/ibm/ibmveth.h
+index 4e9bf3421f4f..db96c8812d18 100644
+--- a/drivers/net/ethernet/ibm/ibmveth.h
++++ b/drivers/net/ethernet/ibm/ibmveth.h
+@@ -162,6 +162,9 @@ struct ibmveth_adapter {
+ u64 tx_send_failed;
+ u64 tx_large_packets;
+ u64 rx_large_packets;
++ /* Ethtool settings */
++ u8 duplex;
++ u32 speed;
+ };
+
+ /*
+--
+2.12.3
+
diff --git a/patches.suse/module-fix-livepatch-ftrace-module-text-permissions-race.patch b/patches.suse/module-fix-livepatch-ftrace-module-text-permissions-race.patch
new file mode 100644
index 0000000000..66088c57bc
--- /dev/null
+++ b/patches.suse/module-fix-livepatch-ftrace-module-text-permissions-race.patch
@@ -0,0 +1,170 @@
+From: Josh Poimboeuf <jpoimboe@redhat.com>
+Date: Thu, 13 Jun 2019 20:07:22 -0500
+Subject: module: Fix livepatch/ftrace module text permissions race
+Git-commit: 9f255b632bf12c4dd7fc31caee89aa991ef75176
+Patch-mainline: v5.2-rc5
+References: bsc#1071995 fate#323487
+
+It's possible for livepatch and ftrace to be toggling a module's text
+permissions at the same time, resulting in the following panic:
+
+ BUG: unable to handle page fault for address: ffffffffc005b1d9
+ #PF: supervisor write access in kernel mode
+ #PF: error_code(0x0003) - permissions violation
+ PGD 3ea0c067 P4D 3ea0c067 PUD 3ea0e067 PMD 3cc13067 PTE 3b8a1061
+ Oops: 0003 [#1] PREEMPT SMP PTI
+ CPU: 1 PID: 453 Comm: insmod Tainted: G O K 5.2.0-rc1-a188339ca5 #1
+ Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-20181126_142135-anatol 04/01/2014
+ RIP: 0010:apply_relocate_add+0xbe/0x14c
+ Code: fa 0b 74 21 48 83 fa 18 74 38 48 83 fa 0a 75 40 eb 08 48 83 38 00 74 33 eb 53 83 38 00 75 4e 89 08 89 c8 eb 0a 83 38 00 75 43 <89> 08 48 63 c1 48 39 c8 74 2e eb 48 83 38 00 75 32 48 29 c1 89 08
+ RSP: 0018:ffffb223c00dbb10 EFLAGS: 00010246
+ RAX: ffffffffc005b1d9 RBX: 0000000000000000 RCX: ffffffff8b200060
+ RDX: 000000000000000b RSI: 0000004b0000000b RDI: ffff96bdfcd33000
+ RBP: ffffb223c00dbb38 R08: ffffffffc005d040 R09: ffffffffc005c1f0
+ R10: ffff96bdfcd33c40 R11: ffff96bdfcd33b80 R12: 0000000000000018
+ R13: ffffffffc005c1f0 R14: ffffffffc005e708 R15: ffffffff8b2fbc74
+ FS: 00007f5f447beba8(0000) GS:ffff96bdff900000(0000) knlGS:0000000000000000
+ CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+ CR2: ffffffffc005b1d9 CR3: 000000003cedc002 CR4: 0000000000360ea0
+ DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+ DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+ Call Trace:
+ klp_init_object_loaded+0x10f/0x219
+ ? preempt_latency_start+0x21/0x57
+ klp_enable_patch+0x662/0x809
+ ? virt_to_head_page+0x3a/0x3c
+ ? kfree+0x8c/0x126
+ patch_init+0x2ed/0x1000 [livepatch_test02]
+ ? 0xffffffffc0060000
+ do_one_initcall+0x9f/0x1c5
+ ? kmem_cache_alloc_trace+0xc4/0xd4
+ ? do_init_module+0x27/0x210
+ do_init_module+0x5f/0x210
+ load_module+0x1c41/0x2290
+ ? fsnotify_path+0x3b/0x42
+ ? strstarts+0x2b/0x2b
+ ? kernel_read+0x58/0x65
+ __do_sys_finit_module+0x9f/0xc3
+ ? __do_sys_finit_module+0x9f/0xc3
+ __x64_sys_finit_module+0x1a/0x1c
+ do_syscall_64+0x52/0x61
+ entry_SYSCALL_64_after_hwframe+0x44/0xa9
+
+The above panic occurs when loading two modules at the same time with
+ftrace enabled, where at least one of the modules is a livepatch module:
+
+CPU0 CPU1
+klp_enable_patch()
+ klp_init_object_loaded()
+ module_disable_ro()
+ ftrace_module_enable()
+ ftrace_arch_code_modify_post_process()
+ set_all_modules_text_ro()
+ klp_write_object_relocations()
+ apply_relocate_add()
+ *patches read-only code* - BOOM
+
+A similar race exists when toggling ftrace while loading a livepatch
+module.
+
+Fix it by ensuring that the livepatch and ftrace code patching
+operations -- and their respective permissions changes -- are protected
+by the text_mutex.
+
+Link: http://lkml.kernel.org/r/ab43d56ab909469ac5d2520c5d944ad6d4abd476.1560474114.git.jpoimboe@redhat.com
+
+Reported-by: Johannes Erdfelt <johannes@erdfelt.com>
+Fixes: 444d13ff10fb ("modules: add ro_after_init support")
+Acked-by: Jessica Yu <jeyu@kernel.org>
+Reviewed-by: Petr Mladek <pmladek@suse.com>
+Reviewed-by: Miroslav Benes <mbenes@suse.cz>
+Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+Acked-by: Miroslav Benes <mbenes@suse.cz>
+---
+ kernel/livepatch/core.c | 6 ++++++
+ kernel/trace/ftrace.c | 10 +++++++++-
+ 2 files changed, 15 insertions(+), 1 deletion(-)
+
+--- a/kernel/livepatch/core.c
++++ b/kernel/livepatch/core.c
+@@ -30,6 +30,7 @@
+ #include <linux/elf.h>
+ #include <linux/moduleloader.h>
+ #include <linux/completion.h>
++#include <linux/memory.h>
+ #include <asm/cacheflush.h>
+ #include "core.h"
+ #include "patch.h"
+@@ -729,16 +730,21 @@ static int klp_init_object_loaded(struct
+ struct klp_func *func;
+ int ret;
+
++ mutex_lock(&text_mutex);
++
+ module_disable_ro(patch->mod);
+ ret = klp_write_object_relocations(patch->mod, obj);
+ if (ret) {
+ module_enable_ro(patch->mod, true);
++ mutex_unlock(&text_mutex);
+ return ret;
+ }
+
+ arch_klp_init_object_loaded(patch, obj);
+ module_enable_ro(patch->mod, true);
+
++ mutex_unlock(&text_mutex);
++
+ klp_for_each_func(obj, func) {
+ ret = klp_find_object_symbol(obj->name, func->old_name,
+ func->old_sympos,
+--- a/kernel/trace/ftrace.c
++++ b/kernel/trace/ftrace.c
+@@ -33,6 +33,7 @@
+ #include <linux/list.h>
+ #include <linux/hash.h>
+ #include <linux/rcupdate.h>
++#include <linux/memory.h>
+
+ #include <trace/events/sched.h>
+
+@@ -2629,10 +2630,12 @@ static void ftrace_run_update_code(int c
+ {
+ int ret;
+
++ mutex_lock(&text_mutex);
++
+ ret = ftrace_arch_code_modify_prepare();
+ FTRACE_WARN_ON(ret);
+ if (ret)
+- return;
++ goto out_unlock;
+
+ /*
+ * By default we use stop_machine() to modify the code.
+@@ -2644,6 +2647,9 @@ static void ftrace_run_update_code(int c
+
+ ret = ftrace_arch_code_modify_post_process();
+ FTRACE_WARN_ON(ret);
++
++out_unlock:
++ mutex_unlock(&text_mutex);
+ }
+
+ static void ftrace_run_modify_code(struct ftrace_ops *ops, int command,
+@@ -5409,6 +5415,7 @@ void ftrace_module_enable(struct module
+ struct ftrace_page *pg;
+
+ mutex_lock(&ftrace_lock);
++ mutex_lock(&text_mutex);
+
+ if (ftrace_disabled)
+ goto out_unlock;
+@@ -5469,6 +5476,7 @@ void ftrace_module_enable(struct module
+ ftrace_arch_code_modify_post_process();
+
+ out_unlock:
++ mutex_unlock(&text_mutex);
+ mutex_unlock(&ftrace_lock);
+ }
+
diff --git a/patches.suse/pci-iov-add-flag-so-platforms-can-skip-vf-scanning b/patches.suse/pci-iov-add-flag-so-platforms-can-skip-vf-scanning
new file mode 100644
index 0000000000..839de348fb
--- /dev/null
+++ b/patches.suse/pci-iov-add-flag-so-platforms-can-skip-vf-scanning
@@ -0,0 +1,52 @@
+From: Sebastian Ott <sebott@linux.ibm.com>
+Date: Fri, 21 Dec 2018 15:14:19 +0100
+Subject: PCI/IOV: Add flag so platforms can skip VF scanning
+Git-commit: aff68a5a621e2569d126b817d0d42f658df524bf
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-5803 FATE#327056
+
+Provide a flag to skip scanning for new VFs after SR-IOV enablement. This
+can be set by implementations for which the VFs are already reported by
+other means.
+
+Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ drivers/pci/iov.c | 6 ++++++
+ include/linux/pci.h | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/pci/iov.c
++++ b/drivers/pci/iov.c
+@@ -229,6 +229,9 @@ static int sriov_add_vfs(struct pci_dev
+ unsigned int i;
+ int rc;
+
++ if (dev->no_vf_scan)
++ return 0;
++
+ for (i = 0; i < num_vfs; i++) {
+ rc = pci_iov_add_virtfn(dev, i);
+ if (rc)
+@@ -357,6 +360,9 @@ static void sriov_del_vfs(struct pci_dev
+ struct pci_sriov *iov = dev->sriov;
+ int i;
+
++ if (dev->no_vf_scan)
++ return;
++
+ for (i = 0; i < iov->num_VFs; i++)
+ pci_iov_remove_virtfn(dev, i);
+ }
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -404,6 +404,7 @@ struct pci_dev {
+ unsigned int irq_managed:1;
+ unsigned int has_secondary_link:1;
+ unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
++ unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
+ pci_dev_flags_t dev_flags;
+ atomic_t enable_cnt; /* pci_enable_device has been called */
+
diff --git a/patches.suse/pci-iov-factor-out-sriov_add_vfs b/patches.suse/pci-iov-factor-out-sriov_add_vfs
new file mode 100644
index 0000000000..4797bdbbff
--- /dev/null
+++ b/patches.suse/pci-iov-factor-out-sriov_add_vfs
@@ -0,0 +1,98 @@
+From: Sebastian Ott <sebott@linux.ibm.com>
+Date: Fri, 21 Dec 2018 15:14:18 +0100
+Subject: PCI/IOV: Factor out sriov_add_vfs()
+Git-commit: 18f9e9d150fccfa747875df6f0a9f606740762b3
+Patch-mainline: v5.0-rc1
+References: jsc#SLE-5803 FATE#327056
+
+Provide sriov_add_vfs() as a wrapper to scan for VFs that cleans up after
+itself. This is just a code simplification. No functional change.
+
+Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Acked-by: Petr Tesarik <ptesarik@suse.com>
+---
+ drivers/pci/iov.c | 44 +++++++++++++++++++++++++++++++-------------
+ 1 file changed, 31 insertions(+), 13 deletions(-)
+
+--- a/drivers/pci/iov.c
++++ b/drivers/pci/iov.c
+@@ -224,6 +224,24 @@ int __weak pcibios_sriov_disable(struct
+ return 0;
+ }
+
++static int sriov_add_vfs(struct pci_dev *dev, u16 num_vfs)
++{
++ unsigned int i;
++ int rc;
++
++ for (i = 0; i < num_vfs; i++) {
++ rc = pci_iov_add_virtfn(dev, i);
++ if (rc)
++ goto failed;
++ }
++ return 0;
++failed:
++ while (i--)
++ pci_iov_remove_virtfn(dev, i);
++
++ return rc;
++}
++
+ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
+ {
+ int rc;
+@@ -309,21 +327,15 @@ static int sriov_enable(struct pci_dev *
+ msleep(100);
+ pci_cfg_access_unlock(dev);
+
+- for (i = 0; i < initial; i++) {
+- rc = pci_iov_add_virtfn(dev, i);
+- if (rc)
+- goto failed;
+- }
++ rc = sriov_add_vfs(dev, initial);
++ if (rc)
++ goto err_pcibios;
+
+ kobject_uevent(&dev->dev.kobj, KOBJ_CHANGE);
+ iov->num_VFs = nr_virtfn;
+
+ return 0;
+
+-failed:
+- while (i--)
+- pci_iov_remove_virtfn(dev, i);
+-
+ err_pcibios:
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ pci_cfg_access_lock(dev);
+@@ -340,17 +352,23 @@ err_pcibios:
+ return rc;
+ }
+
+-static void sriov_disable(struct pci_dev *dev)
++static void sriov_del_vfs(struct pci_dev *dev)
+ {
++ struct pci_sriov *iov = dev->sriov;
+ int i;
++
++ for (i = 0; i < iov->num_VFs; i++)
++ pci_iov_remove_virtfn(dev, i);
++}
++
++static void sriov_disable(struct pci_dev *dev)
++{
+ struct pci_sriov *iov = dev->sriov;
+
+ if (!iov->num_VFs)
+ return;
+
+- for (i = 0; i < iov->num_VFs; i++)
+- pci_iov_remove_virtfn(dev, i);
+-
++ sriov_del_vfs(dev);
+ iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ pci_cfg_access_lock(dev);
+ pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
diff --git a/patches.suse/perf-x86-intel-cstate-Support-multi-die-package.patch b/patches.suse/perf-x86-intel-cstate-Support-multi-die-package.patch
new file mode 100644
index 0000000000..f6e2c811cb
--- /dev/null
+++ b/patches.suse/perf-x86-intel-cstate-Support-multi-die-package.patch
@@ -0,0 +1,73 @@
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Mon, 13 May 2019 13:58:59 -0400
+Subject: perf/x86/intel/cstate: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: cb63ba0f670df1f0ddf21c6cc4bbe74db398742c
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Some cstate counters become die-scoped on Xeon Cascade Lake-AP. Perf cstate
+driver needs to support die-scope cstate counters.
+
+Use topology_die_cpumask() to replace topology_core_cpumask(). For
+previous platforms which doesn't have multi-die, topology_die_cpumask() is
+identical as topology_core_cpumask(). There is no functional change for
+previous platforms.
+
+Name the die-scope PMU "cstate_die".
+
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lkml.kernel.org/r/acb5e483287280eeb2b6daabe04a600b85e72a78.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/cstate.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/arch/x86/events/intel/cstate.c
++++ b/arch/x86/events/intel/cstate.c
+@@ -306,7 +306,7 @@ static int cstate_pmu_event_init(struct
+ return -EINVAL;
+ event->hw.event_base = pkg_msr[cfg].msr;
+ cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
+- topology_core_cpumask(event->cpu));
++ topology_die_cpumask(event->cpu));
+ } else {
+ return -ENOENT;
+ }
+@@ -389,7 +389,7 @@ static int cstate_cpu_exit(unsigned int
+ if (has_cstate_pkg &&
+ cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
+
+- target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
++ target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
+ /* Migrate events if there is a valid target */
+ if (target < nr_cpu_ids) {
+ cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
+@@ -418,7 +418,7 @@ static int cstate_cpu_init(unsigned int
+ * in the package cpu mask as the designated reader.
+ */
+ target = cpumask_any_and(&cstate_pkg_cpu_mask,
+- topology_core_cpumask(cpu));
++ topology_die_cpumask(cpu));
+ if (has_cstate_pkg && target >= nr_cpu_ids)
+ cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
+
+@@ -631,7 +631,13 @@ static int __init cstate_init(void)
+ }
+
+ if (has_cstate_pkg) {
+- err = perf_pmu_register(&cstate_pkg_pmu, cstate_pkg_pmu.name, -1);
++ if (topology_max_die_per_package() > 1) {
++ err = perf_pmu_register(&cstate_pkg_pmu,
++ "cstate_die", -1);
++ } else {
++ err = perf_pmu_register(&cstate_pkg_pmu,
++ cstate_pkg_pmu.name, -1);
++ }
+ if (err) {
+ has_cstate_pkg = false;
+ pr_info("Failed to register cstate pkg pmu\n");
diff --git a/patches.suse/perf-x86-intel-rapl-Cosmetic-rename-internal-variabl.patch b/patches.suse/perf-x86-intel-rapl-Cosmetic-rename-internal-variabl.patch
new file mode 100644
index 0000000000..5cc98f2cbe
--- /dev/null
+++ b/patches.suse/perf-x86-intel-rapl-Cosmetic-rename-internal-variabl.patch
@@ -0,0 +1,82 @@
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Mon, 13 May 2019 13:59:03 -0400
+Subject: perf/x86/intel/rapl: Cosmetic rename internal variables in response
+ to multi-die/pkg support
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: eb876fbc248e6eb4773a5bc80d205ff7262b1bb5
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Syntax update only -- no logical or functional change.
+
+In response to the new multi-die/package changes, update variable names to
+use "die" terminology, instead of "pkg".
+
+For previous platforms which doesn't have multi-die, "die" is identical as
+"pkg".
+
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lkml.kernel.org/r/0ddb97e121397d37933233da303556141814fa47.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/rapl.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/x86/events/intel/rapl.c
++++ b/arch/x86/events/intel/rapl.c
+@@ -148,7 +148,7 @@ struct rapl_pmu {
+
+ struct rapl_pmus {
+ struct pmu pmu;
+- unsigned int maxpkg;
++ unsigned int maxdie;
+ struct rapl_pmu *pmus[];
+ };
+
+@@ -161,13 +161,13 @@ static u64 rapl_timer_ms;
+
+ static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu)
+ {
+- unsigned int pkgid = topology_logical_die_id(cpu);
++ unsigned int dieid = topology_logical_die_id(cpu);
+
+ /*
+ * The unsigned check also catches the '-1' return value for non
+ * existent mappings in the topology map.
+ */
+- return pkgid < rapl_pmus->maxpkg ? rapl_pmus->pmus[pkgid] : NULL;
++ return dieid < rapl_pmus->maxdie ? rapl_pmus->pmus[dieid] : NULL;
+ }
+
+ static inline u64 rapl_read_counter(struct perf_event *event)
+@@ -674,22 +674,22 @@ static void cleanup_rapl_pmus(void)
+ {
+ int i;
+
+- for (i = 0; i < rapl_pmus->maxpkg; i++)
++ for (i = 0; i < rapl_pmus->maxdie; i++)
+ kfree(rapl_pmus->pmus[i]);
+ kfree(rapl_pmus);
+ }
+
+ static int __init init_rapl_pmus(void)
+ {
+- int maxpkg = topology_max_packages() * topology_max_die_per_package();
++ int maxdie = topology_max_packages() * topology_max_die_per_package();
+ size_t size;
+
+- size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *);
++ size = sizeof(*rapl_pmus) + maxdie * sizeof(struct rapl_pmu *);
+ rapl_pmus = kzalloc(size, GFP_KERNEL);
+ if (!rapl_pmus)
+ return -ENOMEM;
+
+- rapl_pmus->maxpkg = maxpkg;
++ rapl_pmus->maxdie = maxdie;
+ rapl_pmus->pmu.attr_groups = rapl_attr_groups;
+ rapl_pmus->pmu.task_ctx_nr = perf_invalid_context;
+ rapl_pmus->pmu.event_init = rapl_pmu_event_init;
diff --git a/patches.suse/perf-x86-intel-rapl-Support-multi-die-package.patch b/patches.suse/perf-x86-intel-rapl-Support-multi-die-package.patch
new file mode 100644
index 0000000000..08ad428cea
--- /dev/null
+++ b/patches.suse/perf-x86-intel-rapl-Support-multi-die-package.patch
@@ -0,0 +1,78 @@
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Mon, 13 May 2019 13:58:58 -0400
+Subject: perf/x86/intel/rapl: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: b10b3efb88e7bba12f09f71740bab9b7225631c9
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+RAPL becomes die-scope on Xeon Cascade Lake-AP. Perf RAPL driver needs to
+support die-scope RAPL domain.
+
+Use topology_logical_die_id() to replace topology_logical_package_id().
+For previous platforms which doesn't have multi-die,
+topology_logical_die_id() is identical as topology_logical_package_id().
+
+Use topology_die_cpumask() to replace topology_core_cpumask(). For
+previous platforms which doesn't have multi-die, topology_die_cpumask() is
+identical as topology_core_cpumask().
+
+There is no functional change for previous platforms.
+
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lkml.kernel.org/r/851320c8c87ba7a54e58ee8579c1bf566ce23cbb.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/rapl.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/events/intel/rapl.c
++++ b/arch/x86/events/intel/rapl.c
+@@ -161,7 +161,7 @@ static u64 rapl_timer_ms;
+
+ static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu)
+ {
+- unsigned int pkgid = topology_logical_package_id(cpu);
++ unsigned int pkgid = topology_logical_die_id(cpu);
+
+ /*
+ * The unsigned check also catches the '-1' return value for non
+@@ -577,7 +577,7 @@ static int rapl_cpu_offline(unsigned int
+
+ pmu->cpu = -1;
+ /* Find a new cpu to collect rapl events */
+- target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
++ target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
+
+ /* Migrate rapl events to the new target */
+ if (target < nr_cpu_ids) {
+@@ -604,14 +604,14 @@ static int rapl_cpu_online(unsigned int
+ pmu->timer_interval = ms_to_ktime(rapl_timer_ms);
+ rapl_hrtimer_init(pmu);
+
+- rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu;
++ rapl_pmus->pmus[topology_logical_die_id(cpu)] = pmu;
+ }
+
+ /*
+ * Check if there is an online cpu in the package which collects rapl
+ * events already.
+ */
+- target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu));
++ target = cpumask_any_and(&rapl_cpu_mask, topology_die_cpumask(cpu));
+ if (target < nr_cpu_ids)
+ return 0;
+
+@@ -681,7 +681,7 @@ static void cleanup_rapl_pmus(void)
+
+ static int __init init_rapl_pmus(void)
+ {
+- int maxpkg = topology_max_packages();
++ int maxpkg = topology_max_packages() * topology_max_die_per_package();
+ size_t size;
+
+ size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *);
diff --git a/patches.suse/perf-x86-intel-uncore-Cosmetic-renames-in-response-t.patch b/patches.suse/perf-x86-intel-uncore-Cosmetic-renames-in-response-t.patch
new file mode 100644
index 0000000000..8f661739f6
--- /dev/null
+++ b/patches.suse/perf-x86-intel-uncore-Cosmetic-renames-in-response-t.patch
@@ -0,0 +1,326 @@
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Mon, 13 May 2019 13:59:02 -0400
+Subject: perf/x86/intel/uncore: Cosmetic renames in response to multi-die/pkg
+ support
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: b0529b9cafacfd054837ea6b8c4ef7b402716744
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Syntax update only -- no logical or functional change.
+
+In response to the new multi-die/package changes, update variable names to
+use "die" terminology, instead of "pkg".
+
+For previous platforms which doesn't have multi-die, "die" is identical as
+"pkg".
+
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lkml.kernel.org/r/f0ea5e501288329135e94f51969ff54a03c50e2e.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/uncore.c | 74 +++++++++++++++++------------------
+ arch/x86/events/intel/uncore.h | 4 -
+ arch/x86/events/intel/uncore_snbep.c | 4 -
+ 3 files changed, 41 insertions(+), 41 deletions(-)
+
+--- a/arch/x86/events/intel/uncore.c
++++ b/arch/x86/events/intel/uncore.c
+@@ -14,7 +14,7 @@ struct pci_driver *uncore_pci_driver;
+ DEFINE_RAW_SPINLOCK(pci2phy_map_lock);
+ struct list_head pci2phy_map_head = LIST_HEAD_INIT(pci2phy_map_head);
+ struct pci_extra_dev *uncore_extra_pci_dev;
+-static int max_packages;
++static int max_dies;
+
+ /* mask of cpus that collect uncore events */
+ static cpumask_t uncore_cpu_mask;
+@@ -100,13 +100,13 @@ ssize_t uncore_event_show(struct kobject
+
+ struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
+ {
+- unsigned int pkgid = topology_logical_die_id(cpu);
++ unsigned int dieid = topology_logical_die_id(cpu);
+
+ /*
+ * The unsigned check also catches the '-1' return value for non
+ * existent mappings in the topology map.
+ */
+- return pkgid < max_packages ? pmu->boxes[pkgid] : NULL;
++ return dieid < max_dies ? pmu->boxes[dieid] : NULL;
+ }
+
+ u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
+@@ -311,7 +311,7 @@ static struct intel_uncore_box *uncore_a
+ uncore_pmu_init_hrtimer(box);
+ box->cpu = -1;
+ box->pci_phys_id = -1;
+- box->pkgid = -1;
++ box->dieid = -1;
+
+ /* set default hrtimer timeout */
+ box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
+@@ -832,10 +832,10 @@ static void uncore_pmu_unregister(struct
+
+ static void uncore_free_boxes(struct intel_uncore_pmu *pmu)
+ {
+- int pkg;
++ int die;
+
+- for (pkg = 0; pkg < max_packages; pkg++)
+- kfree(pmu->boxes[pkg]);
++ for (die = 0; die < max_dies; die++)
++ kfree(pmu->boxes[die]);
+ kfree(pmu->boxes);
+ }
+
+@@ -874,7 +874,7 @@ static int __init uncore_type_init(struc
+ if (!pmus)
+ return -ENOMEM;
+
+- size = max_packages * sizeof(struct intel_uncore_box *);
++ size = max_dies * sizeof(struct intel_uncore_box *);
+
+ for (i = 0; i < type->num_boxes; i++) {
+ pmus[i].func_id = setid ? i : -1;
+@@ -941,21 +941,21 @@ static int uncore_pci_probe(struct pci_d
+ struct intel_uncore_type *type;
+ struct intel_uncore_pmu *pmu = NULL;
+ struct intel_uncore_box *box;
+- int phys_id, pkg, ret;
++ int phys_id, die, ret;
+
+ phys_id = uncore_pcibus_to_physid(pdev->bus);
+ if (phys_id < 0)
+ return -ENODEV;
+
+- pkg = (topology_max_die_per_package() > 1) ? phys_id :
++ die = (topology_max_die_per_package() > 1) ? phys_id :
+ topology_phys_to_logical_pkg(phys_id);
+- if (pkg < 0)
++ if (die < 0)
+ return -EINVAL;
+
+ if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
+ int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
+
+- uncore_extra_pci_dev[pkg].dev[idx] = pdev;
++ uncore_extra_pci_dev[die].dev[idx] = pdev;
+ pci_set_drvdata(pdev, NULL);
+ return 0;
+ }
+@@ -994,7 +994,7 @@ static int uncore_pci_probe(struct pci_d
+ pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
+ }
+
+- if (WARN_ON_ONCE(pmu->boxes[pkg] != NULL))
++ if (WARN_ON_ONCE(pmu->boxes[die] != NULL))
+ return -EINVAL;
+
+ box = uncore_alloc_box(type, NUMA_NO_NODE);
+@@ -1008,13 +1008,13 @@ static int uncore_pci_probe(struct pci_d
+
+ atomic_inc(&box->refcnt);
+ box->pci_phys_id = phys_id;
+- box->pkgid = pkg;
++ box->dieid = die;
+ box->pci_dev = pdev;
+ box->pmu = pmu;
+ uncore_box_init(box);
+ pci_set_drvdata(pdev, box);
+
+- pmu->boxes[pkg] = box;
++ pmu->boxes[die] = box;
+ if (atomic_inc_return(&pmu->activeboxes) > 1)
+ return 0;
+
+@@ -1022,7 +1022,7 @@ static int uncore_pci_probe(struct pci_d
+ ret = uncore_pmu_register(pmu);
+ if (ret) {
+ pci_set_drvdata(pdev, NULL);
+- pmu->boxes[pkg] = NULL;
++ pmu->boxes[die] = NULL;
+ uncore_box_exit(box);
+ kfree(box);
+ }
+@@ -1033,17 +1033,17 @@ static void uncore_pci_remove(struct pci
+ {
+ struct intel_uncore_box *box;
+ struct intel_uncore_pmu *pmu;
+- int i, phys_id, pkg;
++ int i, phys_id, die;
+
+ phys_id = uncore_pcibus_to_physid(pdev->bus);
+- pkg = (topology_max_die_per_package() > 1) ? phys_id :
++ die = (topology_max_die_per_package() > 1) ? phys_id :
+ topology_phys_to_logical_pkg(phys_id);
+
+ box = pci_get_drvdata(pdev);
+ if (!box) {
+ for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
+- if (uncore_extra_pci_dev[pkg].dev[i] == pdev) {
+- uncore_extra_pci_dev[pkg].dev[i] = NULL;
++ if (uncore_extra_pci_dev[die].dev[i] == pdev) {
++ uncore_extra_pci_dev[die].dev[i] = NULL;
+ break;
+ }
+ }
+@@ -1056,7 +1056,7 @@ static void uncore_pci_remove(struct pci
+ return;
+
+ pci_set_drvdata(pdev, NULL);
+- pmu->boxes[pkg] = NULL;
++ pmu->boxes[die] = NULL;
+ if (atomic_dec_return(&pmu->activeboxes) == 0)
+ uncore_pmu_unregister(pmu);
+ uncore_box_exit(box);
+@@ -1068,7 +1068,7 @@ static int __init uncore_pci_init(void)
+ size_t size;
+ int ret;
+
+- size = max_packages * sizeof(struct pci_extra_dev);
++ size = max_dies * sizeof(struct pci_extra_dev);
+ uncore_extra_pci_dev = kzalloc(size, GFP_KERNEL);
+ if (!uncore_extra_pci_dev) {
+ ret = -ENOMEM;
+@@ -1115,11 +1115,11 @@ static void uncore_change_type_ctx(struc
+ {
+ struct intel_uncore_pmu *pmu = type->pmus;
+ struct intel_uncore_box *box;
+- int i, pkg;
++ int i, die;
+
+- pkg = topology_logical_die_id(old_cpu < 0 ? new_cpu : old_cpu);
++ die = topology_logical_die_id(old_cpu < 0 ? new_cpu : old_cpu);
+ for (i = 0; i < type->num_boxes; i++, pmu++) {
+- box = pmu->boxes[pkg];
++ box = pmu->boxes[die];
+ if (!box)
+ continue;
+
+@@ -1152,7 +1152,7 @@ static int uncore_event_cpu_offline(unsi
+ struct intel_uncore_type *type, **types = uncore_msr_uncores;
+ struct intel_uncore_pmu *pmu;
+ struct intel_uncore_box *box;
+- int i, pkg, target;
++ int i, die, target;
+
+ /* Check if exiting cpu is used for collecting uncore events */
+ if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
+@@ -1171,12 +1171,12 @@ static int uncore_event_cpu_offline(unsi
+
+ unref:
+ /* Clear the references */
+- pkg = topology_logical_die_id(cpu);
++ die = topology_logical_die_id(cpu);
+ for (; *types; types++) {
+ type = *types;
+ pmu = type->pmus;
+ for (i = 0; i < type->num_boxes; i++, pmu++) {
+- box = pmu->boxes[pkg];
++ box = pmu->boxes[die];
+ if (box && atomic_dec_return(&box->refcnt) == 0)
+ uncore_box_exit(box);
+ }
+@@ -1185,7 +1185,7 @@ unref:
+ }
+
+ static int allocate_boxes(struct intel_uncore_type **types,
+- unsigned int pkg, unsigned int cpu)
++ unsigned int die, unsigned int cpu)
+ {
+ struct intel_uncore_box *box, *tmp;
+ struct intel_uncore_type *type;
+@@ -1198,20 +1198,20 @@ static int allocate_boxes(struct intel_u
+ type = *types;
+ pmu = type->pmus;
+ for (i = 0; i < type->num_boxes; i++, pmu++) {
+- if (pmu->boxes[pkg])
++ if (pmu->boxes[die])
+ continue;
+ box = uncore_alloc_box(type, cpu_to_node(cpu));
+ if (!box)
+ goto cleanup;
+ box->pmu = pmu;
+- box->pkgid = pkg;
++ box->dieid = die;
+ list_add(&box->active_list, &allocated);
+ }
+ }
+ /* Install them in the pmus */
+ list_for_each_entry_safe(box, tmp, &allocated, active_list) {
+ list_del_init(&box->active_list);
+- box->pmu->boxes[pkg] = box;
++ box->pmu->boxes[die] = box;
+ }
+ return 0;
+
+@@ -1228,10 +1228,10 @@ static int uncore_event_cpu_online(unsig
+ struct intel_uncore_type *type, **types = uncore_msr_uncores;
+ struct intel_uncore_pmu *pmu;
+ struct intel_uncore_box *box;
+- int i, ret, pkg, target;
++ int i, ret, die, target;
+
+- pkg = topology_logical_die_id(cpu);
+- ret = allocate_boxes(types, pkg, cpu);
++ die = topology_logical_die_id(cpu);
++ ret = allocate_boxes(types, die, cpu);
+ if (ret)
+ return ret;
+
+@@ -1239,7 +1239,7 @@ static int uncore_event_cpu_online(unsig
+ type = *types;
+ pmu = type->pmus;
+ for (i = 0; i < type->num_boxes; i++, pmu++) {
+- box = pmu->boxes[pkg];
++ box = pmu->boxes[die];
+ if (box && atomic_inc_return(&box->refcnt) == 1)
+ uncore_box_init(box);
+ }
+@@ -1418,7 +1418,7 @@ static int __init intel_uncore_init(void
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ return -ENODEV;
+
+- max_packages = topology_max_packages() * topology_max_die_per_package();
++ max_dies = topology_max_packages() * topology_max_die_per_package();
+
+ uncore_init = (struct intel_uncore_init_fun *)id->driver_data;
+ if (uncore_init->pci_init) {
+--- a/arch/x86/events/intel/uncore.h
++++ b/arch/x86/events/intel/uncore.h
+@@ -107,7 +107,7 @@ struct intel_uncore_extra_reg {
+
+ struct intel_uncore_box {
+ int pci_phys_id;
+- int pkgid;
++ int dieid; /* Logical die ID */
+ int n_active; /* number of active events */
+ int n_events;
+ int cpu; /* cpu to collect events */
+@@ -466,7 +466,7 @@ static inline void uncore_box_exit(struc
+
+ static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
+ {
+- return (box->pkgid < 0);
++ return (box->dieid < 0);
+ }
+
+ static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
+--- a/arch/x86/events/intel/uncore_snbep.c
++++ b/arch/x86/events/intel/uncore_snbep.c
+@@ -1056,8 +1056,8 @@ static void snbep_qpi_enable_event(struc
+
+ if (reg1->idx != EXTRA_REG_NONE) {
+ int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
+- int pkg = topology_phys_to_logical_pkg(box->pci_phys_id);
+- struct pci_dev *filter_pdev = uncore_extra_pci_dev[pkg].dev[idx];
++ int die = topology_phys_to_logical_pkg(box->pci_phys_id);
++ struct pci_dev *filter_pdev = uncore_extra_pci_dev[die].dev[idx];
+
+ if (filter_pdev) {
+ pci_write_config_dword(filter_pdev, reg1->reg,
diff --git a/patches.suse/perf-x86-intel-uncore-Support-multi-die-package.patch b/patches.suse/perf-x86-intel-uncore-Support-multi-die-package.patch
new file mode 100644
index 0000000000..65a67f2462
--- /dev/null
+++ b/patches.suse/perf-x86-intel-uncore-Support-multi-die-package.patch
@@ -0,0 +1,120 @@
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Mon, 13 May 2019 13:58:57 -0400
+Subject: perf/x86/intel/uncore: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 1ff4a47b2d0c13b755b2eeeb0e23be6c056d5dd9
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Uncore becomes die-scope on Xeon Cascade Lake-AP. Uncore driver needs to
+support die-scope uncore units.
+
+Use topology_logical_die_id() to replace topology_logical_package_id().
+For previous platforms which doesn't have multi-die,
+topology_logical_die_id() is identical as topology_logical_package_id().
+
+In pci_probe()/remove(), the group id reads from PCI BUS is logical die id
+for multi-die systems.
+
+Use topology_die_cpumask() to replace topology_core_cpumask().
+For previous platforms which doesn't have multi-die,
+topology_die_cpumask() is identical as topology_core_cpumask().
+
+There is no functional change for previous platforms.
+
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lkml.kernel.org/r/a25bba4a5b480aa4e9f8190005d7f5f53e29c8da.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/uncore.c | 20 +++++++++++---------
+ 1 file changed, 11 insertions(+), 9 deletions(-)
+
+--- a/arch/x86/events/intel/uncore.c
++++ b/arch/x86/events/intel/uncore.c
+@@ -100,7 +100,7 @@ ssize_t uncore_event_show(struct kobject
+
+ struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
+ {
+- unsigned int pkgid = topology_logical_package_id(cpu);
++ unsigned int pkgid = topology_logical_die_id(cpu);
+
+ /*
+ * The unsigned check also catches the '-1' return value for non
+@@ -947,7 +947,8 @@ static int uncore_pci_probe(struct pci_d
+ if (phys_id < 0)
+ return -ENODEV;
+
+- pkg = topology_phys_to_logical_pkg(phys_id);
++ pkg = (topology_max_die_per_package() > 1) ? phys_id :
++ topology_phys_to_logical_pkg(phys_id);
+ if (pkg < 0)
+ return -EINVAL;
+
+@@ -1035,7 +1036,8 @@ static void uncore_pci_remove(struct pci
+ int i, phys_id, pkg;
+
+ phys_id = uncore_pcibus_to_physid(pdev->bus);
+- pkg = topology_phys_to_logical_pkg(phys_id);
++ pkg = (topology_max_die_per_package() > 1) ? phys_id :
++ topology_phys_to_logical_pkg(phys_id);
+
+ box = pci_get_drvdata(pdev);
+ if (!box) {
+@@ -1115,7 +1117,7 @@ static void uncore_change_type_ctx(struc
+ struct intel_uncore_box *box;
+ int i, pkg;
+
+- pkg = topology_logical_package_id(old_cpu < 0 ? new_cpu : old_cpu);
++ pkg = topology_logical_die_id(old_cpu < 0 ? new_cpu : old_cpu);
+ for (i = 0; i < type->num_boxes; i++, pmu++) {
+ box = pmu->boxes[pkg];
+ if (!box)
+@@ -1156,7 +1158,7 @@ static int uncore_event_cpu_offline(unsi
+ if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
+ goto unref;
+ /* Find a new cpu to collect uncore events */
+- target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
++ target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
+
+ /* Migrate uncore events to the new target */
+ if (target < nr_cpu_ids)
+@@ -1169,7 +1171,7 @@ static int uncore_event_cpu_offline(unsi
+
+ unref:
+ /* Clear the references */
+- pkg = topology_logical_package_id(cpu);
++ pkg = topology_logical_die_id(cpu);
+ for (; *types; types++) {
+ type = *types;
+ pmu = type->pmus;
+@@ -1228,7 +1230,7 @@ static int uncore_event_cpu_online(unsig
+ struct intel_uncore_box *box;
+ int i, ret, pkg, target;
+
+- pkg = topology_logical_package_id(cpu);
++ pkg = topology_logical_die_id(cpu);
+ ret = allocate_boxes(types, pkg, cpu);
+ if (ret)
+ return ret;
+@@ -1247,7 +1249,7 @@ static int uncore_event_cpu_online(unsig
+ * Check if there is an online cpu in the package
+ * which collects uncore events already.
+ */
+- target = cpumask_any_and(&uncore_cpu_mask, topology_core_cpumask(cpu));
++ target = cpumask_any_and(&uncore_cpu_mask, topology_die_cpumask(cpu));
+ if (target < nr_cpu_ids)
+ return 0;
+
+@@ -1416,7 +1418,7 @@ static int __init intel_uncore_init(void
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ return -ENODEV;
+
+- max_packages = topology_max_packages();
++ max_packages = topology_max_packages() * topology_max_die_per_package();
+
+ uncore_init = (struct intel_uncore_init_fun *)id->driver_data;
+ if (uncore_init->pci_init) {
diff --git a/patches.suse/powercap-intel_rapl-Simplify-rapl_find_package.patch b/patches.suse/powercap-intel_rapl-Simplify-rapl_find_package.patch
new file mode 100644
index 0000000000..c867a0a6f7
--- /dev/null
+++ b/patches.suse/powercap-intel_rapl-Simplify-rapl_find_package.patch
@@ -0,0 +1,96 @@
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 13 May 2019 13:58:50 -0400
+Subject: powercap/intel_rapl: Simplify rapl_find_package()
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: aadf7b38337108627b014fb285147aacdfafe42e
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Simplify how the code to discover a package is called. Rename
+find_package_by_id() to rapl_find_package_domain()
+
+Syntax only, no functional or semantic change.
+
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: linux-pm@vger.kernel.org
+Link: https://lkml.kernel.org/r/ae3d1903407fd6e3684234b674f4f0e62c2ab54c.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/powercap/intel_rapl.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/drivers/powercap/intel_rapl.c
++++ b/drivers/powercap/intel_rapl.c
+@@ -262,8 +262,9 @@ static struct powercap_control_type *con
+ static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
+
+ /* caller to ensure CPU hotplug lock is held */
+-static struct rapl_package *find_package_by_id(int id)
++static struct rapl_package *rapl_find_package_domain(int cpu)
+ {
++ int id = topology_physical_package_id(cpu);
+ struct rapl_package *rp;
+
+ list_for_each_entry(rp, &rapl_packages, plist) {
+@@ -1302,7 +1303,7 @@ static int __init rapl_register_psys(voi
+ rd->rpl[0].name = pl1_name;
+ rd->rpl[1].prim_id = PL2_ENABLE;
+ rd->rpl[1].name = pl2_name;
+- rd->rp = find_package_by_id(0);
++ rd->rp = rapl_find_package_domain(0);
+
+ power_zone = powercap_register_zone(&rd->power_zone, control_type,
+ "psys", NULL,
+@@ -1458,8 +1459,9 @@ static void rapl_remove_package(struct r
+ }
+
+ /* called from CPU hotplug notifier, hotplug lock held */
+-static struct rapl_package *rapl_add_package(int cpu, int pkgid)
++static struct rapl_package *rapl_add_package(int cpu)
+ {
++ int id = topology_physical_package_id(cpu);
+ struct rapl_package *rp;
+ int ret;
+
+@@ -1468,7 +1470,7 @@ static struct rapl_package *rapl_add_pac
+ return ERR_PTR(-ENOMEM);
+
+ /* add the new package to the list */
+- rp->id = pkgid;
++ rp->id = id;
+ rp->lead_cpu = cpu;
+
+ /* check if the package contains valid domains */
+@@ -1499,12 +1501,11 @@ err_free_package:
+ */
+ static int rapl_cpu_online(unsigned int cpu)
+ {
+- int pkgid = topology_physical_package_id(cpu);
+ struct rapl_package *rp;
+
+- rp = find_package_by_id(pkgid);
++ rp = rapl_find_package_domain(cpu);
+ if (!rp) {
+- rp = rapl_add_package(cpu, pkgid);
++ rp = rapl_add_package(cpu);
+ if (IS_ERR(rp))
+ return PTR_ERR(rp);
+ }
+@@ -1514,11 +1515,10 @@ static int rapl_cpu_online(unsigned int
+
+ static int rapl_cpu_down_prep(unsigned int cpu)
+ {
+- int pkgid = topology_physical_package_id(cpu);
+ struct rapl_package *rp;
+ int lead_cpu;
+
+- rp = find_package_by_id(pkgid);
++ rp = rapl_find_package_domain(cpu);
+ if (!rp)
+ return 0;
+
diff --git a/patches.suse/powercap-intel_rapl-Support-multi-die-package.patch b/patches.suse/powercap-intel_rapl-Support-multi-die-package.patch
new file mode 100644
index 0000000000..2eb7a21daa
--- /dev/null
+++ b/patches.suse/powercap-intel_rapl-Support-multi-die-package.patch
@@ -0,0 +1,49 @@
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 13 May 2019 13:58:51 -0400
+Subject: powercap/intel_rapl: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 32fb480e0a2cf1f71e4174d6477198c94dbc746c
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+RAPL "package" domains are actually implemented in hardware per-die.
+Thus, the new multi-die/package systems have mulitple domains
+within each physical package.
+
+Update the intel_rapl driver to be "die aware" -- exporting multiple
+domains within a single package, when present. No change on single
+die/package systems.
+
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: linux-pm@vger.kernel.org
+Link: https://lkml.kernel.org/r/9fcb4719aeb7efccf3bc75ed8dd559e46121649f.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/powercap/intel_rapl.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/powercap/intel_rapl.c
++++ b/drivers/powercap/intel_rapl.c
+@@ -264,7 +264,7 @@ static struct rapl_domain *platform_rapl
+ /* caller to ensure CPU hotplug lock is held */
+ static struct rapl_package *rapl_find_package_domain(int cpu)
+ {
+- int id = topology_physical_package_id(cpu);
++ int id = topology_logical_die_id(cpu);
+ struct rapl_package *rp;
+
+ list_for_each_entry(rp, &rapl_packages, plist) {
+@@ -1461,7 +1461,7 @@ static void rapl_remove_package(struct r
+ /* called from CPU hotplug notifier, hotplug lock held */
+ static struct rapl_package *rapl_add_package(int cpu)
+ {
+- int id = topology_physical_package_id(cpu);
++ int id = topology_logical_die_id(cpu);
+ struct rapl_package *rp;
+ int ret;
+
diff --git a/patches.suse/powercap-intel_rapl-Update-RAPL-domain-name-and-debu.patch b/patches.suse/powercap-intel_rapl-Update-RAPL-domain-name-and-debu.patch
new file mode 100644
index 0000000000..d471e3f571
--- /dev/null
+++ b/patches.suse/powercap-intel_rapl-Update-RAPL-domain-name-and-debu.patch
@@ -0,0 +1,199 @@
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 13 May 2019 13:58:53 -0400
+Subject: powercap/intel_rapl: Update RAPL domain name and debug messages
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 9ea7612c46586d9eacfd517e73ff76ef294feca0
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+The RAPL domain "name" attribute contains "Package-N", which is ambiguous
+on multi-die per-package systems.
+
+Update the name to "package-X-die-Y" on those systems.
+
+No change on systems without multi-die/package.
+
+Update driver debug messages.
+
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: linux-pm@vger.kernel.org
+Link: https://lkml.kernel.org/r/6510b784e16374447965925588ec6e46d5d007d8.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/powercap/intel_rapl.c | 57 +++++++++++++++++++++++-------------------
+ 1 file changed, 32 insertions(+), 25 deletions(-)
+
+--- a/drivers/powercap/intel_rapl.c
++++ b/drivers/powercap/intel_rapl.c
+@@ -176,12 +176,15 @@ struct rapl_domain {
+ #define power_zone_to_rapl_domain(_zone) \
+ container_of(_zone, struct rapl_domain, power_zone)
+
++/* maximum rapl package domain name: package-%d-die-%d */
++#define PACKAGE_DOMAIN_NAME_LENGTH 30
+
+-/* Each physical package contains multiple domains, these are the common
++
++/* Each rapl package contains multiple domains, these are the common
+ * data across RAPL domains within a package.
+ */
+ struct rapl_package {
+- unsigned int id; /* physical package/socket id */
++ unsigned int id; /* logical die id, equals physical 1-die systems */
+ unsigned int nr_domains;
+ unsigned long domain_map; /* bit map of active domains */
+ unsigned int power_unit;
+@@ -196,6 +199,7 @@ struct rapl_package {
+ int lead_cpu; /* one active cpu per package for access */
+ /* Track active cpus */
+ struct cpumask cpumask;
++ char name[PACKAGE_DOMAIN_NAME_LENGTH];
+ };
+
+ struct rapl_defaults {
+@@ -922,8 +926,8 @@ static int rapl_check_unit_core(struct r
+ value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
+ rp->time_unit = 1000000 / (1 << value);
+
+- pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
+- rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
++ pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n",
++ rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
+
+ return 0;
+ }
+@@ -947,8 +951,8 @@ static int rapl_check_unit_atom(struct r
+ value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
+ rp->time_unit = 1000000 / (1 << value);
+
+- pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
+- rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
++ pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n",
++ rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
+
+ return 0;
+ }
+@@ -1183,7 +1187,7 @@ static void rapl_update_domain_data(stru
+ u64 val;
+
+ for (dmn = 0; dmn < rp->nr_domains; dmn++) {
+- pr_debug("update package %d domain %s data\n", rp->id,
++ pr_debug("update %s domain %s data\n", rp->name,
+ rp->domains[dmn].name);
+ /* exclude non-raw primitives */
+ for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
+@@ -1208,7 +1212,6 @@ static void rapl_unregister_powercap(voi
+ static int rapl_package_register_powercap(struct rapl_package *rp)
+ {
+ struct rapl_domain *rd;
+- char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
+ struct powercap_zone *power_zone = NULL;
+ int nr_pl, ret;;
+
+@@ -1219,20 +1222,16 @@ static int rapl_package_register_powerca
+ for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
+ if (rd->id == RAPL_DOMAIN_PACKAGE) {
+ nr_pl = find_nr_power_limit(rd);
+- pr_debug("register socket %d package domain %s\n",
+- rp->id, rd->name);
+- memset(dev_name, 0, sizeof(dev_name));
+- snprintf(dev_name, sizeof(dev_name), "%s-%d",
+- rd->name, rp->id);
++ pr_debug("register package domain %s\n", rp->name);
+ power_zone = powercap_register_zone(&rd->power_zone,
+ control_type,
+- dev_name, NULL,
++ rp->name, NULL,
+ &zone_ops[rd->id],
+ nr_pl,
+ &constraint_ops);
+ if (IS_ERR(power_zone)) {
+- pr_debug("failed to register package, %d\n",
+- rp->id);
++ pr_debug("failed to register power zone %s\n",
++ rp->name);
+ return PTR_ERR(power_zone);
+ }
+ /* track parent zone in per package/socket data */
+@@ -1258,8 +1257,8 @@ static int rapl_package_register_powerca
+ &constraint_ops);
+
+ if (IS_ERR(power_zone)) {
+- pr_debug("failed to register power_zone, %d:%s:%s\n",
+- rp->id, rd->name, dev_name);
++ pr_debug("failed to register power_zone, %s:%s\n",
++ rp->name, rd->name);
+ ret = PTR_ERR(power_zone);
+ goto err_cleanup;
+ }
+@@ -1272,7 +1271,7 @@ err_cleanup:
+ * failed after the first domain setup.
+ */
+ while (--rd >= rp->domains) {
+- pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
++ pr_debug("unregister %s domain %s\n", rp->name, rd->name);
+ powercap_unregister_zone(control_type, &rd->power_zone);
+ }
+
+@@ -1382,8 +1381,8 @@ static void rapl_detect_powerlimit(struc
+ /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
+ if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
+ if (val64) {
+- pr_info("RAPL package %d domain %s locked by BIOS\n",
+- rd->rp->id, rd->name);
++ pr_info("RAPL %s domain %s locked by BIOS\n",
++ rd->rp->name, rd->name);
+ rd->state |= DOMAIN_STATE_BIOS_LOCKED;
+ }
+ }
+@@ -1412,10 +1411,10 @@ static int rapl_detect_domains(struct ra
+ }
+ rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
+ if (!rp->nr_domains) {
+- pr_debug("no valid rapl domains found in package %d\n", rp->id);
++ pr_debug("no valid rapl domains found in %s\n", rp->name);
+ return -ENODEV;
+ }
+- pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
++ pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name);
+
+ rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
+ GFP_KERNEL);
+@@ -1448,8 +1447,8 @@ static void rapl_remove_package(struct r
+ rd_package = rd;
+ continue;
+ }
+- pr_debug("remove package, undo power limit on %d: %s\n",
+- rp->id, rd->name);
++ pr_debug("remove package, undo power limit on %s: %s\n",
++ rp->name, rd->name);
+ powercap_unregister_zone(control_type, &rd->power_zone);
+ }
+ /* do parent zone last */
+@@ -1463,6 +1462,7 @@ static struct rapl_package *rapl_add_pac
+ {
+ int id = topology_logical_die_id(cpu);
+ struct rapl_package *rp;
++ struct cpuinfo_x86 *c = &cpu_data(cpu);
+ int ret;
+
+ rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
+@@ -1473,6 +1473,13 @@ static struct rapl_package *rapl_add_pac
+ rp->id = id;
+ rp->lead_cpu = cpu;
+
++ if (topology_max_die_per_package() > 1)
++ snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH,
++ "package-%d-die-%d", c->phys_proc_id, c->cpu_die_id);
++ else
++ snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d",
++ c->phys_proc_id);
++
+ /* check if the package contains valid domains */
+ if (rapl_detect_domains(rp, cpu) ||
+ rapl_defaults->check_unit(rp, cpu)) {
diff --git a/patches.suse/thermal-x86_pkg_temp_thermal-Cosmetic-Rename-interna.patch b/patches.suse/thermal-x86_pkg_temp_thermal-Cosmetic-Rename-interna.patch
new file mode 100644
index 0000000000..7ba159fc65
--- /dev/null
+++ b/patches.suse/thermal-x86_pkg_temp_thermal-Cosmetic-Rename-interna.patch
@@ -0,0 +1,404 @@
+From: Len Brown <len.brown@intel.com>
+Date: Mon, 13 May 2019 13:59:00 -0400
+Subject: thermal/x86_pkg_temp_thermal: Cosmetic: Rename internal variables to
+ zones from packages
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: b2ce1c883df91a231f8138935167273c1767ad66
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Syntax update only -- no logical or functional change.
+
+In response to the new multi-die/package changes, update variable names to
+use the more generic thermal "zone" terminology, instead of "package", as
+the zones can refer to either packages or die.
+
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: Zhang Rui <rui.zhang@intel.com>
+Link: https://lkml.kernel.org/r/b65494a76be13481dc3a809c75debb2574c34eda.1557769318.git.len.brown@intel.com
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/thermal/x86_pkg_temp_thermal.c | 142 ++++++++++++++++-----------------
+ 1 file changed, 72 insertions(+), 70 deletions(-)
+
+--- a/drivers/thermal/x86_pkg_temp_thermal.c
++++ b/drivers/thermal/x86_pkg_temp_thermal.c
+@@ -55,7 +55,7 @@ MODULE_PARM_DESC(notify_delay_ms,
+ */
+ #define MAX_NUMBER_OF_TRIPS 2
+
+-struct pkg_device {
++struct zone_device {
+ int cpu;
+ bool work_scheduled;
+ u32 tj_max;
+@@ -70,10 +70,10 @@ static struct thermal_zone_params pkg_te
+ .no_hwmon = true,
+ };
+
+-/* Keep track of how many package pointers we allocated in init() */
+-static int max_packages __read_mostly;
+-/* Array of package pointers */
+-static struct pkg_device **packages;
++/* Keep track of how many zone pointers we allocated in init() */
++static int max_id __read_mostly;
++/* Array of zone pointers */
++static struct zone_device **zones;
+ /* Serializes interrupt notification, work and hotplug */
+ static DEFINE_SPINLOCK(pkg_temp_lock);
+ /* Protects zone operation in the work function against hotplug removal */
+@@ -120,12 +120,12 @@ err_out:
+ *
+ * - Other callsites: Must hold pkg_temp_lock
+ */
+-static struct pkg_device *pkg_temp_thermal_get_dev(unsigned int cpu)
++static struct zone_device *pkg_temp_thermal_get_dev(unsigned int cpu)
+ {
+- int pkgid = topology_logical_die_id(cpu);
++ int id = topology_logical_die_id(cpu);
+
+- if (pkgid >= 0 && pkgid < max_packages)
+- return packages[pkgid];
++ if (id >= 0 && id < max_id)
++ return zones[id];
+ return NULL;
+ }
+
+@@ -150,12 +150,13 @@ static int get_tj_max(int cpu, u32 *tj_m
+
+ static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp)
+ {
+- struct pkg_device *pkgdev = tzd->devdata;
++ struct zone_device *zonedev = tzd->devdata;
+ u32 eax, edx;
+
+- rdmsr_on_cpu(pkgdev->cpu, MSR_IA32_PACKAGE_THERM_STATUS, &eax, &edx);
++ rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_STATUS,
++ &eax, &edx);
+ if (eax & 0x80000000) {
+- *temp = pkgdev->tj_max - ((eax >> 16) & 0x7f) * 1000;
++ *temp = zonedev->tj_max - ((eax >> 16) & 0x7f) * 1000;
+ pr_debug("sys_get_curr_temp %d\n", *temp);
+ return 0;
+ }
+@@ -165,7 +166,7 @@ static int sys_get_curr_temp(struct ther
+ static int sys_get_trip_temp(struct thermal_zone_device *tzd,
+ int trip, int *temp)
+ {
+- struct pkg_device *pkgdev = tzd->devdata;
++ struct zone_device *zonedev = tzd->devdata;
+ unsigned long thres_reg_value;
+ u32 mask, shift, eax, edx;
+ int ret;
+@@ -181,14 +182,14 @@ static int sys_get_trip_temp(struct ther
+ shift = THERM_SHIFT_THRESHOLD0;
+ }
+
+- ret = rdmsr_on_cpu(pkgdev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT,
++ ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT,
+ &eax, &edx);
+ if (ret < 0)
+ return ret;
+
+ thres_reg_value = (eax & mask) >> shift;
+ if (thres_reg_value)
+- *temp = pkgdev->tj_max - thres_reg_value * 1000;
++ *temp = zonedev->tj_max - thres_reg_value * 1000;
+ else
+ *temp = 0;
+ pr_debug("sys_get_trip_temp %d\n", *temp);
+@@ -199,14 +200,14 @@ static int sys_get_trip_temp(struct ther
+ static int
+ sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, int temp)
+ {
+- struct pkg_device *pkgdev = tzd->devdata;
++ struct zone_device *zonedev = tzd->devdata;
+ u32 l, h, mask, shift, intr;
+ int ret;
+
+- if (trip >= MAX_NUMBER_OF_TRIPS || temp >= pkgdev->tj_max)
++ if (trip >= MAX_NUMBER_OF_TRIPS || temp >= zonedev->tj_max)
+ return -EINVAL;
+
+- ret = rdmsr_on_cpu(pkgdev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT,
++ ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT,
+ &l, &h);
+ if (ret < 0)
+ return ret;
+@@ -228,11 +229,12 @@ sys_set_trip_temp(struct thermal_zone_de
+ if (!temp) {
+ l &= ~intr;
+ } else {
+- l |= (pkgdev->tj_max - temp)/1000 << shift;
++ l |= (zonedev->tj_max - temp)/1000 << shift;
+ l |= intr;
+ }
+
+- return wrmsr_on_cpu(pkgdev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
++ return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT,
++ l, h);
+ }
+
+ static int sys_get_trip_type(struct thermal_zone_device *thermal, int trip,
+@@ -287,26 +289,26 @@ static void pkg_temp_thermal_threshold_w
+ {
+ struct thermal_zone_device *tzone = NULL;
+ int cpu = smp_processor_id();
+- struct pkg_device *pkgdev;
++ struct zone_device *zonedev;
+ u64 msr_val, wr_val;
+
+ mutex_lock(&thermal_zone_mutex);
+ spin_lock_irq(&pkg_temp_lock);
+ ++pkg_work_cnt;
+
+- pkgdev = pkg_temp_thermal_get_dev(cpu);
+- if (!pkgdev) {
++ zonedev = pkg_temp_thermal_get_dev(cpu);
++ if (!zonedev) {
+ spin_unlock_irq(&pkg_temp_lock);
+ mutex_unlock(&thermal_zone_mutex);
+ return;
+ }
+- pkgdev->work_scheduled = false;
++ zonedev->work_scheduled = false;
+
+ rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+ wr_val = msr_val & ~(THERM_LOG_THRESHOLD0 | THERM_LOG_THRESHOLD1);
+ if (wr_val != msr_val) {
+ wrmsrl(MSR_IA32_PACKAGE_THERM_STATUS, wr_val);
+- tzone = pkgdev->tzone;
++ tzone = zonedev->tzone;
+ }
+
+ enable_pkg_thres_interrupt();
+@@ -332,7 +334,7 @@ static void pkg_thermal_schedule_work(in
+ static int pkg_thermal_notify(u64 msr_val)
+ {
+ int cpu = smp_processor_id();
+- struct pkg_device *pkgdev;
++ struct zone_device *zonedev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pkg_temp_lock, flags);
+@@ -341,10 +343,10 @@ static int pkg_thermal_notify(u64 msr_va
+ disable_pkg_thres_interrupt();
+
+ /* Work is per package, so scheduling it once is enough. */
+- pkgdev = pkg_temp_thermal_get_dev(cpu);
+- if (pkgdev && !pkgdev->work_scheduled) {
+- pkgdev->work_scheduled = true;
+- pkg_thermal_schedule_work(pkgdev->cpu, &pkgdev->work);
++ zonedev = pkg_temp_thermal_get_dev(cpu);
++ if (zonedev && !zonedev->work_scheduled) {
++ zonedev->work_scheduled = true;
++ pkg_thermal_schedule_work(zonedev->cpu, &zonedev->work);
+ }
+
+ spin_unlock_irqrestore(&pkg_temp_lock, flags);
+@@ -353,12 +355,12 @@ static int pkg_thermal_notify(u64 msr_va
+
+ static int pkg_temp_thermal_device_add(unsigned int cpu)
+ {
+- int pkgid = topology_logical_die_id(cpu);
++ int id = topology_logical_die_id(cpu);
+ u32 tj_max, eax, ebx, ecx, edx;
+- struct pkg_device *pkgdev;
++ struct zone_device *zonedev;
+ int thres_count, err;
+
+- if (pkgid >= max_packages)
++ if (id >= max_id)
+ return -ENOMEM;
+
+ cpuid(6, &eax, &ebx, &ecx, &edx);
+@@ -372,51 +374,51 @@ static int pkg_temp_thermal_device_add(u
+ if (err)
+ return err;
+
+- pkgdev = kzalloc(sizeof(*pkgdev), GFP_KERNEL);
+- if (!pkgdev)
++ zonedev = kzalloc(sizeof(*zonedev), GFP_KERNEL);
++ if (!zonedev)
+ return -ENOMEM;
+
+- INIT_DELAYED_WORK(&pkgdev->work, pkg_temp_thermal_threshold_work_fn);
+- pkgdev->cpu = cpu;
+- pkgdev->tj_max = tj_max;
+- pkgdev->tzone = thermal_zone_device_register("x86_pkg_temp",
++ INIT_DELAYED_WORK(&zonedev->work, pkg_temp_thermal_threshold_work_fn);
++ zonedev->cpu = cpu;
++ zonedev->tj_max = tj_max;
++ zonedev->tzone = thermal_zone_device_register("x86_pkg_temp",
+ thres_count,
+ (thres_count == MAX_NUMBER_OF_TRIPS) ? 0x03 : 0x01,
+- pkgdev, &tzone_ops, &pkg_temp_tz_params, 0, 0);
+- if (IS_ERR(pkgdev->tzone)) {
+- err = PTR_ERR(pkgdev->tzone);
+- kfree(pkgdev);
++ zonedev, &tzone_ops, &pkg_temp_tz_params, 0, 0);
++ if (IS_ERR(zonedev->tzone)) {
++ err = PTR_ERR(zonedev->tzone);
++ kfree(zonedev);
+ return err;
+ }
+ /* Store MSR value for package thermal interrupt, to restore at exit */
+- rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, pkgdev->msr_pkg_therm_low,
+- pkgdev->msr_pkg_therm_high);
++ rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm_low,
++ zonedev->msr_pkg_therm_high);
+
+- cpumask_set_cpu(cpu, &pkgdev->cpumask);
++ cpumask_set_cpu(cpu, &zonedev->cpumask);
+ spin_lock_irq(&pkg_temp_lock);
+- packages[pkgid] = pkgdev;
++ zones[id] = zonedev;
+ spin_unlock_irq(&pkg_temp_lock);
+ return 0;
+ }
+
+ static int pkg_thermal_cpu_offline(unsigned int cpu)
+ {
+- struct pkg_device *pkgdev = pkg_temp_thermal_get_dev(cpu);
++ struct zone_device *zonedev = pkg_temp_thermal_get_dev(cpu);
+ bool lastcpu, was_target;
+ int target;
+
+- if (!pkgdev)
++ if (!zonedev)
+ return 0;
+
+- target = cpumask_any_but(&pkgdev->cpumask, cpu);
+- cpumask_clear_cpu(cpu, &pkgdev->cpumask);
++ target = cpumask_any_but(&zonedev->cpumask, cpu);
++ cpumask_clear_cpu(cpu, &zonedev->cpumask);
+ lastcpu = target >= nr_cpu_ids;
+ /*
+ * Remove the sysfs files, if this is the last cpu in the package
+ * before doing further cleanups.
+ */
+ if (lastcpu) {
+- struct thermal_zone_device *tzone = pkgdev->tzone;
++ struct thermal_zone_device *tzone = zonedev->tzone;
+
+ /*
+ * We must protect against a work function calling
+@@ -425,7 +427,7 @@ static int pkg_thermal_cpu_offline(unsig
+ * won't try to call.
+ */
+ mutex_lock(&thermal_zone_mutex);
+- pkgdev->tzone = NULL;
++ zonedev->tzone = NULL;
+ mutex_unlock(&thermal_zone_mutex);
+
+ thermal_zone_device_unregister(tzone);
+@@ -439,8 +441,8 @@ static int pkg_thermal_cpu_offline(unsig
+ * one. When we drop the lock, then the interrupt notify function
+ * will see the new target.
+ */
+- was_target = pkgdev->cpu == cpu;
+- pkgdev->cpu = target;
++ was_target = zonedev->cpu == cpu;
++ zonedev->cpu = target;
+
+ /*
+ * If this is the last CPU in the package remove the package
+@@ -449,23 +451,23 @@ static int pkg_thermal_cpu_offline(unsig
+ * worker will see the package anymore.
+ */
+ if (lastcpu) {
+- packages[topology_logical_die_id(cpu)] = NULL;
++ zones[topology_logical_die_id(cpu)] = NULL;
+ /* After this point nothing touches the MSR anymore. */
+ wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+- pkgdev->msr_pkg_therm_low, pkgdev->msr_pkg_therm_high);
++ zonedev->msr_pkg_therm_low, zonedev->msr_pkg_therm_high);
+ }
+
+ /*
+ * Check whether there is work scheduled and whether the work is
+ * targeted at the outgoing CPU.
+ */
+- if (pkgdev->work_scheduled && was_target) {
++ if (zonedev->work_scheduled && was_target) {
+ /*
+ * To cancel the work we need to drop the lock, otherwise
+ * we might deadlock if the work needs to be flushed.
+ */
+ spin_unlock_irq(&pkg_temp_lock);
+- cancel_delayed_work_sync(&pkgdev->work);
++ cancel_delayed_work_sync(&zonedev->work);
+ spin_lock_irq(&pkg_temp_lock);
+ /*
+ * If this is not the last cpu in the package and the work
+@@ -473,21 +475,21 @@ static int pkg_thermal_cpu_offline(unsig
+ * need to reschedule the work, otherwise the interrupt
+ * stays disabled forever.
+ */
+- if (!lastcpu && pkgdev->work_scheduled)
+- pkg_thermal_schedule_work(target, &pkgdev->work);
++ if (!lastcpu && zonedev->work_scheduled)
++ pkg_thermal_schedule_work(target, &zonedev->work);
+ }
+
+ spin_unlock_irq(&pkg_temp_lock);
+
+ /* Final cleanup if this is the last cpu */
+ if (lastcpu)
+- kfree(pkgdev);
++ kfree(zonedev);
+ return 0;
+ }
+
+ static int pkg_thermal_cpu_online(unsigned int cpu)
+ {
+- struct pkg_device *pkgdev = pkg_temp_thermal_get_dev(cpu);
++ struct zone_device *zonedev = pkg_temp_thermal_get_dev(cpu);
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+
+ /* Paranoia check */
+@@ -495,8 +497,8 @@ static int pkg_thermal_cpu_online(unsign
+ return -ENODEV;
+
+ /* If the package exists, nothing to do */
+- if (pkgdev) {
+- cpumask_set_cpu(cpu, &pkgdev->cpumask);
++ if (zonedev) {
++ cpumask_set_cpu(cpu, &zonedev->cpumask);
+ return 0;
+ }
+ return pkg_temp_thermal_device_add(cpu);
+@@ -515,9 +517,9 @@ static int __init pkg_temp_thermal_init(
+ if (!x86_match_cpu(pkg_temp_thermal_ids))
+ return -ENODEV;
+
+- max_packages = topology_max_packages() * topology_max_die_per_package();
+- packages = kzalloc(max_packages * sizeof(struct pkg_device *), GFP_KERNEL);
+- if (!packages)
++ max_id = topology_max_packages() * topology_max_die_per_package();
++ zones = kcalloc(max_id, sizeof(struct zone_device *), GFP_KERNEL);
++ if (!zones)
+ return -ENOMEM;
+
+ ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "thermal/x86_pkg:online",
+@@ -536,7 +538,7 @@ static int __init pkg_temp_thermal_init(
+ return 0;
+
+ err:
+- kfree(packages);
++ kfree(zones);
+ return ret;
+ }
+ module_init(pkg_temp_thermal_init)
+@@ -548,7 +550,7 @@ static void __exit pkg_temp_thermal_exit
+
+ cpuhp_remove_state(pkg_thermal_hp_state);
+ debugfs_remove_recursive(debugfs);
+- kfree(packages);
++ kfree(zones);
+ }
+ module_exit(pkg_temp_thermal_exit)
+
diff --git a/patches.suse/thermal-x86_pkg_temp_thermal-Support-multi-die-packa.patch b/patches.suse/thermal-x86_pkg_temp_thermal-Support-multi-die-packa.patch
new file mode 100644
index 0000000000..97439dab6c
--- /dev/null
+++ b/patches.suse/thermal-x86_pkg_temp_thermal-Support-multi-die-packa.patch
@@ -0,0 +1,64 @@
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 13 May 2019 13:58:52 -0400
+Subject: thermal/x86_pkg_temp_thermal: Support multi-die/package
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
+Git-commit: 724adec33c2491f26f739f285ddca25fca226e48
+Patch-mainline: Queued in subsystem maintainer repository
+References: jsc#SLE-5454
+
+Package temperature sensors are actually implemented in hardware per-die.
+Thus, the new multi-die/package systems sport mulitple package thermal
+zones for each package.
+
+Update the x86_pkg_temp_thermal to be "multi-die-aware", so it can expose
+multiple zones per package, instead of just one.
+
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Ingo Molnar