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authorThomas Zimmermann <tzimmermann@suse.de>2019-01-10 15:53:28 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-01-11 13:41:55 +0100
commitee9b413dc6181deacfa5651b19ff2e1bf39a4101 (patch)
treea164c2da93890be09ad480fe39439a4693146b5c
parent13db7a80c83ecf2bcabef01d9a24214181b54bff (diff)
drm/i915/guc: Move the pin bias value from GuC to GGTT (bsc#1113956)
-rw-r--r--patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch284
-rw-r--r--series.conf1
2 files changed, 285 insertions, 0 deletions
diff --git a/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch b/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
new file mode 100644
index 0000000000..6c048f3499
--- /dev/null
+++ b/patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
@@ -0,0 +1,284 @@
+From dd18cedfa36fbbc19903aed12d6d94c06f5e6dea Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jakub=20Bartmi=C5=84ski?= <jakub.bartminski@intel.com>
+Date: Fri, 27 Jul 2018 16:11:45 +0200
+Subject: drm/i915/guc: Move the pin bias value from GuC to GGTT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: dd18cedfa36fbbc19903aed12d6d94c06f5e6dea
+Patch-mainline: v4.20-rc1
+References: bsc#1113956
+
+Removing the pin bias from GuC allows us to not check for GuC every time
+we pin a context, which fixes the assertion error on unresolved GuC
+platform default in mock contexts selftest.
+
+It also seems that we were using uninitialized WOPCM variables when
+setting the GuC pin bias. The pin bias has to be set after the WOPCM,
+but before the call to i915_gem_contexts_init where the first contexts
+are pinned.
+
+v2:
+This also makes it so that there's no need to set GuC variables from
+within the WOPCM init function or to move the WOPCM init, while keeping
+the correct initialization order. Also for mock tests the pin bias is
+left at 0 and we make sure that the pin bias with GuC will not be
+smaller than without GuC.
+
+v3:
+Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled.
+
+v4:
+Squash with WOPCM init reordering.
+Moved the i915_ggtt_pin_bias helper to this patch, and made some
+functions use it instead of directly dereferencing i915->ggtt.
+
+v5:
+Since we now don't use wopcm.guc.base for the pin bias there's no need to
+validate it. It also has already been verified in WOPCM init.
+
+v6:
+Deleted the now unnecessarily introduced includes from previous versions.
+Dropped naming changes from dev_priv to i915 for better patch readability.
+
+v7:
+Changed some comments to make more sense in the context they're in.
+
+v8:
+Moved and renamed the function which now returns the wopcm.guc.size to
+intel_guc.c:intel_guc_reserved_gtt_size to avoid any possible confusion
+with the pin_bias in ggtt, which should be used for pinning.
+Fixed patch not applying or the most recent upstream.
+
+Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init")
+Testcase: igt/drv_selftest/mock_contexts #GuC
+Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Michał Winiarski <michal.winiarski@intel.com>
+Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180727141148.30874-3-jakub.bartminski@intel.com
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/drm/i915/i915_gem_context.c | 10 -------
+ drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++++++
+ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +
+ drivers/gpu/drm/i915/i915_vma.h | 5 +++
+ drivers/gpu/drm/i915/intel_guc.c | 43 ++++++++++++++------------------
+ drivers/gpu/drm/i915/intel_guc.h | 12 +++-----
+ drivers/gpu/drm/i915/intel_huc.c | 2 -
+ drivers/gpu/drm/i915/intel_uc_fw.c | 2 -
+ 8 files changed, 44 insertions(+), 41 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_gem_context.c
++++ b/drivers/gpu/drm/i915/i915_gem_context.c
+@@ -329,15 +329,7 @@ __create_hw_context(struct drm_i915_priv
+ ctx->desc_template =
+ default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
+
+- /*
+- * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
+- * present or not in use we still need a small bias as ring wraparound
+- * at offset 0 sometimes hangs. No idea why.
+- */
+- if (USES_GUC(dev_priv))
+- ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
+- else
+- ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
++ ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
+
+ return ctx;
+
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
+@@ -2937,6 +2937,15 @@ int i915_gem_init_ggtt(struct drm_i915_p
+ struct drm_mm_node *entry;
+ int ret;
+
++ /*
++ * GuC requires all resources that we're sharing with it to be placed in
++ * non-WOPCM memory. If GuC is not present or not in use we still need a
++ * small bias as ring wraparound at offset 0 sometimes hangs. No idea
++ * why.
++ */
++ ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
++ intel_guc_reserved_gtt_size(&dev_priv->guc));
++
+ ret = intel_vgt_balloon(dev_priv);
+ if (ret)
+ return ret;
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
+@@ -401,6 +401,8 @@ struct i915_ggtt {
+
+ int mtrr;
+
++ u32 pin_bias;
++
+ struct drm_mm_node error_capture;
+ };
+
+--- a/drivers/gpu/drm/i915/i915_vma.h
++++ b/drivers/gpu/drm/i915/i915_vma.h
+@@ -207,6 +207,11 @@ static inline u32 i915_ggtt_offset(const
+ return lower_32_bits(vma->node.start);
+ }
+
++static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
++{
++ return i915_vm_to_ggtt(vma->vm)->pin_bias;
++}
++
+ static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
+ {
+ i915_gem_object_get(vma->obj);
+--- a/drivers/gpu/drm/i915/intel_guc.c
++++ b/drivers/gpu/drm/i915/intel_guc.c
+@@ -27,8 +27,6 @@
+ #include "intel_guc_submission.h"
+ #include "i915_drv.h"
+
+-static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
+-
+ static void gen8_guc_raise_irq(struct intel_guc *guc)
+ {
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+@@ -142,8 +140,6 @@ int intel_guc_init_misc(struct intel_guc
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
+
+- guc_init_ggtt_pin_bias(guc);
+-
+ ret = guc_init_wq(guc);
+ if (ret)
+ return ret;
+@@ -614,23 +610,6 @@ int intel_guc_resume(struct intel_guc *g
+ */
+
+ /**
+- * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
+- * @guc: intel_guc structure.
+- *
+- * This function will calculate and initialize the ggtt_pin_bias value based on
+- * overall WOPCM size and GuC WOPCM size.
+- */
+-static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
+-{
+- struct drm_i915_private *i915 = guc_to_i915(guc);
+-
+- GEM_BUG_ON(!i915->wopcm.size);
+- GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
+-
+- guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
+-}
+-
+-/**
+ * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
+ * @guc: the guc
+ * @size: size of area to allocate (both virtual space and memory)
+@@ -648,6 +627,7 @@ struct i915_vma *intel_guc_allocate_vma(
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
++ u64 flags;
+ int ret;
+
+ obj = i915_gem_object_create(dev_priv, size);
+@@ -658,8 +638,8 @@ struct i915_vma *intel_guc_allocate_vma(
+ if (IS_ERR(vma))
+ goto err;
+
+- ret = i915_vma_pin(vma, 0, PAGE_SIZE,
+- PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
++ flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
++ ret = i915_vma_pin(vma, 0, 0, flags);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+@@ -671,3 +651,20 @@ err:
+ i915_gem_object_put(obj);
+ return vma;
+ }
++
++/**
++ * intel_guc_reserved_gtt_size()
++ * @guc: intel_guc structure
++ *
++ * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
++ * GuC we can't have any objects pinned in that region. This function returns
++ * the size of the shadowed region.
++ *
++ * Returns:
++ * 0 if GuC is not present or not in use.
++ * Otherwise, the GuC WOPCM size.
++ */
++u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
++{
++ return guc_to_i915(guc)->wopcm.guc.size;
++}
+--- a/drivers/gpu/drm/i915/intel_guc.h
++++ b/drivers/gpu/drm/i915/intel_guc.h
+@@ -49,9 +49,6 @@ struct intel_guc {
+ struct intel_guc_log log;
+ struct intel_guc_ct ct;
+
+- /* Offset where Non-WOPCM memory starts. */
+- u32 ggtt_pin_bias;
+-
+ /* Log snapshot if GuC errors during load */
+ struct drm_i915_gem_object *load_err_log;
+
+@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_eve
+ * @vma: i915 graphics virtual memory area.
+ *
+ * GuC does not allow any gfx GGTT address that falls into range
+- * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+- * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
++ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
++ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
+ * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
+- * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
++ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
+ *
+ * Return: GGTT offset of the @vma.
+ */
+@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(
+ {
+ u32 offset = i915_ggtt_offset(vma);
+
+- GEM_BUG_ON(offset < guc->ggtt_pin_bias);
++ GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
+ GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
+
+ return offset;
+@@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc
+ int intel_guc_suspend(struct intel_guc *guc);
+ int intel_guc_resume(struct intel_guc *guc);
+ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
++u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
+
+ static inline int intel_guc_sanitize(struct intel_guc *guc)
+ {
+--- a/drivers/gpu/drm/i915/intel_huc.c
++++ b/drivers/gpu/drm/i915/intel_huc.c
+@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc
+ return -ENOEXEC;
+
+ vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
+- PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
++ PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
+--- a/drivers/gpu/drm/i915/intel_uc_fw.c
++++ b/drivers/gpu/drm/i915/intel_uc_fw.c
+@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_f
+ goto fail;
+ }
+
+- ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
++ ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
+ vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
+ PIN_OFFSET_BIAS | ggtt_pin_bias);
+ if (IS_ERR(vma)) {
diff --git a/series.conf b/series.conf
index cd8c9bc7c3..04674056bc 100644
--- a/series.conf
+++ b/series.conf
@@ -40807,6 +40807,7 @@
patches.drm/0033-drm-panel-Fix-sphinx-warning.patch
patches.drm/0001-drm-virtio-fix-bounds-check-in-virtio_gpu_cmd_get_ca.patch
patches.drm/drm-rockchip-Allow-driver-to-be-shutdown-on-reboot-k.patch
+ patches.drm/0028-drm-i915-guc-Move-the-pin-bias-value-from-GuC-to-GGT.patch
patches.drm/drm-i915-cfl-Add-a-new-CFL-PCI-ID
patches.drm/drm-amdgpu-add-missing-CHIP_HAINAN-in-amdgpu_ucode_g.patch
patches.drm/0001-drm-hisilicon-hibmc-Do-not-carry-error-code-in-HiBMC.patch