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authorMichal Suchanek <msuchanek@suse.de>2019-10-02 13:54:26 +0200
committerMichal Suchanek <msuchanek@suse.de>2019-10-02 21:10:15 +0200
commitab2f8fa2a1ef238e922f9312aafe3b95bf96bb90 (patch)
tree155433923844d28d73b5757e435ea811876887fb
parentb3a8f874f5e11755f3b6f7519c450720096ee8a4 (diff)
powerpc/64s/radix: Implement _tlbie(l)_va_range flush functions (bsc#1152161 ltc#181664).
- Refresh patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch. - Refresh patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch. - Refresh patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch.
-rw-r--r--patches.suse/powerpc-64s-radix-Implement-_tlbie-l-_va_range-flush.patch189
-rw-r--r--patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch24
-rw-r--r--patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch10
-rw-r--r--patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch25
-rw-r--r--series.conf1
5 files changed, 212 insertions, 37 deletions
diff --git a/patches.suse/powerpc-64s-radix-Implement-_tlbie-l-_va_range-flush.patch b/patches.suse/powerpc-64s-radix-Implement-_tlbie-l-_va_range-flush.patch
new file mode 100644
index 0000000000..104ac2853a
--- /dev/null
+++ b/patches.suse/powerpc-64s-radix-Implement-_tlbie-l-_va_range-flush.patch
@@ -0,0 +1,189 @@
+From d665767e39fa4a9e725f92d77ba2060c5ce273dc Mon Sep 17 00:00:00 2001
+From: Nicholas Piggin <npiggin@gmail.com>
+Date: Tue, 7 Nov 2017 18:53:06 +1100
+Subject: [PATCH] powerpc/64s/radix: Implement _tlbie(l)_va_range flush
+ functions
+
+References: bsc#1152161 ltc#181664
+Patch-mainline: v4.15-rc1
+Git-commit: d665767e39fa4a9e725f92d77ba2060c5ce273dc
+
+Move the barriers and range iteration down into the _tlbie* level,
+which improves readability.
+
+Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Acked-by: Michal Suchanek <msuchanek@suse.de>
+---
+ arch/powerpc/mm/tlb-radix.c | 69 +++++++++++++++++++++----------------
+ 1 file changed, 39 insertions(+), 30 deletions(-)
+
+diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
+index 22b657e4b01a..9916ea2fff43 100644
+--- a/arch/powerpc/mm/tlb-radix.c
++++ b/arch/powerpc/mm/tlb-radix.c
+@@ -85,7 +85,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
+ }
+
+ static inline void __tlbiel_va(unsigned long va, unsigned long pid,
+- unsigned long ap, unsigned long ric)
++ unsigned long ap, unsigned long ric)
+ {
+ unsigned long rb,rs,prs,r;
+
+@@ -101,13 +101,28 @@ static inline void __tlbiel_va(unsigned long va, unsigned long pid,
+ }
+
+ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
+- unsigned long ap, unsigned long ric)
++ unsigned long psize, unsigned long ric)
+ {
++ unsigned long ap = mmu_get_ap(psize);
++
+ asm volatile("ptesync": : :"memory");
+ __tlbiel_va(va, pid, ap, ric);
+ asm volatile("ptesync": : :"memory");
+ }
+
++static inline void _tlbiel_va_range(unsigned long start, unsigned long end,
++ unsigned long pid, unsigned long page_size,
++ unsigned long psize)
++{
++ unsigned long addr;
++ unsigned long ap = mmu_get_ap(psize);
++
++ asm volatile("ptesync": : :"memory");
++ for (addr = start; addr < end; addr += page_size)
++ __tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
++ asm volatile("ptesync": : :"memory");
++}
++
+ static inline void __tlbie_va(unsigned long va, unsigned long pid,
+ unsigned long ap, unsigned long ric)
+ {
+@@ -125,13 +140,27 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid,
+ }
+
+ static inline void _tlbie_va(unsigned long va, unsigned long pid,
+- unsigned long ap, unsigned long ric)
++ unsigned long psize, unsigned long ric)
+ {
++ unsigned long ap = mmu_get_ap(psize);
++
+ asm volatile("ptesync": : :"memory");
+ __tlbie_va(va, pid, ap, ric);
+ asm volatile("eieio; tlbsync; ptesync": : :"memory");
+ }
+
++static inline void _tlbie_va_range(unsigned long start, unsigned long end,
++ unsigned long pid, unsigned long page_size,
++ unsigned long psize)
++{
++ unsigned long addr;
++ unsigned long ap = mmu_get_ap(psize);
++
++ asm volatile("ptesync": : :"memory");
++ for (addr = start; addr < end; addr += page_size)
++ __tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
++ asm volatile("eieio; tlbsync; ptesync": : :"memory");
++}
+
+ /*
+ * Base TLB flushing operations:
+@@ -174,12 +203,11 @@ void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmadd
+ int psize)
+ {
+ unsigned long pid;
+- unsigned long ap = mmu_get_ap(psize);
+
+ preempt_disable();
+ pid = mm->context.id;
+ if (pid != MMU_NO_CONTEXT)
+- _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
++ _tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
+ preempt_enable();
+ }
+
+@@ -239,7 +267,6 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
+ int psize)
+ {
+ unsigned long pid;
+- unsigned long ap = mmu_get_ap(psize);
+
+ pid = mm->context.id;
+ if (unlikely(pid == MMU_NO_CONTEXT))
+@@ -247,9 +274,9 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
+
+ preempt_disable();
+ if (!mm_is_thread_local(mm))
+- _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
++ _tlbie_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
+ else
+- _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
++ _tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
+ preempt_enable();
+ }
+
+@@ -336,9 +363,7 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
+ unsigned long end, int psize)
+ {
+ unsigned long pid;
+- unsigned long addr;
+ bool local;
+- unsigned long ap = mmu_get_ap(psize);
+ unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
+
+ pid = mm->context.id;
+@@ -354,17 +379,10 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
+ else
+ _tlbie_pid(pid, RIC_FLUSH_TLB);
+ } else {
+- asm volatile("ptesync": : :"memory");
+- for (addr = start; addr < end; addr += page_size) {
+- if (local)
+- __tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
+- else
+- __tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
+- }
+ if (local)
+- asm volatile("ptesync": : :"memory");
++ _tlbiel_va_range(start, end, pid, page_size, psize);
+ else
+- asm volatile("eieio; tlbsync; ptesync": : :"memory");
++ _tlbie_va_range(start, end, pid, page_size, psize);
+ }
+ preempt_enable();
+ }
+@@ -372,7 +390,6 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
+ #ifdef CONFIG_TRANSPARENT_HUGEPAGE
+ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)
+ {
+- unsigned long ap = mmu_get_ap(mmu_virtual_psize);
+ unsigned long pid, end;
+ bool local;
+
+@@ -395,19 +412,11 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)
+ _tlbie_pid(pid, RIC_FLUSH_PWC);
+
+ /* Then iterate the pages */
+- asm volatile("ptesync": : :"memory");
+ end = addr + HPAGE_PMD_SIZE;
+- for (; addr < end; addr += PAGE_SIZE) {
+- if (local)
+- _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
+- else
+- _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
+- }
+-
+ if (local)
+- asm volatile("ptesync": : :"memory");
++ _tlbiel_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);
+ else
+- asm volatile("eieio; tlbsync; ptesync": : :"memory");
++ _tlbie_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);
+
+ preempt_enable();
+ }
+--
+2.23.0
+
diff --git a/patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch b/patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch
index aac1a78fcc..9780fe56c2 100644
--- a/patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch
+++ b/patches.suse/powerpc-mm-Fixup-tlbie-vs-store-ordering-issue-on-PO.patch
@@ -207,23 +207,19 @@ index 28c980e..adf469f 100644
asm volatile("eieio; tlbsync; ptesync": : :"memory");
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
-@@ -195,6 +207,7 @@ static inline void _tlbie_va(unsigned lo
- {
+@@ -212,6 +224,7 @@ static inline void _tlbie_va(unsigned lo
+
asm volatile("ptesync": : :"memory");
__tlbie_va(va, pid, ap, ric);
+ fixup_tlbie();
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
-@@ -441,8 +454,10 @@ void radix__flush_tlb_range_psize(struct
- for (addr = start; addr < end; addr += page_size) {
- if (local)
- __tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
-- else
-+ else {
- __tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
-+ fixup_tlbie();
-+ }
- }
- if (local)
- asm volatile("ptesync": : :"memory");
+@@ -225,6 +238,7 @@ static inline void _tlbie_va_range(unsig
+ asm volatile("ptesync": : :"memory");
+ for (addr = start; addr < end; addr += page_size)
+ __tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
++ fixup_tlbie();
+ asm volatile("eieio; tlbsync; ptesync": : :"memory");
+ }
+
diff --git a/patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch b/patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch
index 53e00f0cdf..54eb6ae72f 100644
--- a/patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch
+++ b/patches.suse/powerpc-mm-Workaround-Nest-MMU-bug-with-TLB-invalida.patch
@@ -43,7 +43,7 @@ Acked-by: Michal Suchanek <msuchanek@suse.de>
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
-@@ -260,6 +260,16 @@ void radix__local_flush_tlb_page(struct
+@@ -288,6 +288,16 @@ void radix__local_flush_tlb_page(struct
}
EXPORT_SYMBOL(radix__local_flush_tlb_page);
@@ -60,7 +60,7 @@ Acked-by: Michal Suchanek <msuchanek@suse.de>
#ifdef CONFIG_SMP
void radix__flush_tlb_mm(struct mm_struct *mm)
{
-@@ -270,9 +280,12 @@ void radix__flush_tlb_mm(struct mm_struc
+@@ -298,9 +308,12 @@ void radix__flush_tlb_mm(struct mm_struc
return;
preempt_disable();
@@ -76,7 +76,7 @@ Acked-by: Michal Suchanek <msuchanek@suse.de>
_tlbiel_pid(pid, RIC_FLUSH_TLB);
preempt_enable();
}
-@@ -415,10 +428,14 @@ void radix__flush_tlb_range_psize(struct
+@@ -440,10 +453,14 @@ void radix__flush_tlb_range_psize(struct
local = mm_is_thread_local(mm);
if (end == TLB_FLUSH_ALL ||
(end - start) > tlb_single_page_flush_ceiling * page_size) {
@@ -92,5 +92,5 @@ Acked-by: Michal Suchanek <msuchanek@suse.de>
+ _tlbie_pid(pid, RIC_FLUSH_TLB);
+ }
} else {
- asm volatile("ptesync": : :"memory");
- for (addr = start; addr < end; addr += page_size) {
+ if (local)
+ _tlbiel_va_range(start, end, pid, page_size, psize);
diff --git a/patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch b/patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch
index a5552326b7..fcad39edb2 100644
--- a/patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch
+++ b/patches.suse/powerpc-mm-radix-Move-the-functions-that-does-the-ac.patch
@@ -12,22 +12,14 @@ No functionality change. Just code movement to ease code changes later
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-[mauricfo: backport:
- - hunk 1: update context line 1
- - hunk 2: update context lines, update whitespace in 2nd remove line
- - hunk 3: update context lines]
-Signed-off-by: Mauricio Faria de Oliveira <mauricfo@linux.vnet.ibm.com>
-
Acked-by: Michal Suchanek <msuchanek@suse.de>
---
- arch/powerpc/mm/tlb-radix.c | 64 ++++++++++++++++++++++-----------------------
+ arch/powerpc/mm/tlb-radix.c | 64 ++++++++++++++++++-------------------
1 file changed, 32 insertions(+), 32 deletions(-)
-diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
-index e47ee8c..74354c2 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
-@@ -119,6 +119,38 @@ static inline void __tlbie_pid(unsigned long pid, unsigned long ric)
+@@ -105,6 +105,38 @@ static inline void __tlbiel_pid(unsigned
trace_tlbie(0, 1, rb, rs, ric, prs, r);
}
@@ -66,12 +58,12 @@ index e47ee8c..74354c2 100644
/*
* We use 128 set in radix mode and 256 set in hpt mode.
*/
-@@ -171,22 +203,6 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
+@@ -150,22 +182,6 @@ static inline void _tlbie_pid(unsigned l
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
-static inline void __tlbiel_va(unsigned long va, unsigned long pid,
-- unsigned long ap, unsigned long ric)
+- unsigned long ap, unsigned long ric)
-{
- unsigned long rb,rs,prs,r;
-
@@ -87,9 +79,9 @@ index e47ee8c..74354c2 100644
-}
-
static inline void _tlbiel_va(unsigned long va, unsigned long pid,
- unsigned long ap, unsigned long ric)
+ unsigned long psize, unsigned long ric)
{
-@@ -219,22 +235,6 @@ static inline void _tlbiel_va_range(unsigned long start, unsigned long end,
+@@ -189,22 +205,6 @@ static inline void _tlbiel_va_range(unsi
asm volatile("ptesync": : :"memory");
}
@@ -110,8 +102,5 @@ index e47ee8c..74354c2 100644
-}
-
static inline void _tlbie_va(unsigned long va, unsigned long pid,
- unsigned long ap, unsigned long ric)
+ unsigned long psize, unsigned long ric)
{
---
-cgit v1.1
-
diff --git a/series.conf b/series.conf
index 66145a322a..2e00271542 100644
--- a/series.conf
+++ b/series.conf
@@ -10193,6 +10193,7 @@
patches.suse/powerpc-powernv-cpufreq-Fix-the-frequency-read-by-pr.patch
patches.suse/powerpc-powernv-ioda-Remove-explicit-max-window-size.patch
patches.suse/powerpc-64s-radix-Optimize-TLB-range-flush-barriers.patch
+ patches.suse/powerpc-64s-radix-Implement-_tlbie-l-_va_range-flush.patch
patches.suse/powerpc-mm-radix-Fix-crashes-on-Power9-DD1-with-radix.patch
patches.suse/powerpc-kprobes-Disable-preemption-before-invoking-p.patch
patches.suse/powerpc-powernv-idle-Round-up-latency-and-residency-.patch