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authorTony Jones <tonyj@suse.de>2018-08-03 02:42:06 +0200
committerTony Jones <tonyj@suse.de>2018-08-03 02:43:43 +0200
commit9a1e6889e352e9a9e9790af5c8aa9b98cc728f36 (patch)
tree3f264ba611e52e69fa941c328e98bccdee9bd372
parent00138187b7766c463be554121df995a44e1b6b2d (diff)
perf intel-pt: Always set no branch for dummy event
(bsc#1087217).
-rw-r--r--patches.fixes/perf-intel-pt-always-set-no-branch-for-dummy-event.patch56
-rw-r--r--series.conf1
2 files changed, 57 insertions, 0 deletions
diff --git a/patches.fixes/perf-intel-pt-always-set-no-branch-for-dummy-event.patch b/patches.fixes/perf-intel-pt-always-set-no-branch-for-dummy-event.patch
new file mode 100644
index 0000000000..69f59dc33a
--- /dev/null
+++ b/patches.fixes/perf-intel-pt-always-set-no-branch-for-dummy-event.patch
@@ -0,0 +1,56 @@
+From: Kan Liang <kan.liang@intel.com>
+Date: Fri, 30 Jun 2017 10:16:56 -0400
+Subject: perf intel-pt: Always set no branch for dummy event
+Git-commit: 91a8c5b840f2da31280e14b6268761cf14033756
+Patch-mainline: v4.14-rc1
+References: bsc#1087217
+
+An earlier kernel patch allowed enabling PT and LBR at the same time on
+Goldmont.
+
+commit ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity
+if the core supports it")
+
+However, users still cannot use Intel PT and LBRs simultaneously. $
+sudo perf record -e cycles,intel_pt//u -b -- sleep 1 Error: PMU
+Hardware doesn't support sampling/overflow-interrupts.
+
+PT implicitly adds dummy event in perf tool. dummy event is software
+event which doesn't support LBR.
+
+Always setting no branch for dummy event in Intel PT.
+
+Signed-off-by: Kan Liang <kan.liang@intel.com>
+Acked-by: Jiri Olsa <jolsa@redhat.com>
+Cc: Adrian Hunter <adrian.hunter@intel.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Andi Kleen <ak@linux.intel.com>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Link: http://lkml.kernel.org/r/20170630141656.1626-2-kan.liang@intel.com
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Tony Jones <tonyj@suse.de>
+---
+ tools/perf/arch/x86/util/intel-pt.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c
+index 4a461e8ae326..db0ba8caf5a2 100644
+--- a/tools/perf/arch/x86/util/intel-pt.c
++++ b/tools/perf/arch/x86/util/intel-pt.c
+@@ -701,6 +701,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
+ perf_evsel__set_sample_bit(switch_evsel, TID);
+ perf_evsel__set_sample_bit(switch_evsel, TIME);
+ perf_evsel__set_sample_bit(switch_evsel, CPU);
++ perf_evsel__reset_sample_bit(switch_evsel, BRANCH_STACK);
+
+ opts->record_switch_events = false;
+ ptr->have_sched_switch = 3;
+@@ -762,6 +763,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
+ /* And the CPU for switch events */
+ perf_evsel__set_sample_bit(tracking_evsel, CPU);
+ }
++ perf_evsel__reset_sample_bit(tracking_evsel, BRANCH_STACK);
+ }
+
+ /*
+
diff --git a/series.conf b/series.conf
index 981b4eae58..36721980ec 100644
--- a/series.conf
+++ b/series.conf
@@ -5018,6 +5018,7 @@
patches.arch/perf-vendor-events-add-power9-pmu-events.patch
patches.arch/perf-vendor-events-add-power9-pvrs-to-mapfile.patch
patches.fixes/perf-intel-pt-set-no_aux_samples-for-the-tracking-event.patch
+ patches.fixes/perf-intel-pt-always-set-no-branch-for-dummy-event.patch
patches.arch/14.1-irq-make-the-irqentry-text-section-unconditional.patch
patches.arch/perf-vendor-events-powerpc-remove-suffix-in-mapfile.patch
patches.arch/perf-vendor-events-powerpc-update-power9-events.patch