Home Home > GIT Browse
summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJoerg Roedel <jroedel@suse.de>2018-08-10 11:55:33 +0200
committerJoerg Roedel <jroedel@suse.de>2018-08-10 11:55:33 +0200
commitd89aa817a41efadf4a7ef6d837d01576bfcdc543 (patch)
treeb01d59e8dea4556e2affc8b9bcc79bef287d0a00
parent7aef11d70b4e2009fe165a23f83c4a0fc908d57f (diff)
- iommu/amd: Add support for higher 64-bit IOMMU Control Register (fate#324429). - iommu/amd: Add support for IOMMU XT mode (fate#324429). - scripts/git_sort/git_sort.py:
-rw-r--r--patches.drivers/0001-x86-irq_remapping-move-irq-remapping-mode-enum56
-rw-r--r--patches.drivers/0002-iommu-amd-add-support-for-higher-64-bit-iommu-control-register78
-rw-r--r--patches.drivers/0003-iommu-amd-add-support-for-iommu-xt-mode230
-rwxr-xr-xscripts/git_sort/git_sort.py1
-rw-r--r--series.conf5
5 files changed, 370 insertions, 0 deletions
diff --git a/patches.drivers/0001-x86-irq_remapping-move-irq-remapping-mode-enum b/patches.drivers/0001-x86-irq_remapping-move-irq-remapping-mode-enum
new file mode 100644
index 0000000000..9768f433f8
--- /dev/null
+++ b/patches.drivers/0001-x86-irq_remapping-move-irq-remapping-mode-enum
@@ -0,0 +1,56 @@
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Date: Wed, 27 Jun 2018 10:31:20 -0500
+Subject: x86: irq_remapping: Move irq remapping mode enum
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
+Git-commit: 818b7587b4d34e989ea6c042eeb8d50ffa5be13e
+Patch-mainline: queued, upstream in v4.19-rc1
+References: fate#324429
+
+The enum is currently defined in Intel-specific DMAR header file,
+but it is also used by APIC common code. Therefore, move it to
+a more appropriate interrupt-remapping common header file.
+This will also be used by subsequent patches.
+
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+---
+ arch/x86/include/asm/irq_remapping.h | 5 +++++
+ include/linux/dmar.h | 5 -----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
+index 023b4a9fc846..5f26962eff42 100644
+--- a/arch/x86/include/asm/irq_remapping.h
++++ b/arch/x86/include/asm/irq_remapping.h
+@@ -33,6 +33,11 @@ enum irq_remap_cap {
+ IRQ_POSTING_CAP = 0,
+ };
+
++enum {
++ IRQ_REMAP_XAPIC_MODE,
++ IRQ_REMAP_X2APIC_MODE,
++};
++
+ struct vcpu_data {
+ u64 pi_desc_addr; /* Physical address of PI Descriptor */
+ u32 vector; /* Guest vector of the interrupt */
+diff --git a/include/linux/dmar.h b/include/linux/dmar.h
+index e2433bc50210..843a41ba7e28 100644
+--- a/include/linux/dmar.h
++++ b/include/linux/dmar.h
+@@ -265,11 +265,6 @@ static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
+ #define PDA_LOW_BIT 26
+ #define PDA_HIGH_BIT 32
+
+-enum {
+- IRQ_REMAP_XAPIC_MODE,
+- IRQ_REMAP_X2APIC_MODE,
+-};
+-
+ /* Can't use the common MSI interrupt functions
+ * since DMAR is not a pci device
+ */
+
diff --git a/patches.drivers/0002-iommu-amd-add-support-for-higher-64-bit-iommu-control-register b/patches.drivers/0002-iommu-amd-add-support-for-higher-64-bit-iommu-control-register
new file mode 100644
index 0000000000..7b42e7b239
--- /dev/null
+++ b/patches.drivers/0002-iommu-amd-add-support-for-higher-64-bit-iommu-control-register
@@ -0,0 +1,78 @@
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Date: Wed, 27 Jun 2018 10:31:21 -0500
+Subject: iommu/amd: Add support for higher 64-bit IOMMU Control Register
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
+Git-commit: e881dbd5d4a6950c9e2e7623c79d9578949365c9
+Patch-mainline: queued, upstream in v4.19-rc1
+References: fate#324429
+
+Currently, the driver only supports lower 32-bit of IOMMU Control register.
+However, newer AMD IOMMU specification has extended this register
+to 64-bit. Therefore, replace the accessing API with the 64-bit version.
+
+Cc: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+---
+ drivers/iommu/amd_iommu_init.c | 26 +++++++++++++-------------
+ 1 file changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
+index 904c575d1677..7d494f2c28a1 100644
+--- a/drivers/iommu/amd_iommu_init.c
++++ b/drivers/iommu/amd_iommu_init.c
+@@ -280,9 +280,9 @@ static void clear_translation_pre_enabled(struct amd_iommu *iommu)
+
+ static void init_translation_status(struct amd_iommu *iommu)
+ {
+- u32 ctrl;
++ u64 ctrl;
+
+- ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+ if (ctrl & (1<<CONTROL_IOMMU_EN))
+ iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
+ }
+@@ -386,30 +386,30 @@ static void iommu_set_device_table(struct amd_iommu *iommu)
+ /* Generic functions to enable/disable certain features of the IOMMU. */
+ static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
+ {
+- u32 ctrl;
++ u64 ctrl;
+
+- ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+- ctrl |= (1 << bit);
+- writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl |= (1ULL << bit);
++ writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+ }
+
+ static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
+ {
+- u32 ctrl;
++ u64 ctrl;
+
+- ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+- ctrl &= ~(1 << bit);
+- writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl &= ~(1ULL << bit);
++ writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+ }
+
+ static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
+ {
+- u32 ctrl;
++ u64 ctrl;
+
+- ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+ ctrl &= ~CTRL_INV_TO_MASK;
+ ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
+- writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
++ writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
+ }
+
+ /* Function to enable the hardware */
+
diff --git a/patches.drivers/0003-iommu-amd-add-support-for-iommu-xt-mode b/patches.drivers/0003-iommu-amd-add-support-for-iommu-xt-mode
new file mode 100644
index 0000000000..07d33ad3f8
--- /dev/null
+++ b/patches.drivers/0003-iommu-amd-add-support-for-iommu-xt-mode
@@ -0,0 +1,230 @@
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Date: Wed, 27 Jun 2018 10:31:22 -0500
+Subject: iommu/amd: Add support for IOMMU XT mode
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
+Git-commit: 90fcffd9cf5e7cc593169f529799f3e3c5437e75
+Patch-mainline: queued, upstream in v4.19-rc1
+References: fate#324429
+
+The AMD IOMMU XT mode enables interrupt remapping with 32-bit destination
+APIC ID, which is required for x2APIC. The feature is available when
+the XTSup bit is set in the IOMMU Extended Feature register
+and/or the IVHD Type 10h IOMMU Feature Reporting field.
+
+For more information, please see section "IOMMU x2APIC Support" of
+the AMD I/O Virtualization Technology (IOMMU) Specification.
+
+Cc: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+---
+ drivers/iommu/amd_iommu.c | 21 ++++++++++++++++-----
+ drivers/iommu/amd_iommu_init.c | 25 +++++++++++++++++++++++--
+ drivers/iommu/amd_iommu_types.h | 17 +++++++++++------
+ 3 files changed, 50 insertions(+), 13 deletions(-)
+
+--- a/drivers/iommu/amd_iommu.c
++++ b/drivers/iommu/amd_iommu.c
+@@ -3809,7 +3809,8 @@ static void irte_ga_prepare(void *entry,
+ irte->lo.fields_remap.int_type = delivery_mode;
+ irte->lo.fields_remap.dm = dest_mode;
+ irte->hi.fields.vector = vector;
+- irte->lo.fields_remap.destination = dest_apicid;
++ irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
++ irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
+ irte->lo.fields_remap.valid = 1;
+ }
+
+@@ -3864,7 +3865,10 @@ static void irte_ga_set_affinity(void *e
+ if (!dev_data || !dev_data->use_vapic ||
+ !irte->lo.fields_remap.guest_mode) {
+ irte->hi.fields.vector = vector;
+- irte->lo.fields_remap.destination = dest_apicid;
++ irte->lo.fields_remap.destination =
++ APICID_TO_IRTE_DEST_LO(dest_apicid);
++ irte->hi.fields.destination =
++ APICID_TO_IRTE_DEST_HI(dest_apicid);
+ modify_irte_ga(devid, index, irte, NULL);
+ }
+ }
+@@ -4255,7 +4259,10 @@ static int amd_ir_set_vcpu_affinity(stru
+ irte->lo.val = 0;
+ irte->hi.fields.vector = cfg->vector;
+ irte->lo.fields_remap.guest_mode = 0;
+- irte->lo.fields_remap.destination = cfg->dest_apicid;
++ irte->lo.fields_remap.destination =
++ APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
++ irte->hi.fields.destination =
++ APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
+ irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
+ irte->lo.fields_remap.dm = apic->irq_dest_mode;
+
+@@ -4354,8 +4361,12 @@ int amd_iommu_update_ga(int cpu, bool is
+ spin_lock_irqsave(&irt->lock, flags);
+
+ if (ref->lo.fields_vapic.guest_mode) {
+- if (cpu >= 0)
+- ref->lo.fields_vapic.destination = cpu;
++ if (cpu >= 0) {
++ ref->lo.fields_vapic.destination =
++ APICID_TO_IRTE_DEST_LO(cpu);
++ ref->hi.fields.destination =
++ APICID_TO_IRTE_DEST_HI(cpu);
++ }
+ ref->lo.fields_vapic.is_run = is_run;
+ barrier();
+ }
+--- a/drivers/iommu/amd_iommu_init.c
++++ b/drivers/iommu/amd_iommu_init.c
+@@ -153,6 +153,7 @@ bool amd_iommu_dump;
+ bool amd_iommu_irq_remap __read_mostly;
+
+ int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
++static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
+
+ static bool amd_iommu_detected;
+ static bool __initdata amd_iommu_disabled;
+@@ -827,6 +828,19 @@ static int iommu_init_ga(struct amd_iomm
+ return ret;
+ }
+
++static void iommu_enable_xt(struct amd_iommu *iommu)
++{
++#ifdef CONFIG_IRQ_REMAP
++ /*
++ * XT mode (32-bit APIC destination ID) requires
++ * GA mode (128-bit IRTE support) as a prerequisite.
++ */
++ if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
++ amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
++ iommu_feature_enable(iommu, CONTROL_XT_EN);
++#endif /* CONFIG_IRQ_REMAP */
++}
++
+ static void iommu_enable_gt(struct amd_iommu *iommu)
+ {
+ if (!iommu_feature(iommu, FEATURE_GT))
+@@ -1507,6 +1521,8 @@ static int __init init_iommu_one(struct
+ iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
+ if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
+ amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
++ if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
++ amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
+ break;
+ case 0x11:
+ case 0x40:
+@@ -1516,6 +1532,8 @@ static int __init init_iommu_one(struct
+ iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
+ if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
+ amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
++ if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
++ amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
+ break;
+ default:
+ return -EINVAL;
+@@ -1831,6 +1849,8 @@ static void print_iommu_info(void)
+ pr_info("AMD-Vi: Interrupt remapping enabled\n");
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
+ pr_info("AMD-Vi: virtual APIC enabled\n");
++ if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
++ pr_info("AMD-Vi: X2APIC enabled\n");
+ }
+ }
+
+@@ -2167,6 +2187,7 @@ static void early_enable_iommu(struct am
+ iommu_enable_event_buffer(iommu);
+ iommu_set_exclusion_range(iommu);
+ iommu_enable_ga(iommu);
++ iommu_enable_xt(iommu);
+ iommu_enable(iommu);
+ iommu_flush_all_caches(iommu);
+ }
+@@ -2211,6 +2232,7 @@ static void early_enable_iommus(void)
+ iommu_enable_command_buffer(iommu);
+ iommu_enable_event_buffer(iommu);
+ iommu_enable_ga(iommu);
++ iommu_enable_xt(iommu);
+ iommu_set_device_table(iommu);
+ iommu_flush_all_caches(iommu);
+ }
+@@ -2690,8 +2712,7 @@ int __init amd_iommu_enable(void)
+ return ret;
+
+ irq_remapping_enabled = 1;
+-
+- return 0;
++ return amd_iommu_xt_mode;
+ }
+
+ void amd_iommu_disable(void)
+--- a/drivers/iommu/amd_iommu_types.h
++++ b/drivers/iommu/amd_iommu_types.h
+@@ -159,6 +159,7 @@
+ #define CONTROL_GAM_EN 0x19ULL
+ #define CONTROL_GALOG_EN 0x1CULL
+ #define CONTROL_GAINT_EN 0x1DULL
++#define CONTROL_XT_EN 0x32ULL
+
+ #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
+ #define CTRL_INV_TO_NONE 0
+@@ -375,9 +376,11 @@
+ #define IOMMU_CAP_EFR 27
+
+ /* IOMMU Feature Reporting Field (for IVHD type 10h */
++#define IOMMU_FEAT_XTSUP_SHIFT 0
+ #define IOMMU_FEAT_GASUP_SHIFT 6
+
+ /* IOMMU Extended Feature Register (EFR) */
++#define IOMMU_EFR_XTSUP_SHIFT 2
+ #define IOMMU_EFR_GASUP_SHIFT 7
+
+ #define MAX_DOMAIN_ID 65536
+@@ -434,7 +437,6 @@ extern struct kmem_cache *amd_iommu_irq_
+ #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
+ #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
+
+-
+ /*
+ * This struct is used to pass information about
+ * incoming PPR faults around.
+@@ -807,6 +809,9 @@ union irte {
+ } fields;
+ };
+
++#define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
++#define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
++
+ union irte_ga_lo {
+ u64 val;
+
+@@ -820,8 +825,8 @@ union irte_ga_lo {
+ dm : 1,
+ /* ------ */
+ guest_mode : 1,
+- destination : 8,
+- rsvd : 48;
++ destination : 24,
++ ga_tag : 32;
+ } fields_remap;
+
+ /* For guest vAPIC */
+@@ -834,8 +839,7 @@ union irte_ga_lo {
+ is_run : 1,
+ /* ------ */
+ guest_mode : 1,
+- destination : 8,
+- rsvd2 : 16,
++ destination : 24,
+ ga_tag : 32;
+ } fields_vapic;
+ };
+@@ -846,7 +850,8 @@ union irte_ga_hi {
+ u64 vector : 8,
+ rsvd_1 : 4,
+ ga_root_ptr : 40,
+- rsvd_2 : 12;
++ rsvd_2 : 4,
++ destination : 8;
+ } fields;
+ };
+
diff --git a/scripts/git_sort/git_sort.py b/scripts/git_sort/git_sort.py
index 203a948957..dc8d17d82c 100755
--- a/scripts/git_sort/git_sort.py
+++ b/scripts/git_sort/git_sort.py
@@ -206,6 +206,7 @@ remotes = (
Head(RepoURL("helgaas/pci.git"), "next"),
Head(RepoURL("viro/vfs.git"), "for-linus"),
Head(RepoURL("jeyu/linux.git"), "modules-next"),
+ Head(RepoURL("joro/iommu.git"), "next"),
)
diff --git a/series.conf b/series.conf
index a4a4cd171b..264f42d15e 100644
--- a/series.conf
+++ b/series.conf
@@ -16445,6 +16445,11 @@
patches.suse/0003-modsign-log-module-name-in-the-event-of-an-error.patch
patches.suse/0004-ARM-module-fix-modsign-build-error.patch
+ # joro/iommu next
+ patches.drivers/0001-x86-irq_remapping-move-irq-remapping-mode-enum
+ patches.drivers/0002-iommu-amd-add-support-for-higher-64-bit-iommu-control-register
+ patches.drivers/0003-iommu-amd-add-support-for-iommu-xt-mode
+
# out-of-tree patches
patches.suse/0001-kvm-Introduce-nopvspin-kernel-parameter.patch