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authorJiri Slaby <jslaby@suse.cz>2019-08-16 22:01:45 +0200
committerJiri Slaby <jslaby@suse.cz>2019-08-16 22:25:10 +0200
commit7652c406f0dc29f7e0c093e0fe98603c3bc256c9 (patch)
tree424f409e3ced0d3d1d949492b96a625111b3943e
parent8ac25894b95d88c22b7b9422e0de61dd956525d3 (diff)
perf/x86/intel: Fix invalid Bit 13 for Icelake MSR_OFFCORE_RSP_x
register (bnc#1012628).
-rw-r--r--patches.kernel.org/5.2.9-113-perf-x86-intel-Fix-invalid-Bit-13-for-Icelake-M.patch62
-rw-r--r--series.conf1
2 files changed, 63 insertions, 0 deletions
diff --git a/patches.kernel.org/5.2.9-113-perf-x86-intel-Fix-invalid-Bit-13-for-Icelake-M.patch b/patches.kernel.org/5.2.9-113-perf-x86-intel-Fix-invalid-Bit-13-for-Icelake-M.patch
new file mode 100644
index 0000000000..c33c59005d
--- /dev/null
+++ b/patches.kernel.org/5.2.9-113-perf-x86-intel-Fix-invalid-Bit-13-for-Icelake-M.patch
@@ -0,0 +1,62 @@
+From: Yunying Sun <yunying.sun@intel.com>
+Date: Wed, 24 Jul 2019 16:29:32 +0800
+Subject: [PATCH] perf/x86/intel: Fix invalid Bit 13 for Icelake
+ MSR_OFFCORE_RSP_x register
+References: bnc#1012628
+Patch-mainline: 5.2.9
+Git-commit: 3b238a64c3009fed36eaea1af629d9377759d87d
+
+[ Upstream commit 3b238a64c3009fed36eaea1af629d9377759d87d ]
+
+The Intel SDM states that bit 13 of Icelake's MSR_OFFCORE_RSP_x
+register is valid, and used for counting hardware generated prefetches
+of L3 cache. Update the bitmask to allow bit 13.
+
+Before:
+$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
+ Performance counter stats for 'sleep 3':
+ <not supported> cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
+
+After:
+$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
+ Performance counter stats for 'sleep 3':
+ 9,293 cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
+
+Signed-off-by: Yunying Sun <yunying.sun@intel.com>
+Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: acme@kernel.org
+Cc: alexander.shishkin@linux.intel.com
+Cc: bp@alien8.de
+Cc: hpa@zytor.com
+Cc: jolsa@redhat.com
+Cc: namhyung@kernel.org
+Link: https://lkml.kernel.org/r/20190724082932.12833-1-yunying.sun@intel.com
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ arch/x86/events/intel/core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
+index 2889dd023566..e9042e3f3052 100644
+--- a/arch/x86/events/intel/core.c
++++ b/arch/x86/events/intel/core.c
+@@ -263,8 +263,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
+ };
+
+ static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
+- INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
+- INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
++ INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
++ INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
+ INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
+ INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
+ EVENT_EXTRA_END
+--
+2.22.0
+
diff --git a/series.conf b/series.conf
index 04b5a8744a..6911e78389 100644
--- a/series.conf
+++ b/series.conf
@@ -1133,6 +1133,7 @@
patches.kernel.org/5.2.9-110-test_firmware-fix-a-memory-leak-bug.patch
patches.kernel.org/5.2.9-111-tty-ldsem-locking-rwsem-Add-missing-ACQUIRE-to-.patch
patches.kernel.org/5.2.9-112-perf-x86-intel-Fix-SLOTS-PEBS-event-constraint.patch
+ patches.kernel.org/5.2.9-113-perf-x86-intel-Fix-invalid-Bit-13-for-Icelake-M.patch
########################################################
# Build fixes that apply to the vanilla kernel too.