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authorJohannes Thumshirn <jthumshirn@suse.de>2018-07-27 09:40:31 +0200
committerJohannes Thumshirn <jthumshirn@suse.de>2018-07-27 09:40:31 +0200
commit65a4b496c75a77d855f54be38ea40e9cee6de3da (patch)
tree36b4f511f531f7b2fbcdb37d78c056714426f40c
parent1d68293567e57b0be893b2e2d224714f59dbbb81 (diff)
parent4b2acbbbb0ec506a31bd549c42f1f18bbb5fb0fd (diff)
Merge remote-tracking branch 'origin/SLE15' into SLE12-SP4rpm-4.12.14-94.30
Conflicts: series.conf
-rw-r--r--blacklist.conf12
-rw-r--r--patches.drivers/IIO-BME280-Updates-to-Humidity-readings-need-ctrl_re48
-rw-r--r--patches.drivers/atl1c-reserve-min-skb-headroom47
-rw-r--r--patches.drivers/b44-Initialize-64-bit-stats-seqcount37
-rw-r--r--patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-leaks100
-rw-r--r--patches.drivers/can-bcm-check-for-null-sk-before-deferencing-it-via-50
-rw-r--r--patches.drivers/can-mpc5xxx_can-check-of_iomap-return-before-use40
-rw-r--r--patches.drivers/can-xilinx_can-fix-RX-loop-if-RXNEMP-is-asserted-wit102
-rw-r--r--patches.drivers/can-xilinx_can-fix-RX-overflow-interrupt-not-being-e41
-rw-r--r--patches.drivers/can-xilinx_can-fix-device-dropping-off-bus-on-RX-ove45
-rw-r--r--patches.drivers/can-xilinx_can-fix-incorrect-clear-of-non-processed-58
-rw-r--r--patches.drivers/can-xilinx_can-fix-recovery-from-error-states-not-be238
-rw-r--r--patches.drivers/can-xilinx_can-keep-only-1-2-frames-in-TX-FIFO-to-fi339
-rw-r--r--patches.drivers/clk-Don-t-show-the-incorrect-clock-phase58
-rw-r--r--patches.drivers/clk-Don-t-write-error-code-into-divider-register54
-rw-r--r--patches.drivers/clk-Fix-__set_clk_rates-error-print-string38
-rw-r--r--patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI68
-rw-r--r--patches.drivers/clk-at91-fix-clk-generated-parenting43
-rw-r--r--patches.drivers/clk-axi-clkgen-Correctly-handle-nocount-bit-in-recal76
-rw-r--r--patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a53
-rw-r--r--patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning75
-rw-r--r--patches.drivers/clk-fix-mux-clock-documentation42
-rw-r--r--patches.drivers/clk-fix-set_rate_range-when-current-rate-is-out-of-r83
-rw-r--r--patches.drivers/clk-hi3660-fix-incorrect-uart3-clock-freqency41
-rw-r--r--patches.drivers/clk-hi6220-change-watchdog-clock-source43
-rw-r--r--patches.drivers/clk-hi6220-mark-clock-cs_atb_syspll-as-critical41
-rw-r--r--patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi49
-rw-r--r--patches.drivers/clk-hisilicon-mark-wdt_mux_p-as-const38
-rw-r--r--patches.drivers/clk-honor-CLK_MUX_ROUND_CLOSEST-in-generic-clk-mux93
-rw-r--r--patches.drivers/clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work58
-rw-r--r--patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent54
-rw-r--r--patches.drivers/clk-mediatek-add-the-option-for-determining-PLL-sour54
-rw-r--r--patches.drivers/clk-mediatek-mark-mtk_infrasys_init_early-__init44
-rw-r--r--patches.drivers/clk-meson-gxbb-fix-clk_mclk_i958-divider-flags52
-rw-r--r--patches.drivers/clk-meson-gxbb-fix-meson-cts_amclk-divider-flags43
-rw-r--r--patches.drivers/clk-meson-gxbb-fix-wrong-clock-for-SARADC-SANA53
-rw-r--r--patches.drivers/clk-meson-meson8b-fix-protection-against-undefined-c39
-rw-r--r--patches.drivers/clk-meson-mpll-fix-mpll0-fractional-part-ignored88
-rw-r--r--patches.drivers/clk-meson-mpll-use-64-bit-maths-in-params_from_rate48
-rw-r--r--patches.drivers/clk-meson-remove-unnecessary-rounding-in-the-pll-clo71
-rw-r--r--patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND35
-rw-r--r--patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency40
-rw-r--r--patches.drivers/clk-qcom-clk-smd-rpm-Fix-the-reported-rate-of-branch42
-rw-r--r--patches.drivers/clk-qcom-common-fix-legacy-board-clock-registration42
-rw-r--r--patches.drivers/clk-qcom-msm8916-Fix-bimc-gpu-clock-ops41
-rw-r--r--patches.drivers/clk-qcom-msm8916-fix-mnd_width-for-codec_digcodec35
-rw-r--r--patches.drivers/clk-renesas-div6-Document-fields-used-for-parent-sel37
-rw-r--r--patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-063
-rw-r--r--patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789-42
-rw-r--r--patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent-101
-rw-r--r--patches.drivers/clk-renesas-rcar-gen2-Fix-PLL0-on-R-Car-V2H-and-E281
-rw-r--r--patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-41
-rw-r--r--patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-68
-rw-r--r--patches.drivers/clk-samsung-Fix-m2m-scaler-clock-on-Exynos542x39
-rw-r--r--patches.drivers/clk-samsung-exynos3250-Fix-PLL-rates59
-rw-r--r--patches.drivers/clk-samsung-exynos5250-Add-missing-clocks-for-FIMC-L51
-rw-r--r--patches.drivers/clk-samsung-exynos5250-Fix-PLL-rates56
-rw-r--r--patches.drivers/clk-samsung-exynos5260-Fix-PLL-rates47
-rw-r--r--patches.drivers/clk-samsung-exynos5433-Fix-PLL-rates60
-rw-r--r--patches.drivers/clk-samsung-exynos7-Fix-PLL-rates47
-rw-r--r--patches.drivers/clk-samsung-s3c2410-Fix-PLL-rates73
-rw-r--r--patches.drivers/clk-scpi-error-when-clock-fails-to-register50
-rw-r--r--patches.drivers/clk-scpi-fix-return-type-of-__scpi_dvfs_round_rate51
-rw-r--r--patches.drivers/clk-si5351-Rename-internal-plls-to-avoid-name-collis40
-rw-r--r--patches.drivers/clk-si5351-fix-PLL-reset67
-rw-r--r--patches.drivers/clk-socfpga-Fix-the-smplsel-on-Arria10-and-Stratix1054
-rw-r--r--patches.drivers/clk-sunxi-fix-build-warning43
-rw-r--r--patches.drivers/clk-sunxi-fix-uninitialized-access46
-rw-r--r--patches.drivers/clk-sunxi-ng-Fix-fractional-mode-for-N-M-clocks57
-rw-r--r--patches.drivers/clk-sunxi-ng-Make-fractional-helper-less-chatty53
-rw-r--r--patches.drivers/clk-sunxi-ng-Wait-for-lock-when-using-fractional-mod89
-rw-r--r--patches.drivers/clk-sunxi-ng-a31-Fix-CLK_OUT_-clock-ops71
-rw-r--r--patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_PARENT-flag-to-H3-GPU-40
-rw-r--r--patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_UNGATE-to-all-H3-PLLs111
-rw-r--r--patches.drivers/clk-sunxi-ng-allow-set-parent-clock-PLL_CPUX-for-CPU40
-rw-r--r--patches.drivers/clk-sunxi-ng-h3-gate-then-ungate-PLL-CPU-clk-after-r55
-rw-r--r--patches.drivers/clk-sunxi-ng-multiplier-Fix-fractional-mode40
-rw-r--r--patches.drivers/clk-sunxi-ng-nm-Check-if-requested-rate-is-supported43
-rw-r--r--patches.drivers/clk-sunxi-ng-sun5i-Fix-bit-offset-of-audio-PLL-post-46
-rw-r--r--patches.drivers/clk-sunxi-ng-sun6i-Export-video-PLLs70
-rw-r--r--patches.drivers/clk-sunxi-ng-sun6i-Rename-HDMI-DDC-clock-to-avoid-na39
-rw-r--r--patches.drivers/clk-tegra-Fix-cclk_lp-divisor-register40
-rw-r--r--patches.drivers/clk-tegra-Fix-pll_u-rate-configuration61
-rw-r--r--patches.drivers/clk-tegra-Use-readl_relaxed_poll_timeout_atomic-in-t50
-rw-r--r--patches.drivers/clk-ti-dra7-atl-clock-fix-child-node-lookups46
-rw-r--r--patches.drivers/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro529
-rw-r--r--patches.drivers/clk-x86-Do-not-gate-clocks-enabled-by-the-firmware44
-rw-r--r--patches.drivers/drm-exynos-Fix-dma-buf-import86
-rw-r--r--patches.drivers/drm-i915-Fix-hotplug-irq-ack-on-i965-g4x84
-rw-r--r--patches.drivers/drm-i915-Only-call-tasklet_kill-on-the-first-prepare56
-rw-r--r--patches.drivers/drm-i915-Specify-which-engines-to-reset-following-se1
-rw-r--r--patches.drivers/drm-i915-dp-Send-DPCD-ON-for-MST-before-phy_up122
-rw-r--r--patches.drivers/drm-i915-dp-Write-to-SET_POWER-dpcd-to-enable-MST-hu1
-rw-r--r--patches.drivers/drm-nouveau-Avoid-looping-through-fake-MST-connector207
-rw-r--r--patches.drivers/drm-nouveau-Use-drm_connector_list_iter_-for-iterati164
-rw-r--r--patches.drivers/iio-pressure-zpa2326-Remove-always-true-check-which-68
-rw-r--r--patches.drivers/libnvdimm-label-fix-index-block-size-calculation.patch73
-rw-r--r--patches.drivers/media-staging-omap4iss-Include-asm-cacheflush.h-afte65
-rw-r--r--patches.drivers/pinctrl-bcm2835-Avoid-warning-from-__irq_do_set_hand40
-rw-r--r--patches.drivers/pinctrl-imx-fix-debug-message-for-SHARE_MUX_CONF_REG60
-rw-r--r--patches.drivers/pinctrl-intel-Read-back-TX-buffer-state49
-rw-r--r--patches.drivers/pinctrl-meson-gxbb-remove-non-existing-pin-GPIOX_2244
-rw-r--r--patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-I2S-pins38
-rw-r--r--patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-SPDIF-pins38
-rw-r--r--patches.drivers/pinctrl-mvebu-use-correct-MPP-sel-value-for-dev-pins71
-rw-r--r--patches.drivers/pinctrl-nand-meson-gxbb-fix-missing-data-pins39
-rw-r--r--patches.drivers/pinctrl-nsp-Fix-potential-NULL-dereference50
-rw-r--r--patches.drivers/pinctrl-pinctrl-single-Fix-pcs_request_gpio-when-bit58
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_55
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi189
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu87
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register109
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu87
-rw-r--r--patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-FSCLKST-pin-and66
-rw-r--r--patches.drivers/pinctrl-sunxi-fix-V3s-pinctrl-driver-IRQ-bank-base39
-rw-r--r--patches.drivers/pinctrl-sunxi-fix-wrong-irq_banks-number-for-H5-pinc82
-rw-r--r--patches.drivers/pinctrl-uniphier-fix-members-of-rmii-group-for-Pro437
-rw-r--r--patches.drivers/pinctrl-uniphier-fix-pin_config_get-for-input-enable73
-rw-r--r--patches.drivers/power-gemini-poweroff-Avoid-spurious-poweroff87
-rw-r--r--patches.drivers/power-supply-act8945a_charger-fix-of_irq_get-error-c46
-rw-r--r--patches.drivers/power-supply-cpcap-charger-add-OMAP_USB2-dependency43
-rw-r--r--patches.drivers/pwm-meson-Fix-allocation-of-PWM-channel-array51
-rw-r--r--patches.drivers/pwm-meson-Improve-PWM-calculation-precision79
-rw-r--r--patches.drivers/pwm-stm32-Enforce-dependency-on-CONFIG_MFD_STM32_TIM44
-rw-r--r--patches.drivers/pwm-stm32-Remove-unused-struct-device35
-rw-r--r--patches.drivers/pwm-tiehrpwm-Fix-runtime-PM-imbalance-at-unbind35
-rw-r--r--patches.drivers/pwm-tiehrpwm-fix-clock-imbalance-in-probe-error-path46
-rw-r--r--patches.drivers/r8152-fix-tx-packets-accounting38
-rw-r--r--patches.drivers/r8152-napi-hangup-fix-after-disconnect51
-rw-r--r--patches.drivers/r8169-Be-drop-monitor-friendly47
-rw-r--r--patches.drivers/regulator-max8998-Fix-platform-data-retrieval41
-rw-r--r--patches.drivers/regulator-qcom_spmi-Include-offset-when-translating-108
-rw-r--r--patches.drivers/regulator-tps65218-Fix-strobe-assignment36
-rw-r--r--patches.drivers/s390-qdio-don-t-retry-eqbs-after-ccq-96.patch77
-rw-r--r--patches.drivers/s390-qeth-fix-error-handling-in-adapter-command-callbacks.patch215
-rw-r--r--patches.drivers/scsi-zfcp-fix-infinite-iteration-on-erp-ready-list.patch186
-rw-r--r--patches.drivers/scsi-zfcp-fix-misleading-rec-trigger-trace-where-erp_action-setup-failed.patch117
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-for-all-objects-in-erp_failed.patch185
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-enqueue-without-erp-thread.patch58
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-early-return.patch116
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-for-erp_failed.patch128
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-result-of-eh_host_reset_handler.patch143
-rw-r--r--patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-retry-of-abort-scsi_eh-tmf.patch101
-rw-r--r--patches.drivers/thermal-bcm2835-fix-an-error-code-in-probe37
-rw-r--r--patches.drivers/thermal-drivers-hisi-Fix-kernel-panic-on-alarm-inter58
-rw-r--r--patches.drivers/thermal-drivers-hisi-Fix-missing-interrupt-enablemen56
-rw-r--r--patches.drivers/thermal-drivers-hisi-Fix-multiple-alarm-interrupts-f74
-rw-r--r--patches.drivers/thermal-drivers-hisi-Simplify-the-temperature-step-c104
-rw-r--r--patches.drivers/thermal-fix-INTEL_SOC_DTS_IOSF_CORE-dependencies52
-rw-r--r--patches.fixes/0001-Revert-xhci-plat-Register-shutdown-for-xhci_plat.patch40
-rw-r--r--patches.fixes/0001-USB-OHCI-Fix-NULL-dereference-in-HCDs-using-HCD_LOCA.patch69
-rw-r--r--patches.fixes/0001-pinctrl-intel-Initialize-GPIO-properly-when-used-thr.patch94
-rw-r--r--patches.fixes/0001-pinctrl-nsp-off-by-ones-in-nsp_pinmux_enable.patch38
-rw-r--r--patches.fixes/0001-usb-cdc_acm-prevent-race-at-write-to-acm-while-syste.patch97
-rw-r--r--patches.fixes/0001-usb-dwc2-Improve-gadget-state-disconnection-handling.patch81
-rw-r--r--patches.fixes/0001-usb-option-Add-support-for-FS040U-modem.patch48
-rw-r--r--patches.fixes/xen-grant-table-log-the-lack-of-grants.patch49
-rw-r--r--series.conf154
158 files changed, 10533 insertions, 0 deletions
diff --git a/blacklist.conf b/blacklist.conf
index 37bc4b3c15..8abd77e3ce 100644
--- a/blacklist.conf
+++ b/blacklist.conf
@@ -400,3 +400,15 @@ bfc133515ffba42cf81389275ec24ea3c744bb17 # media: atomisp: not enabled
e4b28b3c3a405b251fa25db58abe1512814a680a # firmware: vpd: not enabled
0631fb8b027f5968c2f5031f0b3ff7be3e4bebcc # firmware: vpd: not enabled
36eb93509c45d0bdbd8d09a01ab9d857972f5963 # warning fix we do not need
+03310a15484ab6a8f6d91bbf7fe486b17275c09a # feature not used in SLE15
+ec897569ad7dbc6d595873a487c3fac23f463f76 # KConfig cosmetics
+7a1646d922577b5b48c0d222e03831141664bb59 # totally superseeded by later patch
+ffaa36448985ac948031d1e99997cb4c78bbbb50 # pinctrl: sunxi: already applied
+24cfe1a9704711a62eef3bc7b921c976abd27cd2 # pinctrl: sh-pfc: not applicable
+e3678b64701e4aa48b1d91a494206dea9ec8bafa # pinctrl: meson: already applied
+bc3322bc166a2905bc91f774d7b22773dc7c063a # pinctrl: devicetree: not applicable
+f90a21c898db58eaea14b8ad7e9af3b9e15e5f8a # pinctrl: nsp: already applied
+4ebb9d7f901027e1740f69829cf10af0193e8e17 # regulator: cpcap: already applied
+ce046e5d9b489554c29ae9277cdc2f86dee76a84 # thermal: max77620: function not available
+0eb875d88aaa98ceb7134cb54638e49b35ab0946 # thermal: exynos: already applied
+2f590f8419c6abb6d87d89c99931a13404a7dbe1 # drm: amd: already applied
diff --git a/patches.drivers/IIO-BME280-Updates-to-Humidity-readings-need-ctrl_re b/patches.drivers/IIO-BME280-Updates-to-Humidity-readings-need-ctrl_re
new file mode 100644
index 0000000000..774c641f2f
--- /dev/null
+++ b/patches.drivers/IIO-BME280-Updates-to-Humidity-readings-need-ctrl_re
@@ -0,0 +1,48 @@
+From 4b1f0c31f96c45e8521dd84aae50f2aa4aecfb7b Mon Sep 17 00:00:00 2001
+From: Colin Parker <colin.parker@aclima.io>
+Date: Mon, 28 Aug 2017 16:21:39 -0700
+Subject: [PATCH] IIO: BME280: Updates to Humidity readings need ctrl_reg write!
+Git-commit: 4b1f0c31f96c45e8521dd84aae50f2aa4aecfb7b
+Patch-mainline: v4.14-rc4
+References: bsc#1051510
+
+The ctrl_reg register needs to be written after any write to
+the humidity registers. The value written to the ctrl_reg register
+does not necessarily need to change, but a write operation must
+occur.
+
+The regmap_update_bits functions will not write to a register
+if the register value matches the value to be written. This saves
+unnecessary bus operations. The change in this patch forces a bus
+write during the chip_config operation by switching to
+regmap_write_bits.
+
+This will fix issues where the Humidity Sensor Oversampling bits
+are not updated after initialization.
+
+Signed-off-by: Colin Parker <colin.parker@aclima.io>
+Acked-by: Andreas Klinger <ak@it-klinger.de>
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/iio/pressure/bmp280-core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c
+index d82b788374b6..e442c5248427 100644
+--- a/drivers/iio/pressure/bmp280-core.c
++++ b/drivers/iio/pressure/bmp280-core.c
+@@ -558,7 +558,7 @@ static int bmp280_chip_config(struct bmp280_data *data)
+ u8 osrs = BMP280_OSRS_TEMP_X(data->oversampling_temp + 1) |
+ BMP280_OSRS_PRESS_X(data->oversampling_press + 1);
+
+- ret = regmap_update_bits(data->regmap, BMP280_REG_CTRL_MEAS,
++ ret = regmap_write_bits(data->regmap, BMP280_REG_CTRL_MEAS,
+ BMP280_OSRS_TEMP_MASK |
+ BMP280_OSRS_PRESS_MASK |
+ BMP280_MODE_MASK,
+--
+2.18.0
+
diff --git a/patches.drivers/atl1c-reserve-min-skb-headroom b/patches.drivers/atl1c-reserve-min-skb-headroom
new file mode 100644
index 0000000000..7acc443ee6
--- /dev/null
+++ b/patches.drivers/atl1c-reserve-min-skb-headroom
@@ -0,0 +1,47 @@
+From 6e56830776828d8ca9897fc4429eeab47c3bb432 Mon Sep 17 00:00:00 2001
+From: Florian Westphal <fw@strlen.de>
+Date: Fri, 20 Jul 2018 19:30:57 +0200
+Subject: [PATCH] atl1c: reserve min skb headroom
+Git-commit: 6e56830776828d8ca9897fc4429eeab47c3bb432
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+Got crash report with following backtrace:
+Bug: unable to handle kernel paging request at ffff8801869daffe
+Rip: 0010:[<ffffffff816429c4>] [<ffffffff816429c4>] ip6_finish_output2+0x394/0x4c0
+Rsp: 0018:ffff880186c83a98 EFLAGS: 00010283
+Rax: ffff8801869db00e ... [<ffffffff81644cdc>] ip6_finish_output+0x8c/0xf0 [<ffffffff81644d97>] ip6_output+0x57/0x100 [<ffffffff81643dc9>] ip6_forward+0x4b9/0x840 [<ffffffff81645566>] ip6_rcv_finish+0x66/0xc0 [<ffffffff81645db9>] ipv6_rcv+0x319/0x530 [<ffffffff815892ac>] netif_receive_skb+0x1c/0x70 [<ffffffffc0060bec>] atl1c_clean+0x1ec/0x310 [atl1c] ...
+
+The bad access is in neigh_hh_output(), at skb->data - 16 (HH_DATA_MOD).
+atl1c driver provided skb with no headroom, so 14 bytes (ethernet
+header) got pulled, but then 16 are copied.
+
+Reserve NET_SKB_PAD bytes headroom, like netdev_alloc_skb().
+
+Compile tested only; I lack hardware.
+
+Fixes: 7b7017642199 ("atl1c: Fix misuse of netdev_alloc_skb in refilling rx ring")
+Signed-off-by: Florian Westphal <fw@strlen.de>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+index 94270f654b3b..7087b88550db 100644
+--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
++++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+@@ -1686,6 +1686,7 @@ static struct sk_buff *atl1c_alloc_skb(struct atl1c_adapter *adapter)
+ skb = build_skb(page_address(page) + adapter->rx_page_offset,
+ adapter->rx_frag_size);
+ if (likely(skb)) {
++ skb_reserve(skb, NET_SKB_PAD);
+ adapter->rx_page_offset += adapter->rx_frag_size;
+ if (adapter->rx_page_offset >= PAGE_SIZE)
+ adapter->rx_page = NULL;
+--
+2.18.0
+
diff --git a/patches.drivers/b44-Initialize-64-bit-stats-seqcount b/patches.drivers/b44-Initialize-64-bit-stats-seqcount
new file mode 100644
index 0000000000..a1b3a94d77
--- /dev/null
+++ b/patches.drivers/b44-Initialize-64-bit-stats-seqcount
@@ -0,0 +1,37 @@
+From e43c9f23efadade684773a855675c99da278c862 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Tue, 1 Aug 2017 12:11:06 -0700
+Subject: [PATCH] b44: Initialize 64-bit stats seqcount
+Git-commit: e43c9f23efadade684773a855675c99da278c862
+Patch-mainline: v4.13-rc5
+References: bsc#1051510
+
+On 32-bit hosts and with CONFIG_DEBUG_LOCK_ALLOC we should be seeing a
+lockdep splat indicating this seqcount is not correctly initialized, fix
+that.
+
+Fixes: eeda8585522b ("b44: add 64 bit stats")
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Acked-by: Michael Chan <michael.chan@broadcom.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/ethernet/broadcom/b44.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c
+index f411936b744c..a1125d10c825 100644
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -2368,6 +2368,7 @@ static int b44_init_one(struct ssb_device *sdev,
+ bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
+
+ spin_lock_init(&bp->lock);
++ u64_stats_init(&bp->hw_stats.syncp);
+
+ bp->rx_pending = B44_DEF_RX_RING_PENDING;
+ bp->tx_pending = B44_DEF_TX_RING_PENDING;
+--
+2.18.0
+
diff --git a/patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-leaks b/patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-leaks
new file mode 100644
index 0000000000..46daae20fa
--- /dev/null
+++ b/patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-leaks
@@ -0,0 +1,100 @@
+From d5318d302e7cf6583ec85a2a8bfbb3a3910ae372 Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Mon, 20 Nov 2017 11:45:47 +0100
+Subject: [PATCH] backlight: as3711_bl: Fix Device Tree node leaks
+Git-commit: d5318d302e7cf6583ec85a2a8bfbb3a3910ae372
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+Two framebuffer device-node names were looked up during probe, but were
+only used as flags to indicate the presence of two framebuffer device.
+
+Drop the unused framebuffer name along with a likewise unused device
+pointer from the driver data, and update the platform data to pass in
+booleans instead of the framebuffer strings. This allows us do drop the
+node references acquired during probe, which would otherwise leak.
+
+Note that there are no other in-kernel users of the modified
+platform-data fields.
+
+Fixes: 59eb2b5e57ea ("drivers/video/backlight/as3711_bl.c: add OF support")
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Acked-by: Daniel Thompson <daniel.thompson@linaro.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/video/backlight/as3711_bl.c | 12 ++++++------
+ include/linux/mfd/as3711.h | 4 ++--
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/video/backlight/as3711_bl.c b/drivers/video/backlight/as3711_bl.c
+index e55304d5cf07..ca544aa764b8 100644
+--- a/drivers/video/backlight/as3711_bl.c
++++ b/drivers/video/backlight/as3711_bl.c
+@@ -28,8 +28,6 @@ enum as3711_bl_type {
+
+ struct as3711_bl_data {
+ bool powered;
+- const char *fb_name;
+- struct device *fb_dev;
+ enum as3711_bl_type type;
+ int brightness;
+ struct backlight_device *bl;
+@@ -273,7 +271,9 @@ static int as3711_backlight_parse_dt(struct device *dev)
+
+ fb = of_parse_phandle(bl, "su1-dev", 0);
+ if (fb) {
+- pdata->su1_fb = fb->full_name;
++ of_node_put(fb);
++
++ pdata->su1_fb = true;
+
+ ret = of_property_read_u32(bl, "su1-max-uA", &pdata->su1_max_uA);
+ if (pdata->su1_max_uA <= 0)
+@@ -286,7 +286,9 @@ static int as3711_backlight_parse_dt(struct device *dev)
+ if (fb) {
+ int count = 0;
+
+- pdata->su2_fb = fb->full_name;
++ of_node_put(fb);
++
++ pdata->su2_fb = true;
+
+ ret = of_property_read_u32(bl, "su2-max-uA", &pdata->su2_max_uA);
+ if (pdata->su2_max_uA <= 0)
+@@ -425,7 +427,6 @@ static int as3711_backlight_probe(struct platform_device *pdev)
+
+ if (pdata->su1_fb) {
+ su = &supply->su1;
+- su->fb_name = pdata->su1_fb;
+ su->type = AS3711_BL_SU1;
+
+ max_brightness = min(pdata->su1_max_uA, 31);
+@@ -436,7 +437,6 @@ static int as3711_backlight_probe(struct platform_device *pdev)
+
+ if (pdata->su2_fb) {
+ su = &supply->su2;
+- su->fb_name = pdata->su2_fb;
+ su->type = AS3711_BL_SU2;
+
+ switch (pdata->su2_fbprot) {
+diff --git a/include/linux/mfd/as3711.h b/include/linux/mfd/as3711.h
+index 34cc85864be5..ddd0b953323b 100644
+--- a/include/linux/mfd/as3711.h
++++ b/include/linux/mfd/as3711.h
+@@ -108,9 +108,9 @@ struct as3711_regulator_pdata {
+ };
+
+ struct as3711_bl_pdata {
+- const char *su1_fb;
++ bool su1_fb;
+ int su1_max_uA;
+- const char *su2_fb;
++ bool su2_fb;
+ int su2_max_uA;
+ enum as3711_su2_feedback su2_feedback;
+ enum as3711_su2_fbprot su2_fbprot;
+--
+2.18.0
+
diff --git a/patches.drivers/can-bcm-check-for-null-sk-before-deferencing-it-via- b/patches.drivers/can-bcm-check-for-null-sk-before-deferencing-it-via-
new file mode 100644
index 0000000000..fa1b8849c7
--- /dev/null
+++ b/patches.drivers/can-bcm-check-for-null-sk-before-deferencing-it-via-
@@ -0,0 +1,50 @@
+From 62c04647c6f44fa3d5d0c077133da0aa1cbbc34c Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 8 Sep 2017 16:02:35 +0100
+Subject: [PATCH] can: bcm: check for null sk before deferencing it via the call to sock_net
+Git-commit: 62c04647c6f44fa3d5d0c077133da0aa1cbbc34c
+Patch-mainline: v4.14-rc6
+References: bsc#1051510
+
+The assignment of net via call sock_net will dereference sk. This
+is performed before a sanity null check on sk, so there could be
+a potential null dereference on the sock_net call if sk is null.
+Fix this by assigning net after the sk null check. Also replace
+the sk == NULL with the more usual !sk idiom.
+
+Detected by CoverityScan CID#1431862 ("Dereference before null check")
+
+Fixes: 384317ef4187 ("can: network namespace support for CAN_BCM protocol")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Acked-by: Oliver Hartkopp <socketcan@hartkopp.net>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ net/can/bcm.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/net/can/bcm.c b/net/can/bcm.c
+index 47a8748d953a..13690334efa3 100644
+--- a/net/can/bcm.c
++++ b/net/can/bcm.c
+@@ -1493,13 +1493,14 @@ static int bcm_init(struct sock *sk)
+ static int bcm_release(struct socket *sock)
+ {
+ struct sock *sk = sock->sk;
+- struct net *net = sock_net(sk);
++ struct net *net;
+ struct bcm_sock *bo;
+ struct bcm_op *op, *next;
+
+- if (sk == NULL)
++ if (!sk)
+ return 0;
+
++ net = sock_net(sk);
+ bo = bcm_sk(sk);
+
+ /* remove bcm_ops, timer, rx_unregister(), etc. */
+--
+2.18.0
+
diff --git a/patches.drivers/can-mpc5xxx_can-check-of_iomap-return-before-use b/patches.drivers/can-mpc5xxx_can-check-of_iomap-return-before-use
new file mode 100644
index 0000000000..d9ab746174
--- /dev/null
+++ b/patches.drivers/can-mpc5xxx_can-check-of_iomap-return-before-use
@@ -0,0 +1,40 @@
+From b5c1a23b17e563b656cc9bb76ce5323b997d90e8 Mon Sep 17 00:00:00 2001
+From: Nicholas Mc Guire <hofrat@osadl.org>
+Date: Mon, 9 Jul 2018 21:16:40 +0200
+Subject: [PATCH] can: mpc5xxx_can: check of_iomap return before use
+Git-commit: b5c1a23b17e563b656cc9bb76ce5323b997d90e8
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+of_iomap() can return NULL so that return needs to be checked and NULL
+treated as failure. While at it also take care of the missing
+of_node_put() in the error path.
+
+Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
+Fixes: commit afa17a500a36 ("net/can: add driver for mscan family & mpc52xx_mscan")
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/mscan/mpc5xxx_can.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
+index c7427bdd3a4b..2949a381a94d 100644
+--- a/drivers/net/can/mscan/mpc5xxx_can.c
++++ b/drivers/net/can/mscan/mpc5xxx_can.c
+@@ -86,6 +86,11 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
+ return 0;
+ }
+ cdm = of_iomap(np_cdm, 0);
++ if (!cdm) {
++ of_node_put(np_cdm);
++ dev_err(&ofdev->dev, "can't map clock node!\n");
++ return 0;
++ }
+
+ if (in_8(&cdm->ipb_clk_sel) & 0x1)
+ freq *= 2;
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-fix-RX-loop-if-RXNEMP-is-asserted-wit b/patches.drivers/can-xilinx_can-fix-RX-loop-if-RXNEMP-is-asserted-wit
new file mode 100644
index 0000000000..f2fd90c231
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-fix-RX-loop-if-RXNEMP-is-asserted-wit
@@ -0,0 +1,102 @@
+From 32852c561bffd613d4ed7ec464b1e03e1b7b6c5c Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Tue, 7 Feb 2017 17:01:14 +0200
+Subject: [PATCH] can: xilinx_can: fix RX loop if RXNEMP is asserted without RXOK
+Git-commit: 32852c561bffd613d4ed7ec464b1e03e1b7b6c5c
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+If the device gets into a state where RXNEMP (RX FIFO not empty)
+interrupt is asserted without RXOK (new frame received successfully)
+interrupt being asserted, xcan_rx_poll() will continue to try to clear
+RXNEMP without actually reading frames from RX FIFO. If the RX FIFO is
+not empty, the interrupt will not be cleared and napi_schedule() will
+just be called again.
+
+This situation can occur when:
+
+(a) xcan_rx() returns without reading RX FIFO due to an error condition.
+The code tries to clear both RXOK and RXNEMP but RXNEMP will not clear
+due to a frame still being in the FIFO. The frame will never be read
+from the FIFO as RXOK is no longer set.
+
+(b) A frame is received between xcan_rx_poll() reading interrupt status
+and clearing RXOK. RXOK will be cleared, but RXNEMP will again remain
+set as the new message is still in the FIFO.
+
+I'm able to trigger case (b) by flooding the bus with frames under load.
+
+There does not seem to be any benefit in using both RXNEMP and RXOK in
+the way the driver does, and the polling example in the reference manual
+(UG585 v1.10 18.3.7 Read Messages from RxFIFO) also says that either
+RXOK or RXNEMP can be used for detecting incoming messages.
+
+Fix the issue and simplify the RX processing by only using RXNEMP
+without RXOK.
+
+Tested with the integrated CAN on Zynq-7000 SoC.
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 18 +++++-------------
+ 1 file changed, 5 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index 389a9603db8c..1bda47aa62f5 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -101,7 +101,7 @@ enum xcan_reg {
+ #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
+ XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
+ XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
+- XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
++ XCAN_IXR_ARBLST_MASK)
+
+ /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
+ #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
+@@ -708,15 +708,7 @@ static int xcan_rx_poll(struct napi_struct *napi, int quota)
+
+ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+ while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
+- if (isr & XCAN_IXR_RXOK_MASK) {
+- priv->write_reg(priv, XCAN_ICR_OFFSET,
+- XCAN_IXR_RXOK_MASK);
+- work_done += xcan_rx(ndev);
+- } else {
+- priv->write_reg(priv, XCAN_ICR_OFFSET,
+- XCAN_IXR_RXNEMP_MASK);
+- break;
+- }
++ work_done += xcan_rx(ndev);
+ priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
+ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+ }
+@@ -727,7 +719,7 @@ static int xcan_rx_poll(struct napi_struct *napi, int quota)
+ if (work_done < quota) {
+ napi_complete_done(napi, work_done);
+ ier = priv->read_reg(priv, XCAN_IER_OFFSET);
+- ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
++ ier |= XCAN_IXR_RXNEMP_MASK;
+ priv->write_reg(priv, XCAN_IER_OFFSET, ier);
+ }
+ return work_done;
+@@ -799,9 +791,9 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id)
+ }
+
+ /* Check for the type of receive interrupt and Processing it */
+- if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
++ if (isr & XCAN_IXR_RXNEMP_MASK) {
+ ier = priv->read_reg(priv, XCAN_IER_OFFSET);
+- ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
++ ier &= ~XCAN_IXR_RXNEMP_MASK;
+ priv->write_reg(priv, XCAN_IER_OFFSET, ier);
+ napi_schedule(&priv->napi);
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-fix-RX-overflow-interrupt-not-being-e b/patches.drivers/can-xilinx_can-fix-RX-overflow-interrupt-not-being-e
new file mode 100644
index 0000000000..454b81e124
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-fix-RX-overflow-interrupt-not-being-e
@@ -0,0 +1,41 @@
+From 83997997252f5d3fc7f04abc24a89600c2b504ab Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Mon, 26 Feb 2018 14:27:13 +0200
+Subject: [PATCH] can: xilinx_can: fix RX overflow interrupt not being enabled
+Git-commit: 83997997252f5d3fc7f04abc24a89600c2b504ab
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+RX overflow interrupt (RXOFLW) is disabled even though xcan_interrupt()
+processes it. This means that an RX overflow interrupt will only be
+processed when another interrupt gets asserted (e.g. for RX/TX).
+
+Fix that by enabling the RXOFLW interrupt.
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: Michal Simek <michal.simek@xilinx.com>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index dcbdc3cd651c..ea9f9d1a5ba7 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -104,7 +104,7 @@ enum xcan_reg {
+ #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
+ XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
+ XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
+- XCAN_IXR_ARBLST_MASK)
++ XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK)
+
+ /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
+ #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-fix-device-dropping-off-bus-on-RX-ove b/patches.drivers/can-xilinx_can-fix-device-dropping-off-bus-on-RX-ove
new file mode 100644
index 0000000000..078034e47f
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-fix-device-dropping-off-bus-on-RX-ove
@@ -0,0 +1,45 @@
+From 2574fe54515ed3487405de329e4e9f13d7098c10 Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Tue, 7 Feb 2017 13:23:04 +0200
+Subject: [PATCH] can: xilinx_can: fix device dropping off bus on RX overrun
+Git-commit: 2574fe54515ed3487405de329e4e9f13d7098c10
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+The xilinx_can driver performs a software reset when an RX overrun is
+detected. This causes the device to enter Configuration mode where no
+messages are received or transmitted.
+
+The documentation does not mention any need to perform a reset on an RX
+overrun, and testing by inducing an RX overflow also indicated that the
+device continues to work just fine without a reset.
+
+Remove the software reset.
+
+Tested with the integrated CAN on Zynq-7000 SoC.
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index 89aec07c225f..389a9603db8c 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -600,7 +600,6 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
+ if (isr & XCAN_IXR_RXOFLW_MASK) {
+ stats->rx_over_errors++;
+ stats->rx_errors++;
+- priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
+ if (skb) {
+ cf->can_id |= CAN_ERR_CRTL;
+ cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-fix-incorrect-clear-of-non-processed- b/patches.drivers/can-xilinx_can-fix-incorrect-clear-of-non-processed-
new file mode 100644
index 0000000000..eaadf11395
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-fix-incorrect-clear-of-non-processed-
@@ -0,0 +1,58 @@
+From 2f4f0f338cf453bfcdbcf089e177c16f35f023c8 Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Mon, 26 Feb 2018 14:39:59 +0200
+Subject: [PATCH] can: xilinx_can: fix incorrect clear of non-processed interrupts
+Git-commit: 2f4f0f338cf453bfcdbcf089e177c16f35f023c8
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+xcan_interrupt() clears ERROR|RXOFLV|BSOFF|ARBLST interrupts if any of
+them is asserted. This does not take into account that some of them
+could have been asserted between interrupt status read and interrupt
+clear, therefore clearing them without handling them.
+
+Fix the code to only clear those interrupts that it knows are asserted
+and therefore going to be processed in xcan_err_interrupt().
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: Michal Simek <michal.simek@xilinx.com>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index ea9f9d1a5ba7..cb80a9aa7281 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -938,6 +938,7 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id)
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct xcan_priv *priv = netdev_priv(ndev);
+ u32 isr, ier;
++ u32 isr_errors;
+
+ /* Get the interrupt status from Xilinx CAN */
+ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+@@ -956,11 +957,10 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id)
+ xcan_tx_interrupt(ndev, isr);
+
+ /* Check for the type of error interrupt and Processing it */
+- if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
+- XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
+- priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
+- XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
+- XCAN_IXR_ARBLST_MASK));
++ isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
++ XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK);
++ if (isr_errors) {
++ priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors);
+ xcan_err_interrupt(ndev, isr);
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-fix-recovery-from-error-states-not-be b/patches.drivers/can-xilinx_can-fix-recovery-from-error-states-not-be
new file mode 100644
index 0000000000..e6a55df914
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-fix-recovery-from-error-states-not-be
@@ -0,0 +1,238 @@
+From 877e0b75947e2c7acf5624331bb17ceb093c98ae Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Wed, 8 Feb 2017 13:13:40 +0200
+Subject: [PATCH] can: xilinx_can: fix recovery from error states not being propagated
+Git-commit: 877e0b75947e2c7acf5624331bb17ceb093c98ae
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+The xilinx_can driver contains no mechanism for propagating recovery
+from CAN_STATE_ERROR_WARNING and CAN_STATE_ERROR_PASSIVE.
+
+Add such a mechanism by factoring the handling of
+XCAN_STATE_ERROR_PASSIVE and XCAN_STATE_ERROR_WARNING out of
+xcan_err_interrupt and checking for recovery after RX and TX if the
+interface is in one of those states.
+
+Tested with the integrated CAN on Zynq-7000 SoC.
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 155 ++++++++++++++++++++++++++++-------
+ 1 file changed, 127 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index 1bda47aa62f5..763408a3eafb 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -2,6 +2,7 @@
+ *
+ * Copyright (C) 2012 - 2014 Xilinx, Inc.
+ * Copyright (C) 2009 PetaLogix. All rights reserved.
++ * Copyright (C) 2017 Sandvik Mining and Construction Oy
+ *
+ * Description:
+ * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
+@@ -529,6 +530,123 @@ static int xcan_rx(struct net_device *ndev)
+ return 1;
+ }
+
++/**
++ * xcan_current_error_state - Get current error state from HW
++ * @ndev: Pointer to net_device structure
++ *
++ * Checks the current CAN error state from the HW. Note that this
++ * only checks for ERROR_PASSIVE and ERROR_WARNING.
++ *
++ * Return:
++ * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE
++ * otherwise.
++ */
++static enum can_state xcan_current_error_state(struct net_device *ndev)
++{
++ struct xcan_priv *priv = netdev_priv(ndev);
++ u32 status = priv->read_reg(priv, XCAN_SR_OFFSET);
++
++ if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK)
++ return CAN_STATE_ERROR_PASSIVE;
++ else if (status & XCAN_SR_ERRWRN_MASK)
++ return CAN_STATE_ERROR_WARNING;
++ else
++ return CAN_STATE_ERROR_ACTIVE;
++}
++
++/**
++ * xcan_set_error_state - Set new CAN error state
++ * @ndev: Pointer to net_device structure
++ * @new_state: The new CAN state to be set
++ * @cf: Error frame to be populated or NULL
++ *
++ * Set new CAN error state for the device, updating statistics and
++ * populating the error frame if given.
++ */
++static void xcan_set_error_state(struct net_device *ndev,
++ enum can_state new_state,
++ struct can_frame *cf)
++{
++ struct xcan_priv *priv = netdev_priv(ndev);
++ u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET);
++ u32 txerr = ecr & XCAN_ECR_TEC_MASK;
++ u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT;
++
++ priv->can.state = new_state;
++
++ if (cf) {
++ cf->can_id |= CAN_ERR_CRTL;
++ cf->data[6] = txerr;
++ cf->data[7] = rxerr;
++ }
++
++ switch (new_state) {
++ case CAN_STATE_ERROR_PASSIVE:
++ priv->can.can_stats.error_passive++;
++ if (cf)
++ cf->data[1] = (rxerr > 127) ?
++ CAN_ERR_CRTL_RX_PASSIVE :
++ CAN_ERR_CRTL_TX_PASSIVE;
++ break;
++ case CAN_STATE_ERROR_WARNING:
++ priv->can.can_stats.error_warning++;
++ if (cf)
++ cf->data[1] |= (txerr > rxerr) ?
++ CAN_ERR_CRTL_TX_WARNING :
++ CAN_ERR_CRTL_RX_WARNING;
++ break;
++ case CAN_STATE_ERROR_ACTIVE:
++ if (cf)
++ cf->data[1] |= CAN_ERR_CRTL_ACTIVE;
++ break;
++ default:
++ /* non-ERROR states are handled elsewhere */
++ WARN_ON(1);
++ break;
++ }
++}
++
++/**
++ * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
++ * @ndev: Pointer to net_device structure
++ *
++ * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
++ * the performed RX/TX has caused it to drop to a lesser state and set
++ * the interface state accordingly.
++ */
++static void xcan_update_error_state_after_rxtx(struct net_device *ndev)
++{
++ struct xcan_priv *priv = netdev_priv(ndev);
++ enum can_state old_state = priv->can.state;
++ enum can_state new_state;
++
++ /* changing error state due to successful frame RX/TX can only
++ * occur from these states
++ */
++ if (old_state != CAN_STATE_ERROR_WARNING &&
++ old_state != CAN_STATE_ERROR_PASSIVE)
++ return;
++
++ new_state = xcan_current_error_state(ndev);
++
++ if (new_state != old_state) {
++ struct sk_buff *skb;
++ struct can_frame *cf;
++
++ skb = alloc_can_err_skb(ndev, &cf);
++
++ xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
++
++ if (skb) {
++ struct net_device_stats *stats = &ndev->stats;
++
++ stats->rx_packets++;
++ stats->rx_bytes += cf->can_dlc;
++ netif_rx(skb);
++ }
++ }
++}
++
+ /**
+ * xcan_err_interrupt - error frame Isr
+ * @ndev: net_device pointer
+@@ -544,16 +662,12 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
+ struct net_device_stats *stats = &ndev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+- u32 err_status, status, txerr = 0, rxerr = 0;
++ u32 err_status;
+
+ skb = alloc_can_err_skb(ndev, &cf);
+
+ err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
+ priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
+- txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
+- rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
+- XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
+- status = priv->read_reg(priv, XCAN_SR_OFFSET);
+
+ if (isr & XCAN_IXR_BSOFF_MASK) {
+ priv->can.state = CAN_STATE_BUS_OFF;
+@@ -563,28 +677,10 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
+ can_bus_off(ndev);
+ if (skb)
+ cf->can_id |= CAN_ERR_BUSOFF;
+- } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
+- priv->can.state = CAN_STATE_ERROR_PASSIVE;
+- priv->can.can_stats.error_passive++;
+- if (skb) {
+- cf->can_id |= CAN_ERR_CRTL;
+- cf->data[1] = (rxerr > 127) ?
+- CAN_ERR_CRTL_RX_PASSIVE :
+- CAN_ERR_CRTL_TX_PASSIVE;
+- cf->data[6] = txerr;
+- cf->data[7] = rxerr;
+- }
+- } else if (status & XCAN_SR_ERRWRN_MASK) {
+- priv->can.state = CAN_STATE_ERROR_WARNING;
+- priv->can.can_stats.error_warning++;
+- if (skb) {
+- cf->can_id |= CAN_ERR_CRTL;
+- cf->data[1] |= (txerr > rxerr) ?
+- CAN_ERR_CRTL_TX_WARNING :
+- CAN_ERR_CRTL_RX_WARNING;
+- cf->data[6] = txerr;
+- cf->data[7] = rxerr;
+- }
++ } else {
++ enum can_state new_state = xcan_current_error_state(ndev);
++
++ xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
+ }
+
+ /* Check for Arbitration lost interrupt */
+@@ -713,8 +809,10 @@ static int xcan_rx_poll(struct napi_struct *napi, int quota)
+ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+ }
+
+- if (work_done)
++ if (work_done) {
+ can_led_event(ndev, CAN_LED_EVENT_RX);
++ xcan_update_error_state_after_rxtx(ndev);
++ }
+
+ if (work_done < quota) {
+ napi_complete_done(napi, work_done);
+@@ -745,6 +843,7 @@ static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
+ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+ }
+ can_led_event(ndev, CAN_LED_EVENT_TX);
++ xcan_update_error_state_after_rxtx(ndev);
+ netif_wake_queue(ndev);
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/can-xilinx_can-keep-only-1-2-frames-in-TX-FIFO-to-fi b/patches.drivers/can-xilinx_can-keep-only-1-2-frames-in-TX-FIFO-to-fi
new file mode 100644
index 0000000000..3ca43f589e
--- /dev/null
+++ b/patches.drivers/can-xilinx_can-keep-only-1-2-frames-in-TX-FIFO-to-fi
@@ -0,0 +1,339 @@
+From 620050d9c2be15c47017ba95efe59e0832e99a56 Mon Sep 17 00:00:00 2001
+From: Anssi Hannula <anssi.hannula@bitwise.fi>
+Date: Thu, 23 Feb 2017 14:50:03 +0200
+Subject: [PATCH] can: xilinx_can: keep only 1-2 frames in TX FIFO to fix TX accounting
+Git-commit: 620050d9c2be15c47017ba95efe59e0832e99a56
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+The xilinx_can driver assumes that the TXOK interrupt only clears after
+it has been acknowledged as many times as there have been successfully
+sent frames.
+
+However, the documentation does not mention such behavior, instead
+saying just that the interrupt is cleared when the clear bit is set.
+
+Similarly, testing seems to also suggest that it is immediately cleared
+regardless of the amount of frames having been sent. Performing some
+heavy TX load and then going back to idle has the tx_head drifting
+further away from tx_tail over time, steadily reducing the amount of
+frames the driver keeps in the TX FIFO (but not to zero, as the TXOK
+interrupt always frees up space for 1 frame from the driver's
+perspective, so frames continue to be sent) and delaying the local echo
+frames.
+
+The TX FIFO tracking is also otherwise buggy as it does not account for
+TX FIFO being cleared after software resets, causing
+ BUG!, TX FIFO full when queue awake!
+messages to be output.
+
+There does not seem to be any way to accurately track the state of the
+TX FIFO for local echo support while using the full TX FIFO.
+
+The Zynq version of the HW (but not the soft-AXI version) has watermark
+programming support and with it an additional TX-FIFO-empty interrupt
+bit.
+
+Modify the driver to only put 1 frame into TX FIFO at a time on soft-AXI
+and 2 frames at a time on Zynq. On Zynq the TXFEMP interrupt bit is used
+to detect whether 1 or 2 frames have been sent at interrupt processing
+time.
+
+Tested with the integrated CAN on Zynq-7000 SoC. The 1-frame-FIFO mode
+was also tested.
+
+An alternative way to solve this would be to drop local echo support but
+keep using the full TX FIFO.
+
+V2: Add FIFO space check before TX queue wake with locking to
+synchronize with queue stop. This avoids waking the queue when xmit()
+had just filled it.
+
+V3: Keep local echo support and reduce the amount of frames in FIFO
+instead as suggested by Marc Kleine-Budde.
+
+Fixes: b1201e44f50b ("can: xilinx CAN controller support")
+Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/can/xilinx_can.c | 139 +++++++++++++++++++++++++++++++----
+ 1 file changed, 123 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
+index 763408a3eafb..dcbdc3cd651c 100644
+--- a/drivers/net/can/xilinx_can.c
++++ b/drivers/net/can/xilinx_can.c
+@@ -26,8 +26,10 @@
+ #include <linux/module.h>
+ #include <linux/netdevice.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/skbuff.h>
++#include <linux/spinlock.h>
+ #include <linux/string.h>
+ #include <linux/types.h>
+ #include <linux/can/dev.h>
+@@ -119,6 +121,7 @@ enum xcan_reg {
+ /**
+ * struct xcan_priv - This definition define CAN driver instance
+ * @can: CAN private data structure.
++ * @tx_lock: Lock for synchronizing TX interrupt handling
+ * @tx_head: Tx CAN packets ready to send on the queue
+ * @tx_tail: Tx CAN packets successfully sended on the queue
+ * @tx_max: Maximum number packets the driver can send
+@@ -133,6 +136,7 @@ enum xcan_reg {
+ */
+ struct xcan_priv {
+ struct can_priv can;
++ spinlock_t tx_lock;
+ unsigned int tx_head;
+ unsigned int tx_tail;
+ unsigned int tx_max;
+@@ -160,6 +164,11 @@ static const struct can_bittiming_const xcan_bittiming_const = {
+ .brp_inc = 1,
+ };
+
++#define XCAN_CAP_WATERMARK 0x0001
++struct xcan_devtype_data {
++ unsigned int caps;
++};
++
+ /**
+ * xcan_write_reg_le - Write a value to the device register little endian
+ * @priv: Driver private data structure
+@@ -239,6 +248,10 @@ static int set_reset_mode(struct net_device *ndev)
+ usleep_range(500, 10000);
+ }
+
++ /* reset clears FIFOs */
++ priv->tx_head = 0;
++ priv->tx_tail = 0;
++
+ return 0;
+ }
+
+@@ -393,6 +406,7 @@ static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+ struct net_device_stats *stats = &ndev->stats;
+ struct can_frame *cf = (struct can_frame *)skb->data;
+ u32 id, dlc, data[2] = {0, 0};
++ unsigned long flags;
+
+ if (can_dropped_invalid_skb(ndev, skb))
+ return NETDEV_TX_OK;
+@@ -440,6 +454,9 @@ static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+ data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
+
+ can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
++
++ spin_lock_irqsave(&priv->tx_lock, flags);
++
+ priv->tx_head++;
+
+ /* Write the Frame to Xilinx CAN TX FIFO */
+@@ -455,10 +472,16 @@ static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+ stats->tx_bytes += cf->can_dlc;
+ }
+
++ /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */
++ if (priv->tx_max > 1)
++ priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK);
++
+ /* Check if the TX buffer is full */
+ if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
+ netif_stop_queue(ndev);
+
++ spin_unlock_irqrestore(&priv->tx_lock, flags);
++
+ return NETDEV_TX_OK;
+ }
+
+@@ -832,19 +855,71 @@ static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
+ {
+ struct xcan_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
++ unsigned int frames_in_fifo;
++ int frames_sent = 1; /* TXOK => at least 1 frame was sent */
++ unsigned long flags;
++ int retries = 0;
++
++ /* Synchronize with xmit as we need to know the exact number
++ * of frames in the FIFO to stay in sync due to the TXFEMP
++ * handling.
++ * This also prevents a race between netif_wake_queue() and
++ * netif_stop_queue().
++ */
++ spin_lock_irqsave(&priv->tx_lock, flags);
++
++ frames_in_fifo = priv->tx_head - priv->tx_tail;
+
+- while ((priv->tx_head - priv->tx_tail > 0) &&
+- (isr & XCAN_IXR_TXOK_MASK)) {
++ if (WARN_ON_ONCE(frames_in_fifo == 0)) {
++ /* clear TXOK anyway to avoid getting back here */
+ priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
++ spin_unlock_irqrestore(&priv->tx_lock, flags);
++ return;
++ }
++
++ /* Check if 2 frames were sent (TXOK only means that at least 1
++ * frame was sent).
++ */
++ if (frames_in_fifo > 1) {
++ WARN_ON(frames_in_fifo > priv->tx_max);
++
++ /* Synchronize TXOK and isr so that after the loop:
++ * (1) isr variable is up-to-date at least up to TXOK clear
++ * time. This avoids us clearing a TXOK of a second frame
++ * but not noticing that the FIFO is now empty and thus
++ * marking only a single frame as sent.
++ * (2) No TXOK is left. Having one could mean leaving a
++ * stray TXOK as we might process the associated frame
++ * via TXFEMP handling as we read TXFEMP *after* TXOK
++ * clear to satisfy (1).
++ */
++ while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) {
++ priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
++ isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
++ }
++
++ if (isr & XCAN_IXR_TXFEMP_MASK) {
++ /* nothing in FIFO anymore */
++ frames_sent = frames_in_fifo;
++ }
++ } else {
++ /* single frame in fifo, just clear TXOK */
++ priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
++ }
++
++ while (frames_sent--) {
+ can_get_echo_skb(ndev, priv->tx_tail %
+ priv->tx_max);
+ priv->tx_tail++;
+ stats->tx_packets++;
+- isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
+ }
++
++ netif_wake_queue(ndev);
++
++ spin_unlock_irqrestore(&priv->tx_lock, flags);
++
+ can_led_event(ndev, CAN_LED_EVENT_TX);
+ xcan_update_error_state_after_rxtx(ndev);
+- netif_wake_queue(ndev);
+ }
+
+ /**
+@@ -1151,6 +1226,18 @@ static const struct dev_pm_ops xcan_dev_pm_ops = {
+ SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL)
+ };
+
++static const struct xcan_devtype_data xcan_zynq_data = {
++ .caps = XCAN_CAP_WATERMARK,
++};
++
++/* Match table for OF platform binding */
++static const struct of_device_id xcan_of_match[] = {
++ { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
++ { .compatible = "xlnx,axi-can-1.00.a", },
++ { /* end of list */ },
++};
++MODULE_DEVICE_TABLE(of, xcan_of_match);
++
+ /**
+ * xcan_probe - Platform registration call
+ * @pdev: Handle to the platform device structure
+@@ -1165,8 +1252,10 @@ static int xcan_probe(struct platform_device *pdev)
+ struct resource *res; /* IO mem resources */
+ struct net_device *ndev;
+ struct xcan_priv *priv;
++ const struct of_device_id *of_id;
++ int caps = 0;
+ void __iomem *addr;
+- int ret, rx_max, tx_max;
++ int ret, rx_max, tx_max, tx_fifo_depth;
+
+ /* Get the virtual base address for the device */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -1176,7 +1265,8 @@ static int xcan_probe(struct platform_device *pdev)
+ goto err;
+ }
+
+- ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
++ ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
++ &tx_fifo_depth);
+ if (ret < 0)
+ goto err;
+
+@@ -1184,6 +1274,30 @@ static int xcan_probe(struct platform_device *pdev)
+ if (ret < 0)
+ goto err;
+
++ of_id = of_match_device(xcan_of_match, &pdev->dev);
++ if (of_id) {
++ const struct xcan_devtype_data *devtype_data = of_id->data;
++
++ if (devtype_data)
++ caps = devtype_data->caps;
++ }
++
++ /* There is no way to directly figure out how many frames have been
++ * sent when the TXOK interrupt is processed. If watermark programming
++ * is supported, we can have 2 frames in the FIFO and use TXFEMP
++ * to determine if 1 or 2 frames have been sent.
++ * Theoretically we should be able to use TXFWMEMP to determine up
++ * to 3 frames, but it seems that after putting a second frame in the
++ * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less
++ * than 2 frames in FIFO) is set anyway with no TXOK (a frame was
++ * sent), which is not a sensible state - possibly TXFWMEMP is not
++ * completely synchronized with the rest of the bits?
++ */
++ if (caps & XCAN_CAP_WATERMARK)
++ tx_max = min(tx_fifo_depth, 2);
++ else
++ tx_max = 1;
++
+ /* Create a CAN device instance */
+ ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
+ if (!ndev)
+@@ -1198,6 +1312,7 @@ static int xcan_probe(struct platform_device *pdev)
+ CAN_CTRLMODE_BERR_REPORTING;
+ priv->reg_base = addr;
+ priv->tx_max = tx_max;
++ spin_lock_init(&priv->tx_lock);
+
+ /* Get IRQ for the device */
+ ndev->irq = platform_get_irq(pdev, 0);
+@@ -1262,9 +1377,9 @@ static int xcan_probe(struct platform_device *pdev)
+
+ pm_runtime_put(&pdev->dev);
+
+- netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
++ netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth: actual %d, using %d\n",
+ priv->reg_base, ndev->irq, priv->can.clock.freq,
+- priv->tx_max);
++ tx_fifo_depth, priv->tx_max);
+
+ return 0;
+
+@@ -1298,14 +1413,6 @@ static int xcan_remove(struct platform_device *pdev)
+ return 0;
+ }
+
+-/* Match table for OF platform binding */
+-static const struct of_device_id xcan_of_match[] = {
+- { .compatible = "xlnx,zynq-can-1.0", },
+- { .compatible = "xlnx,axi-can-1.00.a", },
+- { /* end of list */ },
+-};
+-MODULE_DEVICE_TABLE(of, xcan_of_match);
+-
+ static struct platform_driver xcan_driver = {
+ .probe = xcan_probe,
+ .remove = xcan_remove,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-Don-t-show-the-incorrect-clock-phase b/patches.drivers/clk-Don-t-show-the-incorrect-clock-phase
new file mode 100644
index 0000000000..db43a15fb2
--- /dev/null
+++ b/patches.drivers/clk-Don-t-show-the-incorrect-clock-phase
@@ -0,0 +1,58 @@
+From 1f9c63e8de3d7b377c9d74e4a17524cfb60e6384 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 14 Mar 2018 08:28:31 +0800
+Subject: [PATCH] clk: Don't show the incorrect clock phase
+Git-commit: 1f9c63e8de3d7b377c9d74e4a17524cfb60e6384
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+It's found that the clock phase output from clk_summary is
+wrong compared to the actual phase reading from the register.
+
+cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
+sdio_sample 0 1 0 50000000 0 -22
+
+It exposes an issue that clk core, clk_core_get_phase, always
+returns the cached core->phase which should be either updated
+by calling clk_set_phase or directly from the first place the
+clk was registered.
+
+When registering the clk, the core->phase geting from ->get_phase()
+may return negative value indicating error. This is quite common
+since the clk's phase may be highly related to its parent chain,
+but it was temporarily orphan when registered, since its parent
+chains hadn't be ready at that time, so the clk drivers decide to
+return error in this case. However, if no clk_set_phase is called or
+maybe the ->set_phase() isn't even implemented, the core->phase would
+never be updated. This is wrong, and we should try to update it when
+all its parent chains are settled down, like the way of updating clock
+rate for that. But it's not deserved to complicate the code now and
+just update it anyway when calling clk_core_get_phase, which would be
+much simple and enough.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Acked-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index 617e56268b18..d5c477c7bcf1 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -2373,6 +2373,9 @@ static int clk_core_get_phase(struct clk_core *core)
+ int ret;
+
+ clk_prepare_lock();
++ /* Always try to update cached phase if possible */
++ if (core->ops->get_phase)
++ core->phase = core->ops->get_phase(core->hw);
+ ret = core->phase;
+ clk_prepare_unlock();
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-Don-t-write-error-code-into-divider-register b/patches.drivers/clk-Don-t-write-error-code-into-divider-register
new file mode 100644
index 0000000000..da0ea72ffe
--- /dev/null
+++ b/patches.drivers/clk-Don-t-write-error-code-into-divider-register
@@ -0,0 +1,54 @@
+From 2316a7a33408b6e7b24e9d2a9a7c24af9a012289 Mon Sep 17 00:00:00 2001
+From: Alex Frid <afrid@nvidia.com>
+Date: Tue, 25 Jul 2017 13:18:40 +0300
+Subject: [PATCH] clk: Don't write error code into divider register
+Git-commit: 2316a7a33408b6e7b24e9d2a9a7c24af9a012289
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Add a check for error returned by divider value calculation to avoid
+writing error code into hw register.
+
+Signed-off-by: Alex Frid <afrid@nvidia.com>
+Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
+Reviewed-by: Jon Mayo <jmayo@nvidia.com>
+Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere")
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-divider.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
+index 9bb472cccca6..4ed516cb7276 100644
+--- a/drivers/clk/clk-divider.c
++++ b/drivers/clk/clk-divider.c
+@@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+ {
+ struct clk_divider *divider = to_clk_divider(hw);
+- unsigned int value;
++ int value;
+ unsigned long flags = 0;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
++ if (value < 0)
++ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+@@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ val = clk_readl(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ }
+- val |= value << divider->shift;
++ val |= (u32)value << divider->shift;
+ clk_writel(val, divider->reg);
+
+ if (divider->lock)
+--
+2.18.0
+
diff --git a/patches.drivers/clk-Fix-__set_clk_rates-error-print-string b/patches.drivers/clk-Fix-__set_clk_rates-error-print-string
new file mode 100644
index 0000000000..236b9ab979
--- /dev/null
+++ b/patches.drivers/clk-Fix-__set_clk_rates-error-print-string
@@ -0,0 +1,38 @@
+From ee177c5d6369f8e5d3e4793dce501cf4431313a1 Mon Sep 17 00:00:00 2001
+From: Bryan O'Donoghue <pure.logic@nexus-software.ie>
+Date: Mon, 15 May 2017 11:58:59 +0100
+Subject: [PATCH] clk: Fix __set_clk_rates error print-string
+Git-commit: ee177c5d6369f8e5d3e4793dce501cf4431313a1
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+When failing to set a clock the printout emitted is incorrect.
+"u32 rate" is formatted as %d and should be %u whereas "unsigned long
+clk_set_rate()" is formatted as %ld and should be %lu as per
+Documentation/printk-formats.txt.
+
+Fixes: 2885c3b2a3da ("clk: Show correct information when fail to set clock rate")
+Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-conf.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
+index e0e02a6e5900..7ec36722f8ab 100644
+--- a/drivers/clk/clk-conf.c
++++ b/drivers/clk/clk-conf.c
+@@ -109,7 +109,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
+
+ rc = clk_set_rate(clk, rate);
+ if (rc < 0)
+- pr_err("clk: couldn't set %s clk rate to %d (%d), current rate: %ld\n",
++ pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
+ __clk_get_name(clk), rate, rc,
+ clk_get_rate(clk));
+ clk_put(clk);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI b/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
new file mode 100644
index 0000000000..59a1f00107
--- /dev/null
+++ b/patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
@@ -0,0 +1,68 @@
+From a982e45dc150da3a08907b6dd676b735391704b4 Mon Sep 17 00:00:00 2001
+From: Marcin Ziemianowicz <marcin@ziemianowicz.com>
+Date: Sun, 29 Apr 2018 15:01:11 -0400
+Subject: [PATCH] clk: at91: PLL recalc_rate() now using cached MUL and DIV values
+Git-commit: a982e45dc150da3a08907b6dd676b735391704b4
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+When a USB device is connected to the USB host port on the SAM9N12 then
+you get "-62" error which seems to indicate USB replies from the device
+are timing out. Based on a logic sniffer, I saw the USB bus was running
+at half speed.
+
+The PLL code uses cached MUL and DIV values which get set in set_rate()
+and applied in prepare(), but the recalc_rate() function instead
+queries the hardware instead of using these cached values. Therefore,
+if recalc_rate() is called between a set_rate() and prepare(), the
+wrong frequency is calculated and later the USB clock divider for the
+SAM9N12 SOC will be configured for an incorrect clock.
+
+In my case, the PLL hardware was set to 96 Mhz before the OHCI
+driver loads, and therefore the usb clock divider was being set
+to /2 even though the OHCI driver set the PLL to 48 Mhz.
+
+As an alternative explanation, I noticed this was fixed in the past by
+87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
+driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
+At91: make use of syscon/regmap internally").
+
+Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com>
+Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/at91/clk-pll.c | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
+index 7d3223fc7161..72b6091eb7b9 100644
+--- a/drivers/clk/at91/clk-pll.c
++++ b/drivers/clk/at91/clk-pll.c
+@@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
+ struct clk_pll *pll = to_clk_pll(hw);
+- unsigned int pllr;
+- u16 mul;
+- u8 div;
+-
+- regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
+-
+- div = PLL_DIV(pllr);
+- mul = PLL_MUL(pllr, pll->layout);
+-
+- if (!div || !mul)
+- return 0;
+
+- return (parent_rate / div) * (mul + 1);
++ return (parent_rate / pll->div) * (pll->mul + 1);
+ }
+
+ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-at91-fix-clk-generated-parenting b/patches.drivers/clk-at91-fix-clk-generated-parenting
new file mode 100644
index 0000000000..fec25726d2
--- /dev/null
+++ b/patches.drivers/clk-at91-fix-clk-generated-parenting
@@ -0,0 +1,43 @@
+From 8e56133e5c7b7a7a97f6a92d92f664d5ecd30745 Mon Sep 17 00:00:00 2001
+From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+Date: Fri, 12 May 2017 16:25:30 +0200
+Subject: [PATCH] clk: at91: fix clk-generated parenting
+Git-commit: 8e56133e5c7b7a7a97f6a92d92f664d5ecd30745
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+clk_generated_startup is called after clk_hw_register. So the first call to
+get_parent will not have the correct value (i.e. 0) and because this is
+cached, it may never be updated.
+
+Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/at91/clk-generated.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
+index 4e1cd5aa69d8..70474bd97a10 100644
+--- a/drivers/clk/at91/clk-generated.c
++++ b/drivers/clk/at91/clk-generated.c
+@@ -260,13 +260,12 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
+ gck->lock = lock;
+ gck->range = *range;
+
++ clk_generated_startup(gck);
+ hw = &gck->hw;
+ ret = clk_hw_register(NULL, &gck->hw);
+ if (ret) {
+ kfree(gck);
+ hw = ERR_PTR(ret);
+- } else
+- clk_generated_startup(gck);
+
+ return hw;
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/clk-axi-clkgen-Correctly-handle-nocount-bit-in-recal b/patches.drivers/clk-axi-clkgen-Correctly-handle-nocount-bit-in-recal
new file mode 100644
index 0000000000..0e25b05e49
--- /dev/null
+++ b/patches.drivers/clk-axi-clkgen-Correctly-handle-nocount-bit-in-recal
@@ -0,0 +1,76 @@
+From 063578dc5f407f67d149133818efabe457daafda Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Tue, 5 Sep 2017 11:32:40 +0200
+Subject: [PATCH] clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()
+Git-commit: 063578dc5f407f67d149133818efabe457daafda
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+If the nocount bit is set the divider is bypassed and the settings for the
+divider count should be ignored and a divider value of 1 should be assumed.
+Handle this correctly in the driver recalc_rate() callback.
+
+While the driver sets up the part so that the read back dividers values
+yield the correct result the power-on reset settings of the part might not
+reflect this and hence calling e.g. clk_get_rate() without prior calls to
+clk_set_rate() will yield the wrong result.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-axi-clkgen.c | 29 ++++++++++++++++++++++++-----
+ 1 file changed, 24 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
+index 5e918e7afaba..95a6e9834392 100644
+--- a/drivers/clk/clk-axi-clkgen.c
++++ b/drivers/clk/clk-axi-clkgen.c
+@@ -40,6 +40,10 @@
+ #define MMCM_REG_FILTER1 0x4e
+ #define MMCM_REG_FILTER2 0x4f
+
++#define MMCM_CLKOUT_NOCOUNT BIT(6)
++
++#define MMCM_CLK_DIV_NOCOUNT BIT(12)
++
+ struct axi_clkgen {
+ void __iomem *base;
+ struct clk_hw clk_hw;
+@@ -315,12 +319,27 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
+ unsigned int reg;
+ unsigned long long tmp;
+
+- axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
+- dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
++ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);
++ if (reg & MMCM_CLKOUT_NOCOUNT) {
++ dout = 1;
++ } else {
++ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
++ dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
++ }
++
+ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);
+- d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+- axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
+- m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
++ if (reg & MMCM_CLK_DIV_NOCOUNT)
++ d = 1;
++ else
++ d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
++
++ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);
++ if (reg & MMCM_CLKOUT_NOCOUNT) {
++ m = 1;
++ } else {
++ axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
++ m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
++ }
+
+ if (d == 0 || dout == 0)
+ return 0;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a b/patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
new file mode 100644
index 0000000000..c5b3ebcc9d
--- /dev/null
+++ b/patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
@@ -0,0 +1,53 @@
+From 753872373b599384ac7df809aa61ea12d1c4d5d1 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 22 Mar 2018 10:11:30 +0100
+Subject: [PATCH] clk: bcm2835: De-assert/assert PLL reset signal when appropriate
+Git-commit: 753872373b599384ac7df809aa61ea12d1c4d5d1
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+In order to enable a PLL, not only the PLL has to be powered up and
+locked, but you also have to de-assert the reset signal. The last part
+was missing. Add it so PLLs that were not enabled by the FW/bootloader
+can be enabled from Linux.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/bcm/clk-bcm2835.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
+index 44301a3d9963..40acb8ebfb42 100644
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -602,9 +602,7 @@ static void bcm2835_pll_off(struct clk_hw *hw)
+ const struct bcm2835_pll_data *data = pll->data;
+
+ spin_lock(&cprman->regs_lock);
+- cprman_write(cprman, data->cm_ctrl_reg,
+- cprman_read(cprman, data->cm_ctrl_reg) |
+- CM_PLL_ANARST);
++ cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PWRDN);
+@@ -638,6 +636,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
+ cpu_relax();
+ }
+
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) |
++ A2W_PLL_CTRL_PRST_DISABLE);
++
+ return 0;
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning b/patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning
new file mode 100644
index 0000000000..a8cedb33b0
--- /dev/null
+++ b/patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning
@@ -0,0 +1,75 @@
+From ce33f284935e08229046b30635e6aadcbab02b53 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 16 Feb 2018 16:27:47 +0100
+Subject: [PATCH] clk: fix false-positive Wmaybe-uninitialized warning
+Git-commit: ce33f284935e08229046b30635e6aadcbab02b53
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+When we build this driver with on x86-32, gcc produces a false-positive warning:
+
+Drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
+drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+ return clk_register_fixed_factor(NULL, name, parent_name, 0,
+
+We can work around that warning by adding a fake initialization, I tried
+and failed to come up with any better workaround. This is currently one
+of few remaining warnings for a 4.14.y randconfig build, so it would be
+good to also have it backported at least to that version. Older versions
+have more randconfig warnings, so we might not care.
+
+I had not noticed this earlier, because one patch in my randconfig test
+tree removes the '-ffreestanding' option on x86-32, and that avoids
+the warning. The -ffreestanding flag was originally global but moved
+into arch/i386 by Andi Kleen in commit 6edfba1b33c7 ("[PATCH] x86_64:
+Don't define string functions to builtin") as a 'temporary workaround'.
+
+Like many temporary hacks, this turned out to be rather long-lived, from
+all I can tell we still need a simple fix to asm/string_32.h before it
+can be removed, but I'm not sure about how to best do that.
+
+Cc: stable@vger.kernel.org
+Cc: Andi Kleen <ak@linux.intel.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/clk-sh73a0.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
+index eea38f6ea77e..3892346c4fcc 100644
+--- a/drivers/clk/renesas/clk-sh73a0.c
++++ b/drivers/clk/renesas/clk-sh73a0.c
+@@ -46,7 +46,7 @@ struct div4_clk {
+ unsigned int shift;
+ };
+
+-static struct div4_clk div4_clks[] = {
++static const struct div4_clk div4_clks[] = {
+ { "zg", "pll0", CPG_FRQCRA, 16 },
+ { "m3", "pll1", CPG_FRQCRA, 12 },
+ { "b", "pll1", CPG_FRQCRA, 8 },
+@@ -79,7 +79,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
+ {
+ const struct clk_div_table *table = NULL;
+ unsigned int shift, reg, width;
+- const char *parent_name;
++ const char *parent_name = NULL;
+ unsigned int mult = 1;
+ unsigned int div = 1;
+
+@@ -135,7 +135,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
+ shift = 24;
+ width = 5;
+ } else {
+- struct div4_clk *c;
++ const struct div4_clk *c;
+
+ for (c = div4_clks; c->name; c++) {
+ if (!strcmp(name, c->name)) {
+--
+2.18.0
+
diff --git a/patches.drivers/clk-fix-mux-clock-documentation b/patches.drivers/clk-fix-mux-clock-documentation
new file mode 100644
index 0000000000..d19901a9c7
--- /dev/null
+++ b/patches.drivers/clk-fix-mux-clock-documentation
@@ -0,0 +1,42 @@
+From fe3f338f0cb2ed4d4f06da054c21ae2f8a36ef2d Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Wed, 14 Feb 2018 14:43:38 +0100
+Subject: [PATCH] clk: fix mux clock documentation
+Git-commit: fe3f338f0cb2ed4d4f06da054c21ae2f8a36ef2d
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+The mux documentation mentions the non-existing parameter width instead
+of mask, so just sed this.
+
+The table field is missing in the documentation of clk_mux.
+Add a small blurb explaining what it is
+
+Fixes: 9d9f78ed9af0 ("clk: basic clock hardware types")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ include/linux/clk-provider.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
+index fe720d679c31..cb18526d69cb 100644
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -450,8 +450,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling multiplexer
++ * @table: array of register values corresponding to the parent index
+ * @shift: shift to multiplexer bit field
+- * @width: width of mutliplexer bit field
++ * @mask: mask of mutliplexer bit field
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ *
+--
+2.18.0
+
diff --git a/patches.drivers/clk-fix-set_rate_range-when-current-rate-is-out-of-r b/patches.drivers/clk-fix-set_rate_range-when-current-rate-is-out-of-r
new file mode 100644
index 0000000000..5c96e57880
--- /dev/null
+++ b/patches.drivers/clk-fix-set_rate_range-when-current-rate-is-out-of-r
@@ -0,0 +1,83 @@
+From 6562fbcf3ad5ffa56f1fc79bb1afae909cf3627b Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 1 Dec 2017 22:52:00 +0100
+Subject: [PATCH] clk: fix set_rate_range when current rate is out of range
+Git-commit: 6562fbcf3ad5ffa56f1fc79bb1afae909cf3627b
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+Calling clk_core_set_rate() with core->req_rate is basically a no-op
+because of the early bail-out mechanism.
+
+This may leave the clock in inconsistent state if the rate is out the
+requested range. Calling clk_core_set_rate() with the closest rate
+limit could solve the problem but:
+- The underlying determine_rate() callback needs to account for this
+ corner case (rounding within the range, if possible)
+- if only round_rate() is available, we rely on luck unfortunately.
+
+Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks")
+Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Michael Turquette <mturquette@baylibre.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+Link: lkml.kernel.org/r/20171201215200.23523-11-jbrunet@baylibre.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk.c | 37 +++++++++++++++++++++++++++++++++----
+ 1 file changed, 33 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -1648,6 +1648,7 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
+ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
+ {
+ int ret = 0;
++ unsigned long old_min, old_max, rate;
+
+ if (!clk)
+ return 0;
+@@ -1661,10 +1662,38 @@ int clk_set_rate_range(struct clk *clk,
+
+ clk_prepare_lock();
+
+- if (min != clk->min_rate || max != clk->max_rate) {
+- clk->min_rate = min;
+- clk->max_rate = max;
+- ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
++ /* Save the current values in case we need to rollback the change */
++ old_min = clk->min_rate;
++ old_max = clk->max_rate;
++ clk->min_rate = min;
++ clk->max_rate = max;
++
++ rate = clk_core_get_rate_nolock(clk->core);
++ if (rate < min || rate > max) {
++ /*
++ * FIXME:
++ * We are in bit of trouble here, current rate is outside the
++ * the requested range. We are going try to request appropriate
++ * range boundary but there is a catch. It may fail for the
++ * usual reason (clock broken, clock protected, etc) but also
++ * because:
++ * - round_rate() was not favorable and fell on the wrong
++ * side of the boundary
++ * - the determine_rate() callback does not really check for
++ * this corner case when determining the rate
++ */
++
++ if (rate < min)
++ rate = min;
++ else
++ rate = max;
++
++ ret = clk_core_set_rate_nolock(clk->core, rate);
++ if (ret) {
++ /* rollback the changes */
++ clk->min_rate = old_min;
++ clk->max_rate = old_max;
++ }
+ }
+
+ clk_prepare_unlock();
diff --git a/patches.drivers/clk-hi3660-fix-incorrect-uart3-clock-freqency b/patches.drivers/clk-hi3660-fix-incorrect-uart3-clock-freqency
new file mode 100644
index 0000000000..0432d83720
--- /dev/null
+++ b/patches.drivers/clk-hi3660-fix-incorrect-uart3-clock-freqency
@@ -0,0 +1,41 @@
+From d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8 Mon Sep 17 00:00:00 2001
+From: Zhong Kaihua <zhongkaihua@huawei.com>
+Date: Mon, 7 Aug 2017 22:51:56 +0800
+Subject: [PATCH] clk: hi3660: fix incorrect uart3 clock freqency
+Git-commit: d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+UART3 clock rate is doubled in previous commit.
+
+This error is not detected until recently a mezzanine board which makes
+real use of uart3 port (through LS connector of 96boards) was setup
+and tested on hi3660-hikey960 board.
+
+This patch changes clock source rate of clk_factor_uart3 to 100000000.
+
+Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/hisilicon/clk-hi3660.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
+index a18258eb89cb..f40419959656 100644
+--- a/drivers/clk/hisilicon/clk-hi3660.c
++++ b/drivers/clk/hisilicon/clk-hi3660.c
+@@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
+
+ /* crgctrl */
+ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
+- { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, },
++ { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
+ { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
+ { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
+ { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
+--
+2.18.0
+
diff --git a/patches.drivers/clk-hi6220-change-watchdog-clock-source b/patches.drivers/clk-hi6220-change-watchdog-clock-source
new file mode 100644
index 0000000000..88ffc0e74c
--- /dev/null
+++ b/patches.drivers/clk-hi6220-change-watchdog-clock-source
@@ -0,0 +1,43 @@
+From 9fa7231b1979f792b2cbc395c52e197158494948 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Tue, 29 Aug 2017 15:58:37 +0800
+Subject: [PATCH] clk: hi6220: change watchdog clock source
+Git-commit: 9fa7231b1979f792b2cbc395c52e197158494948
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The old code uses tcxo (19.2MHz) as watchdog clock but actually the
+watchdog uses 32K clock, as result the watchdog timeout cannot be set
+correctly and delay long time to reset SoC.
+
+So this patch is to use 'ref32k' as clock source for watchdog.
+
+Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC")
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/hisilicon/clk-hi6220.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
+index 4181b6808545..e786d717f75d 100644
+--- a/drivers/clk/hisilicon/clk-hi6220.c
++++ b/drivers/clk/hisilicon/clk-hi6220.c
+@@ -55,9 +55,9 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
+ };
+
+ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
+- { HI6220_WDT0_PCLK, "wdt0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
+- { HI6220_WDT1_PCLK, "wdt1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
+- { HI6220_WDT2_PCLK, "wdt2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
++ { HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
++ { HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
++ { HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
+ { HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
+ { HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
+ { HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
+--
+2.18.0
+
diff --git a/patches.drivers/clk-hi6220-mark-clock-cs_atb_syspll-as-critical b/patches.drivers/clk-hi6220-mark-clock-cs_atb_syspll-as-critical
new file mode 100644
index 0000000000..abb4ffed57
--- /dev/null
+++ b/patches.drivers/clk-hi6220-mark-clock-cs_atb_syspll-as-critical
@@ -0,0 +1,41 @@
+From d2a3671ebe6479483a12f94fcca63c058d95ad64 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Fri, 1 Sep 2017 08:47:14 +0800
+Subject: [PATCH] clk: hi6220: mark clock cs_atb_syspll as critical
+Git-commit: d2a3671ebe6479483a12f94fcca63c058d95ad64
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Clock cs_atb_syspll is pll used for coresight trace bus; when clock
+cs_atb_syspll is disabled and operates its child clock node cs_atb
+results in system hang. So mark clock cs_atb_syspll as critical to
+keep it enabled.
+
+Cc: Guodong Xu <guodong.xu@linaro.org>
+Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
+Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/hisilicon/clk-hi6220.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
+index e786d717f75d..a87809d4bd52 100644
+--- a/drivers/clk/hisilicon/clk-hi6220.c
++++ b/drivers/clk/hisilicon/clk-hi6220.c
+@@ -145,7 +145,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
+ { HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
+ { HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
+ { HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
+- { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
++ { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
+ };
+
+ static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
+--
+2.18.0
+
diff --git a/patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi b/patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi
new file mode 100644
index 0000000000..299baf2794
--- /dev/null
+++ b/patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi
@@ -0,0 +1,49 @@
+From c744b63b6c422776293cc526ef7887623926f33e Mon Sep 17 00:00:00 2001
+From: Wei Yongjun <weiyongjun1@huawei.com>
+Date: Tue, 20 Mar 2018 14:19:34 +0000
+Subject: [PATCH] clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
+Git-commit: c744b63b6c422776293cc526ef7887623926f33e
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+platform_get_resource() may fail and return NULL, so we should
+better check it's return value to avoid a NULL pointer dereference
+a bit later in the code.
+
+This is detected by Coccinelle semantic patch.
+
+@@
+expression pdev, res, n, t, e, e1, e2;
+@@
+
+res = platform_get_resource(pdev, t, n);
++ if (!res)
++ return -EINVAL;
+... when != res == NULL
+e = devm_ioremap(e1, res->start, e2);
+
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Fixes: 322269163a36 ("clk: hisilicon: add hisi_clk_alloc function.")
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/hisilicon/clk.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
+index 29046b8334c2..953c8dacef8b 100644
+--- a/drivers/clk/hisilicon/clk.c
++++ b/drivers/clk/hisilicon/clk.c
+@@ -49,6 +49,8 @@ struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev,
+ return NULL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return NULL;
+ clk_data->base = devm_ioremap(&pdev->dev,
+ res->start, resource_size(res));
+ if (!clk_data->base)
+--
+2.18.0
+
diff --git a/patches.drivers/clk-hisilicon-mark-wdt_mux_p-as-const b/patches.drivers/clk-hisilicon-mark-wdt_mux_p-as-const
new file mode 100644
index 0000000000..b8be9fea42
--- /dev/null
+++ b/patches.drivers/clk-hisilicon-mark-wdt_mux_p-as-const
@@ -0,0 +1,38 @@
+From df934cbcbff7afbc024bf05f02615917c61f6470 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Tue, 20 Feb 2018 16:15:21 +0100
+Subject: [PATCH] clk: hisilicon: mark wdt_mux_p[] as const
+Git-commit: df934cbcbff7afbc024bf05f02615917c61f6470
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+The symbol is in the __initconst section but not marked init, which
+caused a warning when building with LTO.
+
+This makes it 'const' as was obviously intended.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Fixes: c80dfd9bf54e ("clk: hisilicon: add CRG driver for Hi3516CV300 SoC")
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/hisilicon/crg-hi3516cv300.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
+index 2007123832bb..53450b651e4c 100644
+--- a/drivers/clk/hisilicon/crg-hi3516cv300.c
++++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
+@@ -204,7 +204,7 @@ static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
+ /* hi3516CV300 sysctrl CRG */
+ #define HI3516CV300_SYSCTRL_NR_CLKS 16
+
+-static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
++static const char *const wdt_mux_p[] __initconst = { "3m", "apb" };
+ static u32 wdt_mux_table[] = {0, 1};
+
+ static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
+--
+2.18.0
+
diff --git a/patches.drivers/clk-honor-CLK_MUX_ROUND_CLOSEST-in-generic-clk-mux b/patches.drivers/clk-honor-CLK_MUX_ROUND_CLOSEST-in-generic-clk-mux
new file mode 100644
index 0000000000..c3fadc8bcc
--- /dev/null
+++ b/patches.drivers/clk-honor-CLK_MUX_ROUND_CLOSEST-in-generic-clk-mux
@@ -0,0 +1,93 @@
+From 4ad69b80e886a845f56ce0a3d10211208693d92b Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 9 Apr 2018 15:59:20 +0200
+Subject: [PATCH] clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
+Git-commit: 4ad69b80e886a845f56ce0a3d10211208693d92b
+Patch-mainline: v4.17-rc4
+References: bsc#1051510
+
+CLK_MUX_ROUND_CLOSEST is part of the clk_mux documentation but clk_mux
+directly calls __clk_mux_determine_rate(), which overrides the flag.
+As result, if clk_mux is instantiated with CLK_MUX_ROUND_CLOSEST, the
+flag will be ignored and the clock rounded down.
+
+To solve this, this patch expose clk_mux_determine_rate_flags() in the
+clk-provider API and uses it in the determine_rate() callback of clk_mux.
+
+Fixes: 15a02c1f6dd7 ("clk: Add __clk_mux_determine_rate_closest")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-mux.c | 10 +++++++++-
+ drivers/clk/clk.c | 7 ++++---
+ include/linux/clk-provider.h | 3 +++
+ 3 files changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
+index ac4a042f8658..1628b93655ed 100644
+--- a/drivers/clk/clk-mux.c
++++ b/drivers/clk/clk-mux.c
+@@ -112,10 +112,18 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+ return 0;
+ }
+
++static int clk_mux_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ struct clk_mux *mux = to_clk_mux(hw);
++
++ return clk_mux_determine_rate_flags(hw, req, mux->flags);
++}
++
+ const struct clk_ops clk_mux_ops = {
+ .get_parent = clk_mux_get_parent,
+ .set_parent = clk_mux_set_parent,
+- .determine_rate = __clk_mux_determine_rate,
++ .determine_rate = clk_mux_determine_rate,
+ };
+ EXPORT_SYMBOL_GPL(clk_mux_ops);
+
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index ea67ac81c6f9..7af555f0e60c 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -426,9 +426,9 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
+ return now <= rate && now > best;
+ }
+
+-static int
+-clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
+- unsigned long flags)
++int clk_mux_determine_rate_flags(struct clk_hw *hw,
++ struct clk_rate_request *req,
++ unsigned long flags)
+ {
+ struct clk_core *core = hw->core, *parent, *best_parent = NULL;
+ int i, num_parents, ret;
+@@ -488,6 +488,7 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
+
+ return 0;
+ }
++EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
+
+ struct clk *__clk_lookup(const char *name)
+ {
+diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
+index 210a890008f9..1d25e149c1c5 100644
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -765,6 +765,9 @@ int __clk_mux_determine_rate(struct clk_hw *hw,
+ int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
+ int __clk_mux_determine_rate_closest(struct clk_hw *hw,
+ struct clk_rate_request *req);
++int clk_mux_determine_rate_flags(struct clk_hw *hw,
++ struct clk_rate_request *req,
++ unsigned long flags);
+ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
+ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
+ unsigned long max_rate);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work b/patches.drivers/clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work
new file mode 100644
index 0000000000..2c7a7808b6
--- /dev/null
+++ b/patches.drivers/clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work
@@ -0,0 +1,58 @@
+From c68ee58d9ee7b856ac722f18f4f26579c8fbd2b4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= <sebastien.szymanski@armadeus.com>
+Date: Tue, 1 Aug 2017 12:40:07 +0200
+Subject: [PATCH] clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: c68ee58d9ee7b856ac722f18f4f26579c8fbd2b4
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver
+fails to probe:
+
+[ 2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller
+(0000:00:00)
+[ 2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi
+(ops dw_hdmi_imx_ops): -19
+[ 2.557403] imx-drm display-subsystem: master bind failed: -19
+
+That's because hdmi_isfr's parent, video_27m, is not correctly ungated.
+As explained in commit 5ccc248cc537 ("ARM: imx6q: clk: Add support for
+mipi_core_cfg clock as a shared clock gate"), video_27m is gated by
+CCM_CCGR3[CG8].
+
+On i.MX6 SoCs with VPU, the hdmi is working thanks to the
+CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever
+is in CCM_CCGR3[CG8]. The issue can be reproduced by setting
+CCMEOR[mod_en_ov_vpu] to 0.
+
+Make the HDMI work in every case by setting hdmi_isfr's parent to
+mipi_core_cfg.
+
+Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
+Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/imx/clk-imx6q.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
+index c07df719b8a3..8d518ad5dc13 100644
+--- a/drivers/clk/imx/clk-imx6q.c
++++ b/drivers/clk/imx/clk-imx6q.c
+@@ -761,7 +761,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+ clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
+ clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
+- clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4);
++ clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
+ clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
+ clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
+ clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent b/patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent
new file mode 100644
index 0000000000..382bdce90d
--- /dev/null
+++ b/patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent
@@ -0,0 +1,54 @@
+From 4dd5d5b520dc43f8bd98b65a8382a1bca5d6eb91 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 22 May 2018 15:52:36 +0100
+Subject: [PATCH] clk: imx7d: fix mipi dphy div parent
+Git-commit: 4dd5d5b520dc43f8bd98b65a8382a1bca5d6eb91
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan
+clock and set the correct parent.
+
+Before:
+cat clk_orphan_summary
+ enable prepare protect
+ clock count count count rate accuracy phase
+
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+----------------------------------------------------------------------------------------
+ mipi_dphy_post_div 1 1 0 0 0 0
+ mipi_dphy_root_clk 1 1 0 0 0 0
+
+cat clk_dump | grep mipi_dphy
+mipi_dphy_post_div 1 1 0 0 0 0
+ mipi_dphy_root_clk 1 1 0 0 0 0
+
+after:
+cat clk_dump | grep mipi_dphy
+ mipi_dphy_src 1 1 0 24000000 0 0
+ mipi_dphy_cg 1 1 0 24000000 0 0
+ mipi_dphy_pre_div 1 1 0 24000000 0 0
+ mipi_dphy_post_div 1 1 0 24000000 0 0
+ mipi_dphy_root_clk 1 1 0 24000000 0 0
+
+Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support")
+Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/imx/clk-imx7d.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/imx/clk-imx7d.c
++++ b/drivers/clk/imx/clk-imx7d.c
+@@ -737,7 +737,7 @@ static void __init imx7d_clocks_init(str
+ clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
+ clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
+ clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
+- clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6);
++ clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
+ clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
+ clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
+ clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
diff --git a/patches.drivers/clk-mediatek-add-the-option-for-determining-PLL-sour b/patches.drivers/clk-mediatek-add-the-option-for-determining-PLL-sour
new file mode 100644
index 0000000000..b9f173813d
--- /dev/null
+++ b/patches.drivers/clk-mediatek-add-the-option-for-determining-PLL-sour
@@ -0,0 +1,54 @@
+From c955bf3998efa3355790a4d8c82874582f1bc727 Mon Sep 17 00:00:00 2001
+From: Chen Zhong <chen.zhong@mediatek.com>
+Date: Thu, 5 Oct 2017 11:50:23 +0800
+Subject: [PATCH] clk: mediatek: add the option for determining PLL source clock
+Git-commit: c955bf3998efa3355790a4d8c82874582f1bc727
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Since the previous setup always sets the PLL using crystal 26MHz, this
+doesn't always happen in every MediaTek platform. So the patch added
+flexibility for assigning extra member for determining the PLL source
+clock.
+
+Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/mediatek/clk-mtk.h | 1 +
+ drivers/clk/mediatek/clk-pll.c | 5 ++++-
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
+index f48df75cc901..f10250dcece4 100644
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -218,6 +218,7 @@ struct mtk_pll_data {
+ uint32_t pcw_reg;
+ int pcw_shift;
+ const struct mtk_pll_div_table *div_table;
++ const char *parent_name;
+ };
+
+ void mtk_clk_register_plls(struct device_node *node,
+diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
+index 3c546bae6955..f54e4015b0b1 100644
+--- a/drivers/clk/mediatek/clk-pll.c
++++ b/drivers/clk/mediatek/clk-pll.c
+@@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
+ init.name = data->name;
+ init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
+ init.ops = &mtk_pll_ops;
+- init.parent_names = &parent_name;
++ if (data->parent_name)
++ init.parent_names = &data->parent_name;
++ else
++ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ clk = clk_register(NULL, &pll->hw);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-mediatek-mark-mtk_infrasys_init_early-__init b/patches.drivers/clk-mediatek-mark-mtk_infrasys_init_early-__init
new file mode 100644
index 0000000000..bb2e1803eb
--- /dev/null
+++ b/patches.drivers/clk-mediatek-mark-mtk_infrasys_init_early-__init
@@ -0,0 +1,44 @@
+From 5ef288d42aefef63f728116818a097b3caf000a5 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 15 Sep 2017 21:28:30 +0200
+Subject: [PATCH] clk: mediatek: mark mtk_infrasys_init_early __init
+Git-commit: 5ef288d42aefef63f728116818a097b3caf000a5
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+On gcc-4.6, we get a harmless link-time warning:
+
+Warning: vmlinux.o(.text.unlikely+0x196a0): Section mismatch in reference from the function mtk_infrasys_init_early() to the function .init.text:mtk_clk_register_cpumuxes()
+The function mtk_infrasys_init_early() references
+the function __init mtk_clk_register_cpumuxes().
+This is often because mtk_infrasys_init_early lacks a __init
+annotation or the annotation of mtk_clk_register_cpumuxes is wrong.
+
+Newer compilers inline this function so they don't warn, but
+marking it __init is the right solution for all versions.
+
+Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/mediatek/clk-mt2701.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 9598889f972b..8e7f16fd87c9 100644
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -750,7 +750,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
+
+ static struct clk_onecell_data *infra_clk_data;
+
+-static void mtk_infrasys_init_early(struct device_node *node)
++static void __init mtk_infrasys_init_early(struct device_node *node)
+ {
+ int r, i;
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-gxbb-fix-clk_mclk_i958-divider-flags b/patches.drivers/clk-meson-gxbb-fix-clk_mclk_i958-divider-flags
new file mode 100644
index 0000000000..e787cc2366
--- /dev/null
+++ b/patches.drivers/clk-meson-gxbb-fix-clk_mclk_i958-divider-flags
@@ -0,0 +1,52 @@
+From 7605aa5b4198ad819dde7c39b3c968f57ccb568e Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 27 Jul 2017 15:09:40 +0200
+Subject: [PATCH] clk: meson: gxbb: fix clk_mclk_i958 divider flags
+Git-commit: 7605aa5b4198ad819dde7c39b3c968f57ccb568e
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
+while it should have been in the divider flags
+
+Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/gxbb.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index 0bd028adadd5..60342cfb0bf6 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -876,7 +876,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
+ /* Default parent unknown (register reset value: 0) */
+ .table = (u32[]){ 1, 2, 3 },
+ .lock = &clk_lock,
+- .hw.init = &(struct clk_init_data){
++ .hw.init = &(struct clk_init_data) {
+ .name = "cts_mclk_i958_sel",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+@@ -890,12 +890,13 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
+ .shift = 16,
+ .width = 8,
+ .lock = &clk_lock,
+- .hw.init = &(struct clk_init_data){
++ .flags = CLK_DIVIDER_ROUND_CLOSEST,
++ .hw.init = &(struct clk_init_data) {
+ .name = "cts_mclk_i958_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+ .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
++ .flags = CLK_SET_RATE_PARENT,
+ },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-gxbb-fix-meson-cts_amclk-divider-flags b/patches.drivers/clk-meson-gxbb-fix-meson-cts_amclk-divider-flags
new file mode 100644
index 0000000000..81647bf8eb
--- /dev/null
+++ b/patches.drivers/clk-meson-gxbb-fix-meson-cts_amclk-divider-flags
@@ -0,0 +1,43 @@
+From 004f6f462d4127350fce1a2822d00990baedf3a0 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 27 Jul 2017 15:09:39 +0200
+Subject: [PATCH] clk: meson: gxbb: fix meson cts_amclk divider flags
+Git-commit: 004f6f462d4127350fce1a2822d00990baedf3a0
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
+while it should have been in the divider flags
+
+Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/gxbb.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index 8409d86cda24..0bd028adadd5 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -845,13 +845,14 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
+ .shift = 0,
+ .width = 8,
+ },
++ .flags = CLK_DIVIDER_ROUND_CLOSEST,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "cts_amclk_div",
+ .ops = &meson_clk_audio_divider_ops,
+ .parent_names = (const char *[]){ "cts_amclk_sel" },
+ .num_parents = 1,
+- .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
++ .flags = CLK_SET_RATE_PARENT,
+ },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-gxbb-fix-wrong-clock-for-SARADC-SANA b/patches.drivers/clk-meson-gxbb-fix-wrong-clock-for-SARADC-SANA
new file mode 100644
index 0000000000..08619f110f
--- /dev/null
+++ b/patches.drivers/clk-meson-gxbb-fix-wrong-clock-for-SARADC-SANA
@@ -0,0 +1,53 @@
+From 75eccf5ed83250c0aeaeeb76f7288254ac0a87b4 Mon Sep 17 00:00:00 2001
+From: Yixun Lan <yixun.lan@amlogic.com>
+Date: Tue, 7 Nov 2017 22:12:23 +0800
+Subject: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
+Git-commit: 75eccf5ed83250c0aeaeeb76f7288254ac0a87b4
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+According to the datasheet, in Meson-GXBB/GXL series,
+The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
+while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
+
+Test passed at gxl-s905x-p212 board.
+
+The following published datasheets are wrong and should be updated
+[1] GXBB v1.1.4
+[2] GXL v0.3_20170314
+
+Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
+Tested-by: Xingyu Chen <xingyu.chen@amlogic.com>
+Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/gxbb.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index ae385310e980..2ac9f3fa9578 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -1386,7 +1386,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
+ static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
+ static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
+ static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
+-static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
++static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
+ static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
+ static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
+ static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
+@@ -1437,7 +1437,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
+ static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
+ static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
+ static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
+-static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
++static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
+ static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
+ static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
+ static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-meson8b-fix-protection-against-undefined-c b/patches.drivers/clk-meson-meson8b-fix-protection-against-undefined-c
new file mode 100644
index 0000000000..e732cedddf
--- /dev/null
+++ b/patches.drivers/clk-meson-meson8b-fix-protection-against-undefined-c
@@ -0,0 +1,39 @@
+From de2bc4178b8d475fb0bc06c280606fdf816a3f6c Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 27 Jul 2017 18:17:54 +0200
+Subject: [PATCH] clk: meson: meson8b: fix protection against undefined clks
+Git-commit: de2bc4178b8d475fb0bc06c280606fdf816a3f6c
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+meson8b clock driver gracefully handles case where the clkid is defined
+but the clock hw pointer is not provided, as long as it is not at the end
+of the hw_onecell_data array.
+
+This patch ensure that the last entries are defined as well to handle
+this particular case.
+
+Fixes: e92f7cca446e ("clk: meson8b: clean up fixed rate clocks")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/meson8b.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
+index bb3f1de876b1..7629aa09472a 100644
+--- a/drivers/clk/meson/meson8b.c
++++ b/drivers/clk/meson/meson8b.c
+@@ -585,6 +585,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
++ [CLK_NR_CLKS] = NULL,
+ },
+ .num = CLK_NR_CLKS,
+ };
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-mpll-fix-mpll0-fractional-part-ignored b/patches.drivers/clk-meson-mpll-fix-mpll0-fractional-part-ignored
new file mode 100644
index 0000000000..4f5937336a
--- /dev/null
+++ b/patches.drivers/clk-meson-mpll-fix-mpll0-fractional-part-ignored
@@ -0,0 +1,88 @@
+From 1f737ffa13efd3da2c703d45894ea234e9290c89 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 28 Jul 2017 18:32:28 +0200
+Subject: [PATCH] clk: meson: mpll: fix mpll0 fractional part ignored
+Git-commit: 1f737ffa13efd3da2c703d45894ea234e9290c89
+Patch-mainline: v4.13-rc4
+References: bsc#1051510
+
+mpll0 clock is special compared to the other mplls. It needs another
+bit (ssen) to be set to activate the fractional part the mpll divider
+
+Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/clk-mpll.c | 7 +++++++
+ drivers/clk/meson/clkc.h | 1 +
+ drivers/clk/meson/gxbb.c | 5 +++++
+ drivers/clk/meson/meson8b.c | 5 +++++
+ 4 files changed, 18 insertions(+)
+
+diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
+index 39eab69fe51a..44a5a535ca63 100644
+--- a/drivers/clk/meson/clk-mpll.c
++++ b/drivers/clk/meson/clk-mpll.c
+@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw,
+ reg = PARM_SET(p->width, p->shift, reg, 1);
+ writel(reg, mpll->base + p->reg_off);
+
++ p = &mpll->ssen;
++ if (p->width != 0) {
++ reg = readl(mpll->base + p->reg_off);
++ reg = PARM_SET(p->width, p->shift, reg, 1);
++ writel(reg, mpll->base + p->reg_off);
++ }
++
+ p = &mpll->n2;
+ reg = readl(mpll->base + p->reg_off);
+ reg = PARM_SET(p->width, p->shift, reg, n2);
+diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
+index d6feafe8bd6c..1629da9b4141 100644
+--- a/drivers/clk/meson/clkc.h
++++ b/drivers/clk/meson/clkc.h
+@@ -118,6 +118,7 @@ struct meson_clk_mpll {
+ struct parm sdm_en;
+ struct parm n2;
+ struct parm en;
++ struct parm ssen;
+ spinlock_t *lock;
+ };
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index a897ea45327c..a7ea5f3da89d 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = {
+ .shift = 14,
+ .width = 1,
+ },
++ .ssen = {
++ .reg_off = HHI_MPLL_CNTL,
++ .shift = 25,
++ .width = 1,
++ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
+index bb3f1de876b1..6ec512ad2598 100644
+--- a/drivers/clk/meson/meson8b.c
++++ b/drivers/clk/meson/meson8b.c
+@@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = {
+ .shift = 14,
+ .width = 1,
+ },
++ .ssen = {
++ .reg_off = HHI_MPLL_CNTL,
++ .shift = 25,
++ .width = 1,
++ },
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-mpll-use-64-bit-maths-in-params_from_rate b/patches.drivers/clk-meson-mpll-use-64-bit-maths-in-params_from_rate
new file mode 100644
index 0000000000..2ca1b5d2a3
--- /dev/null
+++ b/patches.drivers/clk-meson-mpll-use-64-bit-maths-in-params_from_rate
@@ -0,0 +1,48 @@
+From 86aacdca66774051cbc0958110a48074b57a060b Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 23 Dec 2017 22:38:32 +0100
+Subject: [PATCH] clk: meson: mpll: use 64-bit maths in params_from_rate
+Git-commit: 86aacdca66774051cbc0958110a48074b57a060b
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+"rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b
+SoCs if the "remainder" (after the division operation) is greater than
+262143Hz. This is likely to happen since the input clock for the MPLLs
+on Meson8 and Meson8b is "fixed_pll", which is running at a rate of
+2550MHz.
+
+One example where this was observed to be problematic was the Ethernet
+clock calculation (which takes MPLL2 as input). When requesting a rate
+of 125MHz there is a remainder of 2500000Hz.
+The resulting MPLL2 rate before this patch was 127488329Hz.
+The resulting MPLL2 rate after this patch is 124999103Hz.
+
+Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in
+rate_from_params") already fixed a similar issue in rate_from_params.
+
+Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/clk-mpll.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
+index 44a5a535ca63..5144360e2c80 100644
+--- a/drivers/clk/meson/clk-mpll.c
++++ b/drivers/clk/meson/clk-mpll.c
+@@ -98,7 +98,7 @@ static void params_from_rate(unsigned long requested_rate,
+ *sdm = SDM_DEN - 1;
+ } else {
+ *n2 = div;
+- *sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
++ *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
+ }
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-meson-remove-unnecessary-rounding-in-the-pll-clo b/patches.drivers/clk-meson-remove-unnecessary-rounding-in-the-pll-clo
new file mode 100644
index 0000000000..7847117f77
--- /dev/null
+++ b/patches.drivers/clk-meson-remove-unnecessary-rounding-in-the-pll-clo
@@ -0,0 +1,71 @@
+From 94aa8a41f1bc807db78567e7031d75998c166150 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 19 Jan 2018 16:55:23 +0100
+Subject: [PATCH] clk: meson: remove unnecessary rounding in the pll clock
+Git-commit: 94aa8a41f1bc807db78567e7031d75998c166150
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+The pll driver performs the rate calculation in Mhz, which adds an
+unnecessary rounding down to the Mhz of the rate. Use 64bits long
+integers to perform this calculation safely on meson8b and perform the
+calculation in Hz instead
+
+Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/meson/clk-pll.c | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
+index 2614341fc4ad..087dfc532ba8 100644
+--- a/drivers/clk/meson/clk-pll.c
++++ b/drivers/clk/meson/clk-pll.c
+@@ -34,6 +34,7 @@
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
++#include <linux/math64.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/slab.h>
+@@ -51,8 +52,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
+ {
+ struct meson_clk_pll *pll = to_meson_clk_pll(hw);
+ struct parm *p;
+- unsigned long parent_rate_mhz = parent_rate / 1000000;
+- unsigned long rate_mhz;
++ u64 rate;
+ u16 n, m, frac = 0, od, od2 = 0;
+ u32 reg;
+
+@@ -74,17 +74,18 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
+ od2 = PARM_GET(p->width, p->shift, reg);
+ }
+
++ rate = (u64)parent_rate * m;
++
+ p = &pll->frac;
+ if (p->width) {
+ reg = readl(pll->base + p->reg_off);
+ frac = PARM_GET(p->width, p->shift, reg);
+- rate_mhz = (parent_rate_mhz * m + \
+- (parent_rate_mhz * frac >> 12)) * 2 / n;
+- rate_mhz = rate_mhz >> od >> od2;
+- } else
+- rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
+
+- return rate_mhz * 1000000;
++ rate += mul_u64_u32_shr(parent_rate, frac, 12);
++ rate *= 2;
++ }
++
++ return div_u64(rate, n) >> od >> od2;
+ }
+
+ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND b/patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND
new file mode 100644
index 0000000000..79a3d6afc3
--- /dev/null
+++ b/patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND
@@ -0,0 +1,35 @@
+From 00c5a926af12a9f0236928dab3dc9faf621406a1 Mon Sep 17 00:00:00 2001
+From: Chris Packham <chris.packham@alliedtelesis.co.nz>
+Date: Thu, 24 May 2018 17:23:41 +1200
+Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND
+Git-commit: 00c5a926af12a9f0236928dab3dc9faf621406a1
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+The correct fieldbit value for the NAND PLL reload trigger is 27.
+
+Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
+Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/mvebu/clk-corediv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
+index 8491979f4096..68f05c53d40e 100644
+--- a/drivers/clk/mvebu/clk-corediv.c
++++ b/drivers/clk/mvebu/clk-corediv.c
+@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
+ };
+
+ static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
+- { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
++ { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
+ };
+
+ #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
+--
+2.18.0
+
diff --git a/patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency b/patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency
new file mode 100644
index 0000000000..df14f043a1
--- /dev/null
+++ b/patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency
@@ -0,0 +1,40 @@
+From c7d2a0eb6c028ba064bfe92d7667977418142c7c Mon Sep 17 00:00:00 2001
+From: Evan Green <evgreen@chromium.org>
+Date: Fri, 13 Apr 2018 13:33:36 -0700
+Subject: [PATCH] clk: qcom: Base rcg parent rate off plan frequency
+Git-commit: c7d2a0eb6c028ba064bfe92d7667977418142c7c
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+_freq_tbl_determine_rate uses the pre_div found in the clock plan
+multiplied by the requested rate from the caller to determine the
+best parent rate to set. If the requested rate is not exactly equal
+to the rate that was found in the clock plan, then using the requested
+rate in parent rate calculations is incorrect. For instance, if 150MHz
+was requested, but 200MHz was the match found, and that plan had a
+pre_div of 3, then the parent should be set to 600MHz, not 450MHz.
+
+Signed-off-by: Evan Green <evgreen@chromium.org>
+Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)")
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/qcom/clk-rcg2.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
+index bbeaf9c09dbb..ec6cee8ff1bc 100644
+--- a/drivers/clk/qcom/clk-rcg2.c
++++ b/drivers/clk/qcom/clk-rcg2.c
+@@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
+ clk_flags = clk_hw_get_flags(hw);
+ p = clk_hw_get_parent_by_index(hw, index);
+ if (clk_flags & CLK_SET_RATE_PARENT) {
++ rate = f->freq;
+ if (f->pre_div) {
+ rate /= 2;
+ rate *= f->pre_div + 1;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-qcom-clk-smd-rpm-Fix-the-reported-rate-of-branch b/patches.drivers/clk-qcom-clk-smd-rpm-Fix-the-reported-rate-of-branch
new file mode 100644
index 0000000000..cfcd6637dc
--- /dev/null
+++ b/patches.drivers/clk-qcom-clk-smd-rpm-Fix-the-reported-rate-of-branch
@@ -0,0 +1,42 @@
+From d515e027a9bcadbabfb95fa15fde94bd372d48bd Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Mon, 17 Jul 2017 18:35:42 +0300
+Subject: [PATCH] clk: qcom: clk-smd-rpm: Fix the reported rate of branches
+Git-commit: d515e027a9bcadbabfb95fa15fde94bd372d48bd
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+As there is no way to actually query the hardware for the current clock
+rate, now racalc_rate() just returns the last rate that was previously
+set. But if the rate was not set yet, we return the bogus rate of 1000Hz.
+
+The branch clocks have the same rate as their parent, so in this case we
+just need to remove recalc_rate ops and then the core framework will handle
+this automagically. The round_rate() is unused, so remove it as well.
+
+Reported-by: Archit Taneja <architt@codeaurora.org>
+Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks")
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/qcom/clk-smd-rpm.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
+index d990fe44aef3..cc03d5508627 100644
+--- a/drivers/clk/qcom/clk-smd-rpm.c
++++ b/drivers/clk/qcom/clk-smd-rpm.c
+@@ -412,8 +412,6 @@ static const struct clk_ops clk_smd_rpm_ops = {
+ static const struct clk_ops clk_smd_rpm_branch_ops = {
+ .prepare = clk_smd_rpm_prepare,
+ .unprepare = clk_smd_rpm_unprepare,
+- .round_rate = clk_smd_rpm_round_rate,
+- .recalc_rate = clk_smd_rpm_recalc_rate,
+ };
+
+ /* msm8916 */
+--
+2.18.0
+
diff --git a/patches.drivers/clk-qcom-common-fix-legacy-board-clock-registration b/patches.drivers/clk-qcom-common-fix-legacy-board-clock-registration
new file mode 100644
index 0000000000..5536ed7a74
--- /dev/null
+++ b/patches.drivers/clk-qcom-common-fix-legacy-board-clock-registration
@@ -0,0 +1,42 @@
+From 43a51019cc8ff1b1cd2ba72e86563beb40d356fc Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Sat, 11 Nov 2017 17:29:28 +0100
+Subject: [PATCH] clk: qcom: common: fix legacy board-clock registration
+Git-commit: 43a51019cc8ff1b1cd2ba72e86563beb40d356fc
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Make sure to search only the child nodes of "/clocks", rather than the
+whole device-tree depth-first starting at "/clocks" when determining
+whether to register a fixed clock in the legacy board-clock registration
+helper.
+
+Fixes: ee15faffef11 ("clk: qcom: common: Add API to register board clocks backwards compatibly")
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/qcom/common.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
+index b35564c0493f..b8064a336d46 100644
+--- a/drivers/clk/qcom/common.c
++++ b/drivers/clk/qcom/common.c
+@@ -133,8 +133,10 @@ static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
+ int ret;
+
+ clocks_node = of_find_node_by_path("/clocks");
+- if (clocks_node)
+- node = of_find_node_by_name(clocks_node, path);
++ if (clocks_node) {
++ node = of_get_child_by_name(clocks_node, path);
++ of_node_put(clocks_node);
++ }
+
+ if (!node) {
+ fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-qcom-msm8916-Fix-bimc-gpu-clock-ops b/patches.drivers/clk-qcom-msm8916-Fix-bimc-gpu-clock-ops
new file mode 100644
index 0000000000..37f05aa5eb
--- /dev/null
+++ b/patches.drivers/clk-qcom-msm8916-Fix-bimc-gpu-clock-ops
@@ -0,0 +1,41 @@
+From de2245540ed84c56ba3d71d1ce8e14fdaf332720 Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Fri, 18 Aug 2017 17:22:50 +0300
+Subject: [PATCH] clk: qcom: msm8916: Fix bimc gpu clock ops
+Git-commit: de2245540ed84c56ba3d71d1ce8e14fdaf332720
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2
+ops, which are for RCGs with child branches controlled by different
+CPUs.
+
+The result of the incorrect ops is that the GPU's PM runtime may leave
+this clock set at a very low rate. Fix this issue by using the correct
+rcg2 ops.
+
+Fixes: a2e8272f3f89 ("clk: qcom: Add MSM8916 gpu clocks")
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/qcom/gcc-msm8916.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
+index 2cfe7000fc60..3410ee68d4bc 100644
+--- a/drivers/clk/qcom/gcc-msm8916.c
++++ b/drivers/clk/qcom/gcc-msm8916.c
+@@ -1176,7 +1176,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
+ .parent_names = gcc_xo_gpll0_bimc,
+ .num_parents = 3,
+ .flags = CLK_GET_RATE_NOCACHE,
+- .ops = &clk_rcg2_shared_ops,
++ .ops = &clk_rcg2_ops,
+ },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-qcom-msm8916-fix-mnd_width-for-codec_digcodec b/patches.drivers/clk-qcom-msm8916-fix-mnd_width-for-codec_digcodec
new file mode 100644
index 0000000000..474b278266
--- /dev/null
+++ b/patches.drivers/clk-qcom-msm8916-fix-mnd_width-for-codec_digcodec
@@ -0,0 +1,35 @@
+From d8e488e8242ecf129eebc440c92d800a99ca109d Mon Sep 17 00:00:00 2001
+From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Date: Wed, 6 Dec 2017 12:11:38 +0000
+Subject: [PATCH] clk: qcom: msm8916: fix mnd_width for codec_digcodec
+Git-commit: d8e488e8242ecf129eebc440c92d800a99ca109d
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+This patch fixes missing mnd_width for codec_digital clk, this is now set to
+8 inline with datasheet.
+
+Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/qcom/gcc-msm8916.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
+index 506e0736bf92..d973aeaab943 100644
+--- a/drivers/clk/qcom/gcc-msm8916.c
++++ b/drivers/clk/qcom/gcc-msm8916.c
+@@ -1443,6 +1443,7 @@ static const struct freq_tbl ftbl_codec_clk[] = {
+
+ static struct clk_rcg2 codec_digcodec_clk_src = {
+ .cmd_rcgr = 0x1c09c,
++ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll1_emclk_sleep_map,
+ .freq_tbl = ftbl_codec_clk,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-renesas-div6-Document-fields-used-for-parent-sel b/patches.drivers/clk-renesas-div6-Document-fields-used-for-parent-sel
new file mode 100644
index 0000000000..0b1fe8bdcb
--- /dev/null
+++ b/patches.drivers/clk-renesas-div6-Document-fields-used-for-parent-sel
@@ -0,0 +1,37 @@
+From 2ebedd8d5ca8747fc7efd8a97129802bc6965468 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 21 Jun 2017 22:02:33 +0200
+Subject: [PATCH] clk: renesas: div6: Document fields used for parent selection
+Git-commit: 2ebedd8d5ca8747fc7efd8a97129802bc6965468
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Add the missing documentation for the fields in struct div6_clock
+related to parent selection for DIV6 clocks with selectable parents, as
+found in R/SH-Mobile SoCs.
+
+Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/clk-div6.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
+index 0627860233cb..3e0040c0ac87 100644
+--- a/drivers/clk/renesas/clk-div6.c
++++ b/drivers/clk/renesas/clk-div6.c
+@@ -29,6 +29,9 @@
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: IO-remapped register
+ * @div: divisor value (1-64)
++ * @src_shift: Shift to access the register bits to select the parent clock
++ * @src_width: Number of register bits to select the parent clock (may be 0)
++ * @parents: Array to map from valid parent clocks indices to hardware indices
+ */
+ struct div6_clock {
+ struct clk_hw hw;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-0 b/patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-0
new file mode 100644
index 0000000000..2218a68b92
--- /dev/null
+++ b/patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-0
@@ -0,0 +1,63 @@
+From 5ed793b3b29c064f0b84c19a94d4e17831cc1dc2 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 31 Mar 2017 17:44:05 +0200
+Subject: [PATCH] clk: renesas: r8a7745: Remove PLL configs for MD19=0
+Git-commit: 5ed793b3b29c064f0b84c19a94d4e17831cc1dc2
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
+Manual Rev.1.00, MD19=0 is a prohibited setting.
+
+Hence stop looking at MD19, and remove all PLL configurations for
+MD19=0.
+
+Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/r8a7745-cpg-mssr.c | 13 ++-----------
+ 1 file changed, 2 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+index 08db21cc6436..9e2360a8e14b 100644
+--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+@@ -190,31 +190,22 @@ static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+- * 0 0 0 15 x200/3 x208/2 x106
+ * 0 0 1 15 x200/3 x208/2 x88
+- * 0 1 0 20 x150/3 x156/2 x80
+ * 0 1 1 20 x150/3 x156/2 x66
+- * 1 0 0 26 / 2 x230/3 x240/2 x122
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+- * 1 1 0 30 / 2 x200/3 x208/2 x106
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
+ */
+-#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+- (((md) & BIT(13)) >> 12) | \
+- (((md) & BIT(19)) >> 19))
++#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
++ (((md) & BIT(13)) >> 13))
+
+ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
+- { 1, 208, 106, 200 },
+ { 1, 208, 88, 200 },
+- { 1, 156, 80, 150 },
+ { 1, 156, 66, 150 },
+- { 2, 240, 122, 230 },
+ { 2, 240, 102, 230 },
+- { 2, 208, 106, 200 },
+ { 2, 208, 88, 200 },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789- b/patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789-
new file mode 100644
index 0000000000..3db75f4b5f
--- /dev/null
+++ b/patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789-
@@ -0,0 +1,42 @@
+From b93e7eb5ed86983acece9aad8a1f82db1020d62b Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 29 Mar 2017 10:05:52 +0200
+Subject: [PATCH] clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
+Git-commit: b93e7eb5ed86983acece9aad8a1f82db1020d62b
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.
+
+Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/r8a7745-cpg-mssr.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+index 2f15ba786c3b..08db21cc6436 100644
+--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
+@@ -167,16 +167,12 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
+--
+2.18.0
+
diff --git a/patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent- b/patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent-
new file mode 100644
index 0000000000..e73050615e
--- /dev/null
+++ b/patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent-
@@ -0,0 +1,101 @@
+From c5c3bdaacebd42a96cca0bd67967ce3b28499efd Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 8 May 2017 11:43:49 +0200
+Subject: [PATCH] clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0
+Git-commit: c5c3bdaacebd42a96cca0bd67967ce3b28499efd
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual
+Rev. 0.53E.
+
+These have no user-visible effect, as the clock frequencies stay the
+same.
+
+Fixes: 5573d194128b4733 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/r8a7795-cpg-mssr.c | 39 +++++++++++++++++---------
+ 1 file changed, 26 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+index 5808803cec48..c091a8e024b8 100644
+--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
+@@ -166,7 +166,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
+ DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
+ DEF_MOD("thermal", 522, R8A7795_CLK_CP),
+- DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
++ DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
+ DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
+@@ -222,22 +222,22 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
+ DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
+ DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
+ DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
+- DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
+- DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
+- DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
+- DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
+- DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
+- DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
+- DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
+- DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
++ DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
++ DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
+- DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
+- DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
++ DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
++ DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
+- DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
+- DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
++ DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
++ DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
+@@ -350,6 +350,7 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
+ { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
+ { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
+ { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
++ { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
+ { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
+ { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
+ { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
+@@ -380,6 +381,18 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
+ { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
+ { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
+ { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
++ { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
++ { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
++ { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
++ { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
++ { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
++ { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
++ { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
++ { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
++ { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
++ { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
++ { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
++ { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
+ };
+
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-renesas-rcar-gen2-Fix-PLL0-on-R-Car-V2H-and-E2 b/patches.drivers/clk-renesas-rcar-gen2-Fix-PLL0-on-R-Car-V2H-and-E2
new file mode 100644
index 0000000000..b66c6e8b5c
--- /dev/null
+++ b/patches.drivers/clk-renesas-rcar-gen2-Fix-PLL0-on-R-Car-V2H-and-E2
@@ -0,0 +1,81 @@
+From b7c563c489e94417efbad68d057ea5d2030ae44c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Wed, 29 Mar 2017 17:22:44 +0200
+Subject: [PATCH] clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
+Git-commit: b7c563c489e94417efbad68d057ea5d2030ae44c
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
+multiplier (depending on mode pins) and divider.
+
+This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
+R-Car V2H and E2 from 1.5 GHz to 1 GHz.
+
+Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
+Clock Pulse Generator support core.
+
+Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
+Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/renesas/clk-rcar-gen2.c | 23 +++++++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
+index f39519edc645..51a2479ed5d7 100644
+--- a/drivers/clk/renesas/clk-rcar-gen2.c
++++ b/drivers/clk/renesas/clk-rcar-gen2.c
+@@ -272,11 +272,14 @@ struct cpg_pll_config {
+ unsigned int extal_div;
+ unsigned int pll1_mult;
+ unsigned int pll3_mult;
++ unsigned int pll0_mult; /* For R-Car V2H and E2 only */
+ };
+
+ static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
+- { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
+- { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
++ { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
++ { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
++ { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
++ { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
+ };
+
+ /* SDHI divisors */
+@@ -298,6 +301,12 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
+
+ static u32 cpg_mode __initdata;
+
++static const char * const pll0_mult_match[] = {
++ "renesas,r8a7792-cpg-clocks",
++ "renesas,r8a7794-cpg-clocks",
++ NULL
++};
++
+ static struct clk * __init
+ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
+ const struct cpg_pll_config *config,
+@@ -318,9 +327,15 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
+ * clock implementation and we currently have no need to change
+ * the multiplier value.
+ */
+- u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
++ if (of_device_compatible_match(np, pll0_mult_match)) {
++ /* R-Car V2H and E2 do not have PLL0CR */
++ mult = config->pll0_mult;
++ div = 3;
++ } else {
++ u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
++ mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
++ }
+ parent_name = "main";
+- mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
+ } else if (!strcmp(name, "pll1")) {
+ parent_name = "main";
+ mult = config->pll1_mult / 2;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock- b/patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
new file mode 100644
index 0000000000..0548a3254d
--- /dev/null
+++ b/patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
@@ -0,0 +1,41 @@
+From 4b0556a441dd37e598887215bc89b49a6ef525b3 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 21 Mar 2018 10:39:19 +0800
+Subject: [PATCH] clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
+Git-commit: 4b0556a441dd37e598887215bc89b49a6ef525b3
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
+if clock rate is zero") catches one gremlin again for clk-rk3228.c
+that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
+sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
+manual with the card clock having the 0 while the hclk is named
+without appended 0. So standardize one one format to prevent
+confusion, as there also is only one (non-sdio) mmc controller on
+the soc.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/rockchip/clk-rk3228.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 11e7f2d1c054..7af48184b022 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -387,7 +387,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
+ RK2928_CLKGATE_CON(2), 15, GFLAGS),
+
+- COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
++ COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
+ RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK2928_CLKGATE_CON(2), 11, GFLAGS),
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock- b/patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
new file mode 100644
index 0000000000..06cfa3fe32
--- /dev/null
+++ b/patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
@@ -0,0 +1,68 @@
+From 4bf59902b50012b1dddeeaa23b217d9c4956cdda Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Mon, 5 Mar 2018 11:25:58 +0800
+Subject: [PATCH] clk: rockchip: Prevent calculating mmc phase if clock rate is zero
+Git-commit: 4bf59902b50012b1dddeeaa23b217d9c4956cdda
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+The MMC sample and drv clock for rockchip platforms are derived from
+the bus clock output to the MMC/SDIO card. So it should never happens
+that the clk rate is zero given it should inherits the clock rate from
+its parent. If something goes wrong and makes the clock rate to be zero,
+the calculation would be wrong but may still make the mmc tuning process
+work luckily. However it makes people harder to debug when the following
+data transfer is unstable.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/rockchip/clk-mmc-phase.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
+index 077fcdc7908b..fe7d9ed1d436 100644
+--- a/drivers/clk/rockchip/clk-mmc-phase.c
++++ b/drivers/clk/rockchip/clk-mmc-phase.c
+@@ -58,6 +58,12 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
+ u16 degrees;
+ u32 delay_num = 0;
+
++ /* See the comment for rockchip_mmc_set_phase below */
++ if (!rate) {
++ pr_err("%s: invalid clk rate\n", __func__);
++ return -EINVAL;
++ }
++
+ raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
+
+ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+@@ -84,6 +90,23 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
+ u32 raw_value;
+ u32 delay;
+
++ /*
++ * The below calculation is based on the output clock from
++ * MMC host to the card, which expects the phase clock inherits
++ * the clock rate from its parent, namely the output clock
++ * provider of MMC host. However, things may go wrong if
++ * (1) It is orphan.
++ * (2) It is assigned to the wrong parent.
++ *
++ * This check help debug the case (1), which seems to be the
++ * most likely problem we often face and which makes it difficult
++ * for people to debug unstable mmc tuning results.
++ */
++ if (!rate) {
++ pr_err("%s: invalid clk rate\n", __func__);
++ return -EINVAL;
++ }
++
+ nineties = degrees / 90;
+ remainder = (degrees % 90);
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-Fix-m2m-scaler-clock-on-Exynos542x b/patches.drivers/clk-samsung-Fix-m2m-scaler-clock-on-Exynos542x
new file mode 100644
index 0000000000..2473589b4f
--- /dev/null
+++ b/patches.drivers/clk-samsung-Fix-m2m-scaler-clock-on-Exynos542x
@@ -0,0 +1,39 @@
+From c07c1a0f68d0f2f7ca9aff924e2772526027b019 Mon Sep 17 00:00:00 2001
+From: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+Date: Fri, 29 Sep 2017 09:32:53 +0200
+Subject: [PATCH] clk: samsung: Fix m2m scaler clock on Exynos542x
+Git-commit: c07c1a0f68d0f2f7ca9aff924e2772526027b019
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The TOP "aclk400_mscl" clock should be kept enabled all the time
+to allow proper access to power management control for MSC power
+domain and devices that are a part of it. This change is required
+for the scaler to work properly after domain power on/off sequence.
+
+Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical")
+Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos5420.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
+index 25601967d1cd..038701a2af4c 100644
+--- a/drivers/clk/samsung/clk-exynos5420.c
++++ b/drivers/clk/samsung/clk-exynos5420.c
+@@ -998,7 +998,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
+ GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
+ GATE_BUS_TOP, 16, 0, 0),
+ GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
+- GATE_BUS_TOP, 17, 0, 0),
++ GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
+ GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
+ GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
+ GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-exynos3250-Fix-PLL-rates b/patches.drivers/clk-samsung-exynos3250-Fix-PLL-rates
new file mode 100644
index 0000000000..207ddcd14a
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos3250-Fix-PLL-rates
@@ -0,0 +1,59 @@
+From a8321e7887410a2b2e80ab89d1ef7b30562658ea Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:48 +0100
+Subject: [PATCH] clk: samsung: exynos3250: Fix PLL rates
+Git-commit: a8321e7887410a2b2e80ab89d1ef7b30562658ea
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated
+from PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+In this patch an erroneous P value for 74176002 output frequency is also
+corrected.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos3250.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
+index 1b81e283f605..ed36728424a2 100644
+--- a/drivers/clk/samsung/clk-exynos3250.c
++++ b/drivers/clk/samsung/clk-exynos3250.c
+@@ -698,7 +698,7 @@ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst =
+ PLL_36XX_RATE(144000000, 96, 2, 3, 0),
+ PLL_36XX_RATE( 96000000, 128, 2, 4, 0),
+ PLL_36XX_RATE( 84000000, 112, 2, 4, 0),
+- PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
++ PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),
+ PLL_36XX_RATE( 73728000, 98, 2, 4, 19923),
+ PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
+ PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
+@@ -734,7 +734,7 @@ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst =
+ PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
+ PLL_36XX_RATE(108000000, 144, 2, 4, 0),
+ PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
+- PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
++ PLL_36XX_RATE( 74176002, 98, 2, 4, 59070),
+ PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
+ PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
+ { /* sentinel */ }
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-exynos5250-Add-missing-clocks-for-FIMC-L b/patches.drivers/clk-samsung-exynos5250-Add-missing-clocks-for-FIMC-L
new file mode 100644
index 0000000000..8bee0cefd6
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos5250-Add-missing-clocks-for-FIMC-L
@@ -0,0 +1,51 @@
+From 5b23fceec1ff94305c5d1accde018cae27448005 Mon Sep 17 00:00:00 2001
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Tue, 13 Mar 2018 11:46:12 +0100
+Subject: [PATCH] clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
+Git-commit: 5b23fceec1ff94305c5d1accde018cae27448005
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+FIMC LITE SYSMMU devices are defined in exynos5250.dtsi, but clocks for
+them are not instantiated by Exynos5250 clock provider driver. Add needed
+definitions for those clocks to fix IOMMU probe failure:
+
+Error: could not get clock /soc/sysmmu@13c40000:sysmmu(0)
+exynos-sysmmu 13c40000.sysmmu: Failed to get device clock(s)!
+Exynos-sysmmu: probe of 13c40000.sysmmu failed with error -38
+Error: could not get clock /soc/sysmmu@13c50000:sysmmu(0)
+exynos-sysmmu 13c50000.sysmmu: Failed to get device clock(s)!
+Exynos-sysmmu: probe of 13c50000.sysmmu failed with error -38
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Fixes: bfed1074f213 ("clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks")
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos5250.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/clk/samsung/clk-exynos5250.c
++++ b/drivers/clk/samsung/clk-exynos5250.c
+@@ -560,6 +560,8 @@ static const struct samsung_gate_clock e
+ 0),
+ GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
+ 0),
++ GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
++ GATE_IP_GSCL, 4, 0, 0),
+ GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
+ GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
+ GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
+@@ -570,6 +572,10 @@ static const struct samsung_gate_clock e
+ GATE_IP_GSCL, 9, 0, 0),
+ GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
+ GATE_IP_GSCL, 10, 0, 0),
++ GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
++ GATE_IP_GSCL, 11, 0, 0),
++ GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
++ GATE_IP_GSCL, 12, 0, 0),
+
+ GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
+ 0),
diff --git a/patches.drivers/clk-samsung-exynos5250-Fix-PLL-rates b/patches.drivers/clk-samsung-exynos5250-Fix-PLL-rates
new file mode 100644
index 0000000000..1927604836
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos5250-Fix-PLL-rates
@@ -0,0 +1,56 @@
+From 2ac051eeabaa411ef89ae7cd5bb8e60cb41ad780 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:49 +0100
+Subject: [PATCH] clk: samsung: exynos5250: Fix PLL rates
+Git-commit: 2ac051eeabaa411ef89ae7cd5bb8e60cb41ad780
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated
+from PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
+index 9b073c98a891..923c608b1b95 100644
+--- a/drivers/clk/samsung/clk-exynos5250.c
++++ b/drivers/clk/samsung/clk-exynos5250.c
+@@ -711,13 +711,13 @@ static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(192000000, 64, 2, 2, 0),
+- PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
++ PLL_36XX_RATE(180633605, 90, 3, 2, 20762),
+ PLL_36XX_RATE(180000000, 90, 3, 2, 0),
+ PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
+- PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
++ PLL_36XX_RATE(67737602, 90, 2, 4, 20762),
+ PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
+- PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
+- PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
++ PLL_36XX_RATE(45158401, 90, 3, 4, 20762),
++ PLL_36XX_RATE(32768001, 131, 3, 5, 4719),
+ { },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-exynos5260-Fix-PLL-rates b/patches.drivers/clk-samsung-exynos5260-Fix-PLL-rates
new file mode 100644
index 0000000000..1dea622a77
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos5260-Fix-PLL-rates
@@ -0,0 +1,47 @@
+From cdb68fbd4e7962be742c4f29475220c5bf28d8a5 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:50 +0100
+Subject: [PATCH] clk: samsung: exynos5260: Fix PLL rates
+Git-commit: cdb68fbd4e7962be742c4f29475220c5bf28d8a5
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated from
+the PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos5260.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
+index fd1d9bfc151b..8eae1752d700 100644
+--- a/drivers/clk/samsung/clk-exynos5260.c
++++ b/drivers/clk/samsung/clk-exynos5260.c
+@@ -65,7 +65,7 @@ static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
+ PLL_36XX_RATE(480000000, 160, 2, 2, 0),
+ PLL_36XX_RATE(432000000, 144, 2, 2, 0),
+ PLL_36XX_RATE(400000000, 200, 3, 2, 0),
+- PLL_36XX_RATE(394073130, 459, 7, 2, 49282),
++ PLL_36XX_RATE(394073128, 459, 7, 2, 49282),
+ PLL_36XX_RATE(333000000, 111, 2, 2, 0),
+ PLL_36XX_RATE(300000000, 100, 2, 2, 0),
+ PLL_36XX_RATE(266000000, 266, 3, 3, 0),
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-exynos5433-Fix-PLL-rates b/patches.drivers/clk-samsung-exynos5433-Fix-PLL-rates
new file mode 100644
index 0000000000..80fbfd38b0
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos5433-Fix-PLL-rates
@@ -0,0 +1,60 @@
+From ab0447845cffc0fd752df2ccd6b4e34006000ce4 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:51 +0100
+Subject: [PATCH] clk: samsung: exynos5433: Fix PLL rates
+Git-commit: ab0447845cffc0fd752df2ccd6b4e34006000ce4
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated from
+the PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos5433.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/samsung/clk-exynos5433.c
++++ b/drivers/clk/samsung/clk-exynos5433.c
+@@ -725,7 +725,7 @@ static const struct samsung_pll_rate_tab
+ PLL_35XX_RATE(800000000U, 400, 6, 1),
+ PLL_35XX_RATE(733000000U, 733, 12, 1),
+ PLL_35XX_RATE(700000000U, 175, 3, 1),
+- PLL_35XX_RATE(667000000U, 222, 4, 1),
++ PLL_35XX_RATE(666000000U, 222, 4, 1),
+ PLL_35XX_RATE(633000000U, 211, 4, 1),
+ PLL_35XX_RATE(600000000U, 500, 5, 2),
+ PLL_35XX_RATE(552000000U, 460, 5, 2),
+@@ -753,12 +753,12 @@ static const struct samsung_pll_rate_tab
+ /* AUD_PLL */
+ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
+ PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
+- PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
++ PLL_36XX_RATE(393216003U, 197, 3, 2, -25690),
+ PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
+- PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
+- PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
+- PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
+- PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
++ PLL_36XX_RATE(368639991U, 246, 4, 2, -15729),
++ PLL_36XX_RATE(361507202U, 181, 3, 2, -16148),
++ PLL_36XX_RATE(338687988U, 113, 2, 2, -6816),
++ PLL_36XX_RATE(294912002U, 98, 1, 3, 19923),
+ PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
+ PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
+ { /* sentinel */ }
diff --git a/patches.drivers/clk-samsung-exynos7-Fix-PLL-rates b/patches.drivers/clk-samsung-exynos7-Fix-PLL-rates
new file mode 100644
index 0000000000..d255d36abb
--- /dev/null
+++ b/patches.drivers/clk-samsung-exynos7-Fix-PLL-rates
@@ -0,0 +1,47 @@
+From 7e4db0c2836e892766565965207eee051c8037b9 Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:52 +0100
+Subject: [PATCH] clk: samsung: exynos7: Fix PLL rates
+Git-commit: 7e4db0c2836e892766565965207eee051c8037b9
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated from
+the PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-exynos7.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
+index 5931a4140c3d..bbfa57b4e017 100644
+--- a/drivers/clk/samsung/clk-exynos7.c
++++ b/drivers/clk/samsung/clk-exynos7.c
+@@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = {
+ };
+
+ static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
+- PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
++ PLL_36XX_RATE(491519897, 20, 1, 0, 31457),
+ {},
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-samsung-s3c2410-Fix-PLL-rates b/patches.drivers/clk-samsung-s3c2410-Fix-PLL-rates
new file mode 100644
index 0000000000..96325d9cd3
--- /dev/null
+++ b/patches.drivers/clk-samsung-s3c2410-Fix-PLL-rates
@@ -0,0 +1,73 @@
+From 179db533c08431f509a3823077549773d519358b Mon Sep 17 00:00:00 2001
+From: Andrzej Hajda <a.hajda@samsung.com>
+Date: Fri, 16 Feb 2018 15:57:53 +0100
+Subject: [PATCH] clk: samsung: s3c2410: Fix PLL rates
+Git-commit: 179db533c08431f509a3823077549773d519358b
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Rates declared in PLL rate tables should match exactly rates calculated from
+the PLL coefficients. If that is not the case, rate of the PLL's child clock
+might be set not as expected. For instance, if in the PLL rates table we have
+a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
+callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
+will return 393216003. If we now attempt to set rate of a PLL's child divider
+clock to 393216000/2 its rate will be 131072001, rather than 196608000.
+That is, the divider will be set to 3 instead of 2, because 393216003/2 is
+greater than 196608000.
+
+To fix this issue declared rates are changed to exactly match rates generated
+by the PLL, as calculated from the P, M, S, K coefficients.
+
+Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/samsung/clk-s3c2410.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
+index e0650c33863b..d8e58a659467 100644
+--- a/drivers/clk/samsung/clk-s3c2410.c
++++ b/drivers/clk/samsung/clk-s3c2410.c
+@@ -168,7 +168,7 @@ static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
+ PLL_35XX_RATE(226000000, 105, 1, 1),
+ PLL_35XX_RATE(210000000, 132, 2, 1),
+ /* 2410 common */
+- PLL_35XX_RATE(203000000, 161, 3, 1),
++ PLL_35XX_RATE(202800000, 161, 3, 1),
+ PLL_35XX_RATE(192000000, 88, 1, 1),
+ PLL_35XX_RATE(186000000, 85, 1, 1),
+ PLL_35XX_RATE(180000000, 82, 1, 1),
+@@ -178,18 +178,18 @@ static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
+ PLL_35XX_RATE(147000000, 90, 2, 1),
+ PLL_35XX_RATE(135000000, 82, 2, 1),
+ PLL_35XX_RATE(124000000, 116, 1, 2),
+- PLL_35XX_RATE(118000000, 150, 2, 2),
++ PLL_35XX_RATE(118500000, 150, 2, 2),
+ PLL_35XX_RATE(113000000, 105, 1, 2),
+- PLL_35XX_RATE(101000000, 127, 2, 2),
++ PLL_35XX_RATE(101250000, 127, 2, 2),
+ PLL_35XX_RATE(90000000, 112, 2, 2),
+- PLL_35XX_RATE(85000000, 105, 2, 2),
++ PLL_35XX_RATE(84750000, 105, 2, 2),
+ PLL_35XX_RATE(79000000, 71, 1, 2),
+- PLL_35XX_RATE(68000000, 82, 2, 2),
+- PLL_35XX_RATE(56000000, 142, 2, 3),
++ PLL_35XX_RATE(67500000, 82, 2, 2),
++ PLL_35XX_RATE(56250000, 142, 2, 3),
+ PLL_35XX_RATE(48000000, 120, 2, 3),
+- PLL_35XX_RATE(51000000, 161, 3, 3),
++ PLL_35XX_RATE(50700000, 161, 3, 3),
+ PLL_35XX_RATE(45000000, 82, 1, 3),
+- PLL_35XX_RATE(34000000, 82, 2, 3),
++ PLL_35XX_RATE(33750000, 82, 2, 3),
+ { /* sentinel */ },
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-scpi-error-when-clock-fails-to-register b/patches.drivers/clk-scpi-error-when-clock-fails-to-register
new file mode 100644
index 0000000000..8c92717281
--- /dev/null
+++ b/patches.drivers/clk-scpi-error-when-clock-fails-to-register
@@ -0,0 +1,50 @@
+From 2b286b09a048df80fd5f7dfc5057c2837679a1ab Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Wed, 28 Jun 2017 15:53:45 +0200
+Subject: [PATCH] clk: scpi: error when clock fails to register
+Git-commit: 2b286b09a048df80fd5f7dfc5057c2837679a1ab
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+Current implementation of scpi_clk_add just print a warning when clock
+fails to register but then keep going as if nothing happened. The
+provider is then registered with bogus data.
+
+This may latter lead to an Oops in __clk_create_clk when
+hlist_add_head(&clk->clks_node, &hw->core->clks) is called.
+
+This patch fixes the issue and errors if a clock fails to register.
+
+Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-scpi.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
+index 8ad458b5ad6e..25854722810e 100644
+--- a/drivers/clk/clk-scpi.c
++++ b/drivers/clk/clk-scpi.c
+@@ -245,10 +245,12 @@ static int scpi_clk_add(struct device *dev, struct device_node *np,
+ sclk->id = val;
+
+ err = scpi_clk_ops_init(dev, match, sclk, name);
+- if (err)
++ if (err) {
+ dev_err(dev, "failed to register clock '%s'\n", name);
+- else
+- dev_dbg(dev, "Registered clock '%s'\n", name);
++ return err;
++ }
++
++ dev_dbg(dev, "Registered clock '%s'\n", name);
+ clk_data->clk[idx] = sclk;
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-scpi-fix-return-type-of-__scpi_dvfs_round_rate b/patches.drivers/clk-scpi-fix-return-type-of-__scpi_dvfs_round_rate
new file mode 100644
index 0000000000..83a1843a25
--- /dev/null
+++ b/patches.drivers/clk-scpi-fix-return-type-of-__scpi_dvfs_round_rate
@@ -0,0 +1,51 @@
+From 7374aec95636ca39409545eba4ef5ff3125c2346 Mon Sep 17 00:00:00 2001
+From: Sudeep Holla <sudeep.holla@arm.com>
+Date: Thu, 18 May 2017 17:19:28 +0100
+Subject: [PATCH] clk: scpi: fix return type of __scpi_dvfs_round_rate
+Git-commit: 7374aec95636ca39409545eba4ef5ff3125c2346
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+The frequencies above the maximum value of signed integer(i.e. 2^31 -1)
+will overflow with the current code.
+
+This patch fixes the return type of __scpi_dvfs_round_rate from 'int'
+to 'unsigned long'.
+
+Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)")
+Cc: Michael Turquette <mturquette@baylibre.com>
+Cc: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-scpi.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
+index 96d37175d0ad..8ad458b5ad6e 100644
+--- a/drivers/clk/clk-scpi.c
++++ b/drivers/clk/clk-scpi.c
+@@ -71,15 +71,15 @@ static const struct clk_ops scpi_clk_ops = {
+ };
+
+ /* find closest match to given frequency in OPP table */
+-static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
++static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
+ {
+ int idx;
+- u32 fmin = 0, fmax = ~0, ftmp;
++ unsigned long fmin = 0, fmax = ~0, ftmp;
+ const struct scpi_opp *opp = clk->info->opps;
+
+ for (idx = 0; idx < clk->info->count; idx++, opp++) {
+ ftmp = opp->freq;
+- if (ftmp >= (u32)rate) {
++ if (ftmp >= rate) {
+ if (ftmp <= fmax)
+ fmax = ftmp;
+ break;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-si5351-Rename-internal-plls-to-avoid-name-collis b/patches.drivers/clk-si5351-Rename-internal-plls-to-avoid-name-collis
new file mode 100644
index 0000000000..52173c242b
--- /dev/null
+++ b/patches.drivers/clk-si5351-Rename-internal-plls-to-avoid-name-collis
@@ -0,0 +1,40 @@
+From cdba9a4fb0b53703959ac861e415816cb61aded4 Mon Sep 17 00:00:00 2001
+From: Sergej Sawazki <sergej@taudac.com>
+Date: Tue, 25 Jul 2017 23:21:02 +0200
+Subject: [PATCH] clk: si5351: Rename internal plls to avoid name collisions
+Git-commit: cdba9a4fb0b53703959ac861e415816cb61aded4
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+This drivers probe fails due to a clock name collision if a clock named
+'plla' or 'pllb' is already registered when registering this drivers
+internal plls.
+
+Fix it by renaming internal plls to avoid name collisions.
+
+Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Cc: Rabeeh Khoury <rabeeh@solid-run.com>
+Signed-off-by: Sergej Sawazki <sergej@taudac.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-si5351.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
+index 79b770fabe05..841d9fe9bfea 100644
+--- a/drivers/clk/clk-si5351.c
++++ b/drivers/clk/clk-si5351.c
+@@ -72,7 +72,7 @@ static const char * const si5351_input_names[] = {
+ "xtal", "clkin"
+ };
+ static const char * const si5351_pll_names[] = {
+- "plla", "pllb", "vxco"
++ "si5351_plla", "si5351_pllb", "si5351_vxco"
+ };
+ static const char * const si5351_msynth_names[] = {
+ "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
+--
+2.18.0
+
diff --git a/patches.drivers/clk-si5351-fix-PLL-reset b/patches.drivers/clk-si5351-fix-PLL-reset
new file mode 100644
index 0000000000..b661cd96d3
--- /dev/null
+++ b/patches.drivers/clk-si5351-fix-PLL-reset
@@ -0,0 +1,67 @@
+From 73c950da6ec523136090d6d4d6907a6ea8e8b67b Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@armlinux.org.uk>
+Date: Wed, 26 Jul 2017 09:18:08 +0100
+Subject: [PATCH] clk: si5351: fix PLL reset
+Git-commit: 73c950da6ec523136090d6d4d6907a6ea8e8b67b
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Changing the audio sample rate on the SolidRun Cubox disrupts the video
+output. The Si5351 provides both the video clock (using PLLA on output
+0) and the audio clock (using PLLB on output 2).
+
+When the rate of clock output 2 is changed, it reconfigures PLLB, which
+results in both PLLA and PLLB being reset. The reset of PLLA causes
+clock output 0 to be disrupted, thereby causing a loss of sync by the
+attached display device.
+
+Hence, each time the audio sample rate changes (eg, when a video player
+starts up, or when starting to play music) the video display momentarily
+blanks while the Si5351 settles down. Prior to the commit below, this
+behaviour did not happen.
+
+Fix this by only resetting only the PLL which has been changed.
+
+Fixes: 6dc669a22c77 ("clk: si5351: Add PLL soft reset")
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/clk-si5351.c | 12 +++++-------
+ 1 file changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
+index 2492442eea77..20d90769cced 100644
+--- a/drivers/clk/clk-si5351.c
++++ b/drivers/clk/clk-si5351.c
+@@ -519,6 +519,11 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ SI5351_CLK_INTEGER_MODE,
+ (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
+
++ /* Do a pll soft reset on the affected pll */
++ si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
++ hwdata->num == 0 ? SI5351_PLL_RESET_A :
++ SI5351_PLL_RESET_B);
++
+ dev_dbg(&hwdata->drvdata->client->dev,
+ "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
+ __func__, clk_hw_get_name(hw),
+@@ -1091,13 +1096,6 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
+ si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
+ SI5351_CLK_POWERDOWN, 0);
+
+- /*
+- * Do a pll soft reset on both plls, needed in some cases to get
+- * all outputs running.
+- */
+- si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
+- SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
+-
+ dev_dbg(&hwdata->drvdata->client->dev,
+ "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
+ __func__, clk_hw_get_name(hw), (1 << rdiv),
+--
+2.18.0
+
diff --git a/patches.drivers/clk-socfpga-Fix-the-smplsel-on-Arria10-and-Stratix10 b/patches.drivers/clk-socfpga-Fix-the-smplsel-on-Arria10-and-Stratix10
new file mode 100644
index 0000000000..2ede1b6217
--- /dev/null
+++ b/patches.drivers/clk-socfpga-Fix-the-smplsel-on-Arria10-and-Stratix10
@@ -0,0 +1,54 @@
+From b7f8101d6e75fefd22c39624a30c9ed3d7a72463 Mon Sep 17 00:00:00 2001
+From: Dinh Nguyen <dinguyen@kernel.org>
+Date: Thu, 8 Jun 2017 09:18:39 -0500
+Subject: [PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10
+Git-commit: b7f8101d6e75fefd22c39624a30c9ed3d7a72463
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
+offset by 1 additional bit.
+
+Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
+Stratix10 platforms.
+
+Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/socfpga/clk-gate-a10.c | 2 +-
+ drivers/clk/socfpga/clk.h | 3 +++
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
+index c2d572748167..36376c542055 100644
+--- a/drivers/clk/socfpga/clk-gate-a10.c
++++ b/drivers/clk/socfpga/clk-gate-a10.c
+@@ -86,7 +86,7 @@ static int socfpga_clk_prepare(struct clk_hw *hwclk)
+ }
+ }
+
+- hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
++ hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
+ if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
+ regmap_write(socfpgaclk->sys_mgr_base_addr,
+ SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
+diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
+index 814c7247bf73..9cf1230115b1 100644
+--- a/drivers/clk/socfpga/clk.h
++++ b/drivers/clk/socfpga/clk.h
+@@ -32,6 +32,9 @@
+ #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
+
++#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
++ ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
++
+ extern void __iomem *clk_mgr_base_addr;
+ extern void __iomem *clk_mgr_a10_base_addr;
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-fix-build-warning b/patches.drivers/clk-sunxi-fix-build-warning
new file mode 100644
index 0000000000..50c8aaf8c8
--- /dev/null
+++ b/patches.drivers/clk-sunxi-fix-build-warning
@@ -0,0 +1,43 @@
+From 02e0114ae1eb776b22f0744762fb0137208c4850 Mon Sep 17 00:00:00 2001
+From: Corentin LABBE <clabbe.montjoie@gmail.com>
+Date: Tue, 24 Oct 2017 19:06:16 +0200
+Subject: [PATCH] clk: sunxi: fix build warning
+Git-commit: 02e0114ae1eb776b22f0744762fb0137208c4850
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+This patch fix the following build warning:
+drivers/clk/sunxi/clk-factors.c:279:14: warning: variable 'name' set but not used [-Wunused-but-set-variable]
+
+Fixes: 4cbeaebb8af1 ("clk: sunxi: factors: Add unregister function")
+
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi/clk-factors.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
+index dfe5e3e32d28..856fef65433b 100644
+--- a/drivers/clk/sunxi/clk-factors.c
++++ b/drivers/clk/sunxi/clk-factors.c
+@@ -276,13 +276,11 @@ void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
+ {
+ struct clk_hw *hw = __clk_get_hw(clk);
+ struct clk_factors *factors;
+- const char *name;
+
+ if (!hw)
+ return;
+
+ factors = to_clk_factors(hw);
+- name = clk_hw_get_name(hw);
+
+ of_clk_del_provider(node);
+ /* TODO: The composite clock stuff will leak a bit here. */
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-fix-uninitialized-access b/patches.drivers/clk-sunxi-fix-uninitialized-access
new file mode 100644
index 0000000000..b74f27b8cb
--- /dev/null
+++ b/patches.drivers/clk-sunxi-fix-uninitialized-access
@@ -0,0 +1,46 @@
+From 4e903450bcb9a6bc90733b981d7cb8b3c4996a0e Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 23 Aug 2017 16:39:27 +0200
+Subject: [PATCH] clk: sunxi: fix uninitialized access
+Git-commit: 4e903450bcb9a6bc90733b981d7cb8b3c4996a0e
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+gcc-8 reports an uninitialized variable access in a code path
+that we would see with incorrect DTB input:
+
+Drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init':
+drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+
+This works around by skipping invalid input and printing a warning
+instead if it ever happens. The problem was apparently part of the
+initiali driver submission, but older compilers don't notice it.
+
+Fixes: ab6e23a4e388 ("clk: sunxi: Add H3 clocks support")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi/clk-sun8i-bus-gates.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+index 63fdb790df29..bee305bdddbe 100644
+--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
++++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+@@ -78,6 +78,10 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
+ clk_parent = APB1;
+ else if (index >= 96 && index <= 127)
+ clk_parent = APB2;
++ else {
++ WARN_ON(true);
++ continue;
++ }
+
+ clk_reg = reg + 4 * (index / 32);
+ clk_bit = index % 32;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-Fix-fractional-mode-for-N-M-clocks b/patches.drivers/clk-sunxi-ng-Fix-fractional-mode-for-N-M-clocks
new file mode 100644
index 0000000000..10f10fe770
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-Fix-fractional-mode-for-N-M-clocks
@@ -0,0 +1,57 @@
+From b64dfec01050a010fa764dae3746353bdbdecfe1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jernej=20=C5=A0krabec?= <jernej.skrabec@siol.net>
+Date: Sun, 30 Jul 2017 18:41:47 +0200
+Subject: [PATCH] clk: sunxi-ng: Fix fractional mode for N-M clocks
+Git-commit: b64dfec01050a010fa764dae3746353bdbdecfe1
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+N-M factor clock driver is missing a call to ccu_frac_helper_enable()
+when fractional mode is used. Additionally, most SoCs require that M
+factor must be set to 0 when fractional mode is used.
+
+Without this patch, clock keeps the old value and clk_set_rate() returns
+without error.
+
+Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
+Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu_nm.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
+index 5e5e90a4a50c..c6ba866b99d3 100644
+--- a/drivers/clk/sunxi-ng/ccu_nm.c
++++ b/drivers/clk/sunxi-ng/ccu_nm.c
+@@ -117,10 +117,22 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long flags;
+ u32 reg;
+
+- if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
++ if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
++ spin_lock_irqsave(nm->common.lock, flags);
++
++ /* most SoCs require M to be 0 if fractional mode is used */
++ reg = readl(nm->common.base + nm->common.reg);
++ reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
++ writel(reg, nm->common.base + nm->common.reg);
++
++ spin_unlock_irqrestore(nm->common.lock, flags);
++
++ ccu_frac_helper_enable(&nm->common, &nm->frac);
++
+ return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
+- else
++ } else {
+ ccu_frac_helper_disable(&nm->common, &nm->frac);
++ }
+
+ _nm.min_n = nm->n.min ?: 1;
+ _nm.max_n = nm->n.max ?: 1 << nm->n.width;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-Make-fractional-helper-less-chatty b/patches.drivers/clk-sunxi-ng-Make-fractional-helper-less-chatty
new file mode 100644
index 0000000000..bcdb511062
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-Make-fractional-helper-less-chatty
@@ -0,0 +1,53 @@
+From b655f36e2071a9a380477e2f07893c31cbf88f59 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jernej=20=C5=A0krabec?= <jernej.skrabec@siol.net>
+Date: Sun, 30 Jul 2017 18:41:49 +0200
+Subject: [PATCH] clk: sunxi-ng: Make fractional helper less chatty
+Git-commit: b655f36e2071a9a380477e2f07893c31cbf88f59
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+ccu_frac_helper_read_rate() prints some info which is not really
+helpful except during debugging.
+
+Replace printk() with pr_debug().
+
+Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu_frac.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
+index 8b5eb7756bf7..ff9e72dc5337 100644
+--- a/drivers/clk/sunxi-ng/ccu_frac.c
++++ b/drivers/clk/sunxi-ng/ccu_frac.c
+@@ -67,18 +67,18 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
+ {
+ u32 reg;
+
+- printk("%s: Read fractional\n", clk_hw_get_name(&common->hw));
++ pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw));
+
+ if (!(common->features & CCU_FEATURE_FRACTIONAL))
+ return 0;
+
+- printk("%s: clock is fractional (rates %lu and %lu)\n",
+- clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
++ pr_debug("%s: clock is fractional (rates %lu and %lu)\n",
++ clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
+
+ reg = readl(common->base + common->reg);
+
+- printk("%s: clock reg is 0x%x (select is 0x%x)\n",
+- clk_hw_get_name(&common->hw), reg, cf->select);
++ pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
++ clk_hw_get_name(&common->hw), reg, cf->select);
+
+ return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-Wait-for-lock-when-using-fractional-mod b/patches.drivers/clk-sunxi-ng-Wait-for-lock-when-using-fractional-mod
new file mode 100644
index 0000000000..9d9242add0
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-Wait-for-lock-when-using-fractional-mod
@@ -0,0 +1,89 @@
+From 1d42460a49347af4d1db345197e5d1277336b312 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jernej=20=C5=A0krabec?= <jernej.skrabec@siol.net>
+Date: Sun, 30 Jul 2017 18:41:50 +0200
+Subject: [PATCH] clk: sunxi-ng: Wait for lock when using fractional mode
+Git-commit: 1d42460a49347af4d1db345197e5d1277336b312
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
+set before returning. Because of that, unstable clock may be used.
+
+Add a wait for lock in the helper function.
+
+Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu_frac.c | 4 +++-
+ drivers/clk/sunxi-ng/ccu_frac.h | 2 +-
+ drivers/clk/sunxi-ng/ccu_mult.c | 3 ++-
+ drivers/clk/sunxi-ng/ccu_nm.c | 3 ++-
+ 4 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
+index ff9e72dc5337..d1d168d4c4f0 100644
+--- a/drivers/clk/sunxi-ng/ccu_frac.c
++++ b/drivers/clk/sunxi-ng/ccu_frac.c
+@@ -85,7 +85,7 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
+
+ int ccu_frac_helper_set_rate(struct ccu_common *common,
+ struct ccu_frac_internal *cf,
+- unsigned long rate)
++ unsigned long rate, u32 lock)
+ {
+ unsigned long flags;
+ u32 reg, sel;
+@@ -106,5 +106,7 @@ int ccu_frac_helper_set_rate(struct ccu_common *common,
+ writel(reg | sel, common->base + common->reg);
+ spin_unlock_irqrestore(common->lock, flags);
+
++ ccu_helper_wait_for_lock(common, lock);
++
+ return 0;
+ }
+diff --git a/drivers/clk/sunxi-ng/ccu_frac.h b/drivers/clk/sunxi-ng/ccu_frac.h
+index 7b1ee380156f..efe2dd6bac01 100644
+--- a/drivers/clk/sunxi-ng/ccu_frac.h
++++ b/drivers/clk/sunxi-ng/ccu_frac.h
+@@ -48,6 +48,6 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
+
+ int ccu_frac_helper_set_rate(struct ccu_common *common,
+ struct ccu_frac_internal *cf,
+- unsigned long rate);
++ unsigned long rate, u32 lock);
+
+ #endif /* _CCU_FRAC_H_ */
+diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
+index ee5e96222cb2..12e0783caee6 100644
+--- a/drivers/clk/sunxi-ng/ccu_mult.c
++++ b/drivers/clk/sunxi-ng/ccu_mult.c
+@@ -114,7 +114,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
+ if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) {
+ ccu_frac_helper_enable(&cm->common, &cm->frac);
+
+- return ccu_frac_helper_set_rate(&cm->common, &cm->frac, rate);
++ return ccu_frac_helper_set_rate(&cm->common, &cm->frac,
++ rate, cm->lock);
+ } else {
+ ccu_frac_helper_disable(&cm->common, &cm->frac);
+ }
+diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
+index c6ba866b99d3..a32158e8f2e3 100644
+--- a/drivers/clk/sunxi-ng/ccu_nm.c
++++ b/drivers/clk/sunxi-ng/ccu_nm.c
+@@ -129,7 +129,8 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
+
+ ccu_frac_helper_enable(&nm->common, &nm->frac);
+
+- return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
++ return ccu_frac_helper_set_rate(&nm->common, &nm->frac,
++ rate, nm->lock);
+ } else {
+ ccu_frac_helper_disable(&nm->common, &nm->frac);
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-a31-Fix-CLK_OUT_-clock-ops b/patches.drivers/clk-sunxi-ng-a31-Fix-CLK_OUT_-clock-ops
new file mode 100644
index 0000000000..80a134f01d
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-a31-Fix-CLK_OUT_-clock-ops
@@ -0,0 +1,71 @@
+From 5682e268350f9eccdbb04006605c1b7068a7b323 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Sat, 17 Feb 2018 21:05:04 +0800
+Subject: [PATCH] clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops
+Git-commit: 5682e268350f9eccdbb04006605c1b7068a7b323
+Patch-mainline: v4.16-rc7
+References: bsc#1051510
+
+When support for the A31/A31s CCU was first added, the clock ops for
+the CLK_OUT_* clocks was set to the wrong type. The clocks are MP-type,
+but the ops was set for div (M) clocks. This went unnoticed until now.
+This was because while they are different clocks, their data structures
+aligned in a way that ccu_div_ops would access the second ccu_div_internal
+and ccu_mux_internal structures, which were valid, if not incorrect.
+
+Furthermore, the use of these CLK_OUT_* was for feeding a precise 32.768
+kHz clock signal to the WiFi chip. This was achievable by using the parent
+with the same clock rate and no divider. So the incorrect divider setting
+did not affect this usage.
+
+Commit 946797aa3f08 ("clk: sunxi-ng: Support fixed post-dividers on MP
+style clocks") added a new field to the ccu_mp structure, which broke
+the aforementioned alignment. Now the system crashes as div_ops tries
+to look up a nonexistent table.
+
+Reported-by: Philipp Rossak <embed3d@gmail.com>
+Tested-by: Philipp Rossak <embed3d@gmail.com>
+Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+index 72b16ed1012b..3b97f60540ad 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
++++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+@@ -762,7 +762,7 @@ static struct ccu_mp out_a_clk = {
+ .features = CCU_FEATURE_FIXED_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("out-a",
+ clk_out_parents,
+- &ccu_div_ops,
++ &ccu_mp_ops,
+ 0),
+ },
+ };
+@@ -783,7 +783,7 @@ static struct ccu_mp out_b_clk = {
+ .features = CCU_FEATURE_FIXED_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("out-b",
+ clk_out_parents,
+- &ccu_div_ops,
++ &ccu_mp_ops,
+ 0),
+ },
+ };
+@@ -804,7 +804,7 @@ static struct ccu_mp out_c_clk = {
+ .features = CCU_FEATURE_FIXED_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("out-c",
+ clk_out_parents,
+- &ccu_div_ops,
++ &ccu_mp_ops,
+ 0),
+ },
+ };
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_PARENT-flag-to-H3-GPU- b/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_PARENT-flag-to-H3-GPU-
new file mode 100644
index 0000000000..6aca1c7287
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_PARENT-flag-to-H3-GPU-
@@ -0,0 +1,40 @@
+From 70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 10 Sep 2017 20:40:06 +0800
+Subject: [PATCH] clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
+Git-commit: 70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only
+the parent of the GPU clock. The GPU clock can be tweaked by tweaking
+the PLL-GPU clock.
+
+Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via
+tweaking PLL-CPU.
+
+Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 7a81c4885836..543c46d0e045 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
+ 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
+
+ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
+- 0x1a0, 0, 3, BIT(31), 0);
++ 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
+
+ static struct ccu_common *sun8i_h3_ccu_clks[] = {
+ &pll_cpux_clk.common,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_UNGATE-to-all-H3-PLLs b/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_UNGATE-to-all-H3-PLLs
new file mode 100644
index 0000000000..faf1f71897
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_UNGATE-to-all-H3-PLLs
@@ -0,0 +1,111 @@
+From 62d212bdb022deeb875f92f6e376c799e3f35eca Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 10 Sep 2017 20:40:05 +0800
+Subject: [PATCH] clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
+Git-commit: 62d212bdb022deeb875f92f6e376c799e3f35eca
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
+is really working.
+
+Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
+trying to set PLL clock frequency without enabling it.
+
+Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 1729ff6a5aae..7a81c4885836 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -37,7 +37,7 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
+ 16, 2, /* P */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ /*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+@@ -55,7 +55,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+ 0, 5, /* M */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
+ "osc24M", 0x0010,
+@@ -67,7 +67,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
+ "osc24M", 0x0018,
+@@ -79,7 +79,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
+ "osc24M", 0x020,
+@@ -88,7 +88,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
+ 0, 2, /* M */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
+ "osc24M", 0x028,
+@@ -97,7 +97,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 2, /* post-div */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
+ "osc24M", 0x0038,
+@@ -109,7 +109,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
+ "osc24M", 0x044,
+@@ -118,7 +118,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ 2, /* post-div */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
+ "osc24M", 0x0048,
+@@ -130,7 +130,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+- 0);
++ CLK_SET_RATE_UNGATE);
+
+ static const char * const cpux_parents[] = { "osc32k", "osc24M",
+ "pll-cpux" , "pll-cpux" };
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-allow-set-parent-clock-PLL_CPUX-for-CPU b/patches.drivers/clk-sunxi-ng-allow-set-parent-clock-PLL_CPUX-for-CPU
new file mode 100644
index 0000000000..0f53baf843
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-allow-set-parent-clock-PLL_CPUX-for-CPU
@@ -0,0 +1,40 @@
+From 913c3d85b4b562e38242765baa95113c8c7f1c14 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 23 Jul 2017 18:27:45 +0800
+Subject: [PATCH] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
+Git-commit: 913c3d85b4b562e38242765baa95113c8c7f1c14
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
+can be adjusted by changing the frequency of the PLL_CPUX clock.
+
+Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
+clock can be adjusted when adjusting the CPUX clock.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Acked-by: Stephen Boyd <sboyd@codeaurora.org>
+Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 406d0aac9fd6..4cdbc88f2783 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
+ static const char * const cpux_parents[] = { "osc32k", "osc24M",
+ "pll-cpux" , "pll-cpux" };
+ static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
+- 0x050, 16, 2, CLK_IS_CRITICAL);
++ 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
+
+ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-h3-gate-then-ungate-PLL-CPU-clk-after-r b/patches.drivers/clk-sunxi-ng-h3-gate-then-ungate-PLL-CPU-clk-after-r
new file mode 100644
index 0000000000..e579d15c07
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-h3-gate-then-ungate-PLL-CPU-clk-after-r
@@ -0,0 +1,55 @@
+From 48d5eb619c15847aba6757deb5c2c8badca2aece Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Sun, 23 Jul 2017 18:27:44 +0800
+Subject: [PATCH] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
+Git-commit: 48d5eb619c15847aba6757deb5c2c8badca2aece
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+This patch utilizes the new PLL clk notifier to gate then ungate the
+PLL CPU clock after rate changes. This should prevent any system hangs
+resulting from cpufreq changes to the clk.
+
+Reported-by: Ondrej Jirman <megous@megous.com>
+Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Tested-by: Icenowy Zheng <icenowy@aosc.io>
+Acked-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 62e4f0d2b2fc..406d0aac9fd6 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
+ .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
+ };
+
++static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
++ .common = &pll_cpux_clk.common,
++ /* copy from pll_cpux_clk */
++ .enable = BIT(31),
++ .lock = BIT(28),
++};
++
+ static struct ccu_mux_nb sun8i_h3_cpu_nb = {
+ .common = &cpux_clk.common,
+ .cm = &cpux_clk.mux,
+@@ -1130,6 +1137,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
+
+ sunxi_ccu_probe(node, reg, desc);
+
++ /* Gate then ungate PLL CPU after any rate changes */
++ ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
++
++ /* Reparent CPU during PLL CPU rate changes */
+ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+ &sun8i_h3_cpu_nb);
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-multiplier-Fix-fractional-mode b/patches.drivers/clk-sunxi-ng-multiplier-Fix-fractional-mode
new file mode 100644
index 0000000000..79626007b3
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-multiplier-Fix-fractional-mode
@@ -0,0 +1,40 @@
+From 1e92ae651e766603d9c582ff356abf96ae90d933 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jernej=20=C5=A0krabec?= <jernej.skrabec@siol.net>
+Date: Sun, 30 Jul 2017 18:41:48 +0200
+Subject: [PATCH] clk: sunxi-ng: multiplier: Fix fractional mode
+Git-commit: 1e92ae651e766603d9c582ff356abf96ae90d933
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Driver for multiplier clock is missing a call to
+ccu_frac_helper_enable() when fractional mode is selected.
+
+Add a call to ccu_frac_helper_enable().
+
+Fixes: d77e8135b340 ("clk: sunxi-ng: multiplier: Add fractional support")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu_mult.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/sunxi-ng/ccu_mult.c
++++ b/drivers/clk/sunxi-ng/ccu_mult.c
+@@ -110,10 +110,13 @@ static int ccu_mult_set_rate(struct clk_
+ unsigned long flags;
+ u32 reg;
+
+- if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate))
++ if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) {
++ ccu_frac_helper_enable(&cm->common, &cm->frac);
++
+ return ccu_frac_helper_set_rate(&cm->common, &cm->frac, rate);
+- else
++ } else {
+ ccu_frac_helper_disable(&cm->common, &cm->frac);
++ }
+
+ ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
+ &parent_rate);
diff --git a/patches.drivers/clk-sunxi-ng-nm-Check-if-requested-rate-is-supported b/patches.drivers/clk-sunxi-ng-nm-Check-if-requested-rate-is-supported
new file mode 100644
index 0000000000..5819643fdb
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-nm-Check-if-requested-rate-is-supported
@@ -0,0 +1,43 @@
+From 4cdbc40d64d4b8303a97e29a52862e4d99502beb Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Thu, 12 Oct 2017 16:36:58 +0800
+Subject: [PATCH] clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock
+Git-commit: 4cdbc40d64d4b8303a97e29a52862e4d99502beb
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The round_rate callback for N-M-factor style clocks does not check if
+the requested clock rate is supported by the fractional clock mode.
+While this doesn't affect usage in practice, since the clock rates
+are also supported through N-M factors, it does not match the set_rate
+code.
+
+Add a check to the round_rate callback so it matches the set_rate
+callback.
+
+Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu_nm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
+index a32158e8f2e3..84a5e7f17f6f 100644
+--- a/drivers/clk/sunxi-ng/ccu_nm.c
++++ b/drivers/clk/sunxi-ng/ccu_nm.c
+@@ -99,6 +99,9 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
+ struct ccu_nm *nm = hw_to_ccu_nm(hw);
+ struct _ccu_nm _nm;
+
++ if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
++ return rate;
++
+ _nm.min_n = nm->n.min ?: 1;
+ _nm.max_n = nm->n.max ?: 1 << nm->n.width;
+ _nm.min_m = 1;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-sun5i-Fix-bit-offset-of-audio-PLL-post- b/patches.drivers/clk-sunxi-ng-sun5i-Fix-bit-offset-of-audio-PLL-post-
new file mode 100644
index 0000000000..94ff614452
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-sun5i-Fix-bit-offset-of-audio-PLL-post-
@@ -0,0 +1,46 @@
+From d51fe3ba9773c8b6fc79f82bbe75d64baf604292 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Thu, 12 Oct 2017 16:36:57 +0800
+Subject: [PATCH] clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider
+Git-commit: d51fe3ba9773c8b6fc79f82bbe75d64baf604292
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The post-divider for the audio PLL is in bits [29:26], as specified
+in the user manual, not [19:16] as currently programmed in the code.
+The post-divider has a default register value of 2, i.e. a divider
+of 3. This means the clock rate fed to the audio codec would be off.
+
+This was discovered when porting sigma-delta modulation for the PLL
+to sun5i, which needs the post-divider to be 1.
+
+Fix the bit offset, so we do actually force the post-divider to a
+certain value.
+
+Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun5i.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
+index ab9e850b3707..2f385a57cd91 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
++++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
+@@ -982,8 +982,8 @@ static void __init sun5i_ccu_init(struct device_node *node,
+
+ /* Force the PLL-Audio-1x divider to 4 */
+ val = readl(reg + SUN5I_PLL_AUDIO_REG);
+- val &= ~GENMASK(19, 16);
+- writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG);
++ val &= ~GENMASK(29, 26);
++ writel(val | (3 << 26), reg + SUN5I_PLL_AUDIO_REG);
+
+ /*
+ * Use the peripheral PLL as the AHB parent, instead of CPU /
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-sun6i-Export-video-PLLs b/patches.drivers/clk-sunxi-ng-sun6i-Export-video-PLLs
new file mode 100644
index 0000000000..4bc8ff6ab1
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-sun6i-Export-video-PLLs
@@ -0,0 +1,70 @@
+From 80815004a45fc68b6e34653af4fca47be7fb96ed Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Fri, 29 Sep 2017 16:22:53 +0800
+Subject: [PATCH] clk: sunxi-ng: sun6i: Export video PLLs
+Git-commit: 80815004a45fc68b6e34653af4fca47be7fb96ed
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The 2x outputs of the 2 video PLL clocks are directly used by the
+HDMI controller block.
+
+Export them so they can be referenced in the device tree.
+
+Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun6i-a31.h | 8 ++++++--
+ include/dt-bindings/clock/sun6i-a31-ccu.h | 4 ++++
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+index 4e434011e9e7..27e6ad4133ab 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
++++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+@@ -27,7 +27,9 @@
+ #define CLK_PLL_AUDIO_4X 4
+ #define CLK_PLL_AUDIO_8X 5
+ #define CLK_PLL_VIDEO0 6
+-#define CLK_PLL_VIDEO0_2X 7
++
++/* The PLL_VIDEO0_2X clock is exported */
++
+ #define CLK_PLL_VE 8
+ #define CLK_PLL_DDR 9
+
+@@ -35,7 +37,9 @@
+
+ #define CLK_PLL_PERIPH_2X 11
+ #define CLK_PLL_VIDEO1 12
+-#define CLK_PLL_VIDEO1_2X 13
++
++/* The PLL_VIDEO1_2X clock is exported */
++
+ #define CLK_PLL_GPU 14
+ #define CLK_PLL_MIPI 15
+ #define CLK_PLL9 16
+diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
+index 4482530fb6f5..c5d13340184a 100644
+--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
++++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
+@@ -43,8 +43,12 @@
+ #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
+ #define _DT_BINDINGS_CLK_SUN6I_A31_H_
+
++#define CLK_PLL_VIDEO0_2X 7
++
+ #define CLK_PLL_PERIPH 10
+
++#define CLK_PLL_VIDEO1_2X 13
++
+ #define CLK_CPU 18
+
+ #define CLK_AHB1_MIPIDSI 23
+--
+2.18.0
+
diff --git a/patches.drivers/clk-sunxi-ng-sun6i-Rename-HDMI-DDC-clock-to-avoid-na b/patches.drivers/clk-sunxi-ng-sun6i-Rename-HDMI-DDC-clock-to-avoid-na
new file mode 100644
index 0000000000..f381761a96
--- /dev/null
+++ b/patches.drivers/clk-sunxi-ng-sun6i-Rename-HDMI-DDC-clock-to-avoid-na
@@ -0,0 +1,39 @@
+From 7f3ed79188f2f094d0ee366fa858857fb7f511ba Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Fri, 29 Sep 2017 16:22:54 +0800
+Subject: [PATCH] clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision
+Git-commit: 7f3ed79188f2f094d0ee366fa858857fb7f511ba
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The HDMI DDC clock found in the CCU is the parent of the actual DDC
+clock within the HDMI controller. That clock is also named "hdmi-ddc".
+
+Rename the one in the CCU to "ddc". This makes more sense than renaming
+the one in the HDMI controller to something else.
+
+Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+index 8af434815fba..241fb13f1c06 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
++++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
+ 0x150, 0, 4, 24, 2, BIT(31),
+ CLK_SET_RATE_PARENT);
+
+-static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
++static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
+
+ static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-tegra-Fix-cclk_lp-divisor-register b/patches.drivers/clk-tegra-Fix-cclk_lp-divisor-register
new file mode 100644
index 0000000000..f31939871f
--- /dev/null
+++ b/patches.drivers/clk-tegra-Fix-cclk_lp-divisor-register
@@ -0,0 +1,40 @@
+From 54eff2264d3e9fd7e3987de1d7eba1d3581c631e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= <mirq-linux@rere.qmqm.pl>
+Date: Tue, 19 Sep 2017 04:48:10 +0200
+Subject: [PATCH] clk: tegra: Fix cclk_lp divisor register
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 54eff2264d3e9fd7e3987de1d7eba1d3581c631e
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+According to comments in code and common sense, cclk_lp uses its
+own divisor, not cclk_g's.
+
+Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
+Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
+Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/tegra/clk-tegra30.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
+index 40ffab0f94e1..bee84c554932 100644
+--- a/drivers/clk/tegra/clk-tegra30.c
++++ b/drivers/clk/tegra/clk-tegra30.c
+@@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void)
+ * U71 divider of cclk_lp.
+ */
+ clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
+- clk_base + SUPER_CCLKG_DIVIDER, 0,
++ clk_base + SUPER_CCLKLP_DIVIDER, 0,
+ TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
+ clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
+
+--
+2.18.0
+
diff --git a/patches.drivers/clk-tegra-Fix-pll_u-rate-configuration b/patches.drivers/clk-tegra-Fix-pll_u-rate-configuration
new file mode 100644
index 0000000000..f009926818
--- /dev/null
+++ b/patches.drivers/clk-tegra-Fix-pll_u-rate-configuration
@@ -0,0 +1,61 @@
+From c35b518f9ba06c9de79fb3ff62eed7462d804995 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Fri, 23 Feb 2018 00:04:51 +0100
+Subject: [PATCH] clk: tegra: Fix pll_u rate configuration
+Git-commit: c35b518f9ba06c9de79fb3ff62eed7462d804995
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+Turns out latest upstream U-Boot does not configure/enable pll_u which
+leaves it at some default rate of 500 kHz:
+
+root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep pll_u
+ pll_u 3 3 0 500000 0
+
+Of course this won't quite work leading to the following messages:
+
+[ 6.559593] usb 2-1: new full-speed USB device number 2 using tegra-
+ehci
+[ 11.759173] usb 2-1: device descriptor read/64, error -110
+[ 27.119453] usb 2-1: device descriptor read/64, error -110
+[ 27.389217] usb 2-1: new full-speed USB device number 3 using tegra-
+ehci
+[ 32.559454] usb 2-1: device descriptor read/64, error -110
+[ 47.929777] usb 2-1: device descriptor read/64, error -110
+[ 48.049658] usb usb2-port1: attempt power cycle
+[ 48.759475] usb 2-1: new full-speed USB device number 4 using tegra-
+ehci
+[ 59.349457] usb 2-1: device not accepting address 4, error -110
+[ 59.509449] usb 2-1: new full-speed USB device number 5 using tegra-
+ehci
+[ 70.069457] usb 2-1: device not accepting address 5, error -110
+[ 70.079721] usb usb2-port1: unable to enumerate USB device
+
+Fix this by actually allowing the rate also being set from within
+the Linux kernel.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Tested-by: Jon Hunter <jonathanh@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/tegra/clk-pll.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
+index 7c369e21c91c..830d1c87fa7c 100644
+--- a/drivers/clk/tegra/clk-pll.c
++++ b/drivers/clk/tegra/clk-pll.c
+@@ -1151,6 +1151,8 @@ static const struct clk_ops tegra_clk_pllu_ops = {
+ .enable = clk_pllu_enable,
+ .disable = clk_pll_disable,
+ .recalc_rate = clk_pll_recalc_rate,
++ .round_rate = clk_pll_round_rate,
++ .set_rate = clk_pll_set_rate,
+ };
+
+ static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
+--
+2.18.0
+
diff --git a/patches.drivers/clk-tegra-Use-readl_relaxed_poll_timeout_atomic-in-t b/patches.drivers/clk-tegra-Use-readl_relaxed_poll_timeout_atomic-in-t
new file mode 100644
index 0000000000..c4de6c3085
--- /dev/null
+++ b/patches.drivers/clk-tegra-Use-readl_relaxed_poll_timeout_atomic-in-t
@@ -0,0 +1,50 @@
+From 22ef01a203d27fee8b7694020b7e722db7efd2a7 Mon Sep 17 00:00:00 2001
+From: Nicolin Chen <nicoleotsuka@gmail.com>
+Date: Fri, 15 Sep 2017 12:10:13 -0700
+Subject: [PATCH] clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()
+Git-commit: 22ef01a203d27fee8b7694020b7e722db7efd2a7
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Below is the call trace of tegra210_init_pllu() function:
+ start_kernel()
+ -> time_init()
+ --> of_clk_init()
+ ---> tegra210_clock_init()
+ ----> tegra210_pll_init()
+ -----> tegra210_init_pllu()
+
+Because the preemption is disabled in the start_kernel before calling
+time_init, tegra210_init_pllu is actually in an atomic context while
+it includes a readl_relaxed_poll_timeout that might sleep.
+
+So this patch just changes this readl_relaxed_poll_timeout() to its
+atomic version.
+
+Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
+Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/tegra/clk-tegra210.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
+index be7b736371f6..9e6260869eb9 100644
+--- a/drivers/clk/tegra/clk-tegra210.c
++++ b/drivers/clk/tegra/clk-tegra210.c
+@@ -2568,8 +2568,8 @@ static int tegra210_enable_pllu(void)
+ reg |= PLL_ENABLE;
+ writel(reg, clk_base + PLLU_BASE);
+
+- readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg,
+- reg & PLL_BASE_LOCK, 2, 1000);
++ readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
++ reg & PLL_BASE_LOCK, 2, 1000);
+ if (!(reg & PLL_BASE_LOCK)) {
+ pr_err("Timed out waiting for PLL_U to lock\n");
+ return -ETIMEDOUT;
+--
+2.18.0
+
diff --git a/patches.drivers/clk-ti-dra7-atl-clock-fix-child-node-lookups b/patches.drivers/clk-ti-dra7-atl-clock-fix-child-node-lookups
new file mode 100644
index 0000000000..3930075346
--- /dev/null
+++ b/patches.drivers/clk-ti-dra7-atl-clock-fix-child-node-lookups
@@ -0,0 +1,46 @@
+From 33ec6dbc5a02677509d97fe36cd2105753f0f0ea Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Sat, 11 Nov 2017 17:29:29 +0100
+Subject: [PATCH] clk: ti: dra7-atl-clock: fix child-node lookups
+Git-commit: 33ec6dbc5a02677509d97fe36cd2105753f0f0ea
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Fix child node-lookup during probe, which ended up searching the whole
+device tree depth-first starting at parent rather than just matching on
+its children.
+
+Note that the original premature free of the parent node has already
+been fixed separately, but that fix was apparently never backported to
+stable.
+
+Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
+Fixes: 660e15519399 ("clk: ti: dra7-atl-clock: Fix of_node reference counting")
+Cc: stable <stable@vger.kernel.org> # 3.16: 660e15519399
+Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/ti/clk-dra7-atl.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
+index 13eb04f72389..148815470431 100644
+--- a/drivers/clk/ti/clk-dra7-atl.c
++++ b/drivers/clk/ti/clk-dra7-atl.c
+@@ -274,8 +274,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
+
+ /* Get configuration for the ATL instances */
+ snprintf(prop, sizeof(prop), "atl%u", i);
+- of_node_get(node);
+- cfg_node = of_find_node_by_name(node, prop);
++ cfg_node = of_get_child_by_name(node, prop);
+ if (cfg_node) {
+ ret = of_property_read_u32(cfg_node, "bws",
+ &cdesc->bws);
+--
+2.18.0
+
diff --git a/patches.drivers/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5 b/patches.drivers/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5
new file mode 100644
index 0000000000..dfa688cc64
--- /dev/null
+++ b/patches.drivers/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5
@@ -0,0 +1,29 @@
+From 67affb78a4e4feb837953e3434c8402a5c3b272f Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Thu, 5 Oct 2017 11:32:59 +0900
+Subject: [PATCH] clk: uniphier: fix DAPLL2 clock rate of Pro5
+Git-commit: 67affb78a4e4feb837953e3434c8402a5c3b272f
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The parent of DAPLL2 should be DAPLL1. Fix the clock connection.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/uniphier/clk-uniphier-sys.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/uniphier/clk-uniphier-sys.c
++++ b/drivers/clk/uniphier/clk-uniphier-sys.c
+@@ -111,7 +111,7 @@ const struct uniphier_clk_data uniphier_
+ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
+ UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
+- UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
++ UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
+ UNIPHIER_SLD3_SYS_CLK_NAND(2),
diff --git a/patches.drivers/clk-x86-Do-not-gate-clocks-enabled-by-the-firmware b/patches.drivers/clk-x86-Do-not-gate-clocks-enabled-by-the-firmware
new file mode 100644
index 0000000000..fc81a5f789
--- /dev/null
+++ b/patches.drivers/clk-x86-Do-not-gate-clocks-enabled-by-the-firmware
@@ -0,0 +1,44 @@
+From d31fd43c0f9a41e2678a1e78c0f22f0384c6edd3 Mon Sep 17 00:00:00 2001
+From: Carlo Caione <carlo@endlessm.com>
+Date: Fri, 14 Jul 2017 10:23:56 +0200
+Subject: [PATCH] clk: x86: Do not gate clocks enabled by the firmware
+Git-commit: d31fd43c0f9a41e2678a1e78c0f22f0384c6edd3
+Patch-mainline: v4.13-rc4
+References: bsc#1051510
+
+Read the enable register to determine if the clock is already in use by
+the firmware. In this case avoid gating the clock.
+
+Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Darren Hart (VMware) <dvhart@infradead.org>
+Signed-off-by: Carlo Caione <carlo@endlessm.com>
+Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks")
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/clk/x86/clk-pmc-atom.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c
+index f99abc1106f0..08ef69945ffb 100644
+--- a/drivers/clk/x86/clk-pmc-atom.c
++++ b/drivers/clk/x86/clk-pmc-atom.c
+@@ -186,6 +186,13 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
+ pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
+ spin_lock_init(&pclk->lock);
+
++ /*
++ * If the clock was already enabled by the firmware mark it as critical
++ * to avoid it being gated by the clock framework if no driver owns it.
++ */
++ if (plt_clk_is_enabled(&pclk->hw))
++ init.flags |= CLK_IS_CRITICAL;
++
+ ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
+ if (ret) {
+ pclk = ERR_PTR(ret);
+--
+2.18.0
+
diff --git a/patches.drivers/drm-exynos-Fix-dma-buf-import b/patches.drivers/drm-exynos-Fix-dma-buf-import
new file mode 100644
index 0000000000..5412998847
--- /dev/null
+++ b/patches.drivers/drm-exynos-Fix-dma-buf-import
@@ -0,0 +1,86 @@
+From 89452d4ab20745002e50ecf90979708f1ce1d077 Mon Sep 17 00:00:00 2001
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Mon, 30 Oct 2017 08:28:09 +0100
+Subject: [PATCH] drm/exynos: Fix dma-buf import
+Git-commit: 89452d4ab20745002e50ecf90979708f1ce1d077
+Patch-mainline: v4.15-rc3
+References: bsc#1051510
+
+When IOMMU support was enabled, dma-buf import in Exynos DRM was broken
+since commit f43c35966a5a ("drm/exynos: use real device for DMA-mapping
+operations") due to using wrong struct device in drm_gem_prime_import()
+function. This patch fixes following kernel BUG caused by incorrect buffer
+mapping to DMA address space:
+
+exynos-sysmmu 14650000.sysmmu: 14450000.mixer: PAGE FAULT occurred at 0xb2e00000
+
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+------------[ cut here ]------------
+kernel BUG at drivers/iommu/exynos-iommu.c:449!
+Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
+Modules linked in:
+CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.14.0-rc4-next-20171016-00033-g990d723669fd #3165
+Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
+task: c0e0b7c0 task.stack: c0e00000
+PC is at exynos_sysmmu_irq+0x1d0/0x24c
+LR is at exynos_sysmmu_irq+0x154/0x24c
+------------[ cut here ]------------
+
+Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>
+Fixes: f43c35966a5a ("drm/exynos: use real device for DMA-mapping operations")
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Reviewed-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
+Signed-off-by: Inki Dae <inki.dae@samsung.com>
+---
+ drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 +-
+ drivers/gpu/drm/exynos/exynos_drm_gem.c | 6 ++++++
+ drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 ++
+ 3 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
+index 82b72425a42f..a6ff3a538c8a 100644
+--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
++++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
+@@ -148,7 +148,7 @@ static struct drm_driver exynos_drm_driver = {
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_export = drm_gem_prime_export,
+- .gem_prime_import = drm_gem_prime_import,
++ .gem_prime_import = exynos_drm_gem_prime_import,
+ .gem_prime_get_sg_table = exynos_drm_gem_prime_get_sg_table,
+ .gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table,
+ .gem_prime_vmap = exynos_drm_gem_prime_vmap,
+diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
+index 077de014d610..ef35bc23bb36 100644
+--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
++++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
+@@ -506,6 +506,12 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+ }
+
+ /* low-level interface prime helpers */
++struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev,
++ struct dma_buf *dma_buf)
++{
++ return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev));
++}
++
+ struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
+ {
+ struct exynos_drm_gem *exynos_gem = to_exynos_gem(obj);
+diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
+index e86d1a9518c3..5a4c7de80f65 100644
+--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
++++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
+@@ -117,6 +117,8 @@ int exynos_drm_gem_fault(struct vm_fault *vmf);
+ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+
+ /* low-level interface prime helpers */
++struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev,
++ struct dma_buf *dma_buf);
+ struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);
+ struct drm_gem_object *
+ exynos_drm_gem_prime_import_sg_table(struct drm_device *dev,
+--
+2.18.0
+
diff --git a/patches.drivers/drm-i915-Fix-hotplug-irq-ack-on-i965-g4x b/patches.drivers/drm-i915-Fix-hotplug-irq-ack-on-i965-g4x
new file mode 100644
index 0000000000..ebb07a7fc5
--- /dev/null
+++ b/patches.drivers/drm-i915-Fix-hotplug-irq-ack-on-i965-g4x
@@ -0,0 +1,84 @@
+From 96a85cc517a9ee4ae5e8d7f5a36cba05023784eb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 14 Jun 2018 20:56:25 +0300
+Subject: [PATCH] drm/i915: Fix hotplug irq ack on i965/g4x
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 96a85cc517a9ee4ae5e8d7f5a36cba05023784eb
+Patch-mainline: v4.18-rc6
+No-fix: 0ba7c51a6fd80a89236f6ceb52e63f8a7f62bfd3
+References: bsc#1051510
+
+Just like with PIPESTAT, the edge triggered IIR on i965/g4x
+also causes problems for hotplug interrupts. To make sure
+we don't get the IIR port interrupt bit stuck low with the
+ISR bit high we must force an edge in ISR. Unfortunately
+we can't borrow the PIPESTAT trick and toggle the enable
+bits in PORT_HOTPLUG_EN as that act itself generates hotplug
+interrupts. Instead we just have to loop until we've cleared
+PORT_HOTPLUG_STAT, or we just give up and WARN.
+
+V2: Don't frob with PORT_HOTPLUG_EN
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180614175625.1615-1-ville.syrjala@linux.intel.com
+Reviewed-by: Imre Deak <imre.deak@intel.com>
+(cherry picked from commit 0ba7c51a6fd80a89236f6ceb52e63f8a7f62bfd3)
+
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_irq.c | 32 ++++++++++++++++++++++++++++++--
+ 1 file changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
+index 4a02747ac658..c16cb025755e 100644
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -1998,10 +1998,38 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+
+ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
+ {
+- u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
++ u32 hotplug_status = 0, hotplug_status_mask;
++ int i;
++
++ if (IS_G4X(dev_priv) ||
++ IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
++ hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
++ DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
++ else
++ hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
+
+- if (hotplug_status)
++ /*
++ * We absolutely have to clear all the pending interrupt
++ * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
++ * interrupt bit won't have an edge, and the i965/g4x
++ * edge triggered IIR will not notice that an interrupt
++ * is still pending. We can't use PORT_HOTPLUG_EN to
++ * guarantee the edge as the act of toggling the enable
++ * bits can itself generate a new hotplug interrupt :(
++ */
++ for (i = 0; i < 10; i++) {
++ u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
++
++ if (tmp == 0)
++ return hotplug_status;
++
++ hotplug_status |= tmp;
+ I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
++ }
++
++ WARN_ONCE(1,
++ "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
++ I915_READ(PORT_HOTPLUG_STAT));
+
+ return hotplug_status;
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/drm-i915-Only-call-tasklet_kill-on-the-first-prepare b/patches.drivers/drm-i915-Only-call-tasklet_kill-on-the-first-prepare
new file mode 100644
index 0000000000..b6d42d76b6
--- /dev/null
+++ b/patches.drivers/drm-i915-Only-call-tasklet_kill-on-the-first-prepare
@@ -0,0 +1,56 @@
+From 73e2232aa3253d77935112bfc218700f6a2f1000 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 7 Mar 2018 13:42:26 +0000
+Subject: [PATCH] drm/i915: Only call tasklet_kill() on the first prepare_reset
+Git-commit: 73e2232aa3253d77935112bfc218700f6a2f1000
+Patch-mainline: v4.17-rc1
+No-fix: 68ad361285a9cc73b259f59adbaafde196c15987
+References: bsc#1051510
+
+tasklet_kill() will spin waiting for the current tasklet to be executed.
+However, if tasklet_disable() has been called, then the tasklet is never
+executed but permanently put back onto the runlist until
+tasklet_enable() is called. Ergo, we cannot use tasklet_kill() inside a
+disable/enable pair. This is the case when we call set-wedge from inside
+i915_reset(), and another request was submitted to us concurrent to the
+reset.
+
+Fixes: 963ddd63c314 ("drm/i915: Suspend submission tasklets around wedging")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180307134226.25492-6-chris@chris-wilson.co.uk
+(cherry picked from commit 68ad361285a9cc73b259f59adbaafde196c15987)
+
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
+index 8d913d833ab9..0359d6f870b4 100644
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -2940,8 +2940,16 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
+ * calling engine->init_hw() and also writing the ELSP.
+ * Turning off the execlists->tasklet until the reset is over
+ * prevents the race.
++ *
++ * Note that this needs to be a single atomic operation on the
++ * tasklet (flush existing tasks, prevent new tasks) to prevent
++ * a race between reset and set-wedged. It is not, so we do the best
++ * we can atm and make sure we don't lock the machine up in the more
++ * common case of recursively being called from set-wedged from inside
++ * i915_reset.
+ */
+- tasklet_kill(&engine->execlists.tasklet);
++ if (!atomic_read(&engine->execlists.tasklet.count))
++ tasklet_kill(&engine->execlists.tasklet);
+ tasklet_disable(&engine->execlists.tasklet);
+
+ /*
+--
+2.18.0
+
diff --git a/patches.drivers/drm-i915-Specify-which-engines-to-reset-following-se b/patches.drivers/drm-i915-Specify-which-engines-to-reset-following-se
index 377f0df6a1..e8b8e47e02 100644
--- a/patches.drivers/drm-i915-Specify-which-engines-to-reset-following-se
+++ b/patches.drivers/drm-i915-Specify-which-engines-to-reset-following-se
@@ -5,6 +5,7 @@ Subject: [PATCH] drm/i915: Specify which engines to reset following semaphore/ev
Git-commit: 3a088dd1b72dc0fc2e7ee1fca76e26290c5261a0
Patch-mainline: v4.16 or v4.16-rc7 (next release)
No-fix: ca98317b89428e6ac17be0938b467ed78654dd56
+No-fix: 8f30c4085b72485c05e85d56e9a84098da2ba5b7
References: FATE#322643 bsc#1055900
If the GPU is stuck waiting for an event or for a semaphore, we need to
diff --git a/patches.drivers/drm-i915-dp-Send-DPCD-ON-for-MST-before-phy_up b/patches.drivers/drm-i915-dp-Send-DPCD-ON-for-MST-before-phy_up
new file mode 100644
index 0000000000..77853fc6b9
--- /dev/null
+++ b/patches.drivers/drm-i915-dp-Send-DPCD-ON-for-MST-before-phy_up
@@ -0,0 +1,122 @@
+From be1c63c8017bb00a4041abace6cc1e9f0bf26aa9 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Fri, 6 Apr 2018 21:10:53 -0400
+Subject: [PATCH] drm/i915/dp: Send DPCD ON for MST before phy_up
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: be1c63c8017bb00a4041abace6cc1e9f0bf26aa9
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+When doing a modeset where the sink is transitioning from D3 to D0 , it
+would sometimes be possible for the initial power_up_phy() to start
+timing out. This would only be observed in the last action before the
+sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
+originally thought this might be an issue with us accidentally shutting
+off the aux block when putting the sink into D3, but since the DP spec
+mandates that sinks must wake up within 1ms while we have 100ms to
+respond to an ESI irq, this didn't really add up. Turns out that the
+problem is more subtle then that:
+
+It turns out that the timeout is from us not enabling DPMS on the MST
+hub before actually trying to initiate sideband communications. This
+would cause the first sideband communication (power_up_phy()), to start
+timing out because the sink wasn't ready to respond. Afterwards, we
+would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
+intel_ddi_pre_enable_dp(), which would actually result in waking up the
+sink so that sideband requests would work again.
+
+Since DPMS is what lets us actually bring the hub up into a state where
+sideband communications become functional again, we just need to make
+sure to enable DPMS on the display before attempting to perform sideband
+communications.
+
+Changes since v1:
+- Remove comment above if (!intel_dp->is_mst) - vsryjala
+- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
+ keep enable/disable paths symmetrical
+- Improve commit message - dhnkrn
+Changes since v2:
+- Only send DPMS off when we're disabling the last sink, and only send
+ DPMS on when we're enabling the first sink - dhnkrn
+Changes since v3:
+- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
+
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Tested-by: Laura Abbott <labbott@redhat.com>
+Cc: stable@vger.kernel.org
+Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
+Link: https://patchwork.freedesktop.org/patch/msgid/20180407011053.22437-1-lyude@redhat.com
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++--
+ drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++-
+ 2 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
+index a6672a9abd85..92cb26b18a9b 100644
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
+ intel_prepare_dp_ddi_buffers(encoder, crtc_state);
+
+ intel_ddi_init_dp_buf_reg(encoder);
+- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
++ if (!is_mst)
++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_start_link_train(intel_dp);
+ if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ intel_dp_stop_link_train(intel_dp);
+@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ struct intel_dp *intel_dp = &dig_port->dp;
++ bool is_mst = intel_crtc_has_type(old_crtc_state,
++ INTEL_OUTPUT_DP_MST);
+
+ /*
+ * Power down sink before disabling the port, otherwise we end
+ * up getting interrupts from the sink on detecting link loss.
+ */
+- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
++ if (!is_mst)
++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+
+ intel_disable_ddi_buf(encoder);
+
+diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
+index c3de0918ee13..9e6956c08688 100644
+--- a/drivers/gpu/drm/i915/intel_dp_mst.c
++++ b/drivers/gpu/drm/i915/intel_dp_mst.c
+@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
+ intel_dp->active_mst_links--;
+
+ intel_mst->connector = NULL;
+- if (intel_dp->active_mst_links == 0)
++ if (intel_dp->active_mst_links == 0) {
++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+ intel_dig_port->base.post_disable(&intel_dig_port->base,
+ old_crtc_state, NULL);
++ }
+
+ DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
+ }
+@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
+
+ DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
+
++ if (intel_dp->active_mst_links == 0)
++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
++
+ drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
++
+ if (intel_dp->active_mst_links == 0)
+ intel_dig_port->base.pre_enable(&intel_dig_port->base,
+ pipe_config, NULL);
+--
+2.18.0
+
diff --git a/patches.drivers/drm-i915-dp-Write-to-SET_POWER-dpcd-to-enable-MST-hu b/patches.drivers/drm-i915-dp-Write-to-SET_POWER-dpcd-to-enable-MST-hu
index 2c4f7ddbf7..50feb23c29 100644
--- a/patches.drivers/drm-i915-dp-Write-to-SET_POWER-dpcd-to-enable-MST-hu
+++ b/patches.drivers/drm-i915-dp-Write-to-SET_POWER-dpcd-to-enable-MST-hu
@@ -8,6 +8,7 @@ Content-transfer-encoding: 8bit
Git-commit: b1e314462bba76660eec62760bb2e87f28f58866
Patch-mainline: v4.16-rc7
No-fix: ad260ab32a4d94fa974f58262f8000472d34fd5b
+No-fix: 7a7d58dc2997b6ca5bc1eaa4bd8d019cf7c4a148
References: bsc#1051510
If bios sets up an MST output and hardware state readout code sees this is
diff --git a/patches.drivers/drm-nouveau-Avoid-looping-through-fake-MST-connector b/patches.drivers/drm-nouveau-Avoid-looping-through-fake-MST-connector
new file mode 100644
index 0000000000..12ebb8a008
--- /dev/null
+++ b/patches.drivers/drm-nouveau-Avoid-looping-through-fake-MST-connector
@@ -0,0 +1,207 @@
+From 37afe55b4ae0600deafe7c0e0e658593c4754f1b Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Fri, 13 Jul 2018 13:06:33 -0400
+Subject: [PATCH] drm/nouveau: Avoid looping through fake MST connectors
+Git-commit: 37afe55b4ae0600deafe7c0e0e658593c4754f1b
+Patch-mainline: v4.18-rc6
+References: bsc#1051510
+
+When MST and atomic were introduced to nouveau, another structure that
+could contain a drm_connector embedded within it was introduced; struct
+nv50_mstc. This meant that we no longer would be able to simply loop
+through our connector list and assume that nouveau_connector() would
+return a proper pointer for each connector, since the assertion that
+all connectors coming from nouveau have a full nouveau_connector struct
+became invalid.
+
+Unfortunately, none of the actual code that looped through connectors
+ever got updated, which means that we've been causing invalid memory
+accesses for quite a while now.
+
+An example that was caught by KASAN:
+
+[ 201.038698] ==================================================================
+[ 201.038792] BUG: KASAN: slab-out-of-bounds in nvif_notify_get+0x190/0x1a0 [nouveau]
+[ 201.038797] Read of size 4 at addr ffff88076738c650 by task kworker/0:3/718
+[ 201.038800]
+[ 201.038822] CPU: 0 PID: 718 Comm: kworker/0:3 Tainted: G O 4.18.0-rc4Lyude-Test+ #1
+[ 201.038825] Hardware name: LENOVO 20EQS64N0B/20EQS64N0B, BIOS N1EET78W (1.51 ) 05/18/2018
+[ 201.038882] Workqueue: events nouveau_display_hpd_work [nouveau]
+[ 201.038887] Call Trace:
+[ 201.038894] dump_stack+0xa4/0xfd
+[ 201.038900] print_address_description+0x71/0x239
+[ 201.038929] ? nvif_notify_get+0x190/0x1a0 [nouveau]
+[ 201.038935] kasan_report.cold.6+0x242/0x2fe
+[ 201.038942] __asan_report_load4_noabort+0x19/0x20
+[ 201.038970] nvif_notify_get+0x190/0x1a0 [nouveau]
+[ 201.038998] ? nvif_notify_put+0x1f0/0x1f0 [nouveau]
+[ 201.039003] ? kmsg_dump_rewind_nolock+0xe4/0xe4
+[ 201.039049] nouveau_display_init.cold.12+0x34/0x39 [nouveau]
+[ 201.039089] ? nouveau_user_framebuffer_create+0x120/0x120 [nouveau]
+[ 201.039133] nouveau_display_resume+0x5c0/0x810 [nouveau]
+[ 201.039173] ? nvkm_client_ioctl+0x20/0x20 [nouveau]
+[ 201.039215] nouveau_do_resume+0x19f/0x570 [nouveau]
+[ 201.039256] nouveau_pmops_runtime_resume+0xd8/0x2a0 [nouveau]
+[ 201.039264] pci_pm_runtime_resume+0x130/0x250
+[ 201.039269] ? pci_restore_standard_config+0x70/0x70
+[ 201.039275] __rpm_callback+0x1f2/0x5d0
+[ 201.039279] ? rpm_resume+0x560/0x18a0
+[ 201.039283] ? pci_restore_standard_config+0x70/0x70
+[ 201.039287] ? pci_restore_standard_config+0x70/0x70
+[ 201.039291] ? pci_restore_standard_config+0x70/0x70
+[ 201.039296] rpm_callback+0x175/0x210
+[ 201.039300] ? pci_restore_standard_config+0x70/0x70
+[ 201.039305] rpm_resume+0xcc3/0x18a0
+[ 201.039312] ? rpm_callback+0x210/0x210
+[ 201.039317] ? __pm_runtime_resume+0x9e/0x100
+[ 201.039322] ? kasan_check_write+0x14/0x20
+[ 201.039326] ? do_raw_spin_lock+0xc2/0x1c0
+[ 201.039333] __pm_runtime_resume+0xac/0x100
+[ 201.039374] nouveau_display_hpd_work+0x67/0x1f0 [nouveau]
+[ 201.039380] process_one_work+0x7a0/0x14d0
+[ 201.039388] ? cancel_delayed_work_sync+0x20/0x20
+[ 201.039392] ? lock_acquire+0x113/0x310
+[ 201.039398] ? kasan_check_write+0x14/0x20
+[ 201.039402] ? do_raw_spin_lock+0xc2/0x1c0
+[ 201.039409] worker_thread+0x86/0xb50
+[ 201.039418] kthread+0x2e9/0x3a0
+[ 201.039422] ? process_one_work+0x14d0/0x14d0
+[ 201.039426] ? kthread_create_worker_on_cpu+0xc0/0xc0
+[ 201.039431] ret_from_fork+0x3a/0x50
+[ 201.039441]
+[ 201.039444] Allocated by task 79:
+[ 201.039449] save_stack+0x43/0xd0
+[ 201.039452] kasan_kmalloc+0xc4/0xe0
+[ 201.039456] kmem_cache_alloc_trace+0x10a/0x260
+[ 201.039494] nv50_mstm_add_connector+0x9a/0x340 [nouveau]
+[ 201.039504] drm_dp_add_port+0xff5/0x1fc0 [drm_kms_helper]
+[ 201.039511] drm_dp_send_link_address+0x4a7/0x740 [drm_kms_helper]
+[ 201.039518] drm_dp_check_and_send_link_address+0x1a7/0x210 [drm_kms_helper]
+[ 201.039525] drm_dp_mst_link_probe_work+0x71/0xb0 [drm_kms_helper]
+[ 201.039529] process_one_work+0x7a0/0x14d0
+[ 201.039533] worker_thread+0x86/0xb50
+[ 201.039537] kthread+0x2e9/0x3a0
+[ 201.039541] ret_from_fork+0x3a/0x50
+[ 201.039543]
+[ 201.039546] Freed by task 0:
+[ 201.039549] (stack is not available)
+[ 201.039551]
+[ 201.039555] The buggy address belongs to the object at ffff88076738c1a8
+ which belongs to the cache kmalloc-2048 of size 2048
+[ 201.039559] The buggy address is located 1192 bytes inside of
+ 2048-byte region [ffff88076738c1a8, ffff88076738c9a8)
+[ 201.039563] The buggy address belongs to the page:
+[ 201.039567] page:ffffea001d9ce200 count:1 mapcount:0 mapping:ffff88084000d0c0 index:0x0 compound_mapcount: 0
+[ 201.039573] flags: 0x8000000000008100(slab|head)
+[ 201.039578] raw: 8000000000008100 ffffea001da3be08 ffffea001da25a08 ffff88084000d0c0
+[ 201.039582] raw: 0000000000000000 00000000000d000d 00000001ffffffff 0000000000000000
+[ 201.039585] page dumped because: kasan: bad access detected
+[ 201.039588]
+[ 201.039591] Memory state around the buggy address:
+[ 201.039594] ffff88076738c500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+[ 201.039598] ffff88076738c580: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+[ 201.039601] >ffff88076738c600: 00 00 00 00 00 00 00 00 00 00 fc fc fc fc fc fc
+[ 201.039604] ^
+[ 201.039607] ffff88076738c680: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ 201.039611] ffff88076738c700: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
+[ 201.039613] ==================================================================
+
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Cc: stable@vger.kernel.org
+Cc: Karol Herbst <karolherbst@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
+ drivers/gpu/drm/nouveau/nouveau_connector.h | 24 ++++++++++++++++++++-
+ drivers/gpu/drm/nouveau/nouveau_display.c | 4 ++--
+ 3 files changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
+index 7dc380449232..af68eae4c626 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
++++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
+@@ -1213,7 +1213,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
+ bool dummy;
+
+ drm_connector_list_iter_begin(dev, &conn_iter);
+- drm_for_each_connector_iter(connector, &conn_iter) {
++ nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
+ nv_connector = nouveau_connector(connector);
+ if (nv_connector->index == index) {
+ drm_connector_list_iter_end(&conn_iter);
+diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
+index a8cbb4b56fc7..dc7454e7f19a 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
++++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
+@@ -33,6 +33,7 @@
+ #include <drm/drm_encoder.h>
+ #include <drm/drm_dp_helper.h>
+ #include "nouveau_crtc.h"
++#include "nouveau_encoder.h"
+
+ struct nvkm_i2c_port;
+
+@@ -60,6 +61,27 @@ static inline struct nouveau_connector *nouveau_connector(
+ return container_of(con, struct nouveau_connector, base);
+ }
+
++static inline bool
++nouveau_connector_is_mst(struct drm_connector *connector)
++{
++ const struct nouveau_encoder *nv_encoder;
++ const struct drm_encoder *encoder;
++
++ if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
++ return false;
++
++ nv_encoder = find_encoder(connector, DCB_OUTPUT_ANY);
++ if (!nv_encoder)
++ return false;
++
++ encoder = &nv_encoder->base.base;
++ return encoder->encoder_type == DRM_MODE_ENCODER_DPMST;
++}
++
++#define nouveau_for_each_non_mst_connector_iter(connector, iter) \
++ drm_for_each_connector_iter(connector, iter) \
++ for_each_if(!nouveau_connector_is_mst(connector))
++
+ static inline struct nouveau_connector *
+ nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
+ {
+@@ -70,7 +92,7 @@ nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
+ struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
+
+ drm_connector_list_iter_begin(dev, &conn_iter);
+- drm_for_each_connector_iter(connector, &conn_iter) {
++ nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
+ if (connector->encoder && connector->encoder->crtc == crtc) {
+ nv_connector = nouveau_connector(connector);
+ break;
+diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
+index 46b8430ef4aa..ec7861457b84 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_display.c
++++ b/drivers/gpu/drm/nouveau/nouveau_display.c
+@@ -413,7 +413,7 @@ nouveau_display_init(struct drm_device *dev)
+
+ /* enable hotplug interrupts */
+ drm_connector_list_iter_begin(dev, &conn_iter);
+- drm_for_each_connector_iter(connector, &conn_iter) {
++ nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
+ struct nouveau_connector *conn = nouveau_connector(connector);
+ nvif_notify_get(&conn->hpd);
+ }
+@@ -444,7 +444,7 @@ nouveau_display_fini(struct drm_device *dev, bool suspend)
+
+ /* disable hotplug interrupts */
+ drm_connector_list_iter_begin(dev, &conn_iter);
+- drm_for_each_connector_iter(connector, &conn_iter) {
++ nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
+ struct nouveau_connector *conn = nouveau_connector(connector);
+ nvif_notify_put(&conn->hpd);
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/drm-nouveau-Use-drm_connector_list_iter_-for-iterati b/patches.drivers/drm-nouveau-Use-drm_connector_list_iter_-for-iterati
new file mode 100644
index 0000000000..a7ef521736
--- /dev/null
+++ b/patches.drivers/drm-nouveau-Use-drm_connector_list_iter_-for-iterati
@@ -0,0 +1,164 @@
+From 22b76bbe089cd901f5260ecb9a3dc41f9edb97a0 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Fri, 13 Jul 2018 13:06:32 -0400
+Subject: [PATCH] drm/nouveau: Use drm_connector_list_iter_* for iterating connectors
+Git-commit: 22b76bbe089cd901f5260ecb9a3dc41f9edb97a0
+Patch-mainline: v4.18-rc6
+References: bsc#1051510
+
+Every codepath in nouveau that loops through the connector list
+currently does so using the old method, which is prone to race
+conditions from MST connectors being created and destroyed. This has
+been causing a multitude of problems, including memory corruption from
+trying to access connectors that have already been freed!
+
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Cc: stable@vger.kernel.org
+Cc: Karol Herbst <karolherbst@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_backlight.c | 6 ++++--
+ drivers/gpu/drm/nouveau/nouveau_connector.c | 9 +++++++--
+ drivers/gpu/drm/nouveau/nouveau_connector.h | 14 ++++++++++----
+ drivers/gpu/drm/nouveau/nouveau_display.c | 10 ++++++++--
+ 4 files changed, 29 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
+index debbbf0fd4bd..408b955e5c39 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
++++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
+@@ -267,6 +267,7 @@ nouveau_backlight_init(struct drm_device *dev)
+ struct nouveau_drm *drm = nouveau_drm(dev);
+ struct nvif_device *device = &drm->client.device;
+ struct drm_connector *connector;
++ struct drm_connector_list_iter conn_iter;
+
+ INIT_LIST_HEAD(&drm->bl_connectors);
+
+@@ -275,7 +276,8 @@ nouveau_backlight_init(struct drm_device *dev)
+ return 0;
+ }
+
+- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++ drm_connector_list_iter_begin(dev, &conn_iter);
++ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
+ connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ continue;
+@@ -292,7 +294,7 @@ nouveau_backlight_init(struct drm_device *dev)
+ break;
+ }
+ }
+-
++ drm_connector_list_iter_end(&conn_iter);
+
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
+index 7b557c354307..7dc380449232 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
++++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
+@@ -1208,14 +1208,19 @@ nouveau_connector_create(struct drm_device *dev, int index)
+ struct nouveau_display *disp = nouveau_display(dev);
+ struct nouveau_connector *nv_connector = NULL;
+ struct drm_connector *connector;
++ struct drm_connector_list_iter conn_iter;
+ int type, ret = 0;
+ bool dummy;
+
+- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++ drm_connector_list_iter_begin(dev, &conn_iter);
++ drm_for_each_connector_iter(connector, &conn_iter) {
+ nv_connector = nouveau_connector(connector);
+- if (nv_connector->index == index)
++ if (nv_connector->index == index) {
++ drm_connector_list_iter_end(&conn_iter);
+ return connector;
++ }
+ }
++ drm_connector_list_iter_end(&conn_iter);
+
+ nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL);
+ if (!nv_connector)
+diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
+index a4d1a059bd3d..a8cbb4b56fc7 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
++++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
+@@ -65,14 +65,20 @@ nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
+ {
+ struct drm_device *dev = nv_crtc->base.dev;
+ struct drm_connector *connector;
++ struct drm_connector_list_iter conn_iter;
++ struct nouveau_connector *nv_connector = NULL;
+ struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
+
+- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+- if (connector->encoder && connector->encoder->crtc == crtc)
+- return nouveau_connector(connector);
++ drm_connector_list_iter_begin(dev, &conn_iter);
++ drm_for_each_connector_iter(connector, &conn_iter) {
++ if (connector->encoder && connector->encoder->crtc == crtc) {
++ nv_connector = nouveau_connector(connector);
++ break;
++ }
+ }
++ drm_connector_list_iter_end(&conn_iter);
+
+- return NULL;
++ return nv_connector;
+ }
+
+ struct drm_connector *
+diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
+index 774b429142bc..46b8430ef4aa 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_display.c
++++ b/drivers/gpu/drm/nouveau/nouveau_display.c
+@@ -404,6 +404,7 @@ nouveau_display_init(struct drm_device *dev)
+ struct nouveau_display *disp = nouveau_display(dev);
+ struct nouveau_drm *drm = nouveau_drm(dev);
+ struct drm_connector *connector;
++ struct drm_connector_list_iter conn_iter;
+ int ret;
+
+ ret = disp->init(dev);
+@@ -411,10 +412,12 @@ nouveau_display_init(struct drm_device *dev)
+ return ret;
+
+ /* enable hotplug interrupts */
+- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++ drm_connector_list_iter_begin(dev, &conn_iter);
++ drm_for_each_connector_iter(connector, &conn_iter) {
+ struct nouveau_connector *conn = nouveau_connector(connector);
+ nvif_notify_get(&conn->hpd);
+ }
++ drm_connector_list_iter_end(&conn_iter);
+
+ /* enable flip completion events */
+ nvif_notify_get(&drm->flip);
+@@ -427,6 +430,7 @@ nouveau_display_fini(struct drm_device *dev, bool suspend)
+ struct nouveau_display *disp = nouveau_display(dev);
+ struct nouveau_drm *drm = nouveau_drm(dev);
+ struct drm_connector *connector;
++ struct drm_connector_list_iter conn_iter;
+
+ if (!suspend) {
+ if (drm_drv_uses_atomic_modeset(dev))
+@@ -439,10 +443,12 @@ nouveau_display_fini(struct drm_device *dev, bool suspend)
+ nvif_notify_put(&drm->flip);
+
+ /* disable hotplug interrupts */
+- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++ drm_connector_list_iter_begin(dev, &conn_iter);
++ drm_for_each_connector_iter(connector, &conn_iter) {
+ struct nouveau_connector *conn = nouveau_connector(connector);
+ nvif_notify_put(&conn->hpd);
+ }
++ drm_connector_list_iter_end(&conn_iter);
+
+ drm_kms_helper_poll_disable(dev);
+ disp->fini(dev);
+--
+2.18.0
+
diff --git a/patches.drivers/iio-pressure-zpa2326-Remove-always-true-check-which- b/patches.drivers/iio-pressure-zpa2326-Remove-always-true-check-which-
new file mode 100644
index 0000000000..82595cef11
--- /dev/null
+++ b/patches.drivers/iio-pressure-zpa2326-Remove-always-true-check-which-
@@ -0,0 +1,68 @@
+From f61dfff2f5b9fcb087bf5c444bc44b444709588f Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Wed, 5 Jul 2017 10:14:59 +0200
+Subject: [PATCH] iio: pressure: zpa2326: Remove always-true check which confuses gcc
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: f61dfff2f5b9fcb087bf5c444bc44b444709588f
+Patch-mainline: v4.14-rc6
+References: bsc#1051510
+
+With gcc 4.1.2:
+
+ drivers/iio/pressure/zpa2326.c: In function ‘zpa2326_wait_oneshot_completion’:
+ drivers/iio/pressure/zpa2326.c:868: warning: ‘ret’ may be used uninitialized in this function
+
+When testing for "timeout < 0", timeout is already guaranteed to be
+strict negative, so the branch is always taken, and ret is thus always
+initialized. But (some version of) gcc is not smart enough to notice.
+
+Remove the check to fix this.
+As there is no other code in between assigning the error codes and
+returning them, the error codes can be returned immediately, and the
+intermediate variable can be dropped.
+Drop the "else" to please checkpatch.
+
+Fixes: e7215fe4d51e69c9 ("iio: pressure: zpa2326: report interrupted case as failure")
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/iio/pressure/zpa2326.c | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/iio/pressure/zpa2326.c b/drivers/iio/pressure/zpa2326.c
+index ebfb1de7377f..91431454eb85 100644
+--- a/drivers/iio/pressure/zpa2326.c
++++ b/drivers/iio/pressure/zpa2326.c
+@@ -865,7 +865,6 @@ static irqreturn_t zpa2326_handle_threaded_irq(int irq, void *data)
+ static int zpa2326_wait_oneshot_completion(const struct iio_dev *indio_dev,
+ struct zpa2326_private *private)
+ {
+- int ret;
+ unsigned int val;
+ long timeout;
+
+@@ -887,14 +886,11 @@ static int zpa2326_wait_oneshot_completion(const struct iio_dev *indio_dev,
+ /* Timed out. */
+ zpa2326_warn(indio_dev, "no one shot interrupt occurred (%ld)",
+ timeout);
+- ret = -ETIME;
+- } else if (timeout < 0) {
+- zpa2326_warn(indio_dev,
+- "wait for one shot interrupt cancelled");
+- ret = -ERESTARTSYS;
++ return -ETIME;
+ }
+
+- return ret;
++ zpa2326_warn(indio_dev, "wait for one shot interrupt cancelled");
++ return -ERESTARTSYS;
+ }
+
+ static int zpa2326_init_managed_irq(struct device *parent,
+--
+2.18.0
+
diff --git a/patches.drivers/libnvdimm-label-fix-index-block-size-calculation.patch b/patches.drivers/libnvdimm-label-fix-index-block-size-calculation.patch
new file mode 100644
index 0000000000..7e9dfe5158
--- /dev/null
+++ b/patches.drivers/libnvdimm-label-fix-index-block-size-calculation.patch
@@ -0,0 +1,73 @@
+From: Dan Williams <dan.j.williams@intel.com>
+Date: Tue, 29 Aug 2017 18:28:18 -0700
+Subject: libnvdimm, label: fix index block size calculation
+Git-commit: 02881768695da29772f6f9e0d857a8637c6b0e90
+Patch-mainline: v4.14-rc1
+References: bsc#1102147
+
+The old calculation assumed that the label space was 128k and the label
+size is 128. With v1.2 labels where the label size is 256 this
+calculation will return zero. We are saved by the fact that the
+nsindex_size is always pre-initialized from a previous 128 byte
+assumption and we are lucky that the index sizes turn out the same.
+
+Fix this going forward in case we start encountering different
+geometries of label areas besides 128k.
+
+Since the label size can change from one call to the next, drop the
+caching of nsindex_size.
+
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/nvdimm/label.c | 30 ++++++++++++++++--------------
+ 1 file changed, 16 insertions(+), 14 deletions(-)
+
+--- a/drivers/nvdimm/label.c
++++ b/drivers/nvdimm/label.c
+@@ -45,12 +45,14 @@ unsigned sizeof_namespace_label(struct n
+ return ndd->nslabel_size;
+ }
+
+-size_t sizeof_namespace_index(struct nvdimm_drvdata *ndd)
++int nvdimm_num_label_slots(struct nvdimm_drvdata *ndd)
+ {
+- u32 index_span;
++ return ndd->nsarea.config_size / (sizeof_namespace_label(ndd) + 1);
++}
+
+- if (ndd->nsindex_size)
+- return ndd->nsindex_size;
++size_t sizeof_namespace_index(struct nvdimm_drvdata *ndd)
++{
++ u32 nslot, space, size;
+
+ /*
+ * The minimum index space is 512 bytes, with that amount of
+@@ -60,16 +62,16 @@ size_t sizeof_namespace_index(struct nvd
+ * starts to waste space at larger config_sizes, but it's
+ * unlikely we'll ever see anything but 128K.
+ */
+- index_span = ndd->nsarea.config_size / (sizeof_namespace_label(ndd) + 1);
+- index_span /= NSINDEX_ALIGN * 2;
+- ndd->nsindex_size = index_span * NSINDEX_ALIGN;
+-
+- return ndd->nsindex_size;
+-}
+-
+-int nvdimm_num_label_slots(struct nvdimm_drvdata *ndd)
+-{
+- return ndd->nsarea.config_size / (sizeof_namespace_label(ndd) + 1);
++ nslot = nvdimm_num_label_slots(ndd);
++ space = ndd->nsarea.config_size - nslot * sizeof_namespace_label(ndd);
++ size = ALIGN(sizeof(struct nd_namespace_index) + DIV_ROUND_UP(nslot, 8),
++ NSINDEX_ALIGN) * 2;
++ if (size <= space)
++ return size / 2;
++
++ dev_err(ndd->dev, "label area (%d) too small to host (%d byte) labels\n",
++ ndd->nsarea.config_size, sizeof_namespace_label(ndd));
++ return 0;
+ }
+
+ static int __nd_label_validate(struct nvdimm_drvdata *ndd)
diff --git a/patches.drivers/media-staging-omap4iss-Include-asm-cacheflush.h-afte b/patches.drivers/media-staging-omap4iss-Include-asm-cacheflush.h-afte
new file mode 100644
index 0000000000..2cdd00e6da
--- /dev/null
+++ b/patches.drivers/media-staging-omap4iss-Include-asm-cacheflush.h-afte
@@ -0,0 +1,65 @@
+From 0894da849f145af51bde88a6b84f95b9c9e0bc66 Mon Sep 17 00:00:00 2001
+From: Guenter Roeck <linux@roeck-us.net>
+Date: Mon, 23 Jul 2018 14:39:33 -0700
+Subject: [PATCH] media: staging: omap4iss: Include asm/cacheflush.h after generic includes
+Git-commit: 0894da849f145af51bde88a6b84f95b9c9e0bc66
+Patch-mainline: v4.18-rc7
+References: bsc#1051510
+
+Including asm/cacheflush.h first results in the following build error
+when trying to build sparc32:allmodconfig, because 'struct page' has not
+been declared, and the function declaration ends up creating a separate
+(private) declaration of struct page (as a result of function arguments
+being in the scope of the function declaration and definition, not in
+global scope).
+
+The C scoping rules do not just affect variable visibility, they also
+affect type declaration visibility.
+
+The end result is that when the actual call site is seen in
+<linux/highmem.h>, the 'struct page' type in the caller is not the same
+'struct page' that the function was declared with, resulting in:
+
+ In file included from arch/sparc/include/asm/page.h:10:0,
+ ...
+ from drivers/staging/media/omap4iss/iss_video.c:15:
+ include/linux/highmem.h: In function 'clear_user_highpage':
+ include/linux/highmem.h:137:31: error:
+ passing argument 1 of 'sparc_flush_page_to_ram' from incompatible
+ pointer type
+
+Include generic includes files first to fix the problem.
+
+Fixes: fc96d58c10162 ("[media] v4l: omap4iss: Add support for OMAP4 camera interface - Video devices")
+Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: David S. Miller <davem@davemloft.net>
+Cc: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+[ Added explanation of C scope rules - Linus ]
+
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/staging/media/omap4iss/iss_video.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/staging/media/omap4iss/iss_video.c
++++ b/drivers/staging/media/omap4iss/iss_video.c
+@@ -11,7 +11,6 @@
+ * (at your option) any later version.
+ */
+
+-#include <asm/cacheflush.h>
+ #include <linux/clk.h>
+ #include <linux/mm.h>
+ #include <linux/pagemap.h>
+@@ -24,6 +23,8 @@
+ #include <media/v4l2-ioctl.h>
+ #include <media/v4l2-mc.h>
+
++#include <asm/cacheflush.h>
++
+ #include "iss_video.h"
+ #include "iss.h"
+
diff --git a/patches.drivers/pinctrl-bcm2835-Avoid-warning-from-__irq_do_set_hand b/patches.drivers/pinctrl-bcm2835-Avoid-warning-from-__irq_do_set_hand
new file mode 100644
index 0000000000..7572f5b80d
--- /dev/null
+++ b/patches.drivers/pinctrl-bcm2835-Avoid-warning-from-__irq_do_set_hand
@@ -0,0 +1,40 @@
+From 37a2f8e5522abd8e206a0da1622034382aa6683d Mon Sep 17 00:00:00 2001
+From: Stefan Wahren <stefan.wahren@i2se.com>
+Date: Wed, 21 Jun 2017 20:20:04 +0200
+Subject: [PATCH] pinctrl: bcm2835: Avoid warning from __irq_do_set_handler
+Git-commit: 37a2f8e5522abd8e206a0da1622034382aa6683d
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+We get a warning during boot with enabled EARLY_PRINTK that
+we try to set a irq_chip without data. This is caused by ignoring
+the return value of irq_of_parse_and_map(). So avoid calling
+gpiochip_set_chained_irqchip() in error case.
+
+Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
+Fixes: 85ae9e512f43 ("pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/bcm/pinctrl-bcm2835.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+index 1eb7a1a5a4bb..230883168e99 100644
+--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+@@ -1048,6 +1048,10 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
+ for (i = 0; i < BCM2835_NUM_IRQS; i++) {
+ pc->irq[i] = irq_of_parse_and_map(np, i);
+ pc->irq_group[i] = i;
++
++ if (pc->irq[i] == 0)
++ continue;
++
+ /*
+ * Use the same handler for all groups: this is necessary
+ * since we use one gpiochip to cover all lines - the
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-imx-fix-debug-message-for-SHARE_MUX_CONF_REG b/patches.drivers/pinctrl-imx-fix-debug-message-for-SHARE_MUX_CONF_REG
new file mode 100644
index 0000000000..1f6cc31d0c
--- /dev/null
+++ b/patches.drivers/pinctrl-imx-fix-debug-message-for-SHARE_MUX_CONF_REG
@@ -0,0 +1,60 @@
+From 66b54e3a5a64925d9819eae86b8f36e90e60037f Mon Sep 17 00:00:00 2001
+From: Dong Aisheng <aisheng.dong@nxp.com>
+Date: Fri, 19 May 2017 15:05:41 +0800
+Subject: [PATCH] pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case
+Git-commit: 66b54e3a5a64925d9819eae86b8f36e90e60037f
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+The original implemented debug message does not work for
+SHARE_MUX_CONF_REG case. This patch fixes it.
+
+Fixes: bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+Acked-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/freescale/pinctrl-imx.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
+index 90a946c028ff..89421f532726 100644
+--- a/drivers/pinctrl/freescale/pinctrl-imx.c
++++ b/drivers/pinctrl/freescale/pinctrl-imx.c
+@@ -199,11 +199,13 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ reg &= ~(0x7 << 20);
+ reg |= (pin->mux_mode << 20);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
++ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
++ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
++ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
++ pin_reg->mux_reg, pin->mux_mode);
+ }
+- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+- pin_reg->mux_reg, pin->mux_mode);
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+@@ -405,11 +407,13 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ reg &= ~0xffff;
+ reg |= configs[i];
+ writel(reg, ipctl->base + pin_reg->conf_reg);
++ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
++ pin_reg->conf_reg, reg);
+ } else {
+ writel(configs[i], ipctl->base + pin_reg->conf_reg);
++ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
++ pin_reg->conf_reg, configs[i]);
+ }
+- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+- pin_reg->conf_reg, configs[i]);
+ } /* for each config */
+
+ return 0;
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-intel-Read-back-TX-buffer-state b/patches.drivers/pinctrl-intel-Read-back-TX-buffer-state
new file mode 100644
index 0000000000..2e0cf39de7
--- /dev/null
+++ b/patches.drivers/pinctrl-intel-Read-back-TX-buffer-state
@@ -0,0 +1,49 @@
+From d68b42e30bbacd24354d644f430d088435b15e83 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Thu, 24 Aug 2017 11:19:33 +0300
+Subject: [PATCH] pinctrl: intel: Read back TX buffer state
+Git-commit: d68b42e30bbacd24354d644f430d088435b15e83
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+In the same way as it's done in pinctrl-cherryview.c we would provide
+a readback TX buffer state.
+
+Fixes: 17fab473693 ("pinctrl: intel: Set pin direction properly")
+Reported-by: "Bourque, Francis" <francis.bourque@intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Tested-by: "Bourque, Francis" <francis.bourque@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/intel/pinctrl-intel.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
+index ac806891ff81..71df0f70b61f 100644
+--- a/drivers/pinctrl/intel/pinctrl-intel.c
++++ b/drivers/pinctrl/intel/pinctrl-intel.c
+@@ -751,12 +751,17 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
+ {
+ struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
+ void __iomem *reg;
++ u32 padcfg0;
+
+ reg = intel_get_padcfg(pctrl, offset, PADCFG0);
+ if (!reg)
+ return -EINVAL;
+
+- return !!(readl(reg) & PADCFG0_GPIORXSTATE);
++ padcfg0 = readl(reg);
++ if (!(padcfg0 & PADCFG0_GPIOTXDIS))
++ return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
++
++ return !!(padcfg0 & PADCFG0_GPIORXSTATE);
+ }
+
+ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-meson-gxbb-remove-non-existing-pin-GPIOX_22 b/patches.drivers/pinctrl-meson-gxbb-remove-non-existing-pin-GPIOX_22
new file mode 100644
index 0000000000..936018873a
--- /dev/null
+++ b/patches.drivers/pinctrl-meson-gxbb-remove-non-existing-pin-GPIOX_22
@@ -0,0 +1,44 @@
+From 4c8127cb523982e0a474ad80b14b665dc2f37b3b Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Wed, 7 Jun 2017 07:44:20 +0200
+Subject: [PATCH] pinctrl: meson-gxbb: remove non-existing pin GPIOX_22
+Git-commit: 4c8127cb523982e0a474ad80b14b665dc2f37b3b
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+After commit 34e61801a3b9 "pinctrl: meson-gxbb: Add missing GPIODV_18
+pin entry" I started to get the following warning:
+
+"meson-pinctrl c8834000.periphs:pinctrl@4b0: names 119 do not match
+number of GPIOs 120"
+
+It turned out that not the mentioned commit has a problem, it just
+revealed another problem which had existed before.
+
+There is no PIN GPIOX_22 on Meson GXBB.
+
+Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+index 8b716b939e30..a879cf0777ab 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+@@ -138,7 +138,6 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
+ MESON_PIN(GPIOX_19, EE_OFF),
+ MESON_PIN(GPIOX_20, EE_OFF),
+ MESON_PIN(GPIOX_21, EE_OFF),
+- MESON_PIN(GPIOX_22, EE_OFF),
+
+ MESON_PIN(GPIOCLK_0, EE_OFF),
+ MESON_PIN(GPIOCLK_1, EE_OFF),
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-I2S-pins b/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-I2S-pins
new file mode 100644
index 0000000000..d7f07f6b0f
--- /dev/null
+++ b/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-I2S-pins
@@ -0,0 +1,38 @@
+From 13586b31c749a9b6a55660be433bf077139d32b0 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 24 May 2017 10:20:38 +0200
+Subject: [PATCH] pinctrl: meson-gxl: Fix typo in AO I2S pins
+Git-commit: 13586b31c749a9b6a55660be433bf077139d32b0
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+The AO I2S pins were incorrectly defined with the EE pin offset.
+
+Fixes: 2899adf0422 ("pinctrl: meson: gxl: add i2s output pins")
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+index 2bc1e3d7cfe5..5422297bb032 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+@@ -277,8 +277,8 @@ static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) };
+ static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) };
+ static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) };
+
+-static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, EE_OFF) };
+-static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, EE_OFF) };
++static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) };
++static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) };
+
+ static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, EE_OFF) };
+ static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, EE_OFF) };
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-SPDIF-pins b/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-SPDIF-pins
new file mode 100644
index 0000000000..3e84c18c9e
--- /dev/null
+++ b/patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-SPDIF-pins
@@ -0,0 +1,38 @@
+From b11ec68fe12cf3645c64892fe30f559ce7eddfd8 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 24 May 2017 10:20:39 +0200
+Subject: [PATCH] pinctrl: meson-gxl: Fix typo in AO SPDIF pins
+Git-commit: b11ec68fe12cf3645c64892fe30f559ce7eddfd8
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+The AO SPDIF pins were incorrectly defined with the EE pin offset.
+
+Fixes: b840d649f9ec ("pinctrl: meson: gxl: add spdif output pins")
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+index 5422297bb032..73f5d3745b51 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+@@ -280,8 +280,8 @@ static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) };
+ static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) };
+ static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) };
+
+-static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, EE_OFF) };
+-static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, EE_OFF) };
++static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) };
++static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) };
+
+ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
+ GPIO_GROUP(GPIOZ_0, EE_OFF),
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-mvebu-use-correct-MPP-sel-value-for-dev-pins b/patches.drivers/pinctrl-mvebu-use-correct-MPP-sel-value-for-dev-pins
new file mode 100644
index 0000000000..bf3c26124e
--- /dev/null
+++ b/patches.drivers/pinctrl-mvebu-use-correct-MPP-sel-value-for-dev-pins
@@ -0,0 +1,71 @@
+From c3234d3b4b96dedc473d9872db46b201ca444d39 Mon Sep 17 00:00:00 2001
+From: Chris Packham <chris.packham@alliedtelesis.co.nz>
+Date: Mon, 7 May 2018 14:25:55 +1200
+Subject: [PATCH] pinctrl: mvebu: use correct MPP sel value for dev pins
+Git-commit: c3234d3b4b96dedc473d9872db46b201ca444d39
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+The "dev" function is selected with the value 0x4 not 0x01.
+
+Fixes: commit d7ae8f8dee7f ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC")
+Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+index b854f1ee5de5..e732f3a1efb7 100644
+--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+@@ -437,34 +437,34 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
+ MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad0", V_98DX3236_PLUS)),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad1", V_98DX3236_PLUS)),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad2", V_98DX3236_PLUS)),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad3", V_98DX3236_PLUS)),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad4", V_98DX3236_PLUS)),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad5", V_98DX3236_PLUS)),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad6", V_98DX3236_PLUS)),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "ad7", V_98DX3236_PLUS)),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "a0", V_98DX3236_PLUS)),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+- MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "a1", V_98DX3236_PLUS)),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-nand-meson-gxbb-fix-missing-data-pins b/patches.drivers/pinctrl-nand-meson-gxbb-fix-missing-data-pins
new file mode 100644
index 0000000000..d30599b320
--- /dev/null
+++ b/patches.drivers/pinctrl-nand-meson-gxbb-fix-missing-data-pins
@@ -0,0 +1,39 @@
+From e3678b64701e4aa48b1d91a494206dea9ec8bafa Mon Sep 17 00:00:00 2001
+From: Yixun Lan <yixun.lan@amlogic.com>
+Date: Wed, 9 May 2018 22:08:26 +0000
+Subject: [PATCH] pinctrl: nand: meson-gxbb: fix missing data pins
+Git-commit: e3678b64701e4aa48b1d91a494206dea9ec8bafa
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+The data pin 0-7 of the NAND controller are actually missing from
+the nand pinctrl group, so we fix it here.
+
+Fixes: cd1e3b01c7d3 ("pinctrl: amlogic: gxbb: add nand pins")
+Reported-by: Liang Yang <liang.yang@amlogic.com>
+Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+index 9079020259c5..2c97a2e07a5f 100644
+--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
++++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+@@ -627,8 +627,8 @@ static const char * const sdio_groups[] = {
+ };
+
+ static const char * const nand_groups[] = {
+- "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+- "nand_wen_clk", "nand_ren_wr", "nand_dqs",
++ "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
++ "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+ };
+
+ static const char * const uart_a_groups[] = {
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-nsp-Fix-potential-NULL-dereference b/patches.drivers/pinctrl-nsp-Fix-potential-NULL-dereference
new file mode 100644
index 0000000000..407d6b2b3c
--- /dev/null
+++ b/patches.drivers/pinctrl-nsp-Fix-potential-NULL-dereference
@@ -0,0 +1,50 @@
+From c29e9da56bebb4c2c794e871b0dc0298bbf08142 Mon Sep 17 00:00:00 2001
+From: Wei Yongjun <weiyongjun1@huawei.com>
+Date: Wed, 11 Jul 2018 12:34:21 +0000
+Subject: [PATCH] pinctrl: nsp: Fix potential NULL dereference
+Git-commit: c29e9da56bebb4c2c794e871b0dc0298bbf08142
+Patch-mainline: v4.18-rc6
+References: bsc#1051510
+
+platform_get_resource() may fail and return NULL, so we should
+better check it's return value to avoid a NULL pointer dereference
+a bit later in the code.
+
+This is detected by Coccinelle semantic patch.
+
+@@
+expression pdev, res, n, t, e, e1, e2;
+@@
+
+res = platform_get_resource(pdev, t, n);
++ if (!res)
++ return -EINVAL;
+... when != res == NULL
+e = devm_ioremap_nocache(e1, res->start, e2);
+
+Fixes: cc4fa83f66e9 ("pinctrl: nsp: add pinmux driver support for Broadcom NSP SoC")
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Reviewed-by: Ray Jui <ray.jui@broadcom.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/bcm/pinctrl-nsp-mux.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+index 5cd8166fbbc8..87618a4e90e4 100644
+--- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
++++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+@@ -577,6 +577,8 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
+ return PTR_ERR(pinctrl->base0);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!res)
++ return -EINVAL;
+ pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (!pinctrl->base1) {
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-pinctrl-single-Fix-pcs_request_gpio-when-bit b/patches.drivers/pinctrl-pinctrl-single-Fix-pcs_request_gpio-when-bit
new file mode 100644
index 0000000000..8df7b22e8c
--- /dev/null
+++ b/patches.drivers/pinctrl-pinctrl-single-Fix-pcs_request_gpio-when-bit
@@ -0,0 +1,58 @@
+From 45dcb54f014d3d1f5cc3919b5f0c97087d7cb3dd Mon Sep 17 00:00:00 2001
+From: David Lechner <david@lechnology.com>
+Date: Mon, 19 Feb 2018 15:57:07 -0600
+Subject: [PATCH] pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0
+Git-commit: 45dcb54f014d3d1f5cc3919b5f0c97087d7cb3dd
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+This fixes pcs_request_gpio() in the pinctrl-single driver when
+bits_per_mux != 0. It appears this was overlooked when the multiple
+pins per register feature was added.
+
+Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
+Signed-off-by: David Lechner <david@lechnology.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/pinctrl-single.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
+index cec75379f936..a7c5eb39b1eb 100644
+--- a/drivers/pinctrl/pinctrl-single.c
++++ b/drivers/pinctrl/pinctrl-single.c
+@@ -391,9 +391,25 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
+ || pin < frange->offset)
+ continue;
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+- data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
+- data |= frange->gpiofunc;
+- pcs->write(data, pcs->base + pin * mux_bytes);
++
++ if (pcs->bits_per_mux) {
++ int byte_num, offset, pin_shift;
++
++ byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
++ offset = (byte_num / mux_bytes) * mux_bytes;
++ pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
++ pcs->bits_per_pin;
++
++ data = pcs->read(pcs->base + offset);
++ data &= ~(pcs->fmask << pin_shift);
++ data |= frange->gpiofunc << pin_shift;
++ pcs->write(data, pcs->base + offset);
++ } else {
++ data = pcs->read(pcs->base + pin * mux_bytes);
++ data &= ~pcs->fmask;
++ data |= frange->gpiofunc;
++ pcs->write(data, pcs->base + pin * mux_bytes);
++ }
+ break;
+ }
+ return 0;
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_ b/patches.drivers/pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_
new file mode 100644
index 0000000000..ed933956b6
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_
@@ -0,0 +1,55 @@
+From 66e9fe1ec73929a9f7326856699d262bab8e9fb0 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 12 Mar 2018 13:13:47 +0100
+Subject: [PATCH] pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group
+Git-commit: 66e9fe1ec73929a9f7326856699d262bab8e9fb0
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+The pin controller drivers for all R-Car Gen2 SoCs have entries for the
+EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.
+
+Add the missing pin to restore consistency.
+
+Note that technically TX_ER is an optional signal in the MII bus, and
+thus could have its own group, but this is currently not supported by
+any R-Car Gen2 pin controller driver.
+
+Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+index b769c05480da..f6332f247368 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+@@ -1835,8 +1835,8 @@ static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(2, 2),
+
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+- RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
+- RCAR_GP_PIN(3, 12),
++ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
+ };
+ static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+@@ -1846,8 +1846,8 @@ static const unsigned int avb_mii_mux[] = {
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+- AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
+- AVB_COL_MARK,
++ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
++ AVB_TX_CLK_MARK, AVB_COL_MARK,
+ };
+ static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi b/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi
new file mode 100644
index 0000000000..b12e67a92b
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi
@@ -0,0 +1,189 @@
+From 740a4a3aa76ed46a425909ba34cc82c4ddb91252 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:02 +0100
+Subject: [PATCH] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI pins group
+Git-commit: 740a4a3aa76ed46a425909ba34cc82c4ddb91252
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
+for SSI pins group.
+
+This is a correction because MOD_SEL register specification for R8A7795
+ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 +++++++++++++++++------------------
+ 1 file changed, 20 insertions(+), 20 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -1,7 +1,7 @@
+ /*
+ * R8A7795 ES2.0+ processor support - PFC hardware block.
+ *
+- * Copyright (C) 2015-2016 Renesas Electronics Corporation
++ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -472,7 +472,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28)
+ #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
+ #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
+ #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
++#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
+ #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
+ #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
+ #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
+@@ -1220,7 +1220,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
+ PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+- PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
+ PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
+@@ -1228,14 +1228,14 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
+ PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
+- PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
+
+ PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
+ PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
+- PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
+@@ -1243,7 +1243,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
+ PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
+- PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
+@@ -1252,7 +1252,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
+ PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
+- PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
+ PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
+@@ -1267,7 +1267,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+- PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
+ PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
+ PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
+@@ -1276,7 +1276,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+- PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
+ PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
+ PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
+@@ -1304,10 +1304,10 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
+
+ /* IPSR15 */
+- PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
+
+- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
+- PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
++ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
+
+ PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
+ PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
+@@ -1396,11 +1396,11 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
+ PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
+
+- PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
+ PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
+ PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
+- PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
+ PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
+ PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
+ PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
+@@ -1432,7 +1432,7 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
+ PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
+- PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
+@@ -1442,7 +1442,7 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
+ PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
+- PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
++ PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
+ PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
+@@ -1452,7 +1452,7 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
+ PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
+- PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
+@@ -1464,7 +1464,7 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
+ PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
+- PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
+ PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
+ PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
+@@ -1475,7 +1475,7 @@ static const u16 pinmux_data[] = {
+ /* IPSR18 */
+ PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN),
+ PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
+- PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
+@@ -1485,7 +1485,7 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC),
+ PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
+- PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
++ PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
+ PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
+ PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu b/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu
new file mode 100644
index 0000000000..fe833102ee
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu
@@ -0,0 +1,87 @@
+From 7716c51b5e96a289df954b1fe91faf711fb51da9 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 12:16:48 +0900
+Subject: [PATCH] pinctrl: sh-pfc: r8a7795: Fix to delete A20..A25 pins function definitions
+Git-commit: 7716c51b5e96a289df954b1fe91faf711fb51da9
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+This patch fixes the macro definitions of A20..A25 pins function deleted.
+
+This is a correction because IPSR register specification for R8A7795 ES2.0
+SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -218,12 +218,12 @@
+ #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -652,7 +652,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
+ PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
+- PINMUX_IPSR_GPSR(IP1_7_4, A25),
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
+@@ -660,7 +659,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
+ PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
+- PINMUX_IPSR_GPSR(IP1_11_8, A24),
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
+@@ -668,7 +666,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
+ PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
+- PINMUX_IPSR_GPSR(IP1_15_12, A23),
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
+@@ -677,18 +674,15 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
+ PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
+- PINMUX_IPSR_GPSR(IP1_19_16, A22),
+ PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
+- PINMUX_IPSR_GPSR(IP1_23_20, A21),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
+- PINMUX_IPSR_GPSR(IP1_27_24, A20),
+ PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register
new file mode 100644
index 0000000000..2ab403e02a
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register
@@ -0,0 +1,109 @@
+From 8b446c4d388dc25d325f63a6642391f00ec44c4c Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Fri, 16 Feb 2018 15:25:04 +0100
+Subject: [PATCH] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for NDFC pins group
+Git-commit: 8b446c4d388dc25d325f63a6642391f00ec44c4c
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
+NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
+definition name to SEL_NDFC.
+
+This is a correction to the incorrect implementation of MOD_SEL register
+pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
+User's Manual Rev.0.53E.
+
+Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
+Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -504,7 +504,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28)
+ #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
+ #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
+ #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
++#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+ #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
+ #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
+ #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
+@@ -1018,35 +1018,35 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
+ PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
+- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
++ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
+ PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
+ PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
+- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
++ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
+ PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
+- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
++ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
+ PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
+- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
++ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
+ PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
+- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
++ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
+
+@@ -1112,16 +1112,20 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
+
+ PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
++ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
+
+ PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
++ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
+
+ PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
++ PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
+
+ PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
++ PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
+
+ PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
+@@ -1266,7 +1270,7 @@ static const u16 pinmux_data[] = {
+ /* IPSR14 */
+ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
+ PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
+- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
++ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu
new file mode 100644
index 0000000000..0f306bdd4b
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu
@@ -0,0 +1,87 @@
+From fbd81e345c9393b96e8ad252eef390f8c6f9cf60 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 16 Nov 2017 12:17:18 +0900
+Subject: [PATCH] pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25 pins function definitions
+Git-commit: fbd81e345c9393b96e8ad252eef390f8c6f9cf60
+Patch-mainline: v4.16-rc1
+References: bsc#1051510
+
+This patch fixes the macro definitions of A20..A25 pins function deleted.
+
+This is a correction because IPSR register specification for R8A7796 SoC
+was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
+
+Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -224,12 +224,12 @@
+ #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
++#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -656,7 +656,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
+ PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
+- PINMUX_IPSR_GPSR(IP1_7_4, A25),
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
+ PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
+@@ -664,7 +663,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
+ PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
+- PINMUX_IPSR_GPSR(IP1_11_8, A24),
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
+@@ -672,7 +670,6 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
+ PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
+- PINMUX_IPSR_GPSR(IP1_15_12, A23),
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
+@@ -680,18 +677,15 @@ static const u16 pinmux_data[] = {
+
+ PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
+ PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
+- PINMUX_IPSR_GPSR(IP1_19_16, A22),
+ PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
+- PINMUX_IPSR_GPSR(IP1_23_20, A21),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
+ PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+
+ PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
+- PINMUX_IPSR_GPSR(IP1_27_24, A20),
+ PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+
diff --git a/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-FSCLKST-pin-and b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-FSCLKST-pin-and
new file mode 100644
index 0000000000..eea1e42ee5
--- /dev/null
+++ b/patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-FSCLKST-pin-and
@@ -0,0 +1,66 @@
+From 8921778241188e9752aeac2aa54584795c043ce0 Mon Sep 17 00:00:00 2001
+From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Date: Thu, 13 Jul 2017 01:55:43 +0900
+Subject: [PATCH] pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions
+Git-commit: 8921778241188e9752aeac2aa54584795c043ce0
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+This patch fixes the macro definitions of FSCLKST pins function and IPSR7
+bit[15:12] register deleted.
+
+This is a correction because IPSR register specification for R8A7796 SoC
+was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later.
+
+Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
+Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
+Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+index d878638b8306..a843368baae0 100644
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+@@ -278,7 +278,6 @@
+ #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+-#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+ #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+@@ -419,7 +418,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3
+ FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+ FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+ FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+-FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
++FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
+ FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+ FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+ FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+@@ -990,8 +989,6 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
+ PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
+
+- PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
+-
+ PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
+ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
+ PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
+@@ -4927,7 +4924,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+- IP7_15_12
++ /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-sunxi-fix-V3s-pinctrl-driver-IRQ-bank-base b/patches.drivers/pinctrl-sunxi-fix-V3s-pinctrl-driver-IRQ-bank-base
new file mode 100644
index 0000000000..4c02afd65a
--- /dev/null
+++ b/patches.drivers/pinctrl-sunxi-fix-V3s-pinctrl-driver-IRQ-bank-base
@@ -0,0 +1,39 @@
+From f547b3de907d45683fc4ff15315e11cb0a3df32d Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 1 Aug 2017 22:54:16 +0800
+Subject: [PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base
+Git-commit: f547b3de907d45683fc4ff15315e11cb0a3df32d
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The V3s pin controller doesn't have the bank 0 (starts at address
+0x200), which is like A33. However, this is not worked around when
+developing the driver, which makes IRQ not working.
+
+Fix the IRQ bank base.
+
+Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+index c86d3c42a905..496ba34e1f5f 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+@@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
+ .pins = sun8i_v3s_pins,
+ .npins = ARRAY_SIZE(sun8i_v3s_pins),
+ .irq_banks = 2,
++ .irq_bank_base = 1,
+ .irq_read_needs_mux = true
+ };
+
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-sunxi-fix-wrong-irq_banks-number-for-H5-pinc b/patches.drivers/pinctrl-sunxi-fix-wrong-irq_banks-number-for-H5-pinc
new file mode 100644
index 0000000000..efc9a82969
--- /dev/null
+++ b/patches.drivers/pinctrl-sunxi-fix-wrong-irq_banks-number-for-H5-pinc
@@ -0,0 +1,82 @@
+From 1899ccc041069e86557d6952d97f3b41b7333d87 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Fri, 11 Aug 2017 22:27:34 +0800
+Subject: [PATCH] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl
+Git-commit: 1899ccc041069e86557d6952d97f3b41b7333d87
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The pin controller of Allwinner H5 has three IRQ banks, however in old
+versions of drivers and device trees, only two are set, which makes
+PG bank IRQ not available.
+
+If it's directly set to 3, the old device trees will fail to boot.
+
+Add a workaround (and a warning) for older device trees, and allow new
+device trees to use correct 3 IRQ banks.
+
+Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Acked-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 26 ++++++++++++++++++++---
+ 1 file changed, 23 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
+index ccf9419e9418..97b48336f84a 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
+@@ -19,6 +19,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/of_irq.h>
+ #include <linux/pinctrl/pinctrl.h>
+
+ #include "pinctrl-sunxi.h"
+@@ -530,17 +531,36 @@ static const struct sunxi_desc_pin sun50i_h5_pins[] = {
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
+ };
+
+-static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
++static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
+ .pins = sun50i_h5_pins,
+ .npins = ARRAY_SIZE(sun50i_h5_pins),
+ .irq_banks = 2,
+ .irq_read_needs_mux = true
+ };
+
++static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
++ .pins = sun50i_h5_pins,
++ .npins = ARRAY_SIZE(sun50i_h5_pins),
++ .irq_banks = 3,
++ .irq_read_needs_mux = true
++};
++
+ static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
+ {
+- return sunxi_pinctrl_init(pdev,
+- &sun50i_h5_pinctrl_data);
++ switch (of_irq_count(pdev->dev.of_node)) {
++ case 2:
++ dev_warn(&pdev->dev,
++ "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
++ dev_warn(&pdev->dev,
++ "Please update the device tree, otherwise PG bank IRQ won't work.\n");
++ return sunxi_pinctrl_init(pdev,
++ &sun50i_h5_pinctrl_data_broken);
++ case 3:
++ return sunxi_pinctrl_init(pdev,
++ &sun50i_h5_pinctrl_data);
++ default:
++ return -EINVAL;
++ }
+ }
+
+ static const struct of_device_id sun50i_h5_pinctrl_match[] = {
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-uniphier-fix-members-of-rmii-group-for-Pro4 b/patches.drivers/pinctrl-uniphier-fix-members-of-rmii-group-for-Pro4
new file mode 100644
index 0000000000..d5575c2eac
--- /dev/null
+++ b/patches.drivers/pinctrl-uniphier-fix-members-of-rmii-group-for-Pro4
@@ -0,0 +1,37 @@
+From 12219fd2bf5304293f5cf014cbc2e6bfdfcab7b5 Mon Sep 17 00:00:00 2001
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Date: Mon, 28 Aug 2017 11:21:26 +0900
+Subject: [PATCH] pinctrl: uniphier: fix members of rmii group for Pro4
+Git-commit: 12219fd2bf5304293f5cf014cbc2e6bfdfcab7b5
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+The ether_rmii_groups should have "ether_rmii" and "ether_rmiib" as
+members. This patch replaces to them.
+
+Fixes: 1e359ab1285e ("pinctrl: uniphier: add Ethernet pin-mux settings")
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+index ed46d110f946..603204a00213 100644
+--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
++++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+@@ -1159,7 +1159,7 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
+ static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+ static const char * const ether_mii_groups[] = {"ether_mii"};
+ static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+-static const char * const ether_rmii_groups[] = {"ether_rgmii", "ether_rgmiib"};
++static const char * const ether_rmii_groups[] = {"ether_rmii", "ether_rmiib"};
+ static const char * const i2c0_groups[] = {"i2c0"};
+ static const char * const i2c1_groups[] = {"i2c1"};
+ static const char * const i2c2_groups[] = {"i2c2"};
+--
+2.18.0
+
diff --git a/patches.drivers/pinctrl-uniphier-fix-pin_config_get-for-input-enable b/patches.drivers/pinctrl-uniphier-fix-pin_config_get-for-input-enable
new file mode 100644
index 0000000000..118017a7b9
--- /dev/null
+++ b/patches.drivers/pinctrl-uniphier-fix-pin_config_get-for-input-enable
@@ -0,0 +1,73 @@
+From e3829d15460feb884805012c72ec4a17402822eb Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Mon, 31 Jul 2017 15:21:07 +0900
+Subject: [PATCH] pinctrl: uniphier: fix pin_config_get() for input-enable
+Git-commit: e3829d15460feb884805012c72ec4a17402822eb
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
+located across multiple registers. So, the register offset must be
+taken into account. Otherwise, wrong input-enable status is displayed.
+
+While we here, rename the macro because it is a base address.
+
+Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs")
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+index c649e835bd54..f2f0f9dcfec3 100644
+--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
++++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+@@ -32,7 +32,7 @@
+ #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
+ #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
+ #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
+-#define UNIPHIER_PINCTRL_IECTRL 0x1d00
++#define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00
+
+ struct uniphier_pinctrl_priv {
+ struct pinctrl_desc pctldesc;
+@@ -252,18 +252,21 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
+ {
+ struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
+- unsigned int val;
++ unsigned int reg, mask, val;
+ int ret;
+
+ if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
+ /* This pin is always input-enabled. */
+ return 0;
+
+- ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
++ reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
++ mask = BIT(iectrl % 32);
++
++ ret = regmap_read(priv->regmap, reg, &val);
+ if (ret)
+ return ret;
+
+- return val & BIT(iectrl) ? 0 : -EINVAL;
++ return val & mask ? 0 : -EINVAL;
+ }
+
+ static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
+@@ -456,7 +459,7 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
+ if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
+ return enable ? 0 : -EINVAL;
+
+- reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
++ reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
+ mask = BIT(iectrl % 32);
+
+ return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
+--
+2.18.0
+
diff --git a/patches.drivers/power-gemini-poweroff-Avoid-spurious-poweroff b/patches.drivers/power-gemini-poweroff-Avoid-spurious-poweroff
new file mode 100644
index 0000000000..ca302592c4
--- /dev/null
+++ b/patches.drivers/power-gemini-poweroff-Avoid-spurious-poweroff
@@ -0,0 +1,87 @@
+From 4a9be940551ab664918ac089b92c47d74e6cb8e7 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 22 Feb 2018 08:45:21 +0100
+Subject: [PATCH] power: gemini-poweroff: Avoid spurious poweroff
+Git-commit: 4a9be940551ab664918ac089b92c47d74e6cb8e7
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+On the D-Link DIR-685 we get spurious poweroff from
+infrared. Since that block (CIR) doesn't even have a
+driver this can be safely ignored, we can revisit this
+code once we have a device supporting CIR.
+
+On the D-Link DNS-313 we get spurious poweroff from
+the power button. This appears to be an initialization
+Issue: we need to enable the block (start the state
+machine) before we clear any dangling IRQ.
+
+This patch fixes both issues.
+
+Fixes: f7a388d6cd1c ("power: reset: Add a driver for the Gemini poweroff")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/power/reset/gemini-poweroff.c | 30 +++++++++++++++------------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/power/reset/gemini-poweroff.c b/drivers/power/reset/gemini-poweroff.c
+index ff75af5abbc5..2ac291af1265 100644
+--- a/drivers/power/reset/gemini-poweroff.c
++++ b/drivers/power/reset/gemini-poweroff.c
+@@ -47,8 +47,12 @@ static irqreturn_t gemini_powerbutton_interrupt(int irq, void *data)
+ val &= 0x70U;
+ switch (val) {
+ case GEMINI_STAT_CIR:
+- dev_info(gpw->dev, "infrared poweroff\n");
+- orderly_poweroff(true);
++ /*
++ * We do not yet have a driver for the infrared
++ * controller so it can cause spurious poweroff
++ * events. Ignore those for now.
++ */
++ dev_info(gpw->dev, "infrared poweroff - ignored\n");
+ break;
+ case GEMINI_STAT_RTC:
+ dev_info(gpw->dev, "RTC poweroff\n");
+@@ -116,7 +120,17 @@ static int gemini_poweroff_probe(struct platform_device *pdev)
+ return -ENODEV;
+ }
+
+- /* Clear the power management IRQ */
++ /*
++ * Enable the power controller. This is crucial on Gemini
++ * systems: if this is not done, pressing the power button
++ * will result in unconditional poweroff without any warning.
++ * This makes the kernel handle the poweroff.
++ */
++ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
++ val |= GEMINI_CTRL_ENABLE;
++ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
++
++ /* Now that the state machine is active, clear the IRQ */
+ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+ val |= GEMINI_CTRL_IRQ_CLR;
+ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+@@ -129,16 +143,6 @@ static int gemini_poweroff_probe(struct platform_device *pdev)
+ pm_power_off = gemini_poweroff;
+ gpw_poweroff = gpw;
+
+- /*
+- * Enable the power controller. This is crucial on Gemini
+- * systems: if this is not done, pressing the power button
+- * will result in unconditional poweroff without any warning.
+- * This makes the kernel handle the poweroff.
+- */
+- val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+- val |= GEMINI_CTRL_ENABLE;
+- writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+-
+ dev_info(dev, "Gemini poweroff driver registered\n");
+
+ return 0;
+--
+2.18.0
+
diff --git a/patches.drivers/power-supply-act8945a_charger-fix-of_irq_get-error-c b/patches.drivers/power-supply-act8945a_charger-fix-of_irq_get-error-c
new file mode 100644
index 0000000000..5fdf2a9816
--- /dev/null
+++ b/patches.drivers/power-supply-act8945a_charger-fix-of_irq_get-error-c
@@ -0,0 +1,46 @@
+From 648b8eba20d0bdce9de41df97677e70aa53693ea Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Sun, 16 Jul 2017 20:52:20 +0300
+Subject: [PATCH] power: supply: act8945a_charger: fix of_irq_get() error check
+Git-commit: 648b8eba20d0bdce9de41df97677e70aa53693ea
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+of_irq_get() may return any negative error number as well as 0 on failure,
+while the driver only checks for -EPROBE_DEFER, blithely continuing with
+the call to devm_request_irq() -- that function expects *unsigned int*,
+so would probably fail anyway when a large IRQ number resulting from a
+conversion of a negative error number is passed to it... This, however,
+is incorrect behavior -- error number is not IRQ number.
+
+Check for 'irq <= 0' instead and return -ENXIO from probe if of_irq_get()
+returned 0.
+
+Fixes: a09209acd6a8 ("power: supply: act8945a_charger: Add status change update support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/power/supply/act8945a_charger.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/act8945a_charger.c b/drivers/power/supply/act8945a_charger.c
+index d1eb2e359532..8e117b31ba79 100644
+--- a/drivers/power/supply/act8945a_charger.c
++++ b/drivers/power/supply/act8945a_charger.c
+@@ -596,9 +596,9 @@ static int act8945a_charger_probe(struct platform_device *pdev)
+ return ret;
+
+ irq = of_irq_get(pdev->dev.of_node, 0);
+- if (irq == -EPROBE_DEFER) {
++ if (irq <= 0) {
+ dev_err(&pdev->dev, "failed to find IRQ number\n");
+- return -EPROBE_DEFER;
++ return irq ?: -ENXIO;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, act8945a_status_changed,
+--
+2.18.0
+
diff --git a/patches.drivers/power-supply-cpcap-charger-add-OMAP_USB2-dependency b/patches.drivers/power-supply-cpcap-charger-add-OMAP_USB2-dependency
new file mode 100644
index 0000000000..e6676c67f7
--- /dev/null
+++ b/patches.drivers/power-supply-cpcap-charger-add-OMAP_USB2-dependency
@@ -0,0 +1,43 @@
+From 8b35bf5927b1e89e9b2f9ddbd701bd9b27456e78 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 21 Jul 2017 18:14:37 +0200
+Subject: [PATCH] power: supply: cpcap-charger: add OMAP_USB2 dependency
+Git-commit: 8b35bf5927b1e89e9b2f9ddbd701bd9b27456e78
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+When CONFIG_OMAP_USB2 is set to 'm' and the charger driver is built-in,
+we get this link failure:
+
+Drivers/power/supply/cpcap-charger.o: In function `cpcap_charger_probe':
+cpcap-charger.c:(.text+0x48c): undefined reference to `omap_usb2_set_comparator'
+Drivers/power/supply/cpcap-charger.o: In function `cpcap_charger_remove':
+cpcap-charger.c:(.text+0x774): undefined reference to `omap_usb2_set_comparator'
+
+This adds a dependency to prevent that problem, while still allowing
+compile-testing with the OMAP_USB2 driver completely disabled.
+
+Fixes: 0c9888e3c192 ("power: supply: cpcap-charger: Add minimal CPCAP PMIC battery charger")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/power/supply/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
+index 969f5005669c..765f9ac0a4e7 100644
+--- a/drivers/power/supply/Kconfig
++++ b/drivers/power/supply/Kconfig
+@@ -365,6 +365,7 @@ config BATTERY_RX51
+ config CHARGER_CPCAP
+ tristate "CPCAP PMIC Charger Driver"
+ depends on MFD_CPCAP && IIO
++ depends on OMAP_USB2 || (!OMAP_USB2 && COMPILE_TEST)
+ default MFD_CPCAP
+ help
+ Say Y to enable support for CPCAP PMIC charger driver for Motorola
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-meson-Fix-allocation-of-PWM-channel-array b/patches.drivers/pwm-meson-Fix-allocation-of-PWM-channel-array
new file mode 100644
index 0000000000..304d44b133
--- /dev/null
+++ b/patches.drivers/pwm-meson-Fix-allocation-of-PWM-channel-array
@@ -0,0 +1,51 @@
+From 735596ca8a1cd3de87f0ff05213bb2ee0495ccbd Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 28 Apr 2018 23:25:21 +0200
+Subject: [PATCH] pwm: meson: Fix allocation of PWM channel array
+Git-commit: 735596ca8a1cd3de87f0ff05213bb2ee0495ccbd
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+Using the pwm-meson driver on the 32-bit SoCs causes memory corruption.
+The result are some hard-to-explain errors, for example
+devm_clk_register() crashes with a NULL dereference somewhere deep in
+the common clock framework code. In some cases the kernel even refused
+to boot when any of the PWM controllers were enabled on Meson8b.
+
+The root cause is an incorrect memory size in the devm_kcalloc() call in
+meson_pwm_probe(). The code allocates an array of meson_pwm_channel
+structs, but the size given is the size of the meson_pwm struct (which
+seems like a small copy-and-paste error, as meson_pwm is allocated a few
+lines above).
+
+Even with this typo the code seemed to work fine on the 64-bit GX SoCs
+(maybe due to the structs having the same size in the compiled result,
+but I haven't checked this further).
+
+Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/pwm-meson.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
+index 0767deba8e62..822860b4801a 100644
+--- a/drivers/pwm/pwm-meson.c
++++ b/drivers/pwm/pwm-meson.c
+@@ -541,8 +541,8 @@ static int meson_pwm_probe(struct platform_device *pdev)
+ meson->data = of_device_get_match_data(&pdev->dev);
+ meson->inverter_mask = BIT(meson->chip.npwm) - 1;
+
+- channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, sizeof(*meson),
+- GFP_KERNEL);
++ channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
++ sizeof(*channels), GFP_KERNEL);
+ if (!channels)
+ return -ENOMEM;
+
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-meson-Improve-PWM-calculation-precision b/patches.drivers/pwm-meson-Improve-PWM-calculation-precision
new file mode 100644
index 0000000000..afc6cdf0e8
--- /dev/null
+++ b/patches.drivers/pwm-meson-Improve-PWM-calculation-precision
@@ -0,0 +1,79 @@
+From fd7b2be8cbcf6cd6d9c9e843ffff36fb91388e51 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 8 Jun 2017 14:24:16 +0200
+Subject: [PATCH] pwm: meson: Improve PWM calculation precision
+Git-commit: fd7b2be8cbcf6cd6d9c9e843ffff36fb91388e51
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+When using input clocks with high rates, such as clk81 (166MHz), the
+fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error.
+
+Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000 fin_ns = 5,9999999
+
+which is, of course, rounded down to 5. This introduces an error of ~20%
+on the period requested from the PWM.
+
+This patch uses ps instead of ns (and 64 bit integers) to perform the
+calculation. This should give a good enough precision.
+
+Fixes: 211ed630753d ("pwm: Add support for Meson PWM Controller")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Acked-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+
+squash! pwm: meson: Improve pwm calculation precision
+
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/pwm-meson.c | 16 ++++++++++------
+ 1 file changed, 10 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
+index defc27d880f3..cb845edfe2b4 100644
+--- a/drivers/pwm/pwm-meson.c
++++ b/drivers/pwm/pwm-meson.c
+@@ -163,7 +163,8 @@ static int meson_pwm_calc(struct meson_pwm *meson,
+ unsigned int duty, unsigned int period)
+ {
+ unsigned int pre_div, cnt, duty_cnt;
+- unsigned long fin_freq = -1, fin_ns;
++ unsigned long fin_freq = -1;
++ u64 fin_ps;
+
+ if (~(meson->inverter_mask >> id) & 0x1)
+ duty = period - duty;
+@@ -179,13 +180,15 @@ static int meson_pwm_calc(struct meson_pwm *meson,
+ }
+
+ dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
+- fin_ns = NSEC_PER_SEC / fin_freq;
++ fin_ps = (u64)NSEC_PER_SEC * 1000;
++ do_div(fin_ps, fin_freq);
+
+ /* Calc pre_div with the period */
+ for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
+- cnt = DIV_ROUND_CLOSEST(period, fin_ns * (pre_div + 1));
+- dev_dbg(meson->chip.dev, "fin_ns=%lu pre_div=%u cnt=%u\n",
+- fin_ns, pre_div, cnt);
++ cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
++ fin_ps * (pre_div + 1));
++ dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
++ fin_ps, pre_div, cnt);
+ if (cnt <= 0xffff)
+ break;
+ }
+@@ -208,7 +211,8 @@ static int meson_pwm_calc(struct meson_pwm *meson,
+ channel->lo = cnt;
+ } else {
+ /* Then check is we can have the duty with the same pre_div */
+- duty_cnt = DIV_ROUND_CLOSEST(duty, fin_ns * (pre_div + 1));
++ duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
++ fin_ps * (pre_div + 1));
+ if (duty_cnt > 0xffff) {
+ dev_err(meson->chip.dev, "unable to get duty cycle\n");
+ return -EINVAL;
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-stm32-Enforce-dependency-on-CONFIG_MFD_STM32_TIM b/patches.drivers/pwm-stm32-Enforce-dependency-on-CONFIG_MFD_STM32_TIM
new file mode 100644
index 0000000000..cd89eacbae
--- /dev/null
+++ b/patches.drivers/pwm-stm32-Enforce-dependency-on-CONFIG_MFD_STM32_TIM
@@ -0,0 +1,44 @@
+From d968e5041fefbc7c4d545cabbc692b11cc49050d Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 25 May 2018 18:04:54 +0200
+Subject: [PATCH] pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS
+Git-commit: d968e5041fefbc7c4d545cabbc692b11cc49050d
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+When compile-testing the PWM driver without also enabling the
+stm32_timers MFD, we run into a link error:
+
+ drivers/pwm/pwm-stm32.o: In function `stm32_pwm_raw_capture.isra.6':
+ pwm-stm32.c:(.text+0xcb0): undefined reference to `stm32_timers_dma_burst_read'
+
+We don't need the '|| COMPILE_TEST' here, since stm32_timers itself
+can be built with CONFIG_COMPILE_TEST on all architectures, so we do
+get the coverage through allmodconfig and randconfig builds even
+when we make it a hard dependency.
+
+Fixes: 7edf7369205b ("pwm: Add driver for STM32 plaftorm")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index 4635cb35008c..a4d262db9945 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -401,7 +401,7 @@ config PWM_STI
+
+ config PWM_STM32
+ tristate "STMicroelectronics STM32 PWM"
+- depends on MFD_STM32_TIMERS || COMPILE_TEST
++ depends on MFD_STM32_TIMERS
+ help
+ Generic PWM framework driver for STM32 SoCs.
+
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-stm32-Remove-unused-struct-device b/patches.drivers/pwm-stm32-Remove-unused-struct-device
new file mode 100644
index 0000000000..4d76f6b055
--- /dev/null
+++ b/patches.drivers/pwm-stm32-Remove-unused-struct-device
@@ -0,0 +1,35 @@
+From 3af0bdd1d027292d40c7f1d13420bc298b3e1660 Mon Sep 17 00:00:00 2001
+From: Fabrice Gasnier <fabrice.gasnier@st.com>
+Date: Wed, 14 Feb 2018 11:04:32 +0100
+Subject: [PATCH] pwm: stm32: Remove unused struct device
+Git-commit: 3af0bdd1d027292d40c7f1d13420bc298b3e1660
+Patch-mainline: v4.17-rc1
+References: bsc#1051510
+
+dev is never assigned or used. Remove it.
+
+Fixes: 7edf7369205b ("pwm: Add driver for STM32 plaftorm")
+Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
+Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/pwm-stm32.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
+index be56d7af89c9..014e2a759fa6 100644
+--- a/drivers/pwm/pwm-stm32.c
++++ b/drivers/pwm/pwm-stm32.c
+@@ -20,7 +20,6 @@
+
+ struct stm32_pwm {
+ struct pwm_chip chip;
+- struct device *dev;
+ struct clk *clk;
+ struct regmap *regmap;
+ u32 max_arr;
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-tiehrpwm-Fix-runtime-PM-imbalance-at-unbind b/patches.drivers/pwm-tiehrpwm-Fix-runtime-PM-imbalance-at-unbind
new file mode 100644
index 0000000000..72d27d500d
--- /dev/null
+++ b/patches.drivers/pwm-tiehrpwm-Fix-runtime-PM-imbalance-at-unbind
@@ -0,0 +1,35 @@
+From c7fdd3f52944b81d807ce7a5fde7d1ca8a2a0919 Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Thu, 20 Jul 2017 12:48:16 +0200
+Subject: [PATCH] pwm: tiehrpwm: Fix runtime PM imbalance at unbind
+Git-commit: c7fdd3f52944b81d807ce7a5fde7d1ca8a2a0919
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Remove unbalanced RPM put at driver unbind which resulted in a negative
+usage count.
+
+Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM")
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/pwm-tiehrpwm.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
+index b5c6b0636893..6e51a075d1a7 100644
+--- a/drivers/pwm/pwm-tiehrpwm.c
++++ b/drivers/pwm/pwm-tiehrpwm.c
+@@ -504,7 +504,6 @@ static int ehrpwm_pwm_remove(struct platform_device *pdev)
+
+ clk_unprepare(pc->tbclk);
+
+- pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ return pwmchip_remove(&pc->chip);
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/pwm-tiehrpwm-fix-clock-imbalance-in-probe-error-path b/patches.drivers/pwm-tiehrpwm-fix-clock-imbalance-in-probe-error-path
new file mode 100644
index 0000000000..d88748bedf
--- /dev/null
+++ b/patches.drivers/pwm-tiehrpwm-fix-clock-imbalance-in-probe-error-path
@@ -0,0 +1,46 @@
+From e2b5602af76dec75f474e4173afb4215007ecfa5 Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan@kernel.org>
+Date: Thu, 20 Jul 2017 12:48:17 +0200
+Subject: [PATCH] pwm: tiehrpwm: fix clock imbalance in probe error path
+Git-commit: e2b5602af76dec75f474e4173afb4215007ecfa5
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+Make sure to unprepare the clock before returning on late probe errors.
+
+Fixes: b388f15fd14c ("pwm: pwm-tiehrpwm: Use clk_enable/disable instead clk_prepare/unprepare.")
+Signed-off-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/pwm/pwm-tiehrpwm.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
+index 6e51a075d1a7..387eaf1bac85 100644
+--- a/drivers/pwm/pwm-tiehrpwm.c
++++ b/drivers/pwm/pwm-tiehrpwm.c
+@@ -489,13 +489,18 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
+ ret = pwmchip_add(&pc->chip);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+- return ret;
++ goto err_clk_unprepare;
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ platform_set_drvdata(pdev, pc);
+ return 0;
++
++err_clk_unprepare:
++ clk_unprepare(pc->tbclk);
++
++ return ret;
+ }
+
+ static int ehrpwm_pwm_remove(struct platform_device *pdev)
+--
+2.18.0
+
diff --git a/patches.drivers/r8152-fix-tx-packets-accounting b/patches.drivers/r8152-fix-tx-packets-accounting
new file mode 100644
index 0000000000..6666eb8bfe
--- /dev/null
+++ b/patches.drivers/r8152-fix-tx-packets-accounting
@@ -0,0 +1,38 @@
+From 4c27bf3c5b7434ccb9ab962301da661c26b467a4 Mon Sep 17 00:00:00 2001
+From: Eric Dumazet <edumazet@google.com>
+Date: Sun, 25 Feb 2018 19:12:10 -0800
+Subject: [PATCH] r8152: fix tx packets accounting
+Git-commit: 4c27bf3c5b7434ccb9ab962301da661c26b467a4
+Patch-mainline: v4.16-rc5
+References: bsc#1051510
+
+r8152 driver handles TSO packets (limited to ~16KB) quite well,
+but pretends each TSO logical packet is a single packet on the wire.
+
+There is also some error since headers are accounted once, but
+error rate is small enough that we do not care.
+
+Signed-off-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/usb/r8152.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index 958b2e8b90f6..86f7196f9d91 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -1794,7 +1794,7 @@ static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
+
+ tx_data += len;
+ agg->skb_len += len;
+- agg->skb_num++;
++ agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
+
+ dev_kfree_skb_any(skb);
+
+--
+2.18.0
+
diff --git a/patches.drivers/r8152-napi-hangup-fix-after-disconnect b/patches.drivers/r8152-napi-hangup-fix-after-disconnect
new file mode 100644
index 0000000000..4427dfbe04
--- /dev/null
+++ b/patches.drivers/r8152-napi-hangup-fix-after-disconnect
@@ -0,0 +1,51 @@
+From 0ee1f4734967af8321ecebaf9c74221ace34f2d5 Mon Sep 17 00:00:00 2001
+From: Jiri Slaby <jslaby@suse.cz>
+Date: Mon, 25 Jun 2018 09:26:27 +0200
+Subject: [PATCH] r8152: napi hangup fix after disconnect
+Git-commit: 0ee1f4734967af8321ecebaf9c74221ace34f2d5
+Patch-mainline: v4.18-rc4
+References: bsc#1051510
+
+When unplugging an r8152 adapter while the interface is UP, the NIC
+becomes unusable. usb->disconnect (aka rtl8152_disconnect) deletes
+napi. Then, rtl8152_disconnect calls unregister_netdev and that invokes
+netdev->ndo_stop (aka rtl8152_close). rtl8152_close tries to
+napi_disable, but the napi is already deleted by disconnect above. So
+the first while loop in napi_disable never finishes. This results in
+complete deadlock of the network layer as there is rtnl_mutex held by
+unregister_netdev.
+
+So avoid the call to napi_disable in rtl8152_close when the device is
+already gone.
+
+The other calls to usb_kill_urb, cancel_delayed_work_sync,
+netif_stop_queue etc. seem to be fine. The urb and netdev is not
+destroyed yet.
+
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+Cc: linux-usb@vger.kernel.org
+Cc: netdev@vger.kernel.org
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/usb/r8152.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index 86f7196f9d91..2a58607a6aea 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -3962,7 +3962,8 @@ static int rtl8152_close(struct net_device *netdev)
+ #ifdef CONFIG_PM_SLEEP
+ unregister_pm_notifier(&tp->pm_notifier);
+ #endif
+- napi_disable(&tp->napi);
++ if (!test_bit(RTL8152_UNPLUG, &tp->flags))
++ napi_disable(&tp->napi);
+ clear_bit(WORK_ENABLE, &tp->flags);
+ usb_kill_urb(tp->intr_urb);
+ cancel_delayed_work_sync(&tp->schedule);
+--
+2.18.0
+
diff --git a/patches.drivers/r8169-Be-drop-monitor-friendly b/patches.drivers/r8169-Be-drop-monitor-friendly
new file mode 100644
index 0000000000..2645966fd2
--- /dev/null
+++ b/patches.drivers/r8169-Be-drop-monitor-friendly
@@ -0,0 +1,47 @@
+From 7a4b813cb739ce598ffbad2e84d19d13fa23e25d Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Thu, 24 Aug 2017 18:34:44 -0700
+Subject: [PATCH] r8169: Be drop monitor friendly
+Git-commit: 7a4b813cb739ce598ffbad2e84d19d13fa23e25d
+Patch-mainline: v4.13
+References: bsc#1051510
+
+rtl_tx() is the TX reclamation process whereas rtl8169_tx_clear_range() does
+the TX ring cleaning during shutdown, both of these functions should call
+dev_consume_skb_any() to be drop monitor friendly.
+
+Fixes: cac4b22f3d6a ("r8169: do not account fragments as packets")
+Fixes: eb781397904e ("r8169: Do not use dev_kfree_skb in xmit path")
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/net/ethernet/realtek/r8169.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
+index 8a1bbd2a6a20..e03fcf914690 100644
+--- a/drivers/net/ethernet/realtek/r8169.c
++++ b/drivers/net/ethernet/realtek/r8169.c
+@@ -6863,7 +6863,7 @@ static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
+ rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
+ tp->TxDescArray + entry);
+ if (skb) {
+- dev_kfree_skb_any(skb);
++ dev_consume_skb_any(skb);
+ tx_skb->skb = NULL;
+ }
+ }
+@@ -7318,7 +7318,7 @@ static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
+ tp->tx_stats.packets++;
+ tp->tx_stats.bytes += tx_skb->skb->len;
+ u64_stats_update_end(&tp->tx_stats.syncp);
+- dev_kfree_skb_any(tx_skb->skb);
++ dev_consume_skb_any(tx_skb->skb);
+ tx_skb->skb = NULL;
+ }
+ dirty_tx++;
+--
+2.18.0
+
diff --git a/patches.drivers/regulator-max8998-Fix-platform-data-retrieval b/patches.drivers/regulator-max8998-Fix-platform-data-retrieval
new file mode 100644
index 0000000000..3280fddda1
--- /dev/null
+++ b/patches.drivers/regulator-max8998-Fix-platform-data-retrieval
@@ -0,0 +1,41 @@
+From c1472737914fe5246a672fef6e85c9455de8473f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= <pawel.mikolaj.chmiel@gmail.com>
+Date: Fri, 27 Apr 2018 18:02:59 +0200
+Subject: [PATCH] regulator: max8998: Fix platform data retrieval.
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: c1472737914fe5246a672fef6e85c9455de8473f
+Patch-mainline: v4.18-rc1
+References: bsc#1051510
+
+Since the max8998 MFD driver supports instantiation by DT, platform data
+retrieval is handled in MFD probe and cell drivers should get use
+the pdata field of max8998_dev struct to obtain them.
+
+Fixes: ee999fb3f17f ("mfd: max8998: Add support for Device Tree")
+Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/regulator/max8998.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/regulator/max8998.c b/drivers/regulator/max8998.c
+index 3027e7ce100b..6a2b61c012b5 100644
+--- a/drivers/regulator/max8998.c
++++ b/drivers/regulator/max8998.c
+@@ -309,8 +309,7 @@ static int max8998_set_voltage_buck_sel(struct regulator_dev *rdev,
+ unsigned selector)
+ {
+ struct max8998_data *max8998 = rdev_get_drvdata(rdev);
+- struct max8998_platform_data *pdata =
+- dev_get_platdata(max8998->iodev->dev);
++ struct max8998_platform_data *pdata = max8998->iodev->pdata;
+ struct i2c_client *i2c = max8998->iodev->i2c;
+ int buck = rdev_get_id(rdev);
+ int reg, shift = 0, mask, ret, j;
+--
+2.18.0
+
diff --git a/patches.drivers/regulator-qcom_spmi-Include-offset-when-translating- b/patches.drivers/regulator-qcom_spmi-Include-offset-when-translating-
new file mode 100644
index 0000000000..69e7eb16f3
--- /dev/null
+++ b/patches.drivers/regulator-qcom_spmi-Include-offset-when-translating-
@@ -0,0 +1,108 @@
+From ab953b9db3a1169fbc675c8de3d2dab919ce3211 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Wed, 1 Nov 2017 22:06:19 -0700
+Subject: [PATCH] regulator: qcom_spmi: Include offset when translating voltages
+Git-commit: ab953b9db3a1169fbc675c8de3d2dab919ce3211
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+This driver converts voltages from a non-linear range in hardware
+to a linear range in software and vice versa. During the
+conversion, we exclude certain voltages that are invalid to use
+because the software interface is more flexible than reality.
+
+For example, the FTSMPS2P5 regulators have a voltage range from
+80000uV to 1355000uV that software could support, but we only
+want to use the range of 350000uV to 1355000uV. If we don't
+account for the hw selectors between 80000uV and 350000uV we'll
+pick a hw selector of 0 to mean 350000uV when it really means
+80000uV. This can cause us to program voltages into the hardware
+that are significantly lower than what we're expecting.
+
+And when we read it back from the hardware we'll have the same
+problem, voltages that are in the invalid band will end up being
+calculated as some software selector that represents a larger
+voltage than what is programmed and the user will be confused.
+
+Fix all this by properly offsetting the software selector and hw
+selector when converting from one number space to another.
+
+Fixes: 1b5b19689278 ("regulator: qcom_spmi: Only use selector based regulator ops")
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/regulator/qcom_spmi-regulator.c | 39 +++++++++++++++++++++----
+ 1 file changed, 33 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c
+index 16c5f84e06a7..c372b244f3da 100644
+--- a/drivers/regulator/qcom_spmi-regulator.c
++++ b/drivers/regulator/qcom_spmi-regulator.c
+@@ -593,13 +593,20 @@ static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
+ u8 *voltage_sel)
+ {
+ const struct spmi_voltage_range *range, *end;
++ unsigned offset;
+
+ range = vreg->set_points->range;
+ end = range + vreg->set_points->count;
+
+ for (; range < end; range++) {
+ if (selector < range->n_voltages) {
+- *voltage_sel = selector;
++ /*
++ * hardware selectors between set point min and real
++ * min are invalid so we ignore them
++ */
++ offset = range->set_point_min_uV - range->min_uV;
++ offset /= range->step_uV;
++ *voltage_sel = selector + offset;
+ *range_sel = range->range_sel;
+ return 0;
+ }
+@@ -613,15 +620,35 @@ static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
+ static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
+ const struct spmi_voltage_range *range)
+ {
+- int sw_sel = hw_sel;
++ unsigned sw_sel = 0;
++ unsigned offset, max_hw_sel;
+ const struct spmi_voltage_range *r = vreg->set_points->range;
+-
+- while (r != range) {
++ const struct spmi_voltage_range *end = r + vreg->set_points->count;
++
++ for (; r < end; r++) {
++ if (r == range && range->n_voltages) {
++ /*
++ * hardware selectors between set point min and real
++ * min and between set point max and real max are
++ * invalid so we return an error if they're
++ * programmed into the hardware
++ */
++ offset = range->set_point_min_uV - range->min_uV;
++ offset /= range->step_uV;
++ if (hw_sel < offset)
++ return -EINVAL;
++
++ max_hw_sel = range->set_point_max_uV - range->min_uV;
++ max_hw_sel /= range->step_uV;
++ if (hw_sel > max_hw_sel)
++ return -EINVAL;
++
++ return sw_sel + hw_sel - offset;
++ }
+ sw_sel += r->n_voltages;
+- r++;
+ }
+
+- return sw_sel;
++ return -EINVAL;
+ }
+
+ static const struct spmi_voltage_range *
+--
+2.18.0
+
diff --git a/patches.drivers/regulator-tps65218-Fix-strobe-assignment b/patches.drivers/regulator-tps65218-Fix-strobe-assignment
new file mode 100644
index 0000000000..7d94109553
--- /dev/null
+++ b/patches.drivers/regulator-tps65218-Fix-strobe-assignment
@@ -0,0 +1,36 @@
+From efeb88c68bd0dbd317c4d24a1b5b58c5e5bd68aa Mon Sep 17 00:00:00 2001
+From: Keerthy <j-keerthy@ti.com>
+Date: Fri, 10 Nov 2017 17:22:43 +0530
+Subject: [PATCH] regulator: tps65218: Fix strobe assignment
+Git-commit: efeb88c68bd0dbd317c4d24a1b5b58c5e5bd68aa
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+Currentlly tps_info structure is no longer used. So use the
+strobes parameter in tps65218 structure to capture the info.
+
+Fixes: 2dc4940360d4c0c (regulator: tps65218: Remove all the compatibles)
+Signed-off-by: Keerthy <j-keerthy@ti.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/regulator/tps65218-regulator.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/regulator/tps65218-regulator.c b/drivers/regulator/tps65218-regulator.c
+index 9aafbb03482d..bc489958fed7 100644
+--- a/drivers/regulator/tps65218-regulator.c
++++ b/drivers/regulator/tps65218-regulator.c
+@@ -154,7 +154,7 @@ static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev)
+
+ if (!tps->strobes[rid]) {
+ if (rid == TPS65218_DCDC_3)
+- tps->info[rid]->strobe = 3;
++ tps->strobes[rid] = 3;
+ else
+ return -EINVAL;
+ }
+--
+2.18.0
+
diff --git a/patches.drivers/s390-qdio-don-t-retry-eqbs-after-ccq-96.patch b/patches.drivers/s390-qdio-don-t-retry-eqbs-after-ccq-96.patch
new file mode 100644
index 0000000000..ef6966bb15
--- /dev/null
+++ b/patches.drivers/s390-qdio-don-t-retry-eqbs-after-ccq-96.patch
@@ -0,0 +1,77 @@
+From: Julian Wiedmann <jwi@linux.vnet.ibm.com>
+Date: Mon, 5 Mar 2018 09:39:38 +0100
+Subject: s390/qdio: don't retry EQBS after CCQ 96
+Git-commit: dae55b6fef58530c13df074bcc182c096609339e
+Patch-mainline: v4.17-rc1
+References: bsc#1102088, LTC#169699
+
+Immediate retry of EQBS after CCQ 96 means that we potentially misreport
+the state of buffers inspected during the first EQBS call.
+
+This occurs when
+1. the first EQBS finds all inspected buffers still in the initial state
+ set by the driver (ie INPUT EMPTY or OUTPUT PRIMED),
+2. the EQBS terminates early with CCQ 96, and
+3. by the time that the second EQBS comes around, the state of those
+ previously inspected buffers has changed.
+
+If the state reported by the second EQBS is 'driver-owned', all we know
+is that the previous buffers are driver-owned now as well. But we can't
+tell if they all have the same state. So for instance
+- the second EQBS reports OUTPUT EMPTY, but any number of the previous
+ buffers could be OUTPUT ERROR by now,
+- the second EQBS reports OUTPUT ERROR, but any number of the previous
+ buffers could be OUTPUT EMPTY by now.
+
+Effectively, this can result in both over- and underreporting of errors.
+
+If the state reported by the second EQBS is 'HW-owned', that doesn't
+guarantee that the previous buffers have not been switched to
+driver-owned in the mean time. So for instance
+- the second EQBS reports INPUT EMPTY, but any number of the previous
+ buffers could be INPUT PRIMED (or INPUT ERROR) by now.
+
+This would result in failure to process pending work on the queue. If
+it's the final check before yielding initiative, this can cause
+a (temporary) queue stall due to IRQ avoidance.
+
+Fixes: 25f269f17316 ("[S390] qdio: EQBS retry after CCQ 96")
+Cc: <stable@vger.kernel.org> #v3.2+
+Signed-off-by: Julian Wiedmann <jwi@linux.vnet.ibm.com>
+Reviewed-by: Benjamin Block <bblock@linux.vnet.ibm.com>
+Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/cio/qdio_main.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c
+index 63c6e9cf958f..de647b7e17b1 100644
+--- a/drivers/s390/cio/qdio_main.c
++++ b/drivers/s390/cio/qdio_main.c
+@@ -128,7 +128,7 @@ static inline int qdio_check_ccq(struct qdio_q *q, unsigned int ccq)
+ static int qdio_do_eqbs(struct qdio_q *q, unsigned char *state,
+ int start, int count, int auto_ack)
+ {
+- int rc, tmp_count = count, tmp_start = start, nr = q->nr, retried = 0;
++ int rc, tmp_count = count, tmp_start = start, nr = q->nr;
+ unsigned int ccq = 0;
+
+ qperf_inc(q, eqbs);
+@@ -151,14 +151,7 @@ static int qdio_do_eqbs(struct qdio_q *q, unsigned char *state,
+ qperf_inc(q, eqbs_partial);
+ DBF_DEV_EVENT(DBF_WARN, q->irq_ptr, "EQBS part:%02x",
+ tmp_count);
+- /*
+- * Retry once, if that fails bail out and process the
+- * extracted buffers before trying again.
+- */
+- if (!retried++)
+- goto again;
+- else
+- return count - tmp_count;
++ return count - tmp_count;
+ }
+
+ DBF_ERROR("%4x EQBS ERROR", SCH_NO(q));
+
diff --git a/patches.drivers/s390-qeth-fix-error-handling-in-adapter-command-callbacks.patch b/patches.drivers/s390-qeth-fix-error-handling-in-adapter-command-callbacks.patch
new file mode 100644
index 0000000000..0aaa2d888c
--- /dev/null
+++ b/patches.drivers/s390-qeth-fix-error-handling-in-adapter-command-callbacks.patch
@@ -0,0 +1,215 @@
+From: Julian Wiedmann <jwi@linux.vnet.ibm.com>
+Date: Thu, 19 Apr 2018 12:52:06 +0200
+Subject: s390/qeth: fix error handling in adapter command callbacks
+Git-commit: 686c97ee29c886ee07d17987d0059874c5c3b5af
+Patch-mainline: v4.17-rc3
+References: bsc#1102088, LTC#169699
+
+Make sure to check both return code fields before(!) processing the
+command response. Otherwise we risk operating on invalid data.
+
+This matches an earlier fix for SETASSPARMS commands, see
+commit ad3cbf613329 ("s390/qeth: fix error handling in checksum cmd callback").
+
+Signed-off-by: Julian Wiedmann <jwi@linux.vnet.ibm.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/net/qeth_core_main.c | 85 ++++++++++++++++----------------------
+ 1 file changed, 37 insertions(+), 48 deletions(-)
+
+--- a/drivers/s390/net/qeth_core_main.c
++++ b/drivers/s390/net/qeth_core_main.c
+@@ -2998,28 +2998,23 @@ static int qeth_send_startlan(struct qet
+ return rc;
+ }
+
+-static int qeth_default_setadapterparms_cb(struct qeth_card *card,
+- struct qeth_reply *reply, unsigned long data)
++static int qeth_setadpparms_inspect_rc(struct qeth_ipa_cmd *cmd)
+ {
+- struct qeth_ipa_cmd *cmd;
+-
+- QETH_CARD_TEXT(card, 4, "defadpcb");
+-
+- cmd = (struct qeth_ipa_cmd *) data;
+- if (cmd->hdr.return_code == 0)
++ if (!cmd->hdr.return_code)
+ cmd->hdr.return_code =
+ cmd->data.setadapterparms.hdr.return_code;
+- return 0;
++ return cmd->hdr.return_code;
+ }
+
+ static int qeth_query_setadapterparms_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *) data;
+
+ QETH_CARD_TEXT(card, 3, "quyadpcb");
++ if (qeth_setadpparms_inspect_rc(cmd))
++ return 0;
+
+- cmd = (struct qeth_ipa_cmd *) data;
+ if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
+ card->info.link_type =
+ cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
+@@ -3027,7 +3022,7 @@ static int qeth_query_setadapterparms_cb
+ }
+ card->options.adp.supported_funcs =
+ cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
+- return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
++ return 0;
+ }
+
+ static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
+@@ -3119,22 +3114,20 @@ EXPORT_SYMBOL_GPL(qeth_query_ipassists);
+ static int qeth_query_switch_attributes_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
+- struct qeth_switch_info *sw_info;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *) data;
+ struct qeth_query_switch_attributes *attrs;
++ struct qeth_switch_info *sw_info;
+
+ QETH_CARD_TEXT(card, 2, "qswiatcb");
+- cmd = (struct qeth_ipa_cmd *) data;
+- sw_info = (struct qeth_switch_info *)reply->param;
+- if (cmd->data.setadapterparms.hdr.return_code == 0) {
+- attrs = &cmd->data.setadapterparms.data.query_switch_attributes;
+- sw_info->capabilities = attrs->capabilities;
+- sw_info->settings = attrs->settings;
+- QETH_CARD_TEXT_(card, 2, "%04x%04x", sw_info->capabilities,
+- sw_info->settings);
+- }
+- qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
++ if (qeth_setadpparms_inspect_rc(cmd))
++ return 0;
+
++ sw_info = (struct qeth_switch_info *)reply->param;
++ attrs = &cmd->data.setadapterparms.data.query_switch_attributes;
++ sw_info->capabilities = attrs->capabilities;
++ sw_info->settings = attrs->settings;
++ QETH_CARD_TEXT_(card, 2, "%04x%04x", sw_info->capabilities,
++ sw_info->settings);
+ return 0;
+ }
+
+@@ -4184,16 +4177,13 @@ EXPORT_SYMBOL_GPL(qeth_do_send_packet);
+ static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *) data;
+ struct qeth_ipacmd_setadpparms *setparms;
+
+ QETH_CARD_TEXT(card, 4, "prmadpcb");
+
+- cmd = (struct qeth_ipa_cmd *) data;
+ setparms = &(cmd->data.setadapterparms);
+-
+- qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
+- if (cmd->hdr.return_code) {
++ if (qeth_setadpparms_inspect_rc(cmd)) {
+ QETH_CARD_TEXT_(card, 4, "prmrc%x", cmd->hdr.return_code);
+ setparms->data.mode = SET_PROMISC_MODE_OFF;
+ }
+@@ -4263,11 +4253,12 @@ EXPORT_SYMBOL_GPL(qeth_get_stats);
+ static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *) data;
+
+ QETH_CARD_TEXT(card, 4, "chgmaccb");
++ if (qeth_setadpparms_inspect_rc(cmd))
++ return 0;
+
+- cmd = (struct qeth_ipa_cmd *) data;
+ if (!card->options.layer2 ||
+ !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
+ memcpy(card->dev->dev_addr,
+@@ -4275,7 +4266,6 @@ static int qeth_setadpparms_change_macad
+ OSA_ADDR_LEN);
+ card->info.mac_bits |= QETH_LAYER2_MAC_READ;
+ }
+- qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
+ return 0;
+ }
+
+@@ -4306,13 +4296,15 @@ EXPORT_SYMBOL_GPL(qeth_setadpparms_chang
+ static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *) data;
+ struct qeth_set_access_ctrl *access_ctrl_req;
+ int fallback = *(int *)reply->param;
+
+ QETH_CARD_TEXT(card, 4, "setaccb");
++ if (cmd->hdr.return_code)
++ return 0;
++ qeth_setadpparms_inspect_rc(cmd);
+
+- cmd = (struct qeth_ipa_cmd *) data;
+ access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
+ QETH_DBF_TEXT_(SETUP, 2, "setaccb");
+ QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
+@@ -4385,7 +4377,6 @@ static int qeth_setadpparms_set_access_c
+ card->options.isolation = card->options.prev_isolation;
+ break;
+ }
+- qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
+ return 0;
+ }
+
+@@ -4673,14 +4664,15 @@ out:
+ static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *)data;
+ struct qeth_qoat_priv *priv;
+ char *resdata;
+ int resdatalen;
+
+ QETH_CARD_TEXT(card, 3, "qoatcb");
++ if (qeth_setadpparms_inspect_rc(cmd))
++ return 0;
+
+- cmd = (struct qeth_ipa_cmd *)data;
+ priv = (struct qeth_qoat_priv *)reply->param;
+ resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
+ resdata = (char *)data + 28;
+@@ -4774,21 +4766,18 @@ out:
+ static int qeth_query_card_info_cb(struct qeth_card *card,
+ struct qeth_reply *reply, unsigned long data)
+ {
+- struct qeth_ipa_cmd *cmd;
++ struct carrier_info *carrier_info = (struct carrier_info *)reply->param;
++ struct qeth_ipa_cmd *cmd = (struct qeth_ipa_cmd *)data;
+ struct qeth_query_card_info *card_info;
+- struct carrier_info *carrier_info;
+
+ QETH_CARD_TEXT(card, 2, "qcrdincb");
+- carrier_info = (struct carrier_info *)reply->param;
+- cmd = (struct qeth_ipa_cmd *)data;
+- card_info = &cmd->data.setadapterparms.data.card_info;
+- if (cmd->data.setadapterparms.hdr.return_code == 0) {
+- carrier_info->card_type = card_info->card_type;
+- carrier_info->port_mode = card_info->port_mode;
+- carrier_info->port_speed = card_info->port_speed;
+- }
++ if (qeth_setadpparms_inspect_rc(cmd))
++ return 0;
+
+- qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
++ card_info = &cmd->data.setadapterparms.data.card_info;
++ carrier_info->card_type = card_info->card_type;
++ carrier_info->port_mode = card_info->port_mode;
++ carrier_info->port_speed = card_info->port_speed;
+ return 0;
+ }
+
diff --git a/patches.drivers/scsi-zfcp-fix-infinite-iteration-on-erp-ready-list.patch b/patches.drivers/scsi-zfcp-fix-infinite-iteration-on-erp-ready-list.patch
new file mode 100644
index 0000000000..b60ca98a8d
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-infinite-iteration-on-erp-ready-list.patch
@@ -0,0 +1,186 @@
+From: Jens Remus <jremus@linux.ibm.com>
+Date: Thu, 3 May 2018 13:52:47 +0200
+Subject: scsi: zfcp: fix infinite iteration on ERP ready list
+Git-commit: fa89adba1941e4f3b213399b81732a5c12fd9131
+Patch-mainline: v4.17-rc7
+References: bsc#1102088, LTC#169699
+
+zfcp_erp_adapter_reopen() schedules blocking of all of the adapter's
+rports via zfcp_scsi_schedule_rports_block() and enqueues a reopen
+adapter ERP action via zfcp_erp_action_enqueue(). Both are separately
+processed asynchronously and concurrently.
+
+Blocking of rports is done in a kworker by zfcp_scsi_rport_work(). It
+calls zfcp_scsi_rport_block(), which then traces a DBF REC "scpdely" via
+zfcp_dbf_rec_trig(). zfcp_dbf_rec_trig() acquires the DBF REC spin lock
+and then iterates with list_for_each() over the adapter's ERP ready list
+without holding the ERP lock. This opens a race window in which the
+current list entry can be moved to another list, causing list_for_each()
+to iterate forever on the wrong list, as the erp_ready_head is never
+encountered as terminal condition.
+
+Meanwhile the ERP action can be processed in the ERP thread by
+zfcp_erp_thread(). It calls zfcp_erp_strategy(), which acquires the ERP
+lock and then calls zfcp_erp_action_to_running() to move the ERP action
+from the ready to the running list. zfcp_erp_action_to_running() can
+move the ERP action using list_move() just during the aforementioned
+race window. It then traces a REC RUN "erator1" via zfcp_dbf_rec_run().
+zfcp_dbf_rec_run() tries to acquire the DBF REC spin lock. If this is
+held by the infinitely looping kworker, it effectively spins forever.
+
+Example Sequence Diagram:
+
+Process ERP Thread rport_work
+------------------- ------------------- -------------------
+zfcp_erp_adapter_reopen()
+zfcp_erp_adapter_block()
+zfcp_scsi_schedule_rports_block()
+lock ERP zfcp_scsi_rport_work()
+zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER)
+list_add_tail() on ready !(rport_task==RPORT_ADD)
+wake_up() ERP thread zfcp_scsi_rport_block()
+zfcp_dbf_rec_trig() zfcp_erp_strategy() zfcp_dbf_rec_trig()
+unlock ERP lock DBF REC
+zfcp_erp_wait() lock ERP
+| zfcp_erp_action_to_running()
+| list_for_each() ready
+| list_move() current entry
+| ready to running
+| zfcp_dbf_rec_run() endless loop over running
+| zfcp_dbf_rec_run_lvl()
+| lock DBF REC spins forever
+
+Any adapter recovery can trigger this, such as setting the device offline
+or reboot.
+
+V4.9 commit 4eeaa4f3f1d6 ("zfcp: close window with unblocked rport
+during rport gone") introduced additional tracing of (un)blocking of
+rports. It missed that the adapter->erp_lock must be held when calling
+zfcp_dbf_rec_trig().
+
+This fix uses the approach formerly introduced by commit aa0fec62391c
+("[SCSI] zfcp: Fix sparse warning by providing new entry in dbf") that got
+later removed by commit ae0904f60fab ("[SCSI] zfcp: Redesign of the debug
+tracing for recovery actions.").
+
+Introduce zfcp_dbf_rec_trig_lock(), a wrapper for zfcp_dbf_rec_trig() that
+acquires and releases the adapter->erp_lock for read.
+
+Reported-by: Sebastian Ott <sebott@linux.ibm.com>
+Signed-off-by: Jens Remus <jremus@linux.ibm.com>
+Fixes: 4eeaa4f3f1d6 ("zfcp: close window with unblocked rport during rport gone")
+Cc: <stable@vger.kernel.org> # 2.6.32+
+Reviewed-by: Benjamin Block <bblock@linux.vnet.ibm.com>
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_dbf.c | 23 ++++++++++++++++++++++-
+ drivers/s390/scsi/zfcp_ext.h | 5 ++++-
+ drivers/s390/scsi/zfcp_scsi.c | 14 +++++++-------
+ 3 files changed, 33 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c
+index a8b831000b2d..18c4f933e8b9 100644
+--- a/drivers/s390/scsi/zfcp_dbf.c
++++ b/drivers/s390/scsi/zfcp_dbf.c
+@@ -4,7 +4,7 @@
+ *
+ * Debug traces for zfcp.
+ *
+- * Copyright IBM Corp. 2002, 2017
++ * Copyright IBM Corp. 2002, 2018
+ */
+
+ #define KMSG_COMPONENT "zfcp"
+@@ -308,6 +308,27 @@ void zfcp_dbf_rec_trig(char *tag, struct zfcp_adapter *adapter,
+ spin_unlock_irqrestore(&dbf->rec_lock, flags);
+ }
+
++/**
++ * zfcp_dbf_rec_trig_lock - trace event related to triggered recovery with lock
++ * @tag: identifier for event
++ * @adapter: adapter on which the erp_action should run
++ * @port: remote port involved in the erp_action
++ * @sdev: scsi device involved in the erp_action
++ * @want: wanted erp_action
++ * @need: required erp_action
++ *
++ * The adapter->erp_lock must not be held.
++ */
++void zfcp_dbf_rec_trig_lock(char *tag, struct zfcp_adapter *adapter,
++ struct zfcp_port *port, struct scsi_device *sdev,
++ u8 want, u8 need)
++{
++ unsigned long flags;
++
++ read_lock_irqsave(&adapter->erp_lock, flags);
++ zfcp_dbf_rec_trig(tag, adapter, port, sdev, want, need);
++ read_unlock_irqrestore(&adapter->erp_lock, flags);
++}
+
+ /**
+ * zfcp_dbf_rec_run_lvl - trace event related to running recovery
+diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h
+index bf8ea4df2bb8..e5eed8aac0ce 100644
+--- a/drivers/s390/scsi/zfcp_ext.h
++++ b/drivers/s390/scsi/zfcp_ext.h
+@@ -4,7 +4,7 @@
+ *
+ * External function declarations.
+ *
+- * Copyright IBM Corp. 2002, 2016
++ * Copyright IBM Corp. 2002, 2018
+ */
+
+ #ifndef ZFCP_EXT_H
+@@ -35,6 +35,9 @@ extern int zfcp_dbf_adapter_register(struct zfcp_adapter *);
+ extern void zfcp_dbf_adapter_unregister(struct zfcp_adapter *);
+ extern void zfcp_dbf_rec_trig(char *, struct zfcp_adapter *,
+ struct zfcp_port *, struct scsi_device *, u8, u8);
++extern void zfcp_dbf_rec_trig_lock(char *tag, struct zfcp_adapter *adapter,
++ struct zfcp_port *port,
++ struct scsi_device *sdev, u8 want, u8 need);
+ extern void zfcp_dbf_rec_run(char *, struct zfcp_erp_action *);
+ extern void zfcp_dbf_rec_run_lvl(int level, char *tag,
+ struct zfcp_erp_action *erp);
+diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
+index 4d2ba5682493..22f9562f415c 100644
+--- a/drivers/s390/scsi/zfcp_scsi.c
++++ b/drivers/s390/scsi/zfcp_scsi.c
+@@ -4,7 +4,7 @@
+ *
+ * Interface to Linux SCSI midlayer.
+ *
+- * Copyright IBM Corp. 2002, 2017
++ * Copyright IBM Corp. 2002, 2018
+ */
+
+ #define KMSG_COMPONENT "zfcp"
+@@ -618,9 +618,9 @@ static void zfcp_scsi_rport_register(struct zfcp_port *port)
+ ids.port_id = port->d_id;
+ ids.roles = FC_RPORT_ROLE_FCP_TARGET;
+
+- zfcp_dbf_rec_trig("scpaddy", port->adapter, port, NULL,
+- ZFCP_PSEUDO_ERP_ACTION_RPORT_ADD,
+- ZFCP_PSEUDO_ERP_ACTION_RPORT_ADD);
++ zfcp_dbf_rec_trig_lock("scpaddy", port->adapter, port, NULL,
++ ZFCP_PSEUDO_ERP_ACTION_RPORT_ADD,
++ ZFCP_PSEUDO_ERP_ACTION_RPORT_ADD);
+ rport = fc_remote_port_add(port->adapter->scsi_host, 0, &ids);
+ if (!rport) {
+ dev_err(&port->adapter->ccw_device->dev,
+@@ -642,9 +642,9 @@ static void zfcp_scsi_rport_block(struct zfcp_port *port)
+ struct fc_rport *rport = port->rport;
+
+ if (rport) {
+- zfcp_dbf_rec_trig("scpdely", port->adapter, port, NULL,
+- ZFCP_PSEUDO_ERP_ACTION_RPORT_DEL,
+- ZFCP_PSEUDO_ERP_ACTION_RPORT_DEL);
++ zfcp_dbf_rec_trig_lock("scpdely", port->adapter, port, NULL,
++ ZFCP_PSEUDO_ERP_ACTION_RPORT_DEL,
++ ZFCP_PSEUDO_ERP_ACTION_RPORT_DEL);
+ fc_remote_port_delete(rport);
+ port->rport = NULL;
+ }
+
diff --git a/patches.drivers/scsi-zfcp-fix-misleading-rec-trigger-trace-where-erp_action-setup-failed.patch b/patches.drivers/scsi-zfcp-fix-misleading-rec-trigger-trace-where-erp_action-setup-failed.patch
new file mode 100644
index 0000000000..2d3f21edbb
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-misleading-rec-trigger-trace-where-erp_action-setup-failed.patch
@@ -0,0 +1,117 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:45 +0200
+Subject: scsi: zfcp: fix misleading REC trigger trace where erp_action setup
+ failed
+Git-commit: 512857a795cbbda5980efa4cdb3c0b6602330408
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+If a SCSI device is deleted during scsi_eh host reset, we cannot get a
+reference to the SCSI device anymore since scsi_device_get returns !=0 by
+design. Assuming the recovery of adapter and port(s) was successful,
+zfcp_erp_strategy_followup_success() attempts to trigger a LUN reset for the
+half-gone SCSI device. Unfortunately, it causes the following confusing
+trace record which states that zfcp will do a LUN recovery as "ERP need" is
+ZFCP_ERP_ACTION_REOPEN_LUN == 1 and equals "ERP want".
+
+Old example trace record formatted with zfcpdbf from s390-tools:
+
+Tag: : ersfs_3 ERP, trigger, unit reopen, port reopen succeeded
+LUN : 0x<FCP_LUN>
+WWPN : 0x<WWPN>
+D_ID : 0x<N_Port-ID>
+Adapter status : 0x5400050b
+Port status : 0x54000001
+LUN status : 0x40000000 ZFCP_STATUS_COMMON_RUNNING
+ but not ZFCP_STATUS_COMMON_UNBLOCKED as it
+ was closed on close part of adapter reopen
+ERP want : 0x01
+ERP need : 0x01 misleading
+
+However, zfcp_erp_setup_act() returns NULL as it cannot get the reference.
+Hence, zfcp_erp_action_enqueue() takes an early goto out and _NO_ recovery
+actually happens.
+
+We always do want the recovery trigger trace record even if no erp_action
+could be enqueued as in this case. For other cases where we did not enqueue
+an erp_action, 'need' has always been zero to indicate this. In order to
+indicate above goto out, introduce an eyecatcher "flag" to mark the "ERP
+need" as 'not needed' but still keep the information which erp_action type,
+that zfcp_erp_required_act() had decided upon, is needed. 0xc_ is chosen to
+be visibly different from 0x0_ in "ERP want".
+
+New example trace record formatted with zfcpdbf from s390-tools:
+
+Tag: : ersfs_3 ERP, trigger, unit reopen, port reopen succeeded
+LUN : 0x<FCP_LUN>
+WWPN : 0x<WWPN>
+D_ID : 0x<N_Port-ID>
+Adapter status : 0x5400050b
+Port status : 0x54000001
+LUN status : 0x40000000
+ERP want : 0x01
+ERP need : 0xc1 would need LUN ERP, but no action set up
+ ^
+
+Before v2.6.38 commit ae0904f60fab ("[SCSI] zfcp: Redesign of the debug
+tracing for recovery actions.") we could detect this case because the
+"erp_action" field in the trace was NULL. The rework removed erp_action as
+argument and field from the trace.
+
+This patch here is for tracing. A fix to allow LUN recovery in the case at
+hand is a topic for a separate patch.
+
+See also commit fdbd1c5e27da ("[SCSI] zfcp: Allow running unit/LUN shutdown
+without acquiring reference") for a similar case and background info.
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Fixes: ae0904f60fab ("[SCSI] zfcp: Redesign of the debug tracing for recovery actions.")
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_erp.c | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
+index 1d91a32db08e..d9cd25b56cfa 100644
+--- a/drivers/s390/scsi/zfcp_erp.c
++++ b/drivers/s390/scsi/zfcp_erp.c
+@@ -35,11 +35,23 @@ enum zfcp_erp_steps {
+ ZFCP_ERP_STEP_LUN_OPENING = 0x2000,
+ };
+
++/**
++ * enum zfcp_erp_act_type - Type of ERP action object.
++ * @ZFCP_ERP_ACTION_REOPEN_LUN: LUN recovery.
++ * @ZFCP_ERP_ACTION_REOPEN_PORT: Port recovery.
++ * @ZFCP_ERP_ACTION_REOPEN_PORT_FORCED: Forced port recovery.
++ * @ZFCP_ERP_ACTION_REOPEN_ADAPTER: Adapter recovery.
++ * @ZFCP_ERP_ACTION_NONE: Eyecatcher pseudo flag to bitwise or-combine with
++ * either of the other enum values.
++ * Used to indicate that an ERP action could not be
++ * set up despite a detected need for some recovery.
++ */
+ enum zfcp_erp_act_type {
+ ZFCP_ERP_ACTION_REOPEN_LUN = 1,
+ ZFCP_ERP_ACTION_REOPEN_PORT = 2,
+ ZFCP_ERP_ACTION_REOPEN_PORT_FORCED = 3,
+ ZFCP_ERP_ACTION_REOPEN_ADAPTER = 4,
++ ZFCP_ERP_ACTION_NONE = 0xc0,
+ };
+
+ enum zfcp_erp_act_state {
+@@ -257,8 +269,10 @@ static int zfcp_erp_action_enqueue(int want, struct zfcp_adapter *adapter,
+ goto out;
+
+ act = zfcp_erp_setup_act(need, act_status, adapter, port, sdev);
+- if (!act)
++ if (!act) {
++ need |= ZFCP_ERP_ACTION_NONE; /* marker for trace */
+ goto out;
++ }
+ atomic_or(ZFCP_STATUS_ADAPTER_ERP_PENDING, &adapter->status);
+ ++adapter->erp_total_count;
+ list_add_tail(&act->list, &adapter->erp_ready_head);
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-for-all-objects-in-erp_failed.patch b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-for-all-objects-in-erp_failed.patch
new file mode 100644
index 0000000000..c78067e745
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-for-all-objects-in-erp_failed.patch
@@ -0,0 +1,185 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:48 +0200
+Subject: scsi: zfcp: fix missing REC trigger trace for all objects in
+ ERP_FAILED
+Git-commit: 8c3d20aada70042a39c6a6625be037c1472ca610
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+That other commit introduced an inconsistency because it would trace on
+ERP_FAILED for all callers of port forced reopen triggers (not just
+terminate_rport_io), but it would not trace on ERP_FAILED for all callers of
+other ERP triggers such as adapter, port regular, LUN.
+
+Therefore, generalize that other commit. zfcp_erp_action_enqueue() already
+had two early outs which re-used the one zfcp_dbf_rec_trig() call. All ERP
+trigger functions finally run through zfcp_erp_action_enqueue(). So move
+the special handling for ZFCP_STATUS_COMMON_ERP_FAILED into
+zfcp_erp_action_enqueue() and add another early out with new trace marker
+for pseudo ERP need in this case. This removes all early returns from all
+ERP trigger functions so we always end up at zfcp_dbf_rec_trig().
+
+Example trace record formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : REC
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1 ZFCP_DBF_REC_TRIG
+Tag : .......
+LUN : 0x...
+WWPN : 0x...
+D_ID : 0x...
+Adapter status : 0x...
+Port status : 0x...
+LUN status : 0x...
+Ready count : 0x...
+Running count : 0x...
+ERP want : 0x0. ZFCP_ERP_ACTION_REOPEN_...
+ERP need : 0xe0 ZFCP_ERP_ACTION_FAILED
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_erp.c | 79 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 51 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
+index 5c368cdfc455..20fe59300d0e 100644
+--- a/drivers/s390/scsi/zfcp_erp.c
++++ b/drivers/s390/scsi/zfcp_erp.c
+@@ -143,6 +143,49 @@ static void zfcp_erp_action_dismiss_adapter(struct zfcp_adapter *adapter)
+ }
+ }
+
++static int zfcp_erp_handle_failed(int want, struct zfcp_adapter *adapter,
++ struct zfcp_port *port,
++ struct scsi_device *sdev)
++{
++ int need = want;
++ struct zfcp_scsi_dev *zsdev;
++
++ switch (want) {
++ case ZFCP_ERP_ACTION_REOPEN_LUN:
++ zsdev = sdev_to_zfcp(sdev);
++ if (atomic_read(&zsdev->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
++ need = 0;
++ break;
++ case ZFCP_ERP_ACTION_REOPEN_PORT_FORCED:
++ if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
++ need = 0;
++ break;
++ case ZFCP_ERP_ACTION_REOPEN_PORT:
++ if (atomic_read(&port->status) &
++ ZFCP_STATUS_COMMON_ERP_FAILED) {
++ need = 0;
++ /* ensure propagation of failed status to new devices */
++ zfcp_erp_set_port_status(
++ port, ZFCP_STATUS_COMMON_ERP_FAILED);
++ }
++ break;
++ case ZFCP_ERP_ACTION_REOPEN_ADAPTER:
++ if (atomic_read(&adapter->status) &
++ ZFCP_STATUS_COMMON_ERP_FAILED) {
++ need = 0;
++ /* ensure propagation of failed status to new devices */
++ zfcp_erp_set_adapter_status(
++ adapter, ZFCP_STATUS_COMMON_ERP_FAILED);
++ }
++ break;
++ default:
++ need = 0;
++ break;
++ }
++
++ return need;
++}
++
+ static int zfcp_erp_required_act(int want, struct zfcp_adapter *adapter,
+ struct zfcp_port *port,
+ struct scsi_device *sdev)
+@@ -266,6 +309,12 @@ static int zfcp_erp_action_enqueue(int want, struct zfcp_adapter *adapter,
+ int retval = 1, need;
+ struct zfcp_erp_action *act;
+
++ need = zfcp_erp_handle_failed(want, adapter, port, sdev);
++ if (!need) {
++ need = ZFCP_ERP_ACTION_FAILED; /* marker for trace */
++ goto out;
++ }
++
+ if (!adapter->erp_thread)
+ return -EIO;
+
+@@ -314,12 +363,6 @@ static int _zfcp_erp_adapter_reopen(struct zfcp_adapter *adapter,
+ zfcp_erp_adapter_block(adapter, clear_mask);
+ zfcp_scsi_schedule_rports_block(adapter);
+
+- /* ensure propagation of failed status to new devices */
+- if (atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
+- zfcp_erp_set_adapter_status(adapter,
+- ZFCP_STATUS_COMMON_ERP_FAILED);
+- return -EIO;
+- }
+ return zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER,
+ adapter, NULL, NULL, id, 0);
+ }
+@@ -338,12 +381,8 @@ void zfcp_erp_adapter_reopen(struct zfcp_adapter *adapter, int clear, char *id)
+ zfcp_scsi_schedule_rports_block(adapter);
+
+ write_lock_irqsave(&adapter->erp_lock, flags);
+- if (atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
+- zfcp_erp_set_adapter_status(adapter,
+- ZFCP_STATUS_COMMON_ERP_FAILED);
+- else
+- zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER, adapter,
+- NULL, NULL, id, 0);
++ zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_ADAPTER, adapter,
++ NULL, NULL, id, 0);
+ write_unlock_irqrestore(&adapter->erp_lock, flags);
+ }
+
+@@ -384,13 +423,6 @@ static void _zfcp_erp_port_forced_reopen(struct zfcp_port *port, int clear,
+ zfcp_erp_port_block(port, clear);
+ zfcp_scsi_schedule_rport_block(port);
+
+- if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
+- zfcp_dbf_rec_trig(id, port->adapter, port, NULL,
+- ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
+- ZFCP_ERP_ACTION_FAILED);
+- return;
+- }
+-
+ zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
+ port->adapter, port, NULL, id, 0);
+ }
+@@ -416,12 +448,6 @@ static int _zfcp_erp_port_reopen(struct zfcp_port *port, int clear, char *id)
+ zfcp_erp_port_block(port, clear);
+ zfcp_scsi_schedule_rport_block(port);
+
+- if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
+- /* ensure propagation of failed status to new devices */
+- zfcp_erp_set_port_status(port, ZFCP_STATUS_COMMON_ERP_FAILED);
+- return -EIO;
+- }
+-
+ return zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_PORT,
+ port->adapter, port, NULL, id, 0);
+ }
+@@ -461,9 +487,6 @@ static void _zfcp_erp_lun_reopen(struct scsi_device *sdev, int clear, char *id,
+
+ zfcp_erp_lun_block(sdev, clear);
+
+- if (atomic_read(&zfcp_sdev->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
+- return;
+-
+ zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_LUN, adapter,
+ zfcp_sdev->port, sdev, id, act_status);
+ }
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-enqueue-without-erp-thread.patch b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-enqueue-without-erp-thread.patch
new file mode 100644
index 0000000000..e73834bb55
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-enqueue-without-erp-thread.patch
@@ -0,0 +1,58 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:49 +0200
+Subject: scsi: zfcp: fix missing REC trigger trace on enqueue without ERP
+ thread
+Git-commit: 6a76550841d412330bd86aed3238d1888ba70f0e
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+Example trace record formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : REC
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1 ZFCP_DBF_REC_TRIG
+Tag : .......
+LUN : 0x...
+WWPN : 0x...
+D_ID : 0x...
+Adapter status : 0x...
+Port status : 0x...
+LUN status : 0x...
+Ready count : 0x...
+Running count : 0x...
+ERP want : 0x0. ZFCP_ERP_ACTION_REOPEN_...
+ERP need : 0xc0 ZFCP_ERP_ACTION_NONE
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_erp.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
+index 20fe59300d0e..69dfb328dba4 100644
+--- a/drivers/s390/scsi/zfcp_erp.c
++++ b/drivers/s390/scsi/zfcp_erp.c
+@@ -315,8 +315,11 @@ static int zfcp_erp_action_enqueue(int want, struct zfcp_adapter *adapter,
+ goto out;
+ }
+
+- if (!adapter->erp_thread)
+- return -EIO;
++ if (!adapter->erp_thread) {
++ need = ZFCP_ERP_ACTION_NONE; /* marker for trace */
++ retval = -EIO;
++ goto out;
++ }
+
+ need = zfcp_erp_required_act(want, adapter, port, sdev);
+ if (!need)
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-early-return.patch b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-early-return.patch
new file mode 100644
index 0000000000..23b089a3fd
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-early-return.patch
@@ -0,0 +1,116 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:46 +0200
+Subject: scsi: zfcp: fix missing REC trigger trace on terminate_rport_io early
+ return
+Git-commit: 96d9270499471545048ed8a6d7f425a49762283d
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+get_device() and its internally used kobject_get() only return NULL if they
+get passed NULL as argument. zfcp_get_port_by_wwpn() loops over
+adapter->port_list so the iteration variable port is always non-NULL.
+Struct device is embedded in struct zfcp_port so &port->dev is always
+non-NULL. This is the argument to get_device(). However, if we get an
+fc_rport in terminate_rport_io() for which we cannot find a match within
+zfcp_get_port_by_wwpn(), the latter can return NULL. v2.6.30 commit
+70932935b61e ("[SCSI] zfcp: Fix oops when port disappears") introduced an
+early return without adding a trace record for this case. Even if we don't
+need recovery in this case, for debugging we should still see that our
+callback was invoked originally by scsi_transport_fc.
+
+Example trace record formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : REC
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1
+Tag : sctrpin SCSI terminate rport I/O, no zfcp port
+LUN : 0xffffffffffffffff none (invalid)
+WWPN : 0x<wwpn> WWPN
+D_ID : 0x<n_port_id> N_Port-ID
+Adapter status : 0x...
+Port status : 0xffffffff unknown (-1)
+LUN status : 0x00000000 none (invalid)
+Ready count : 0x...
+Running count : 0x...
+ERP want : 0x03 ZFCP_ERP_ACTION_REOPEN_PORT_FORCED
+ERP need : 0xc0 ZFCP_ERP_ACTION_NONE
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Fixes: 70932935b61e ("[SCSI] zfcp: Fix oops when port disappears")
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_erp.c | 20 ++++++++++++++++++++
+ drivers/s390/scsi/zfcp_ext.h | 3 +++
+ drivers/s390/scsi/zfcp_scsi.c | 5 +++++
+ 3 files changed, 28 insertions(+)
+
+diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
+index d9cd25b56cfa..3489b1bc9121 100644
+--- a/drivers/s390/scsi/zfcp_erp.c
++++ b/drivers/s390/scsi/zfcp_erp.c
+@@ -283,6 +283,26 @@ static int zfcp_erp_action_enqueue(int want, struct zfcp_adapter *adapter,
+ return retval;
+ }
+
++void zfcp_erp_port_forced_no_port_dbf(char *id, struct zfcp_adapter *adapter,
++ u64 port_name, u32 port_id)
++{
++ unsigned long flags;
++ static /* don't waste stack */ struct zfcp_port tmpport;
++
++ write_lock_irqsave(&adapter->erp_lock, flags);
++ /* Stand-in zfcp port with fields just good enough for
++ * zfcp_dbf_rec_trig() and zfcp_dbf_set_common().
++ * Under lock because tmpport is static.
++ */
++ atomic_set(&tmpport.status, -1); /* unknown */
++ tmpport.wwpn = port_name;
++ tmpport.d_id = port_id;
++ zfcp_dbf_rec_trig(id, adapter, &tmpport, NULL,
++ ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
++ ZFCP_ERP_ACTION_NONE);
++ write_unlock_irqrestore(&adapter->erp_lock, flags);
++}
++
+ static int _zfcp_erp_adapter_reopen(struct zfcp_adapter *adapter,
+ int clear_mask, char *id)
+ {
+diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h
+index e55f42ce1168..3299bd345076 100644
+--- a/drivers/s390/scsi/zfcp_ext.h
++++ b/drivers/s390/scsi/zfcp_ext.h
+@@ -55,6 +55,9 @@ extern void zfcp_dbf_scsi_eh(char *tag, struct zfcp_adapter *adapter,
+ /* zfcp_erp.c */
+ extern void zfcp_erp_set_adapter_status(struct zfcp_adapter *, u32);
+ extern void zfcp_erp_clear_adapter_status(struct zfcp_adapter *, u32);
++extern void zfcp_erp_port_forced_no_port_dbf(char *id,
++ struct zfcp_adapter *adapter,
++ u64 port_name, u32 port_id);
+ extern void zfcp_erp_adapter_reopen(struct zfcp_adapter *, int, char *);
+ extern void zfcp_erp_adapter_shutdown(struct zfcp_adapter *, int, char *);
+ extern void zfcp_erp_set_port_status(struct zfcp_port *, u32);
+diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
+index 4fdb1665b0e6..478e7ef9ea2f 100644
+--- a/drivers/s390/scsi/zfcp_scsi.c
++++ b/drivers/s390/scsi/zfcp_scsi.c
+@@ -605,6 +605,11 @@ static void zfcp_scsi_terminate_rport_io(struct fc_rport *rport)
+ if (port) {
+ zfcp_erp_port_forced_reopen(port, 0, "sctrpi1");
+ put_device(&port->dev);
++ } else {
++ zfcp_erp_port_forced_no_port_dbf(
++ "sctrpin", adapter,
++ rport->port_name /* zfcp_scsi_rport_register */,
++ rport->port_id /* zfcp_scsi_rport_register */);
+ }
+ }
+
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-for-erp_failed.patch b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-for-erp_failed.patch
new file mode 100644
index 0000000000..8198f49bea
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-for-erp_failed.patch
@@ -0,0 +1,128 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:47 +0200
+Subject: scsi: zfcp: fix missing REC trigger trace on terminate_rport_io for
+ ERP_FAILED
+Git-commit: d70aab55924b44f213fec2b900b095430b33eec6
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+For problem determination we always want to see when we were invoked on the
+terminate_rport_io callback whether we perform something or not.
+
+Temporal event sequence of interest with a long fast_io_fail_tmo of 27 sec:
+
+loose remote port
+
+t workqueue
+[s] zfcp_q_<dev> IRQ zfcperp<dev>
+
+=== ================== =================== ============================
+
+ 0 recv RSCN
+ q p.test_link_work
+ block rport
+ start fast_io_fail_tmo
+ send ADISC ELS
+ 4 recv ADISC fail
+ block zfcp_port
+ port forced reopen
+ send open port
+ 12 recv open port fail
+ q p.gid_pn_work
+ zfcp_erp_wakeup
+ (zfcp_erp_wait would return)
+ GID_PN fail
+
+Before this point, we got a SCSI trace with tag "sctrpi1" on fast_io_fail,
+e.g. with the typical 5 sec setting.
+
+ port.status |= ERP_FAILED
+
+If fast_io_fail_tmo triggers after this point, we missed a SCSI trace.
+
+ workqueue
+ fc_dl_<host>
+ ==================
+ 27 fc_timeout_fail_rport_io
+ fc_terminate_rport_io
+ zfcp_scsi_terminate_rport_io
+ zfcp_erp_port_forced_reopen
+ _zfcp_erp_port_forced_reopen
+ if (port.status & ERP_FAILED)
+ return;
+
+Therefore, write a trace before above early return.
+
+Example trace record formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : REC
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1 ZFCP_DBF_REC_TRIG
+Tag : sctrpi1 SCSI terminate rport I/O
+LUN : 0xffffffffffffffff none (invalid)
+WWPN : 0x<wwpn>
+D_ID : 0x<n_port_id>
+Adapter status : 0x...
+Port status : 0x...
+LUN status : 0x00000000 none (invalid)
+Ready count : 0x...
+Running count : 0x...
+ERP want : 0x03 ZFCP_ERP_ACTION_REOPEN_PORT_FORCED
+ERP need : 0xe0 ZFCP_ERP_ACTION_FAILED
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_erp.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
+index 3489b1bc9121..5c368cdfc455 100644
+--- a/drivers/s390/scsi/zfcp_erp.c
++++ b/drivers/s390/scsi/zfcp_erp.c
+@@ -42,9 +42,13 @@ enum zfcp_erp_steps {
+ * @ZFCP_ERP_ACTION_REOPEN_PORT_FORCED: Forced port recovery.
+ * @ZFCP_ERP_ACTION_REOPEN_ADAPTER: Adapter recovery.
+ * @ZFCP_ERP_ACTION_NONE: Eyecatcher pseudo flag to bitwise or-combine with
+- * either of the other enum values.
++ * either of the first four enum values.
+ * Used to indicate that an ERP action could not be
+ * set up despite a detected need for some recovery.
++ * @ZFCP_ERP_ACTION_FAILED: Eyecatcher pseudo flag to bitwise or-combine with
++ * either of the first four enum values.
++ * Used to indicate that ERP not needed because
++ * the object has ZFCP_STATUS_COMMON_ERP_FAILED.
+ */
+ enum zfcp_erp_act_type {
+ ZFCP_ERP_ACTION_REOPEN_LUN = 1,
+@@ -52,6 +56,7 @@ enum zfcp_erp_act_type {
+ ZFCP_ERP_ACTION_REOPEN_PORT_FORCED = 3,
+ ZFCP_ERP_ACTION_REOPEN_ADAPTER = 4,
+ ZFCP_ERP_ACTION_NONE = 0xc0,
++ ZFCP_ERP_ACTION_FAILED = 0xe0,
+ };
+
+ enum zfcp_erp_act_state {
+@@ -379,8 +384,12 @@ static void _zfcp_erp_port_forced_reopen(struct zfcp_port *port, int clear,
+ zfcp_erp_port_block(port, clear);
+ zfcp_scsi_schedule_rport_block(port);
+
+- if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED)
++ if (atomic_read(&port->status) & ZFCP_STATUS_COMMON_ERP_FAILED) {
++ zfcp_dbf_rec_trig(id, port->adapter, port, NULL,
++ ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
++ ZFCP_ERP_ACTION_FAILED);
+ return;
++ }
+
+ zfcp_erp_action_enqueue(ZFCP_ERP_ACTION_REOPEN_PORT_FORCED,
+ port->adapter, port, NULL, id, 0);
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-result-of-eh_host_reset_handler.patch b/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-result-of-eh_host_reset_handler.patch
new file mode 100644
index 0000000000..572f88fb21
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-result-of-eh_host_reset_handler.patch
@@ -0,0 +1,143 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:43 +0200
+Subject: scsi: zfcp: fix missing SCSI trace for result of eh_host_reset_handler
+Git-commit: df30781699f53e4fd4c494c6f7dd16e3d5c21d30
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+For problem determination we need to see whether and why we were successful
+or not. This allows deduction of scsi_eh escalation.
+
+Example trace record formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : SCSI
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1
+Tag : schrh_r SCSI host reset handler result
+Request ID : 0x0000000000000000 none (invalid)
+SCSI ID : 0xffffffff none (invalid)
+SCSI LUN : 0xffffffff none (invalid)
+SCSI LUN high : 0xffffffff none (invalid)
+SCSI result : 0x00002002 field re-used for midlayer value: SUCCESS
+ or in other cases: 0x2009 == FAST_IO_FAIL
+SCSI retries : 0xff none (invalid)
+SCSI allowed : 0xff none (invalid)
+SCSI scribble : 0xffffffffffffffff none (invalid)
+SCSI opcode : ffffffff ffffffff ffffffff ffffffff none (invalid)
+FCP rsp inf cod: 0xff none (invalid)
+FCP rsp IU : 00000000 00000000 00000000 00000000 none (invalid)
+ 00000000 00000000
+
+v2.6.35 commit a1dbfddd02d2 ("[SCSI] zfcp: Pass return code from
+fc_block_scsi_eh to scsi eh") introduced the first return with something
+other than the previously hardcoded single SUCCESS return path.
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Fixes: a1dbfddd02d2 ("[SCSI] zfcp: Pass return code from fc_block_scsi_eh to scsi eh")
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Jens Remus <jremus@linux.ibm.com>
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_dbf.c | 40 ++++++++++++++++++++++++++++++++++++++++
+ drivers/s390/scsi/zfcp_ext.h | 2 ++
+ drivers/s390/scsi/zfcp_scsi.c | 11 ++++++-----
+ 3 files changed, 48 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c
+index a8b831000b2d..1e5ea5e4992b 100644
+--- a/drivers/s390/scsi/zfcp_dbf.c
++++ b/drivers/s390/scsi/zfcp_dbf.c
+@@ -643,6 +643,46 @@ void zfcp_dbf_scsi(char *tag, int level, struct scsi_cmnd *sc,
+ spin_unlock_irqrestore(&dbf->scsi_lock, flags);
+ }
+
++/**
++ * zfcp_dbf_scsi_eh() - Trace event for special cases of scsi_eh callbacks.
++ * @tag: Identifier for event.
++ * @adapter: Pointer to zfcp adapter as context for this event.
++ * @scsi_id: SCSI ID/target to indicate scope of task management function (TMF).
++ * @ret: Return value of calling function.
++ *
++ * This SCSI trace variant does not depend on any of:
++ * scsi_cmnd, zfcp_fsf_req, scsi_device.
++ */
++void zfcp_dbf_scsi_eh(char *tag, struct zfcp_adapter *adapter,
++ unsigned int scsi_id, int ret)
++{
++ struct zfcp_dbf *dbf = adapter->dbf;
++ struct zfcp_dbf_scsi *rec = &dbf->scsi_buf;
++ unsigned long flags;
++ static int const level = 1;
++
++ if (unlikely(!debug_level_enabled(adapter->dbf->scsi, level)))
++ return;
++
++ spin_lock_irqsave(&dbf->scsi_lock, flags);
++ memset(rec, 0, sizeof(*rec));
++
++ memcpy(rec->tag, tag, ZFCP_DBF_TAG_LEN);
++ rec->id = ZFCP_DBF_SCSI_CMND;
++ rec->scsi_result = ret; /* re-use field, int is 4 bytes and fits */
++ rec->scsi_retries = ~0;
++ rec->scsi_allowed = ~0;
++ rec->fcp_rsp_info = ~0;
++ rec->scsi_id = scsi_id;
++ rec->scsi_lun = (u32)ZFCP_DBF_INVALID_LUN;
++ rec->scsi_lun_64_hi = (u32)(ZFCP_DBF_INVALID_LUN >> 32);
++ rec->host_scribble = ~0;
++ memset(rec->scsi_opcode, 0xff, ZFCP_DBF_SCSI_OPCODE);
++
++ debug_event(dbf->scsi, level, rec, sizeof(*rec));
++ spin_unlock_irqrestore(&dbf->scsi_lock, flags);
++}
++
+ static debug_info_t *zfcp_dbf_reg(const char *name, int size, int rec_size)
+ {
+ struct debug_info *d;
+diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h
+index bf8ea4df2bb8..e55f42ce1168 100644
+--- a/drivers/s390/scsi/zfcp_ext.h
++++ b/drivers/s390/scsi/zfcp_ext.h
+@@ -49,6 +49,8 @@ extern void zfcp_dbf_san_res(char *, struct zfcp_fsf_req *);
+ extern void zfcp_dbf_san_in_els(char *, struct zfcp_fsf_req *);
+ extern void zfcp_dbf_scsi(char *, int, struct scsi_cmnd *,
+ struct zfcp_fsf_req *);
++extern void zfcp_dbf_scsi_eh(char *tag, struct zfcp_adapter *adapter,
++ unsigned int scsi_id, int ret);
+
+ /* zfcp_erp.c */
+ extern void zfcp_erp_set_adapter_status(struct zfcp_adapter *, u32);
+diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
+index 4d2ba5682493..a62357f5e8b4 100644
+--- a/drivers/s390/scsi/zfcp_scsi.c
++++ b/drivers/s390/scsi/zfcp_scsi.c
+@@ -323,15 +323,16 @@ static int zfcp_scsi_eh_host_reset_handler(struct scsi_cmnd *scpnt)
+ {
+ struct zfcp_scsi_dev *zfcp_sdev = sdev_to_zfcp(scpnt->device);
+ struct zfcp_adapter *adapter = zfcp_sdev->port->adapter;
+- int ret;
++ int ret = SUCCESS, fc_ret;
+
+ zfcp_erp_adapter_reopen(adapter, 0, "schrh_1");
+ zfcp_erp_wait(adapter);
+- ret = fc_block_scsi_eh(scpnt);
+- if (ret)
+- return ret;
++ fc_ret = fc_block_scsi_eh(scpnt);
++ if (fc_ret)
++ ret = fc_ret;
+
+- return SUCCESS;
++ zfcp_dbf_scsi_eh("schrh_r", adapter, ~0, ret);
++ return ret;
+ }
+
+ struct scsi_transport_template *zfcp_scsi_transport_template;
+
diff --git a/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-retry-of-abort-scsi_eh-tmf.patch b/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-retry-of-abort-scsi_eh-tmf.patch
new file mode 100644
index 0000000000..135b482f43
--- /dev/null
+++ b/patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-retry-of-abort-scsi_eh-tmf.patch
@@ -0,0 +1,101 @@
+From: Steffen Maier <maier@linux.ibm.com>
+Date: Thu, 17 May 2018 19:14:44 +0200
+Subject: scsi: zfcp: fix missing SCSI trace for retry of abort / scsi_eh TMF
+Git-commit: 81979ae63e872ef650a7197f6ce6590059d37172
+Patch-mainline: v4.18-rc1
+References: bsc#1102088, LTC#169699
+
+We already have a SCSI trace for the end of abort and scsi_eh TMF. Due to
+zfcp_erp_wait() and fc_block_scsi_eh() time can pass between the start of
+our eh callback and an actual send/recv of an abort / TMF request. In order
+to see the temporal sequence including any abort / TMF send retries, add a
+trace before the above two blocking functions. This supports problem
+determination with scsi_eh and parallel zfcp ERP.
+
+No need to explicitly trace the beginning of our eh callback, since we
+typically can send an abort / TMF and see its HBA response (in the worst
+case, it's a pseudo response on dismiss all of adapter recovery, e.g. due to
+an FSF request timeout [fsrth_1] of the abort / TMF). If we cannot send, we
+now get a trace record for the first "abrt_wt" or "[lt]r_wait" which denotes
+almost the beginning of the callback.
+
+No need to explicitly trace the wakeup after the above two blocking
+functions because the next retry loop causes another trace in any case and
+that is sufficient.
+
+Example trace records formatted with zfcpdbf from s390-tools:
+
+Timestamp : ...
+Area : SCSI
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1
+Tag : abrt_wt abort, before zfcp_erp_wait()
+Request ID : 0x0000000000000000 none (invalid)
+SCSI ID : 0x<scsi_id>
+SCSI LUN : 0x<scsi_lun>
+SCSI LUN high : 0x<scsi_lun_high>
+SCSI result : 0x<scsi_result_of_cmd_to_be_aborted>
+SCSI retries : 0x<retries_of_cmd_to_be_aborted>
+SCSI allowed : 0x<allowed_retries_of_cmd_to_be_aborted>
+SCSI scribble : 0x<req_id_of_cmd_to_be_aborted>
+SCSI opcode : <CDB_of_cmd_to_be_aborted>
+FCP rsp inf cod: 0x.. none (invalid)
+FCP rsp IU : ... none (invalid)
+
+Timestamp : ...
+Area : SCSI
+Subarea : 00
+Level : 1
+Exception : -
+CPU ID : ..
+Caller : 0x...
+Record ID : 1
+Tag : lr_wait LUN reset, before zfcp_erp_wait()
+Request ID : 0x0000000000000000 none (invalid)
+SCSI ID : 0x<scsi_id>
+SCSI LUN : 0x<scsi_lun>
+SCSI LUN high : 0x<scsi_lun_high>
+SCSI result : 0x... unrelated
+SCSI retries : 0x.. unrelated
+SCSI allowed : 0x.. unrelated
+SCSI scribble : 0x... unrelated
+SCSI opcode : ... unrelated
+FCP rsp inf cod: 0x.. none (invalid)
+FCP rsp IU : ... none (invalid)
+
+Signed-off-by: Steffen Maier <maier@linux.ibm.com>
+Fixes: 63caf367e1c9 ("[SCSI] zfcp: Improve reliability of SCSI eh handlers in zfcp")
+Fixes: af4de36d911a ("[SCSI] zfcp: Block scsi_eh thread for rport state BLOCKED")
+Cc: <stable@vger.kernel.org> #2.6.38+
+Reviewed-by: Benjamin Block <bblock@linux.ibm.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Acked-by: Johannes Thumshirn <jthumshirn@suse.de>
+---
+ drivers/s390/scsi/zfcp_scsi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
+index a62357f5e8b4..4fdb1665b0e6 100644
+--- a/drivers/s390/scsi/zfcp_scsi.c
++++ b/drivers/s390/scsi/zfcp_scsi.c
+@@ -181,6 +181,7 @@ static int zfcp_scsi_eh_abort_handler(struct scsi_cmnd *scpnt)
+ if (abrt_req)
+ break;
+
++ zfcp_dbf_scsi_abort("abrt_wt", scpnt, NULL);
+ zfcp_erp_wait(adapter);
+ ret = fc_block_scsi_eh(scpnt);
+ if (ret) {
+@@ -277,6 +278,7 @@ static int zfcp_task_mgmt_function(struct scsi_cmnd *scpnt, u8 tm_flags)
+ if (fsf_req)
+ break;
+
++ zfcp_dbf_scsi_devreset("wait", scpnt, tm_flags, NULL);
+ zfcp_erp_wait(adapter);
+ ret = fc_block_scsi_eh(scpnt);
+ if (ret) {
+
diff --git a/patches.drivers/thermal-bcm2835-fix-an-error-code-in-probe b/patches.drivers/thermal-bcm2835-fix-an-error-code-in-probe
new file mode 100644
index 0000000000..5ea5c6d85b
--- /dev/null
+++ b/patches.drivers/thermal-bcm2835-fix-an-error-code-in-probe
@@ -0,0 +1,37 @@
+From 1fe3854a83b580727c9464b37b62ba77ead1d6f6 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Wed, 14 Jun 2017 12:13:27 +0300
+Subject: [PATCH] thermal: bcm2835: fix an error code in probe()
+Git-commit: 1fe3854a83b580727c9464b37b62ba77ead1d6f6
+Patch-mainline: v4.13-rc1
+References: bsc#1051510
+
+This causes a static checker because we're passing a valid pointer to
+PTR_ERR(). "err" is already the correct error code, so we can just
+delete this line.
+
+Fixes: bcb7dd9ef206 ("thermal: bcm2835: add thermal driver for bcm2835 SoC")
+Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/broadcom/bcm2835_thermal.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/thermal/broadcom/bcm2835_thermal.c b/drivers/thermal/broadcom/bcm2835_thermal.c
+index 0ecf80890c84..e6863c841662 100644
+--- a/drivers/thermal/broadcom/bcm2835_thermal.c
++++ b/drivers/thermal/broadcom/bcm2835_thermal.c
+@@ -245,7 +245,6 @@ static int bcm2835_thermal_probe(struct platform_device *pdev)
+ */
+ err = tz->ops->get_trip_temp(tz, 0, &trip_temp);
+ if (err < 0) {
+- err = PTR_ERR(tz);
+ dev_err(&pdev->dev,
+ "Not able to read trip_temp: %d\n",
+ err);
+--
+2.18.0
+
diff --git a/patches.drivers/thermal-drivers-hisi-Fix-kernel-panic-on-alarm-inter b/patches.drivers/thermal-drivers-hisi-Fix-kernel-panic-on-alarm-inter
new file mode 100644
index 0000000000..1bd86982c4
--- /dev/null
+++ b/patches.drivers/thermal-drivers-hisi-Fix-kernel-panic-on-alarm-inter
@@ -0,0 +1,58 @@
+From 2cb4de785c40d4a2132cfc13e63828f5a28c3351 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Thu, 19 Oct 2017 19:05:45 +0200
+Subject: [PATCH] thermal/drivers/hisi: Fix kernel panic on alarm interrupt
+Git-commit: 2cb4de785c40d4a2132cfc13e63828f5a28c3351
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The threaded interrupt for the alarm interrupt is requested before the
+temperature controller is setup. This one can fire an interrupt immediately
+leading to a kernel panic as the sensor data is not initialized.
+
+In order to prevent that, move the threaded irq after the Tsensor is setup.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Leo Yan <leo.yan@linaro.org>
+Tested-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/hisi_thermal.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/drivers/thermal/hisi_thermal.c
++++ b/drivers/thermal/hisi_thermal.c
+@@ -317,15 +317,6 @@ static int hisi_thermal_probe(struct pla
+ if (data->irq < 0)
+ return data->irq;
+
+- ret = devm_request_threaded_irq(&pdev->dev, data->irq,
+- hisi_thermal_alarm_irq,
+- hisi_thermal_alarm_irq_thread,
+- 0, "hisi_thermal", data);
+- if (ret < 0) {
+- dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret);
+- return ret;
+- }
+-
+ platform_set_drvdata(pdev, data);
+
+ data->clk = devm_clk_get(&pdev->dev, "thermal_clk");
+@@ -357,6 +348,15 @@ static int hisi_thermal_probe(struct pla
+ hisi_thermal_toggle_sensor(&data->sensors[i], true);
+ }
+
++ ret = devm_request_threaded_irq(&pdev->dev, data->irq,
++ hisi_thermal_alarm_irq,
++ hisi_thermal_alarm_irq_thread,
++ 0, "hisi_thermal", data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret);
++ return ret;
++ }
++
+ enable_irq(data->irq);
+
+ return 0;
diff --git a/patches.drivers/thermal-drivers-hisi-Fix-missing-interrupt-enablemen b/patches.drivers/thermal-drivers-hisi-Fix-missing-interrupt-enablemen
new file mode 100644
index 0000000000..8ae8d13252
--- /dev/null
+++ b/patches.drivers/thermal-drivers-hisi-Fix-missing-interrupt-enablemen
@@ -0,0 +1,56 @@
+From c176b10b025acee4dc8f2ab1cd64eb73b5ccef53 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Thu, 19 Oct 2017 19:05:43 +0200
+Subject: [PATCH] thermal/drivers/hisi: Fix missing interrupt enablement
+Git-commit: c176b10b025acee4dc8f2ab1cd64eb73b5ccef53
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The interrupt for the temperature threshold is not enabled at the end of the
+probe function, enable it after the setup is complete.
+
+On the other side, the irq_enabled is not correctly set as we are checking if
+the interrupt is masked where 'yes' means irq_enabled=false.
+
+ irq_get_irqchip_state(data->irq, IRQCHIP_STATE_MASKED,
+ &data->irq_enabled);
+
+As we are always enabling the interrupt, it is pointless to check if
+the interrupt is masked or not, just set irq_enabled to 'true'.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Leo Yan <leo.yan@linaro.org>
+Tested-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/hisi_thermal.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c
+index bd3572c41585..8381696241d6 100644
+--- a/drivers/thermal/hisi_thermal.c
++++ b/drivers/thermal/hisi_thermal.c
+@@ -345,8 +345,7 @@ static int hisi_thermal_probe(struct platform_device *pdev)
+ }
+
+ hisi_thermal_enable_bind_irq_sensor(data);
+- irq_get_irqchip_state(data->irq, IRQCHIP_STATE_MASKED,
+- &data->irq_enabled);
++ data->irq_enabled = true;
+
+ for (i = 0; i < HISI_MAX_SENSORS; ++i) {
+ ret = hisi_thermal_register_sensor(pdev, data,
+@@ -358,6 +357,8 @@ static int hisi_thermal_probe(struct platform_device *pdev)
+ hisi_thermal_toggle_sensor(&data->sensors[i], true);
+ }
+
++ enable_irq(data->irq);
++
+ return 0;
+ }
+
+--
+2.18.0
+
diff --git a/patches.drivers/thermal-drivers-hisi-Fix-multiple-alarm-interrupts-f b/patches.drivers/thermal-drivers-hisi-Fix-multiple-alarm-interrupts-f
new file mode 100644
index 0000000000..09703e551e
--- /dev/null
+++ b/patches.drivers/thermal-drivers-hisi-Fix-multiple-alarm-interrupts-f
@@ -0,0 +1,74 @@
+From db2b0332608c8e648ea1e44727d36ad37cdb56cb Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Thu, 19 Oct 2017 19:05:47 +0200
+Subject: [PATCH] thermal/drivers/hisi: Fix multiple alarm interrupts firing
+Git-commit: db2b0332608c8e648ea1e44727d36ad37cdb56cb
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The DT specifies a threshold of 65000, we setup the register with a value in
+the temperature resolution for the controller, 64656.
+
+When we reach 64656, the interrupt fires, the interrupt is disabled. Then the
+irq thread runs and calls thermal_zone_device_update() which will call in turn
+hisi_thermal_get_temp().
+
+The function will look if the temperature decreased, assuming it was more than
+65000, but that is not the case because the current temperature is 64656
+(because of the rounding when setting the threshold). This condition being
+true, we re-enable the interrupt which fires immediately after exiting the irq
+thread. That happens again and again until the temperature goes to more than
+65000.
+
+Potentially, there is here an interrupt storm if the temperature stabilizes at
+this temperature. A very unlikely case but possible.
+
+In any case, it does not make sense to handle dozens of alarm interrupt for
+nothing.
+
+Fix this by rounding the threshold value to the controller resolution so the
+check against the threshold is consistent with the one set in the controller.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Leo Yan <leo.yan@linaro.org>
+Tested-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/hisi_thermal.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/hisi_thermal.c
++++ b/drivers/thermal/hisi_thermal.c
+@@ -90,6 +90,12 @@ static inline long hisi_thermal_temp_to_
+ return (temp - HISI_TEMP_BASE) / HISI_TEMP_STEP;
+ }
+
++static inline long hisi_thermal_round_temp(int temp)
++{
++ return hisi_thermal_step_to_temp(
++ hisi_thermal_temp_to_step(temp));
++}
++
+ static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data,
+ struct hisi_thermal_sensor *sensor)
+ {
+@@ -245,7 +251,7 @@ static irqreturn_t hisi_thermal_alarm_ir
+ sensor = &data->sensors[data->irq_bind_sensor];
+
+ dev_crit(&data->pdev->dev, "THERMAL ALARM: T > %d\n",
+- sensor->thres_temp / 1000);
++ sensor->thres_temp);
+ mutex_unlock(&data->thermal_lock);
+
+ for (i = 0; i < HISI_MAX_SENSORS; i++) {
+@@ -284,7 +290,7 @@ static int hisi_thermal_register_sensor(
+
+ for (i = 0; i < of_thermal_get_ntrips(sensor->tzd); i++) {
+ if (trip[i].type == THERMAL_TRIP_PASSIVE) {
+- sensor->thres_temp = trip[i].temperature;
++ sensor->thres_temp = hisi_thermal_round_temp(trip[i].temperature);
+ break;
+ }
+ }
diff --git a/patches.drivers/thermal-drivers-hisi-Simplify-the-temperature-step-c b/patches.drivers/thermal-drivers-hisi-Simplify-the-temperature-step-c
new file mode 100644
index 0000000000..5141f7c7a9
--- /dev/null
+++ b/patches.drivers/thermal-drivers-hisi-Simplify-the-temperature-step-c
@@ -0,0 +1,104 @@
+From 48880b979cdc9ef5a70af020f42b8ba1e51dbd34 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Thu, 19 Oct 2017 19:05:46 +0200
+Subject: [PATCH] thermal/drivers/hisi: Simplify the temperature/step computation
+Git-commit: 48880b979cdc9ef5a70af020f42b8ba1e51dbd34
+Patch-mainline: v4.15-rc1
+References: bsc#1051510
+
+The step and the base temperature are fixed values, we can simplify the
+computation by converting the base temperature to milli celsius and use a
+pre-computed step value. That saves us a lot of mult + div for nothing at
+runtime.
+
+Take also the opportunity to change the function names to be consistent with
+the rest of the code.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Leo Yan <leo.yan@linaro.org>
+Tested-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/hisi_thermal.c | 41 ++++++++++++++++++++++++++++-------------
+ 1 file changed, 28 insertions(+), 13 deletions(-)
+
+--- a/drivers/thermal/hisi_thermal.c
++++ b/drivers/thermal/hisi_thermal.c
+@@ -35,8 +35,9 @@
+ #define TEMP0_RST_MSK (0x1C)
+ #define TEMP0_VALUE (0x28)
+
+-#define HISI_TEMP_BASE (-60)
++#define HISI_TEMP_BASE (-60000)
+ #define HISI_TEMP_RESET (100000)
++#define HISI_TEMP_STEP (784)
+
+ #define HISI_MAX_SENSORS 4
+
+@@ -61,19 +62,32 @@ struct hisi_thermal_data {
+ void __iomem *regs;
+ };
+
+-/* in millicelsius */
+-static inline int _step_to_temp(int step)
++/*
++ * The temperature computation on the tsensor is as follow:
++ * Unit: millidegree Celsius
++ * Step: 255/200 (0.7843)
++ * Temperature base: -60°C
++ *
++ * The register is programmed in temperature steps, every step is 784
++ * millidegree and begins at -60 000 m°C
++ *
++ * The temperature from the steps:
++ *
++ * Temp = TempBase + (steps x 784)
++ *
++ * and the steps from the temperature:
++ *
++ * steps = (Temp - TempBase) / 784
++ *
++ */
++static inline int hisi_thermal_step_to_temp(int step)
+ {
+- /*
+- * Every step equals (1 * 200) / 255 celsius, and finally
+- * need convert to millicelsius.
+- */
+- return (HISI_TEMP_BASE * 1000 + (step * 200000 / 255));
++ return HISI_TEMP_BASE + (step * HISI_TEMP_STEP);
+ }
+
+-static inline long _temp_to_step(long temp)
++static inline long hisi_thermal_temp_to_step(long temp)
+ {
+- return ((temp - HISI_TEMP_BASE * 1000) * 255) / 200000;
++ return (temp - HISI_TEMP_BASE) / HISI_TEMP_STEP;
+ }
+
+ static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data,
+@@ -99,7 +113,7 @@ static long hisi_thermal_get_sensor_temp
+ usleep_range(3000, 5000);
+
+ val = readl(data->regs + TEMP0_VALUE);
+- val = _step_to_temp(val);
++ val = hisi_thermal_step_to_temp(val);
+
+ mutex_unlock(&data->thermal_lock);
+
+@@ -126,10 +140,11 @@ static void hisi_thermal_enable_bind_irq
+ writel((sensor->id << 12), data->regs + TEMP0_CFG);
+
+ /* enable for interrupt */
+- writel(_temp_to_step(sensor->thres_temp) | 0x0FFFFFF00,
++ writel(hisi_thermal_temp_to_step(sensor->thres_temp) | 0x0FFFFFF00,
+ data->regs + TEMP0_TH);
+
+- writel(_temp_to_step(HISI_TEMP_RESET), data->regs + TEMP0_RST_TH);
++ writel(hisi_thermal_temp_to_step(HISI_TEMP_RESET),
++ data->regs + TEMP0_RST_TH);
+
+ /* enable module */
+ writel(0x1, data->regs + TEMP0_RST_MSK);
diff --git a/patches.drivers/thermal-fix-INTEL_SOC_DTS_IOSF_CORE-dependencies b/patches.drivers/thermal-fix-INTEL_SOC_DTS_IOSF_CORE-dependencies
new file mode 100644
index 0000000000..4771165ecb
--- /dev/null
+++ b/patches.drivers/thermal-fix-INTEL_SOC_DTS_IOSF_CORE-dependencies
@@ -0,0 +1,52 @@
+From 68fd77cf8a4b045594231f07e5fc92e1a34c0a9e Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 21 Jul 2017 18:16:28 +0200
+Subject: [PATCH] thermal: fix INTEL_SOC_DTS_IOSF_CORE dependencies
+Git-commit: 68fd77cf8a4b045594231f07e5fc92e1a34c0a9e
+Patch-mainline: v4.14-rc1
+References: bsc#1051510
+
+We get a Kconfig warning when selecting this without also enabling
+Config_pci:
+
+Warning: (X86_INTEL_LPSS && INTEL_SOC_DTS_IOSF_CORE
+&& SND_SST_IPC_ACPI && MMC_SDHCI_ACPI && PUNIT_ATOM_DEBUG)
+selects IOSF_MBI which has unmet direct dependencies (PCI)
+
+This adds a new depedency.
+
+Fixes: 3a2419f865a6 ("Thermal: Intel SoC: DTS thermal use common APIs")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/thermal/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
+index b5b5facb8747..ac2a53823576 100644
+--- a/drivers/thermal/Kconfig
++++ b/drivers/thermal/Kconfig
+@@ -342,7 +342,7 @@ config X86_PKG_TEMP_THERMAL
+
+ config INTEL_SOC_DTS_IOSF_CORE
+ tristate
+- depends on X86
++ depends on X86 && PCI
+ select IOSF_MBI
+ help
+ This is becoming a common feature for Intel SoCs to expose the additional
+@@ -352,7 +352,7 @@ config INTEL_SOC_DTS_IOSF_CORE
+
+ config INTEL_SOC_DTS_THERMAL
+ tristate "Intel SoCs DTS thermal driver"
+- depends on X86
++ depends on X86 && PCI
+ select INTEL_SOC_DTS_IOSF_CORE
+ select THERMAL_WRITABLE_TRIPS
+ help
+--
+2.18.0
+
diff --git a/patches.fixes/0001-Revert-xhci-plat-Register-shutdown-for-xhci_plat.patch b/patches.fixes/0001-Revert-xhci-plat-Register-shutdown-for-xhci_plat.patch
new file mode 100644
index 0000000000..46cad5a3a0
--- /dev/null
+++ b/patches.fixes/0001-Revert-xhci-plat-Register-shutdown-for-xhci_plat.patch
@@ -0,0 +1,40 @@
+From c20f53c58261b121d0989e147368803b9773b413 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Sun, 22 Apr 2018 14:31:03 +0200
+Subject: [PATCH] Revert "xhci: plat: Register shutdown for xhci_plat"
+Git-commit: c20f53c58261b121d0989e147368803b9773b413
+Patch-mainline: v4.17
+References: bsc#1090888
+
+This reverts commit b07c12517f2aed0add8ce18146bb426b14099392
+
+It is incomplete and causes hangs on devices when shutting down. It
+needs a much more "complete" fix in order to work properly. As that fix
+has not been merged, revert this patch for now before it causes any more
+problems.
+
+Cc: Greg Hackmann <ghackmann@google.com>
+Cc: Adam Wallis <awallis@codeaurora.org>
+Cc: Mathias Nyman <mathias.nyman@intel.com>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/host/xhci-plat.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 596e7a71b666..c1b22fc64e38 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -435,7 +435,6 @@ MODULE_DEVICE_TABLE(acpi, usb_xhci_acpi_match);
+ static struct platform_driver usb_xhci_driver = {
+ .probe = xhci_plat_probe,
+ .remove = xhci_plat_remove,
+- .shutdown = usb_hcd_platform_shutdown,
+ .driver = {
+ .name = "xhci-hcd",
+ .pm = &xhci_plat_pm_ops,
+--
+2.16.4
+
diff --git a/patches.fixes/0001-USB-OHCI-Fix-NULL-dereference-in-HCDs-using-HCD_LOCA.patch b/patches.fixes/0001-USB-OHCI-Fix-NULL-dereference-in-HCDs-using-HCD_LOCA.patch
new file mode 100644
index 0000000000..9d7f007381
--- /dev/null
+++ b/patches.fixes/0001-USB-OHCI-Fix-NULL-dereference-in-HCDs-using-HCD_LOCA.patch
@@ -0,0 +1,69 @@
+From d6c931ea32dc08ac2665bb5f009f9c40ad1bbdb3 Mon Sep 17 00:00:00 2001
+From: Fredrik Noring <noring@nocrew.org>
+Date: Fri, 9 Mar 2018 18:34:34 +0100
+Subject: [PATCH] USB: OHCI: Fix NULL dereference in HCDs using HCD_LOCAL_MEM
+Git-commit: d6c931ea32dc08ac2665bb5f009f9c40ad1bbdb3
+Patch-mainline: v4.16
+References: bsc#1087092
+
+Scatter-gather needs to be disabled when using dma_declare_coherent_memory
+and HCD_LOCAL_MEM. Andrea Righi made the equivalent fix for EHCI drivers
+in commit 4307a28eb01284 "USB: EHCI: fix NULL pointer dererence in HCDs
+that use HCD_LOCAL_MEM".
+
+The following NULL pointer WARN_ON_ONCE triggered with OHCI drivers:
+
+------------[ cut here ]------------
+WARNING: CPU: 0 PID: 49 at drivers/usb/core/hcd.c:1379 hcd_alloc_coherent+0x4c/0xc8
+Modules linked in:
+CPU: 0 PID: 49 Comm: usb-storage Not tainted 4.15.0+ #1014
+Stack : 00000000 00000000 805a78d2 0000003a 81f5c2cc 8053d367 804d77fc 00000031
+ 805a3a08 00000563 81ee9400 805a0000 00000000 10058c00 81f61b10 805c0000
+ 00000000 00000000 805a0000 00d9038e 00000004 803ee818 00000006 312e3420
+ 805c0000 00000000 00000073 81f61958 00000000 00000000 802eb380 804fd538
+ 00000009 00000563 81ee9400 805a0000 00000002 80056148 00000000 805a0000
+ ...
+Call Trace:
+[<578af360>] show_stack+0x74/0x104
+[<2f3702c6>] __warn+0x118/0x120
+[<ae93fc9e>] warn_slowpath_null+0x44/0x58
+[<a891a517>] hcd_alloc_coherent+0x4c/0xc8
+[<3578fa36>] usb_hcd_map_urb_for_dma+0x4d8/0x534
+[<110bc94c>] usb_hcd_submit_urb+0x82c/0x834
+[<02eb5baf>] usb_sg_wait+0x14c/0x1a0
+[<ccd09e85>] usb_stor_bulk_transfer_sglist.part.1+0xac/0x124
+[<87a5c34c>] usb_stor_bulk_srb+0x40/0x60
+[<ff1792ac>] usb_stor_Bulk_transport+0x160/0x37c
+[<b9e2709c>] usb_stor_invoke_transport+0x3c/0x500
+[<004754f4>] usb_stor_control_thread+0x258/0x28c
+[<22edf42e>] kthread+0x134/0x13c
+[<a419ffd0>] ret_from_kernel_thread+0x14/0x1c
+---[ end trace bcdb825805eefdcc ]---
+
+Signed-off-by: Fredrik Noring <noring@nocrew.org>
+Acked-by: Alan Stern <stern@rowland.harvard.edu>
+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/host/ohci-hcd.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
+index 84f88fa411cd..d088c340e4d0 100644
+--- a/drivers/usb/host/ohci-hcd.c
++++ b/drivers/usb/host/ohci-hcd.c
+@@ -447,7 +447,8 @@ static int ohci_init (struct ohci_hcd *ohci)
+ struct usb_hcd *hcd = ohci_to_hcd(ohci);
+
+ /* Accept arbitrarily long scatter-gather lists */
+- hcd->self.sg_tablesize = ~0;
++ if (!(hcd->driver->flags & HCD_LOCAL_MEM))
++ hcd->self.sg_tablesize = ~0;
+
+ if (distrust_firmware)
+ ohci->flags |= OHCI_QUIRK_HUB_POWER;
+--
+2.16.4
+
diff --git a/patches.fixes/0001-pinctrl-intel-Initialize-GPIO-properly-when-used-thr.patch b/patches.fixes/0001-pinctrl-intel-Initialize-GPIO-properly-when-used-thr.patch
new file mode 100644
index 0000000000..c39a6f1be5
--- /dev/null
+++ b/patches.fixes/0001-pinctrl-intel-Initialize-GPIO-properly-when-used-thr.patch
@@ -0,0 +1,94 @@
+From f5a26acf0162477af6ee4c11b4fb9cffe5d3e257 Mon Sep 17 00:00:00 2001
+From: Mika Westerberg <mika.westerberg@linux.intel.com>
+Date: Wed, 29 Nov 2017 16:25:44 +0300
+Subject: [PATCH] pinctrl: intel: Initialize GPIO properly when used through
+ irqchip
+Git-commit: f5a26acf0162477af6ee4c11b4fb9cffe5d3e257
+Patch-mainline: v4.16
+References: bsc#1087092
+
+When a GPIO is requested using gpiod_get_* APIs the intel pinctrl driver
+switches the pin to GPIO mode and makes sure interrupts are routed to
+the GPIO hardware instead of IOAPIC. However, if the GPIO is used
+directly through irqchip, as is the case with many I2C-HID devices where
+I2C core automatically configures interrupt for the device, the pin is
+not initialized as GPIO. Instead we rely that the BIOS configures the
+pin accordingly which seems not to be the case at least in Asus X540NA
+SKU3 with Focaltech touchpad.
+
+When the pin is not properly configured it might result weird behaviour
+like interrupts suddenly stop firing completely and the touchpad stops
+responding to user input.
+
+Fix this by properly initializing the pin to GPIO mode also when it is
+used directly through irqchip.
+
+Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
+Reported-by: Daniel Drake <drake@endlessm.com>
+Reported-and-tested-by: Chris Chiu <chiu@endlessm.com>
+Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/pinctrl/intel/pinctrl-intel.c | 23 +++++++++++++++--------
+ 1 file changed, 15 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
+index 4c2369a8d926..359800fcb951 100644
+--- a/drivers/pinctrl/intel/pinctrl-intel.c
++++ b/drivers/pinctrl/intel/pinctrl-intel.c
+@@ -425,6 +425,18 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
+ writel(value, padcfg0);
+ }
+
++static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
++{
++ u32 value;
++
++ /* Put the pad into GPIO mode */
++ value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
++ /* Disable SCI/SMI/NMI generation */
++ value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
++ value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
++ writel(value, padcfg0);
++}
++
+ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned pin)
+@@ -432,7 +444,6 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *padcfg0;
+ unsigned long flags;
+- u32 value;
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+@@ -442,13 +453,7 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
+ }
+
+ padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
+- /* Put the pad into GPIO mode */
+- value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
+- /* Disable SCI/SMI/NMI generation */
+- value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
+- value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
+- writel(value, padcfg0);
+-
++ intel_gpio_set_gpio_mode(padcfg0);
+ /* Disable TX buffer and enable RX (this will be input) */
+ __intel_gpio_set_direction(padcfg0, true);
+
+@@ -968,6 +973,8 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
++ intel_gpio_set_gpio_mode(reg);
++
+ value = readl(reg);
+
+ value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
+--
+2.16.4
+
diff --git a/patches.fixes/0001-pinctrl-nsp-off-by-ones-in-nsp_pinmux_enable.patch b/patches.fixes/0001-pinctrl-nsp-off-by-ones-in-nsp_pinmux_enable.patch
new file mode 100644
index 0000000000..21a7db1187
--- /dev/null
+++ b/patches.fixes/0001-pinctrl-nsp-off-by-ones-in-nsp_pinmux_enable.patch
@@ -0,0 +1,38 @@
+From f90a21c898db58eaea14b8ad7e9af3b9e15e5f8a Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 3 Jul 2018 15:04:25 +0300
+Subject: [PATCH] pinctrl: nsp: off by ones in nsp_pinmux_enable()
+Git-commit: f90a21c898db58eaea14b8ad7e9af3b9e15e5f8a
+Patch-mainline: v4.18
+References: bsc#1100132
+
+The > comparisons should be >= or else we read beyond the end of the
+pinctrl->functions[] array.
+
+Fixes: cc4fa83f66e9 ("pinctrl: nsp: add pinmux driver support for Broadcom NSP SoC")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Ray Jui <ray.jui@broadcom.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/pinctrl/bcm/pinctrl-nsp-mux.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+index 35c17653c694..5cd8166fbbc8 100644
+--- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
++++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+@@ -460,8 +460,8 @@ static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
+ const struct nsp_pin_function *func;
+ const struct nsp_pin_group *grp;
+
+- if (grp_select > pinctrl->num_groups ||
+- func_select > pinctrl->num_functions)
++ if (grp_select >= pinctrl->num_groups ||
++ func_select >= pinctrl->num_functions)
+ return -EINVAL;
+
+ func = &pinctrl->functions[func_select];
+--
+2.16.4
+
diff --git a/patches.fixes/0001-usb-cdc_acm-prevent-race-at-write-to-acm-while-syste.patch b/patches.fixes/0001-usb-cdc_acm-prevent-race-at-write-to-acm-while-syste.patch
new file mode 100644
index 0000000000..caf138a702
--- /dev/null
+++ b/patches.fixes/0001-usb-cdc_acm-prevent-race-at-write-to-acm-while-syste.patch
@@ -0,0 +1,97 @@
+From b86b8eb6fecb5a4bac1ed0ca925c4082a61ea6e9 Mon Sep 17 00:00:00 2001
+From: Dominik Bozek <dominikx.bozek@intel.com>
+Date: Thu, 15 Feb 2018 21:27:48 -0800
+Subject: [PATCH] usb: cdc_acm: prevent race at write to acm while system
+ resumes
+Git-commit: b86b8eb6fecb5a4bac1ed0ca925c4082a61ea6e9
+Patch-mainline: v4.16
+References: bsc#1087092
+
+ACM driver may accept data to transmit while system is not fully
+resumed. In this case ACM driver buffers data and prepare URBs
+on usb anchor list.
+There is a little chance that two tasks put a char and initiate
+acm_tty_flush_chars(). In such a case, driver will put one URB
+twice on usb anchor list.
+This patch also reset length of data before resue of a buffer.
+This not only prevent sending rubbish, but also lower risc of race.
+
+Without this patch we hit following kernel panic in one of our
+stabilty/stress tests.
+
+[ 46.884442] *list_add double add*: new=ffff9b2ab7289330, prev=ffff9b2ab7289330, next=ffff9b2ab81e28e0.
+[ 46.884476] Modules linked in: hci_uart btbcm bluetooth rfkill_gpio igb_avb(O) cfg80211 snd_soc_sst_bxt_tdf8532 snd_soc_skl snd_soc_skl_ipc snd_soc_sst_ipc snd_soc_sst_dsp snd_soc_sst_acpi snd_soc_sst_match snd_hda_ext_core snd_hda_core trusty_timer trusty_wall trusty_log trusty_virtio trusty_ipc trusty_mem trusty_irq trusty virtio_ring virtio intel_ipu4_mmu_bxtB0 lib2600_mod_bxtB0 intel_ipu4_isys_mod_bxtB0 lib2600psys_mod_bxtB0 intel_ipu4_psys_mod_bxtB0 intel_ipu4_mod_bxtB0 intel_ipu4_wrapper_bxtB0 intel_ipu4_acpi videobuf2_dma_contig as3638 dw9714 lm3643 crlmodule smiapp smiapp_pll
+[ 46.884480] CPU: 1 PID: 33 Comm: kworker/u8:1 Tainted: G U W O 4.9.56-quilt-2e5dc0ac-g618ed69ced6e-dirty #4
+[ 46.884489] Workqueue: events_unbound flush_to_ldisc
+[ 46.884494] ffffb98ac012bb08 ffffffffad3e82e5 ffffb98ac012bb58 0000000000000000
+[ 46.884497] ffffb98ac012bb48 ffffffffad0a23d1 00000024ad6374dd ffff9b2ab7289330
+[ 46.884500] ffff9b2ab81e28e0 ffff9b2ab7289330 0000000000000002 0000000000000000
+[ 46.884501] Call Trace:
+[ 46.884507] [<ffffffffad3e82e5>] dump_stack+0x67/0x92
+[ 46.884511] [<ffffffffad0a23d1>] __warn+0xd1/0xf0
+[ 46.884513] [<ffffffffad0a244f>] warn_slowpath_fmt+0x5f/0x80
+[ 46.884516] [<ffffffffad407443>] __list_add+0xb3/0xc0
+[ 46.884521] [<ffffffffad71133c>] *usb_anchor_urb*+0x4c/0xa0
+[ 46.884524] [<ffffffffad782c6f>] *acm_tty_flush_chars*+0x8f/0xb0
+[ 46.884527] [<ffffffffad782cd1>] *acm_tty_put_char*+0x41/0x100
+[ 46.884530] [<ffffffffad4ced34>] tty_put_char+0x24/0x40
+[ 46.884533] [<ffffffffad4d3bf5>] do_output_char+0xa5/0x200
+[ 46.884535] [<ffffffffad4d3e98>] __process_echoes+0x148/0x290
+[ 46.884538] [<ffffffffad4d654c>] n_tty_receive_buf_common+0x57c/0xb00
+[ 46.884541] [<ffffffffad4d6ae4>] n_tty_receive_buf2+0x14/0x20
+[ 46.884543] [<ffffffffad4d9662>] tty_ldisc_receive_buf+0x22/0x50
+[ 46.884545] [<ffffffffad4d9c05>] flush_to_ldisc+0xc5/0xe0
+[ 46.884549] [<ffffffffad0bcfe8>] process_one_work+0x148/0x440
+[ 46.884551] [<ffffffffad0bdc19>] worker_thread+0x69/0x4a0
+[ 46.884554] [<ffffffffad0bdbb0>] ? max_active_store+0x80/0x80
+[ 46.884556] [<ffffffffad0c2e10>] kthread+0x110/0x130
+[ 46.884559] [<ffffffffad0c2d00>] ? kthread_park+0x60/0x60
+[ 46.884563] [<ffffffffadad9917>] ret_from_fork+0x27/0x40
+[ 46.884566] ---[ end trace 3bd599058b8a9eb3 ]---
+
+Signed-off-by: Dominik Bozek <dominikx.bozek@intel.com>
+Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
+Acked-by: Oliver Neukum <oneukum@suse.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/class/cdc-acm.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
+index 06b3b54a0e68..7b366a6c0b49 100644
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -174,6 +174,7 @@ static int acm_wb_alloc(struct acm *acm)
+ wb = &acm->wb[wbn];
+ if (!wb->use) {
+ wb->use = 1;
++ wb->len = 0;
+ return wbn;
+ }
+ wbn = (wbn + 1) % ACM_NW;
+@@ -805,16 +806,18 @@ static int acm_tty_write(struct tty_struct *tty,
+ static void acm_tty_flush_chars(struct tty_struct *tty)
+ {
+ struct acm *acm = tty->driver_data;
+- struct acm_wb *cur = acm->putbuffer;
++ struct acm_wb *cur;
+ int err;
+ unsigned long flags;
+
++ spin_lock_irqsave(&acm->write_lock, flags);
++
++ cur = acm->putbuffer;
+ if (!cur) /* nothing to do */
+- return;
++ goto out;
+
+ acm->putbuffer = NULL;
+ err = usb_autopm_get_interface_async(acm->control);
+- spin_lock_irqsave(&acm->write_lock, flags);
+ if (err < 0) {
+ cur->use = 0;
+ acm->putbuffer = cur;
+--
+2.16.4
+
diff --git a/patches.fixes/0001-usb-dwc2-Improve-gadget-state-disconnection-handling.patch b/patches.fixes/0001-usb-dwc2-Improve-gadget-state-disconnection-handling.patch
new file mode 100644
index 0000000000..b7bac712d2
--- /dev/null
+++ b/patches.fixes/0001-usb-dwc2-Improve-gadget-state-disconnection-handling.patch
@@ -0,0 +1,81 @@
+From d2471d4a24dfbff5e463d382e2c6fec7d7e25a09 Mon Sep 17 00:00:00 2001
+From: John Stultz <john.stultz@linaro.org>
+Date: Mon, 23 Oct 2017 14:32:48 -0700
+Subject: [PATCH] usb: dwc2: Improve gadget state disconnection handling
+Git-commit: d2471d4a24dfbff5e463d382e2c6fec7d7e25a09
+Patch-mainline: v4.15
+References: bsc#1085539
+
+In the earlier commit dad3f793f20f ("usb: dwc2: Make sure we
+disconnect the gadget state"), I was trying to fix up the
+fact that we somehow weren't disconnecting the gadget state,
+so that when the OTG port was plugged in the second time we
+would get warnings about the state tracking being wrong.
+
+(This seems to be due to a quirk of the HiKey board where
+we do not ever get any otg interrupts, particularly the session
+end detected signal. Instead we only see status change
+interrupt.)
+
+The fix there was somewhat simple, as it just made sure to
+call dwc2_hsotg_disconnect() before we connected things up
+in OTG mode, ensuring the state handling didn't throw errors.
+
+But in looking at a different issue I was seeing with UDC
+state handling, I realized that it would be much better
+to call dwc2_hsotg_disconnect when we get the state change
+signal moving to host mode.
+
+Thus, this patch removes the earlier disconnect call I added
+and moves it (and the needed locking) to the host mode
+transition.
+
+Cc: Wei Xu <xuwei5@hisilicon.com>
+Cc: Guodong Xu <guodong.xu@linaro.org>
+Cc: Amit Pundir <amit.pundir@linaro.org>
+Cc: YongQin Liu <yongqin.liu@linaro.org>
+Cc: John Youn <johnyoun@synopsys.com>
+Cc: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
+Cc: Douglas Anderson <dianders@chromium.org>
+Cc: Chen Yu <chenyu56@huawei.com>
+Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: linux-usb@vger.kernel.org
+Acked-by: Minas Harutyunyan <hminas@synopsys.com>
+Tested-by: Minas Harutyunyan <hminas@synopsys.com>
+Signed-off-by: John Stultz <john.stultz@linaro.org>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/dwc2/hcd.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
+index 5e2033616aca..e8fee0f969f0 100644
+--- a/drivers/usb/dwc2/hcd.c
++++ b/drivers/usb/dwc2/hcd.c
+@@ -3282,7 +3282,6 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
+ dwc2_core_init(hsotg, false);
+ dwc2_enable_global_interrupts(hsotg);
+ spin_lock_irqsave(&hsotg->lock, flags);
+- dwc2_hsotg_disconnect(hsotg);
+ dwc2_hsotg_core_init_disconnected(hsotg, false);
+ spin_unlock_irqrestore(&hsotg->lock, flags);
+ dwc2_hsotg_core_connect(hsotg);
+@@ -3301,8 +3300,12 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
+ if (count > 250)
+ dev_err(hsotg->dev,
+ "Connection id status change timed out\n");
+- hsotg->op_state = OTG_STATE_A_HOST;
+
++ spin_lock_irqsave(&hsotg->lock, flags);
++ dwc2_hsotg_disconnect(hsotg);
++ spin_unlock_irqrestore(&hsotg->lock, flags);
++
++ hsotg->op_state = OTG_STATE_A_HOST;
+ /* Initialize the Core for Host mode */
+ dwc2_core_init(hsotg, false);
+ dwc2_enable_global_interrupts(hsotg);
+--
+2.16.4
+
diff --git a/patches.fixes/0001-usb-option-Add-support-for-FS040U-modem.patch b/patches.fixes/0001-usb-option-Add-support-for-FS040U-modem.patch
new file mode 100644
index 0000000000..031616db64
--- /dev/null
+++ b/patches.fixes/0001-usb-option-Add-support-for-FS040U-modem.patch
@@ -0,0 +1,48 @@
+From 69341bd15018da0a662847e210f9b2380c71e623 Mon Sep 17 00:00:00 2001
+From: OKAMOTO Yoshiaki <yokamoto@allied-telesis.co.jp>
+Date: Tue, 16 Jan 2018 09:51:17 +0000
+Subject: [PATCH] usb: option: Add support for FS040U modem
+Git-commit: 69341bd15018da0a662847e210f9b2380c71e623
+Patch-mainline: v4.16
+References: bsc#1087092
+
+FS040U modem is manufactured by omega, and sold by Fujisoft. This patch
+adds ID of the modem to use option1 driver. Interface 3 is used as
+qmi_wwan, so the interface is ignored.
+
+Signed-off-by: Yoshiaki Okamoto <yokamoto@allied-telesis.co.jp>
+Signed-off-by: Hiroyuki Yamamoto <hyamamo@allied-telesis.co.jp>
+Cc: stable <stable@vger.kernel.org>
+Acked-by: Johan Hovold <johan@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+---
+ drivers/usb/serial/option.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index b6320e3be429..5db8ed517e0e 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -380,6 +380,9 @@ static void option_instat_callback(struct urb *urb);
+ #define FOUR_G_SYSTEMS_PRODUCT_W14 0x9603
+ #define FOUR_G_SYSTEMS_PRODUCT_W100 0x9b01
+
++/* Fujisoft products */
++#define FUJISOFT_PRODUCT_FS040U 0x9b02
++
+ /* iBall 3.5G connect wireless modem */
+ #define IBALL_3_5G_CONNECT 0x9605
+
+@@ -1894,6 +1897,8 @@ static const struct usb_device_id option_ids[] = {
+ { USB_DEVICE(LONGCHEER_VENDOR_ID, FOUR_G_SYSTEMS_PRODUCT_W100),
+ .driver_info = (kernel_ulong_t)&four_g_w100_blacklist
+ },
++ {USB_DEVICE(LONGCHEER_VENDOR_ID, FUJISOFT_PRODUCT_FS040U),
++ .driver_info = (kernel_ulong_t)&net_intf3_blacklist},
+ { USB_DEVICE_INTERFACE_CLASS(LONGCHEER_VENDOR_ID, SPEEDUP_PRODUCT_SU9800, 0xff) },
+ { USB_DEVICE_INTERFACE_CLASS(LONGCHEER_VENDOR_ID, 0x9801, 0xff),
+ .driver_info = (kernel_ulong_t)&net_intf3_blacklist },
+--
+2.16.4
+
diff --git a/patches.fixes/xen-grant-table-log-the-lack-of-grants.patch b/patches.fixes/xen-grant-table-log-the-lack-of-grants.patch
new file mode 100644
index 0000000000..702bde4bc4
--- /dev/null
+++ b/patches.fixes/xen-grant-table-log-the-lack-of-grants.patch
@@ -0,0 +1,49 @@
+From: Wengang Wang <wen.gang.wang@oracle.com>
+Date: Tue Jul 18 09:40:35 2017 +0200
+Subject: xen/grant-table: log the lack of grants
+Patch-mainline: 4.13
+Git-commit: 29d11cfd8698038b87458ba4d1329b9da81150a5
+References: bnc#1085042
+
+log a message when we enter this situation:
+1) we already allocated the max number of available grants from hypervisor
+and
+2) we still need more (but the request fails because of 1)).
+
+Sometimes the lack of grants causes IO hangs in xen_blkfront devices.
+Adding this log would help debuging.
+
+Signed-off-by: Wengang Wang <wen.gang.wang@oracle.com>
+Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Reviewed-by: Junxiao Bi <junxiao.bi@oracle.com>
+Reviewed-by: Juergen Gross <jgross@suse.com>
+Signed-off-by: Juergen Gross <jgross@suse.com>
+
+diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
+index d6786b87e13b..2c6a9114d332 100644
+--- a/drivers/xen/grant-table.c
++++ b/drivers/xen/grant-table.c
+@@ -43,6 +43,7 @@
+ #include <linux/delay.h>
+ #include <linux/hardirq.h>
+ #include <linux/workqueue.h>
++#include <linux/ratelimit.h>
+
+ #include <xen/xen.h>
+ #include <xen/interface/xen.h>
+@@ -1073,8 +1074,14 @@ static int gnttab_expand(unsigned int req_entries)
+ cur = nr_grant_frames;
+ extra = ((req_entries + (grefs_per_grant_frame-1)) /
+ grefs_per_grant_frame);
+- if (cur + extra > gnttab_max_grant_frames())
++ if (cur + extra > gnttab_max_grant_frames()) {
++ pr_warn_ratelimited("xen/grant-table: max_grant_frames reached"
++ " cur=%u extra=%u limit=%u"
++ " gnttab_free_count=%u req_entries=%u\n",
++ cur, extra, gnttab_max_grant_frames(),
++ gnttab_free_count, req_entries);
+ return -ENOSPC;
++ }
+
+ rc = gnttab_map(cur, cur + extra - 1);
+ if (rc == 0)
diff --git a/series.conf b/series.conf
index 70ad46a456..0a7d07dfc4 100644
--- a/series.conf
+++ b/series.conf
@@ -2357,13 +2357,18 @@
patches.drivers/media-mceusb-fix-memory-leaks-in-error-path.patch
patches.drivers/media-dvb-uapi-docs-enums-are-passed-by-value-not-re
patches.drivers/0005-pinctrl-rockchip-remove-unneeded-void-casts-in-of_ma.patch
+ patches.drivers/pinctrl-imx-fix-debug-message-for-SHARE_MUX_CONF_REG
+ patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-I2S-pins
+ patches.drivers/pinctrl-meson-gxl-Fix-typo-in-AO-SPDIF-pins
patches.drivers/0006-pinctrl-rockchip-Add-iomux-route-switching-support.patch
patches.drivers/0007-pinctrl-rockchip-Add-iomux-route-switching-support-f.patch
patches.drivers/0008-pinctrl-rockchip-Add-iomux-route-switching-support-f.patch
patches.drivers/0009-pinctrl-rockchip-Add-iomux-route-switching-support-f.patch
+ patches.drivers/pinctrl-meson-gxbb-remove-non-existing-pin-GPIOX_22
patches.drivers/0001-pinctrl-intel-Add-support-for-variable-size-pad-grou.patch
patches.drivers/0002-pinctrl-intel-Make-it-possible-to-specify-mode-per-p.patch
patches.drivers/0003-pinctrl-intel-Add-Intel-Cannon-Lake-PCH-pin-controll.patch
+ patches.drivers/pinctrl-bcm2835-Avoid-warning-from-__irq_do_set_hand
patches.drivers/IB-opa_vnic-Use-GFP_ATOMIC-while-sending-trap.patch
patches.drivers/IB-opa_vnic-Use-spinlock-instead-of-mutex-for-stats_.patch
patches.drivers/IB-core-opa_vnic-hfi1-mlx5-Properly-free-rdma_netdev.patch
@@ -2807,8 +2812,17 @@
patches.drivers/dax-convert-to-bitmask-for-flags.patch
patches.drivers/libnvdimm-pmem-dax-export-a-cache-control-attribute.patch
patches.drivers/libnvdimm-pmem-disable-dax-flushing-when-pmem-is-fro.patch
+ patches.drivers/clk-at91-fix-clk-generated-parenting
+ patches.drivers/clk-scpi-fix-return-type-of-__scpi_dvfs_round_rate
+ patches.drivers/clk-Fix-__set_clk_rates-error-print-string
+ patches.drivers/clk-renesas-rcar-gen2-Fix-PLL0-on-R-Car-V2H-and-E2
+ patches.drivers/clk-renesas-r8a7745-Remove-nonexisting-scu-src-0789-
+ patches.drivers/clk-renesas-r8a7745-Remove-PLL-configs-for-MD19-0
+ patches.drivers/clk-renesas-r8a7795-Correct-pwm-gpio-and-i2c-parent-
patches.drivers/0023-clk-rockchip-add-dt-binding-header-for-rk3128.patch
patches.drivers/0024-clk-rockchip-add-ids-for-rk3399-testclks-used-for-ca.patch
+ patches.drivers/clk-socfpga-Fix-the-smplsel-on-Arria10-and-Stratix10
+ patches.drivers/clk-scpi-error-when-clock-fails-to-register
patches.drivers/0003-mfd-intel-lpss-Add-Intel-Cannonlake-PCI-IDs.patch
patches.drivers/mfd-rn5t618-Unregister-restart-handler-on-remove
patches.drivers/mfd-intel_soc_pmic-Select-designware-i2c-bus-driver
@@ -3631,6 +3645,7 @@
patches.drivers/0056-drm-rockchip-gem-add-the-lacks-lock-and-trivial-chan.patch
patches.drivers/drm-vblank-Fix-vblank-timestamp-update
patches.drivers/0062-drm-rockchip-fix-NULL-check-on-devm_kzalloc-return-v.patch
+ patches.drivers/pwm-meson-Improve-PWM-calculation-precision
patches.suse/0001-mtd-partitions-add-helper-for-deleting-partition.patch
patches.suse/0001-mtd-partitions-remove-sysfs-files-when-deleting-all-.patch
patches.arch/rtc-opal-Handle-disabled-TPO-in-opal_get_tpo_time.patch
@@ -3749,6 +3764,7 @@
patches.drivers/ALSA-hda-realtek-New-codec-device-ID-for-ALC1220
patches.drivers/ALSA-hda-Add-hdmi-id-for-a-Geminilake-variant
patches.drivers/mmc-sdhci-acpi-Workaround-conflict-with-PCI-wifi-on-
+ patches.drivers/thermal-bcm2835-fix-an-error-code-in-probe
patches.arch/powerpc-powernv-Tell-OPAL-about-our-MMU-mode-on-POWER9.patch
patches.arch/powerpc-mm-radix-Synchronize-updates-to-the-process-table.patch
patches.arch/powerpc-powernv-Fix-local-TLB-flush-for-boot-and-MCE.patch
@@ -3912,6 +3928,7 @@
patches.drivers/0018-usb-typec-include-linux-device.h-in-ucsi.h.patch
patches.drivers/0027-thunderbolt-Correct-access-permissions-for-active-NV.patch
patches.drivers/fsi-core-register-with-postcore_initcall
+ patches.fixes/xen-grant-table-log-the-lack-of-grants.patch
patches.fixes/xen-balloon-don-t-online-new-memory-initially.patch
patches.suse/s390-perf-fix-problem-state-detection.patch
patches.drivers/0017-uuid-fix-incorrect-uuid_equal-conversion-in-test_uui.patch
@@ -4026,6 +4043,8 @@
patches.suse/KVM-arm-arm64-Fix-bug-in-advertising-KVM_CAP_MSI_DEV.patch
patches.suse/KVM-arm-arm64-PMU-Fix-overflow-interrupt-injection.patch
patches.suse/KVM-arm-arm64-vgic-Use-READ_ONCE-fo-cmpxchg.patch
+ patches.drivers/clk-x86-Do-not-gate-clocks-enabled-by-the-firmware
+ patches.drivers/clk-meson-mpll-fix-mpll0-fractional-part-ignored
patches.drivers/gpio-tegra-fix-unbalanced-chained_irq_enter-exit
patches.drivers/media-Revert-media-et8ek8-Export-OF-device-ID-as-mod.patch
patches.drivers/media-rainshadow-cec-avoid-Wmaybe-uninitialized-warn2.patch
@@ -4054,6 +4073,7 @@
patches.drivers/IB-ipoib-Notify-on-modify-QP-failure-only-when-relev.patch
patches.drivers/vxlan-fix-remcsum-when-GRO-on-and-CHECKSUM_PARTIAL-b.patch
patches.drivers/gue-fix-remcsum-when-GRO-on-and-CHECKSUM_PARTIAL-bou.patch
+ patches.drivers/b44-Initialize-64-bit-stats-seqcount
patches.drivers/i40e-Initialize-64-bit-statistics-TX-ring-seqcount.patch
patches.drivers/ixgbe-Initialize-64-bit-stats-seqcounts.patch
patches.drivers/nfp-Initialize-RX-and-TX-ring-64-bit-stats-seqcounts.patch
@@ -4247,6 +4267,7 @@
patches.fixes/netfilter-nf_tables-Fix-nft-limit-burst-handling.patch
patches.fixes/tipc-reassign-pointers-after-skb-reallocation-linear.patch
patches.drivers/r8169-Do-not-increment-tx_dropped-in-TX-ring-cleanin
+ patches.drivers/r8169-Be-drop-monitor-friendly
patches.drivers/0145-iwlwifi-pcie-move-rx-workqueue-initialization-to-iwl.patch
patches.fixes/l2tp-initialise-session-s-refcount-before-making-it-.patch
patches.fixes/l2tp-hold-tunnel-while-looking-up-sessions-in-l2tp_n.patch
@@ -5266,12 +5287,18 @@
patches.fixes/regulator-da9063-return-an-error-code-on-probe-failure.patch
patches.drivers/0001-regulator-fan53555-Use-of_device_get_match_data-to-s.patch
patches.drivers/0002-regulator-fan53555-fix-I2C-device-ids.patch
+ patches.drivers/pinctrl-uniphier-fix-pin_config_get-for-input-enable
patches.drivers/0010-pinctrl-rockchip-Use-common-interface-for-recalced-i.patch
+ patches.drivers/pinctrl-sunxi-fix-V3s-pinctrl-driver-IRQ-bank-base
patches.drivers/pinctrl-intel-Add-Intel-Denverton-pin-controller-sup.patch
patches.drivers/0001-pinctrl-check-ops-pin_config_set-in-pinconf_set_conf.patch
patches.drivers/pinctrl-samsung-Fix-NULL-pointer-exception-on-extern
patches.drivers/pinctrl-samsung-Fix-invalid-register-offset-used-for
+ patches.drivers/pinctrl-sunxi-fix-wrong-irq_banks-number-for-H5-pinc
+ patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-FSCLKST-pin-and
patches.drivers/0011-pinctrl-intel-Add-Intel-Cannon-Lake-PCH-H-pin-contro.patch
+ patches.drivers/pinctrl-intel-Read-back-TX-buffer-state
+ patches.drivers/pinctrl-uniphier-fix-members-of-rmii-group-for-Pro4
patches.drivers/gpio-brcmstb-check-return-value-of-gpiochip_irqchip_
patches.suse/cpufreq-intel_pstate-Improve-IO-performance-with-per-core-P-states.patch
patches.drivers/PM-devfreq-Fix-memory-leak-when-fail-to-register-dev
@@ -6414,6 +6441,8 @@
patches.drivers/rdma-core-Add-rdma_rw_mr_payload.patch
patches.drivers/svcrdma-Estimate-Send-Queue-depth-properly.patch
patches.drivers/04-i2c-i801-restore-the-presence-state-of-p2sb-pci-device-after-reading-bar.patch
+ patches.drivers/power-supply-cpcap-charger-add-OMAP_USB2-dependency
+ patches.drivers/power-supply-act8945a_charger-fix-of_irq_get-error-c
patches.drivers/0001-power-supply-Fix-power_supply_am_i_supplied-to-retur.patch
patches.drivers/0013-iommu-rockchip-add-multi-irqs-support.patch
patches.drivers/0014-iommu-rockchip-ignore-isp-mmu-reset-operation.patch
@@ -6443,11 +6472,15 @@
patches.drivers/0013-iommu-amd-check-if-domain-is-null-in-get_domain-and-return-ebusy
patches.arch/21-x86-mm-64-fix-an-incorrect-warning-with-config_debug_vm-y-pcid.patch
patches.drivers/firmware-arm_scpi-fix-endianness-of-dev_id-in-struct
+ patches.drivers/clk-meson-meson8b-fix-protection-against-undefined-c
patches.drivers/0047-pwm-rockchip-Add-APB-and-function-both-clocks-suppor.patch
patches.drivers/0048-pwm-rockchip-Remove-the-judge-from-return-value-of-p.patch
patches.drivers/0049-pwm-rockchip-Use-pwm_apply-instead-of-pwm_enable.patch
patches.drivers/0050-pwm-rockchip-Move-the-configuration-of-polarity.patch
patches.drivers/0051-pwm-rockchip-Use-same-PWM-ops-for-each-IP.patch
+ patches.drivers/pwm-tiehrpwm-Fix-runtime-PM-imbalance-at-unbind
+ patches.drivers/pwm-tiehrpwm-fix-clock-imbalance-in-probe-error-path
+ patches.drivers/libnvdimm-label-fix-index-block-size-calculation.patch
patches.drivers/libnvdimm-btt-check-memory-allocation-failure.patch
patches.drivers/libnvdimm-nfit-export-an-ecc_unit_size-sysfs-attribu.patch
patches.drivers/libnvdimm-btt-fix-a-missed-NVDIMM_IO_ATOMIC-case-in-.patch
@@ -6469,6 +6502,7 @@
patches.fixes/0001-NFSv4.1-don-t-use-machine-credentials-for-CLOSE-when.patch
patches.fixes/0001-NFS-Fix-NFSv2-security-settings.patch
patches.fixes/0001-NFS-flush-data-when-locking-a-file-to-ensure-cache-c.patch
+ patches.drivers/thermal-fix-INTEL_SOC_DTS_IOSF_CORE-dependencies
patches.arch/s390-sles15-01-zcrypt-externalize-test-AP-queue.patch
patches.arch/s390-sles15-02-zcrypt-externalize-AP-config-info-query.patch
patches.arch/s390-sles15-03-zcrypt-externalize-AP-queue-interrupt-control.patch
@@ -6525,9 +6559,24 @@
patches.drivers/block-directly-insert-blk-mq-request-from-blk_insert.patch
patches.drivers/ALSA-seq-Cancel-pending-autoload-work-at-unbinding-d
patches.drivers/rtc-sa1100-fix-unbalanced-clk_prepare_enable-clk_dis.patch
+ patches.drivers/clk-qcom-clk-smd-rpm-Fix-the-reported-rate-of-branch
+ patches.drivers/clk-meson-gxbb-fix-meson-cts_amclk-divider-flags
+ patches.drivers/clk-meson-gxbb-fix-clk_mclk_i958-divider-flags
+ patches.drivers/clk-sunxi-ng-Fix-fractional-mode-for-N-M-clocks
+ patches.drivers/clk-sunxi-ng-multiplier-Fix-fractional-mode
+ patches.drivers/clk-sunxi-ng-Make-fractional-helper-less-chatty
+ patches.drivers/clk-sunxi-ng-Wait-for-lock-when-using-fractional-mod
+ patches.drivers/clk-sunxi-ng-h3-gate-then-ungate-PLL-CPU-clk-after-r
+ patches.drivers/clk-sunxi-ng-allow-set-parent-clock-PLL_CPUX-for-CPU
patches.drivers/0025-clk-fractional-divider-allow-overriding-of-approxima.patch
patches.drivers/0026-clk-rockchip-add-special-approximation-to-fix-up-fra.patch
patches.drivers/0027-clk-rockchip-Mark-rockchip_fractional_approximation-.patch
+ patches.drivers/clk-renesas-div6-Document-fields-used-for-parent-sel
+ patches.drivers/clk-qcom-msm8916-Fix-bimc-gpu-clock-ops
+ patches.drivers/clk-sunxi-fix-uninitialized-access
+ patches.drivers/clk-hi6220-change-watchdog-clock-source
+ patches.drivers/clk-Don-t-write-error-code-into-divider-register
+ patches.drivers/clk-si5351-fix-PLL-reset
patches.arch/22-x86-mm-get-rid-of-vm_bug_on-in-switch_tlb_irqs_off.patch
patches.arch/31-x86-hibernate-64-mask-off-cr3-s-pcid-bits-in-the-saved-cr3.patch
patches.arch/32-x86-mm-64-initialize-cr4-pcide-early.patch
@@ -6884,6 +6933,7 @@
patches.drivers/iio-trigger-stm32-timer-fix-a-corner-case-to-write-p
patches.drivers/iio-adc-mcp320x-Fix-oops-on-module-unload
patches.drivers/iio-adc-mcp320x-Fix-readout-of-negative-voltages
+ patches.drivers/IIO-BME280-Updates-to-Humidity-readings-need-ctrl_re
patches.drivers/iio-ad_sigma_delta-Implement-a-dedicated-reset-funct
patches.drivers/iio-ad7793-Fix-the-serial-interface-reset
patches.drivers/iio-core-Return-error-for-failed-read_reg
@@ -7221,6 +7271,7 @@
patches.drivers/can-flexcan-fix-i.MX6-state-transition-issue
patches.drivers/can-flexcan-fix-i.MX28-state-transition-issue
patches.drivers/can-flexcan-fix-p1010-state-transition-issue
+ patches.drivers/can-bcm-check-for-null-sk-before-deferencing-it-via-
patches.drivers/can-af_can-can_pernet_init-add-missing-error-handlin
patches.drivers/can-esd_usb2-Fix-can_dlc-value-for-received-RTR-fram
patches.drivers/can-gs_usb-fix-busy-loop-if-no-more-TX-context-is-av
@@ -7260,6 +7311,7 @@
patches.fixes/0001-USB-serial-metro-usb-add-MS7820-device-id.patch
patches.fixes/0001-usb-hub-Allow-reset-retry-for-USB2-devices-on-connec.patch
patches.suse/msft-hv-1485-vmbus-hvsock-add-proper-sync-for-vmbus_hvsock_device.patch
+ patches.drivers/iio-pressure-zpa2326-Remove-always-true-check-which-
patches.drivers/staging-iio-ade7759-fix-signed-extension-bug-on-shif
patches.drivers/iio-dummy-events-Add-missing-break.patch
patches.drivers/staging-bcm2835-audio-Fix-memory-corruption
@@ -7455,6 +7507,8 @@
patches.drivers/edac-skx_edac-handle-systems-with-segmented-pci-busses.patch
patches.drivers/edac-sb_edac-fix-missing-dimm-sysfs-entries-with-knl-snc2-snc4-mode.patch
patches.drivers/hwmon-pmbus-core-Prevent-unintentional-setting-of-pa.patch
+ patches.drivers/regulator-qcom_spmi-Include-offset-when-translating-
+ patches.drivers/regulator-tps65218-Fix-strobe-assignment
patches.drivers/spi-sh-msiof-Fix-DMA-transfer-size-check
patches.drivers/spi-spi-axi-fix-potential-use-after-free-after-dereg
patches.drivers/mmc-sdhci-pci-remove-outdated-declaration
@@ -7653,6 +7707,7 @@
patches.fixes/0001-usb-xhci-Return-error-when-host-is-dead-in-xhci_disa.patch
patches.fixes/0001-usb-mtu3-fix-error-return-code-in-ssusb_gadget_init.patch
patches.fixes/0001-usb-phy-tahvo-fix-error-handling-in-tahvo_usb_probe.patch
+ patches.fixes/0001-usb-dwc2-Improve-gadget-state-disconnection-handling.patch
patches.drivers/0045-phy-rockchip-typec-Avoid-magic-numbers-add-delays-in.patch
patches.drivers/0046-phy-rockchip-typec-Do-the-calibration-more-correctly.patch
patches.fixes/0001-USB-serial-garmin_gps-fix-I-O-after-failed-probe-and.patch
@@ -9451,6 +9506,10 @@
patches.fixes/0001-NFS-Revert-NFS-Move-the-flock-open-mode-check-into-n.patch
patches.arch/s390-sles15-02-01-s390-disassembler-increase-show_code-buffer-size.patch
patches.drivers/thermal-enable-broadcom-menu-for-arm64-bcm2835.patch
+ patches.drivers/thermal-drivers-hisi-Fix-missing-interrupt-enablemen
+ patches.drivers/thermal-drivers-hisi-Fix-kernel-panic-on-alarm-inter
+ patches.drivers/thermal-drivers-hisi-Simplify-the-temperature-step-c
+ patches.drivers/thermal-drivers-hisi-Fix-multiple-alarm-interrupts-f
patches.drivers/thermal-drivers-step_wise-Fix-temperature-regulation
patches.drivers/PM-runtime-Drop-children-check-from-__pm_runtime_set
patches.drivers/dynamic-debug-howto-fix-optional-omitted-ending-line
@@ -9466,8 +9525,26 @@
patches.fixes/kernel-signal.c-protect-the-traced-SIGNAL_UNKILLABLE-tasks-from-SIGKILL.patch
patches.fixes/kernel-signal.c-protect-the-SIGNAL_UNKILLABLE-tasks-from-sig_kernel_only-signals.patch
patches.fixes/kernel-signal.c-remove-the-no-longer-needed-SIGNAL_UNKILLABLE-check-in-complete_signal.patch
+ patches.drivers/clk-samsung-Fix-m2m-scaler-clock-on-Exynos542x
+ patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_UNGATE-to-all-H3-PLLs
+ patches.drivers/clk-sunxi-ng-add-CLK_SET_RATE_PARENT-flag-to-H3-GPU-
+ patches.drivers/clk-sunxi-ng-sun6i-Export-video-PLLs
+ patches.drivers/clk-sunxi-ng-sun6i-Rename-HDMI-DDC-clock-to-avoid-na
+ patches.drivers/clk-sunxi-ng-sun5i-Fix-bit-offset-of-audio-PLL-post-
+ patches.drivers/clk-sunxi-ng-nm-Check-if-requested-rate-is-supported
patches.drivers/0028-clk-rockchip-Remove-superfluous-error-message-in-roc.patch
+ patches.drivers/clk-tegra-Fix-cclk_lp-divisor-register
+ patches.drivers/clk-tegra-Use-readl_relaxed_poll_timeout_atomic-in-t
+ patches.drivers/clk-hi6220-mark-clock-cs_atb_syspll-as-critical
+ patches.drivers/clk-hi3660-fix-incorrect-uart3-clock-freqency
+ patches.drivers/clk-sunxi-fix-build-warning
+ patches.drivers/clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work
patches.arch/clk-imx-imx7d-Fix-parent-clock-for-OCRAM_CLK.patch
+ patches.drivers/clk-mediatek-mark-mtk_infrasys_init_early-__init
+ patches.drivers/clk-mediatek-add-the-option-for-determining-PLL-sour
+ patches.drivers/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5
+ patches.drivers/clk-qcom-common-fix-legacy-board-clock-registration
+ patches.drivers/clk-ti-dra7-atl-clock-fix-child-node-lookups
patches.fixes/sctp-check-stream-reset-info-len-before-making-recon.patch
patches.drivers/qed-use-kzalloc-instead-of-kmalloc-and-memset.patch
patches.suse/msft-hv-1517-hv_netvsc-preserve-hw_features-on-mtu-channels-ringp.patch
@@ -9852,6 +9929,7 @@
patches.suse/0084-md-limit-mdstat-resync-progress-to-max_sectors.patch
patches.suse/0085-md-raid1-10-add-missed-blk-plug.patch
patches.drivers/drm-safely-free-connectors-from-connector_iter
+ patches.drivers/drm-exynos-Fix-dma-buf-import
patches.drivers/drm-exynos-gem-Drop-NONCONTIG-flag-for-buffers-alloc
patches.drivers/drm-i915-Skip-switch-to-kernel-context-on-suspend-wh
patches.drivers/drm-i915-Fix-vblank-timestamp-frame-counter-jumps-on
@@ -11446,6 +11524,7 @@
patches.fixes/0001-USB-usbip-remove-useless-call-in-usbip_recv.patch
patches.fixes/0001-USB-serial-io_edgeport-fix-possible-sleep-in-atomic.patch
patches.fixes/0001-usb-uas-unconditionally-bring-back-host-after-reset.patch
+ patches.fixes/0001-usb-option-Add-support-for-FS040U-modem.patch
patches.fixes/0001-CDC-ACM-apply-quirk-for-card-reader.patch
patches.fixes/0001-USB-serial-simple-add-Motorola-Tetra-driver.patch
patches.fixes/0001-usbip-prevent-bind-loops-on-devices-attached-to-vhci.patch
@@ -11493,7 +11572,13 @@
patches.fixes/printk-Add-console-owner-and-waiter-logic-to-load-ba.patch
patches.fixes/printk-Hide-console-waiter-logic-into-helpers.patch
patches.fixes/printk-Never-set-console_may_schedule-in-console_try.patch
+ patches.drivers/clk-qcom-msm8916-fix-mnd_width-for-codec_digcodec
+ patches.drivers/clk-fix-set_rate_range-when-current-rate-is-out-of-r
patches.arch/clk-Don-t-touch-hardware-when-reparenting-during-reg.patch
+ patches.drivers/clk-axi-clkgen-Correctly-handle-nocount-bit-in-recal
+ patches.drivers/clk-si5351-Rename-internal-plls-to-avoid-name-collis
+ patches.drivers/clk-meson-gxbb-fix-wrong-clock-for-SARADC-SANA
+ patches.drivers/clk-meson-mpll-use-64-bit-maths-in-params_from_rate
patches.drivers/0001-drm-rockchip-analogix_dp-Remove-unnecessary-init-cod.patch
patches.drivers/0001-drm-rockchip-Fix-build-warning-in-analogix_dp-rockch.patch
patches.drivers/drm-edid-set-ELD-connector-type-in-drm_edid_to_eld
@@ -11993,9 +12078,12 @@
patches.arch/powerpc-pseries-Fix-cpu-hotplug-crash-with-memoryles.patch
patches.drivers/rtc-opal-Fix-handling-of-firmware-error-codes-preven
patches.drivers/pinctrl-pxa-pxa2xx-add-missing-MODULE_DESCRIPTION-AU
+ patches.fixes/0001-pinctrl-intel-Initialize-GPIO-properly-when-used-thr.patch
patches.drivers/pinctrl-Really-force-states-during-suspend-resume
patches.drivers/pinctrl-rockchip-enable-clock-when-reading-pin-direc
patches.drivers/pinctrl-sh-pfc-r8a7795-es1-Fix-MOD_SEL1-bit-25-24-to
+ patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-to-delete-A20.A25-pins-fu
+ patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-to-delete-A20.A25-pins-fu
patches.drivers/pinctrl-baytrail-Enable-glitch-filter-for-GPIOs-used
patches.drivers/pinctrl-sx150x-Unregister-the-pinctrl-on-release
patches.drivers/pinctrl-sx150x-Register-pinctrl-before-adding-the-gp
@@ -12492,6 +12580,7 @@
patches.fixes/0001-usbip-keep-usbip_device-sockfd-state-in-sync-with-tc.patch
patches.fixes/0001-usb-host-ehci-use-correct-device-pointer-for-dma-ops.patch
patches.fixes/0001-usb-ohci-Proper-handling-of-ed_rm_list-to-handle-rac.patch
+ patches.fixes/0001-usb-cdc_acm-prevent-race-at-write-to-acm-while-syste.patch
patches.fixes/0001-Revert-usb-musb-host-don-t-start-next-rx-urb-if-curr.patch
patches.drivers/crypto-s5p-sss-Fix-kernel-Oops-in-AES-ECB-mode
patches.drivers/drm-exynos-g2d-use-monotonic-timestamps
@@ -12667,6 +12756,7 @@
patches.fixes/l2tp-fix-tunnel-lookup-use-after-free-race.patch
patches.drivers/ixgbe-fix-crash-in-build_skb-Rx-code-path.patch
patches.suse/hdlc_ppp-carrier-detect-ok-don-t-turn-off-negotiatio.patch
+ patches.drivers/r8152-fix-tx-packets-accounting
patches.drivers/Bluetooth-btusb-Use-DMI-matching-for-QCA-reset_resum
patches.suse/net-ipv4-don-t-allow-setting-net.ipv4.route.min_pmtu.patch
patches.fixes/ip_gre-fix-IFLA_MTU-ignored-on-NEWLINK.patch
@@ -12790,6 +12880,7 @@
patches.fixes/0001-usb-usbmon-Read-text-within-supplied-buffer-size.patch
patches.fixes/0001-xhci-Fix-front-USB-ports-on-ASUS-PRIME-B350M-A.patch
patches.fixes/0001-usbip-vudc-fix-null-pointer-dereference-on-udc-lock.patch
+ patches.fixes/0001-USB-OHCI-Fix-NULL-dereference-in-HCDs-using-HCD_LOCA.patch
patches.fixes/fs-aio-Add-explicit-RCU-grace-period-when-freeing-ki.patch
patches.fixes/fs-aio-Use-RCU-accessors-for-kioctx_table-table.patch
patches.drivers/RDMAVT-Fix-synchronization-around-percpu_ref.patch
@@ -12845,6 +12936,7 @@
patches.drivers/RDMA-ucma-Fix-use-after-free-access-in-ucma_close.patch
patches.drivers/RDMA-ucma-Ensure-that-CM_ID-exists-prior-to-access-i.patch
patches.arch/clk-migrate-the-count-of-orphaned-clocks-at-init.patch
+ patches.drivers/clk-sunxi-ng-a31-Fix-CLK_OUT_-clock-ops
patches.arch/clk-bcm2835-Fix-ana-maskX-definitions.patch
patches.arch/clk-bcm2835-Protect-sections-updating-shared-registe.patch
patches.drivers/0001-mmc-dw_mmc-Fix-the-DTO-CTO-timeout-overflow-calculat.patch
@@ -13108,6 +13200,7 @@
patches.drivers/0001-drm-mali-dp-Uninitialized-variable-in-malidp_se_chec.patch
patches.drivers/drm-vmwgfx-Unpin-the-screen-object-backup-buffer-whe
patches.drivers/drm-i915-Wrap-engine-schedule-in-RCU-locks-for-set-w
+ patches.drivers/drm-i915-Only-call-tasklet_kill-on-the-first-prepare
patches.drivers/drm-amdgpu-Add-an-ATPX-quirk-for-hybrid-laptop
patches.drivers/drm-i915-execlists-Use-a-locked-clear_bit-for-synchr
patches.drivers/drm-i915-Fix-hibernation-with-ACPI-S0-target-state
@@ -13136,8 +13229,13 @@
patches.fixes/regulator-gpio-fix-some-error-handling-paths-in-gpio_regulator_probe.patch
patches.drivers/spi-Fix-scatterlist-elements-size-in-spi_map_buf
patches.drivers/spi-atmel-init-FIFOs-before-spi-enable
+ patches.drivers/power-gemini-poweroff-Avoid-spurious-poweroff
patches.drivers/pinctrl-artpec6-dt-add-missing-pin-group-uart5nocts
+ patches.drivers/pinctrl-sh-pfc-r8a7795-Fix-MOD_SEL-register-pin-assi
patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-MOD_SEL-register-pin-assi
+ patches.drivers/pinctrl-sh-pfc-r8a7796-Fix-IPSR-and-MOD_SEL-register
+ patches.drivers/pinctrl-sh-pfc-r8a7790-Add-missing-TX_ER-pin-to-avb_
+ patches.drivers/pinctrl-pinctrl-single-Fix-pcs_request_gpio-when-bit
patches.drivers/0001-ipmi_ssif-Fix-kernel-panic-at-msg_done_handler.patch
patches.fixes/doc-Rename-.system_keyring-to-.builtin_trusted_keys
patches.drivers/i40e-fix-typo-in-function-description.patch
@@ -13672,6 +13770,7 @@
patches.drivers/ima-Fallback-to-the-builtin-hash-algorithm
patches.arch/s390-crypto-fix-kernel-crash-on-aes_s390-module-remove.patch
patches.drivers/s390-qdio-don-t-merge-error-output-buffers.patch
+ patches.drivers/s390-qdio-don-t-retry-eqbs-after-ccq-96.patch
patches.drivers/s390-cio-rename-struct-channel_path_desc.patch
patches.drivers/s390-chsc-query-utility-strings-via-fmt3-channel-path-descriptor.patch
patches.drivers/s390-cio-add-util_string-sysfs-attribute.patch
@@ -13807,7 +13906,25 @@
patches.apparmor/apparmor-fix-logging-of-the-existence-test-for-signa.patch
patches.apparmor/apparmor-fix-memory-leak-on-buffer-on-error-exit-path.patch
patches.drivers/watchdog-f71808e_wdt-Fix-WD_EN-register-read
+ patches.drivers/pwm-stm32-Remove-unused-struct-device
patches.drivers/pwm-rcar-Fix-a-condition-to-prevent-mismatch-value-s
+ patches.drivers/clk-fix-mux-clock-documentation
+ patches.drivers/clk-meson-remove-unnecessary-rounding-in-the-pll-clo
+ patches.drivers/clk-tegra-Fix-pll_u-rate-configuration
+ patches.drivers/clk-samsung-exynos3250-Fix-PLL-rates
+ patches.drivers/clk-samsung-exynos5250-Fix-PLL-rates
+ patches.drivers/clk-samsung-exynos5260-Fix-PLL-rates
+ patches.drivers/clk-samsung-exynos5433-Fix-PLL-rates
+ patches.drivers/clk-samsung-exynos7-Fix-PLL-rates
+ patches.drivers/clk-samsung-s3c2410-Fix-PLL-rates
+ patches.drivers/clk-samsung-exynos5250-Add-missing-clocks-for-FIMC-L
+ patches.drivers/clk-Don-t-show-the-incorrect-clock-phase
+ patches.drivers/clk-hisilicon-mark-wdt_mux_p-as-const
+ patches.drivers/clk-hisilicon-fix-potential-NULL-dereference-in-hisi
+ patches.drivers/clk-fix-false-positive-Wmaybe-uninitialized-warning
+ patches.drivers/clk-rockchip-Prevent-calculating-mmc-phase-if-clock-
+ patches.drivers/clk-rockchip-Fix-wrong-parent-for-SDMMC-phase-clock-
+ patches.drivers/clk-bcm2835-De-assert-assert-PLL-reset-signal-when-a
patches.drivers/firmware-dmi_scan-Fix-UUID-length-safety-check
patches.drivers/thermal-imx-Fix-race-condition-in-imx_thermal_probe
patches.fixes/ovl-fix-lookup-with-middle-layer-opaque-dir-and-abso.patch
@@ -13882,6 +13999,7 @@
patches.drivers/drm-i915-bios-filter-out-invalid-DDC-pins-from-VBT-c
patches.drivers/drm-i915-Call-i915_perf_fini-on-init_hw-error-unwind
patches.drivers/drm-i915-audio-Fix-audio-detection-issue-on-GLK
+ patches.drivers/s390-qeth-fix-error-handling-in-adapter-command-callbacks.patch
patches.arch/s390-qeth-fix-MAC-address-update-sequence.patch
patches.suse/llc-delete-timers-synchronously-in-llc_sk_free.patch
patches.suse/net-ethernet-ti-cpsw-fix-tx-vlan-priority-mapping.patch
@@ -13962,6 +14080,7 @@
patches.fixes/0001-xhci-Fix-USB-ports-for-Dell-Inspiron-5775.patch
patches.fixes/0001-usbip-usbip_host-fix-to-hold-parent-lock-for-device_.patch
patches.fixes/0001-usb-core-Add-quirk-for-HP-v222w-16GB-Mini.patch
+ patches.fixes/0001-Revert-xhci-plat-Register-shutdown-for-xhci_plat.patch
patches.fixes/0001-usb-typec-ucsi-Increase-command-completion-timeout-v.patch
patches.drivers/0001-xhci-Fix-Kernel-oops-in-xhci-dbgtty.patch
patches.drivers/tty-n_gsm-Fix-long-delays-with-control-frame-timeout
@@ -14050,6 +14169,7 @@
patches.drivers/drm-i915-glk-Add-MODULE_FIRMWARE-for-Geminilake
patches.drivers/drm-bridge-vga-dac-Fix-edid-memory-leak
patches.drivers/drm-vmwgfx-Fix-a-buffer-object-leak
+ patches.drivers/clk-honor-CLK_MUX_ROUND_CLOSEST-in-generic-clk-mux
patches.fixes/0001-xhci-Fix-use-after-free-in-xhci_free_virt_device.patch
patches.fixes/0001-USB-Accept-bulk-endpoints-with-1024-byte-maxpacket.patch
patches.drivers/platform-x86-asus-wireless-Fix-NULL-pointer-derefere
@@ -14164,6 +14284,7 @@
patches.drivers/cxgb4-fix-offset-in-collecting-TX-rate-limit-info.patch
patches.fixes/0001-iov_iter-fix-return-type-of-_pipe_get_pages.patch
patches.fixes/0002-iov_iter-fix-memory-leak-in-pipe_get_pages_alloc.patch
+ patches.drivers/scsi-zfcp-fix-infinite-iteration-on-erp-ready-list.patch
patches.drivers/scsi-sg-allocate-with-_gfp_zero-in-sg_build_indirect.patch
patches.drivers/libata-Blacklist-some-Sandisk-SSDs-for-NCQ
patches.drivers/libata-blacklist-Micron-500IT-SSD-with-MU01-firmware
@@ -14307,6 +14428,7 @@
patches.drivers/libata-zpodd-small-read-overflow-in-eject_tray
patches.drivers/libata-Drop-SanDisk-SD7UB3Q-G1001-NOLPM-quirk
patches.drivers/drm-i915-Restore-planes-after-load-detection
+ patches.drivers/drm-i915-dp-Send-DPCD-ON-for-MST-before-phy_up
patches.drivers/drm-i915-psr-Chase-psr.enabled-only-under-the-psr.lo
patches.drivers/drm-exynos-Allow-DRM_EXYNOS-on-s5pv210
patches.drivers/drm-i915-Don-t-request-a-bug-report-for-unsafe-modul
@@ -14599,6 +14721,8 @@
patches.drivers/IB-hfi1-Ensure-VL-index-is-within-bounds.patch
patches.drivers/IB-hfi1-Add-bypass-register-defines-and-replace-blin.patch
patches.drivers/mailbox-bcm2835-Fix-of_xlate-return-value
+ patches.drivers/pinctrl-mvebu-use-correct-MPP-sel-value-for-dev-pins
+ patches.drivers/pinctrl-nand-meson-gxbb-fix-missing-data-pins
patches.drivers/auxdisplay-fix-broken-menu
patches.drivers/of-unittest-for-strings-account-for-trailing-0-in-pr
patches.drivers/of-overlay-validate-offset-from-property-fixups
@@ -14607,6 +14731,7 @@
patches.fixes/fs-binfmt_misc-c-do-not-allow-offset-overflow.patch
patches.suse/0001-mtd-cmdlinepart-Update-comment-for-introduction-of-O.patch
patches.fixes/regulator-don-t-return-or-expect-errno-from-of_map_mode.patch
+ patches.drivers/regulator-max8998-Fix-platform-data-retrieval
patches.drivers/block-always-set-partition-number-to-0-in-blk_partit.patch
patches.drivers/nvmet-return-all-zeroed-buffer-when-we-can-t-find-an.patch
patches.drivers/nvme-don-t-hold-nvmf_transports_rwsem-for-more-than-.patch
@@ -14620,6 +14745,10 @@
patches.drivers/iio-tsl2583-correct-values-in-integration_time_avail
patches.drivers/0001-raid10-check-bio-in-r10buf_pool_free-to-void-NULL-po.patch
patches.drivers/0001-md-fix-two-problems-with-setting-the-re-add-device-s.patch
+ patches.drivers/clk-qcom-Base-rcg-parent-rate-off-plan-frequency
+ patches.drivers/clk-imx7d-fix-mipi-dphy-div-parent
+ patches.drivers/clk-mvebu-use-correct-bit-for-98DX3236-NAND
+ patches.drivers/clk-at91-PLL-recalc_rate-now-using-cached-MUL-and-DI
patches.drivers/scsi-lpfc-fix-multiple-prli-completion-error-path.patch
patches.drivers/scsi-lpfc-correct-target-queue-depth-application-changes.patch
patches.drivers/scsi-lpfc-add-per-io-channel-nvme-io-statistics.patch
@@ -14645,6 +14774,13 @@
patches.drivers/scsi-lpfc-comment-cleanup-regarding-broadcom-copyright-header.patch
patches.drivers/scsi-lpfc-fix-spelling-mistakes-mabilbox-and-maibox.patch
patches.drivers/scsi-ipr-new-IOASC-update.patch
+ patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-result-of-eh_host_reset_handler.patch
+ patches.drivers/scsi-zfcp-fix-missing-scsi-trace-for-retry-of-abort-scsi_eh-tmf.patch
+ patches.drivers/scsi-zfcp-fix-misleading-rec-trigger-trace-where-erp_action-setup-failed.patch
+ patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-early-return.patch
+ patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-terminate_rport_io-for-erp_failed.patch
+ patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-for-all-objects-in-erp_failed.patch
+ patches.drivers/scsi-zfcp-fix-missing-rec-trigger-trace-on-enqueue-without-erp-thread.patch
patches.drivers/scsi-lpfc-fix-mds-diagnostics-failure-rx-tx.patch
patches.drivers/scsi-lpfc-correct-oversubscription-of-nvme-io-requests-for-an-adapter.patch
patches.drivers/scsi-lpfc-fix-crash-in-blk_mq-layer-when-executing-modprobe-r-lpfc.patch
@@ -14671,6 +14807,7 @@
patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-lookup
patches.drivers/backlight-max8925_bl-Fix-Device-Tree-node-lookup
patches.drivers/backlight-tps65217_bl-Fix-Device-Tree-node-lookup
+ patches.drivers/backlight-as3711_bl-Fix-Device-Tree-node-leaks
patches.fixes/watchdog-da9063-Fix-setting-changing-timeout.patch
patches.fixes/watchdog-da9063-Fix-updating-timeout-value.patch
patches.fixes/watchdog-da9063-Fix-timeout-handling-during-probe.patch
@@ -14685,8 +14822,10 @@
patches.suse/cpufreq-intel_pstate-enable-boost-for-Skylake-Xeon.patch
patches.fixes/cpufreq-governors-Fix-long-idle-detection-logic-in-l.patch
patches.drivers/i2c-axxia-enable-clock-before-calling-clk_get_rate
+ patches.drivers/pwm-meson-Fix-allocation-of-PWM-channel-array
patches.drivers/pwm-lpss-platform-Save-restore-the-ctrl-register-ove
patches.drivers/ACPI-LPSS-Add-missing-prv_offset-setting-for-byt-cht
+ patches.drivers/pwm-stm32-Enforce-dependency-on-CONFIG_MFD_STM32_TIM
patches.suse/0001-lib-string_helpers-Add-missed-declaration-of-struct-.patch
patches.drivers/platform-x86-ideapad-laptop-Add-MIIX-720-12IKB-to-no
patches.drivers/0001-qla2xxx-Mask-off-Scope-bits-in-retry-delay.patch
@@ -14781,6 +14920,7 @@
patches.drivers/vt-prevent-leaking-uninitialized-data-to-userspace-v
patches.drivers/iio-pressure-bmp280-fix-relative-humidity-unit
patches.drivers/iio-buffer-fix-the-function-signature-to-match-imple
+ patches.drivers/r8152-napi-hangup-fix-after-disconnect
patches.drivers/net-smc-rebuild-nonblocking-connect.patch
patches.drivers/nl80211-relax-ht-operation-checks-for-mesh
patches.fixes/Fix-up-non-directory-creation-in-SGID-directories.patch
@@ -14807,6 +14947,9 @@
patches.drivers/ALSA-hda-realtek-two-more-lenovo-models-need-fixup-o
patches.drivers/RDMA-mlx5-Fix-memory-leak-in-mlx5_ib_create_srq-erro.patch
patches.drivers/i2c-tegra-Fix-NACK-error-handling
+ patches.drivers/drm-i915-Fix-hotplug-irq-ack-on-i965-g4x
+ patches.fixes/0001-pinctrl-nsp-off-by-ones-in-nsp_pinmux_enable.patch
+ patches.drivers/pinctrl-nsp-Fix-potential-NULL-dereference
patches.drivers/rtlwifi-Fix-kernel-Oops-Fw-download-fail
patches.drivers/rtlwifi-rtl8821ae-fix-firmware-is-not-ready-to-run
patches.drivers/qed-Fix-reading-stale-configuration-information.patch
@@ -14817,6 +14960,17 @@
patches.drivers/ALSA-hda-realtek-Add-Panasonic-CF-SZ6-headset-jack-q
patches.drivers/ALSA-rawmidi-Change-resized-buffers-atomically
patches.drivers/drm-nouveau-gem-off-by-one-bugs-in-nouveau_gem_pushb
+ patches.drivers/drm-nouveau-Use-drm_connector_list_iter_-for-iterati
+ patches.drivers/drm-nouveau-Avoid-looping-through-fake-MST-connector
+ patches.drivers/media-staging-omap4iss-Include-asm-cacheflush.h-afte
+ patches.drivers/atl1c-reserve-min-skb-headroom
+ patches.drivers/can-mpc5xxx_can-check-of_iomap-return-before-use
+ patches.drivers/can-xilinx_can-fix-device-dropping-off-bus-on-RX-ove
+ patches.drivers/can-xilinx_can-fix-RX-loop-if-RXNEMP-is-asserted-wit
+ patches.drivers/can-xilinx_can-fix-recovery-from-error-states-not-be
+ patches.drivers/can-xilinx_can-keep-only-1-2-frames-in-TX-FIFO-to-fi
+ patches.drivers/can-xilinx_can-fix-RX-overflow-interrupt-not-being-e
+ patches.drivers/can-xilinx_can-fix-incorrect-clear-of-non-processed-
# davem/net-next
patches.drivers/net-smc-determine-port-attributes-independent-from-pnet-table.patch