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authorPetr Tesarik <ptesarik@suse.cz>2019-02-14 12:56:01 +0100
committerPetr Tesarik <ptesarik@suse.cz>2019-02-14 12:56:01 +0100
commit31bad3127fe785349f75e469140160b7b0ab2db8 (patch)
treee6d22b3148dc255bc50d1c26d80156e0ebd5a1ce
parent7c0773c11ff6461f7b6b590727ba2c13914e7a1e (diff)
parenta59c6c7c0ae9d349d21f6371cd7411caf841b2dd (diff)
Merge branch 'users/tbogendoerfer/SLE15-SP1/for-next' into SLE15-SP1
Pull RDMA fixes from Thomas Bogendoerfer
-rw-r--r--patches.drivers/RDMA-bnxt_en-Enable-RDMA-driver-support-for-57500-ch.patch31
-rw-r--r--patches.drivers/RDMA-bnxt_re-Add-64bit-doorbells-for-57500-series.patch887
-rw-r--r--patches.drivers/RDMA-bnxt_re-Add-chip-context-to-identify-57500-seri.patch169
-rw-r--r--patches.drivers/RDMA-bnxt_re-Add-extended-psn-structure-for-57500-ad.patch233
-rw-r--r--patches.drivers/RDMA-bnxt_re-Enable-GSI-QP-support-for-57500-series.patch358
-rw-r--r--patches.drivers/RDMA-bnxt_re-Increase-depth-of-control-path-command-.patch229
-rw-r--r--patches.drivers/RDMA-bnxt_re-Query-HWRM-Interface-version-from-FW.patch75
-rw-r--r--patches.drivers/RDMA-bnxt_re-Skip-backing-store-allocation-for-57500.patch99
-rw-r--r--patches.drivers/RDMA-bnxt_re-Update-kernel-user-abi-to-pass-chip-con.patch98
-rw-r--r--patches.drivers/RDMA-bnxt_re-fix-a-size-calculation.patch43
-rw-r--r--patches.drivers/RDMA-bnxt_re-fix-or-ing-of-data-into-an-uninitialize.patch33
-rw-r--r--patches.drivers/infiniband-bnxt_re-qplib-Check-the-return-value-of-s.patch32
-rw-r--r--series.conf14
13 files changed, 2301 insertions, 0 deletions
diff --git a/patches.drivers/RDMA-bnxt_en-Enable-RDMA-driver-support-for-57500-ch.patch b/patches.drivers/RDMA-bnxt_en-Enable-RDMA-driver-support-for-57500-ch.patch
new file mode 100644
index 0000000000..ff9b1b22b6
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_en-Enable-RDMA-driver-support-for-57500-ch.patch
@@ -0,0 +1,31 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:28 -0500
+Subject: RDMA/bnxt_en: Enable RDMA driver support for 57500 chip
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: ecb53febfcad565366762b7413b03452874643db
+References: bsc#1125239
+
+Re-enabling RDMA driver support on 57500 chips. Removing the forced error
+code for 57500 chip.
+
+Signed-off-by: Michael Chan <michael.chan@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
++++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
+@@ -43,9 +43,6 @@ static int bnxt_register_dev(struct bnxt
+ if (ulp_id == BNXT_ROCE_ULP) {
+ unsigned int max_stat_ctxs;
+
+- if (bp->flags & BNXT_FLAG_CHIP_P5)
+- return -EOPNOTSUPP;
+-
+ max_stat_ctxs = bnxt_get_max_func_stat_ctxs(bp);
+ if (max_stat_ctxs <= BNXT_MIN_ROCE_STAT_CTXS ||
+ bp->cp_nr_rings == max_stat_ctxs)
diff --git a/patches.drivers/RDMA-bnxt_re-Add-64bit-doorbells-for-57500-series.patch b/patches.drivers/RDMA-bnxt_re-Add-64bit-doorbells-for-57500-series.patch
new file mode 100644
index 0000000000..ba1df3da1c
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Add-64bit-doorbells-for-57500-series.patch
@@ -0,0 +1,887 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:23 -0500
+Subject: RDMA/bnxt_re: Add 64bit doorbells for 57500 series
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: b353ce556d521351eb7daf609e446f3595a6fad6
+References: bsc#1125239
+
+The new chip series has 64 bit doorbell for notification queues. Thus,
+both control and data path event queues need new routines to write 64 bit
+doorbell. Adding the same. There is new doorbell interface between the
+chip and driver. Changing the chip specific data structure definitions.
+
+Additional significant changes are listed below
+- bnxt_re_net_ring_free/alloc takes a new argument
+- bnxt_qplib_enable_nq and enable_rcfw uses new doorbell offset
+ for new chip.
+- DB mapping for NQ and CREQ now maps 8 bytes.
+- DBR_DBR_* macros renames to DBC_DBC_*
+- store nq_db_offset in a 32bit data type.
+- got rid of __iowrite64_copy, used writeq instead.
+- changed the DB header initialization to simpler scheme.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/Kconfig | 1
+ drivers/infiniband/hw/bnxt_re/ib_verbs.c | 4 -
+ drivers/infiniband/hw/bnxt_re/main.c | 85 +++++++++++++---------
+ drivers/infiniband/hw/bnxt_re/qplib_fp.c | 112 ++++++++++++++---------------
+ drivers/infiniband/hw/bnxt_re/qplib_fp.h | 43 +++++++++--
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 31 +++++---
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.h | 44 ++++++++++-
+ drivers/infiniband/hw/bnxt_re/qplib_res.h | 13 +++
+ drivers/infiniband/hw/bnxt_re/roce_hsi.h | 96 +++++++++++++-----------
+ 9 files changed, 276 insertions(+), 153 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/Kconfig
++++ b/drivers/infiniband/hw/bnxt_re/Kconfig
+@@ -1,5 +1,6 @@
+ config INFINIBAND_BNXT_RE
+ tristate "Broadcom Netxtreme HCA support"
++ depends on 64BIT
+ depends on ETHERNET && NETDEVICES && PCI && INET && DCB
+ depends on MAY_USE_DEVLINK
+ select NET_VENDOR_BROADCOM
+--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
++++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+@@ -3298,10 +3298,10 @@ int bnxt_re_req_notify_cq(struct ib_cq *
+ spin_lock_irqsave(&cq->cq_lock, flags);
+ /* Trigger on the very next completion */
+ if (ib_cqn_flags & IB_CQ_NEXT_COMP)
+- type = DBR_DBR_TYPE_CQ_ARMALL;
++ type = DBC_DBC_TYPE_CQ_ARMALL;
+ /* Trigger on the next solicited completion */
+ else if (ib_cqn_flags & IB_CQ_SOLICITED)
+- type = DBR_DBR_TYPE_CQ_ARMSE;
++ type = DBC_DBC_TYPE_CQ_ARMSE;
+
+ /* Poll to see if there are missed events */
+ if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
+--- a/drivers/infiniband/hw/bnxt_re/main.c
++++ b/drivers/infiniband/hw/bnxt_re/main.c
+@@ -369,7 +369,8 @@ static void bnxt_re_fill_fw_msg(struct b
+ fw_msg->timeout = timeout;
+ }
+
+-static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, u16 fw_ring_id)
++static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
++ u16 fw_ring_id, int type)
+ {
+ struct bnxt_en_dev *en_dev = rdev->en_dev;
+ struct hwrm_ring_free_input req = {0};
+@@ -383,7 +384,7 @@ static int bnxt_re_net_ring_free(struct
+ memset(&fw_msg, 0, sizeof(fw_msg));
+
+ bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_RING_FREE, -1, -1);
+- req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
++ req.ring_type = type;
+ req.ring_id = cpu_to_le16(fw_ring_id);
+ bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
+ sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
+@@ -420,7 +421,7 @@ static int bnxt_re_net_ring_alloc(struct
+ /* Association of ring index with doorbell index and MSIX number */
+ req.logical_id = cpu_to_le16(map_index);
+ req.length = cpu_to_le32(ring_mask + 1);
+- req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
++ req.ring_type = type;
+ req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
+ bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
+ sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
+@@ -888,6 +889,12 @@ static int bnxt_re_cqn_handler(struct bn
+ return 0;
+ }
+
++static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)
++{
++ return bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ?
++ 0x10000 : rdev->msix_entries[indx].db_offset;
++}
++
+ static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
+ {
+ int i;
+@@ -901,18 +908,18 @@ static void bnxt_re_cleanup_res(struct b
+
+ static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
+ {
+- int rc = 0, i;
+ int num_vec_enabled = 0;
++ int rc = 0, i;
++ u32 db_offt;
+
+ bnxt_qplib_init_res(&rdev->qplib_res);
+
+ for (i = 1; i < rdev->num_msix ; i++) {
++ db_offt = bnxt_re_get_nqdb_offset(rdev, i);
+ rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
+ i - 1, rdev->msix_entries[i].vector,
+- rdev->msix_entries[i].db_offset,
+- &bnxt_re_cqn_handler,
++ db_offt, &bnxt_re_cqn_handler,
+ &bnxt_re_srqn_handler);
+-
+ if (rc) {
+ dev_err(rdev_to_dev(rdev),
+ "Failed to enable NQ with rc = 0x%x", rc);
+@@ -924,17 +931,18 @@ static int bnxt_re_init_res(struct bnxt_
+ fail:
+ for (i = num_vec_enabled; i >= 0; i--)
+ bnxt_qplib_disable_nq(&rdev->nq[i]);
+-
+ return rc;
+ }
+
+ static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
+ {
++ u8 type;
+ int i;
+
+ for (i = 0; i < rdev->num_msix - 1; i++) {
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
+ rdev->nq[i].res = NULL;
+- bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id);
+ bnxt_qplib_free_nq(&rdev->nq[i]);
+ }
+ }
+@@ -956,8 +964,11 @@ static void bnxt_re_free_res(struct bnxt
+
+ static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
+ {
+- int rc = 0, i;
+ int num_vec_created = 0;
++ dma_addr_t *pg_map;
++ int rc = 0, i;
++ int pages;
++ u8 type;
+
+ /* Configure and allocate resources for qplib */
+ rdev->qplib_res.rcfw = &rdev->rcfw;
+@@ -987,13 +998,13 @@ static int bnxt_re_alloc_res(struct bnxt
+ i, rc);
+ goto free_nq;
+ }
+- rc = bnxt_re_net_ring_alloc
+- (rdev, rdev->nq[i].hwq.pbl[PBL_LVL_0].pg_map_arr,
+- rdev->nq[i].hwq.pbl[rdev->nq[i].hwq.level].pg_count,
+- HWRM_RING_ALLOC_CMPL,
+- BNXT_QPLIB_NQE_MAX_CNT - 1,
+- rdev->msix_entries[i + 1].ring_idx,
+- &rdev->nq[i].ring_id);
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ pg_map = rdev->nq[i].hwq.pbl[PBL_LVL_0].pg_map_arr;
++ pages = rdev->nq[i].hwq.pbl[rdev->nq[i].hwq.level].pg_count;
++ rc = bnxt_re_net_ring_alloc(rdev, pg_map, pages, type,
++ BNXT_QPLIB_NQE_MAX_CNT - 1,
++ rdev->msix_entries[i + 1].ring_idx,
++ &rdev->nq[i].ring_id);
+ if (rc) {
+ dev_err(rdev_to_dev(rdev),
+ "Failed to allocate NQ fw id with rc = 0x%x",
+@@ -1006,7 +1017,8 @@ static int bnxt_re_alloc_res(struct bnxt
+ return 0;
+ free_nq:
+ for (i = num_vec_created; i >= 0; i--) {
+- bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id);
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
+ bnxt_qplib_free_nq(&rdev->nq[i]);
+ }
+ bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
+@@ -1260,6 +1272,7 @@ static void bnxt_re_query_hwrm_intf_vers
+
+ static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev)
+ {
++ u8 type;
+ int rc;
+
+ if (test_and_clear_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags)) {
+@@ -1283,7 +1296,8 @@ static void bnxt_re_ib_unreg(struct bnxt
+ bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
+ bnxt_qplib_free_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx);
+ bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
+- bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id);
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id, type);
+ bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
+ }
+ if (test_and_clear_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags)) {
+@@ -1314,9 +1328,12 @@ static void bnxt_re_worker(struct work_s
+
+ static int bnxt_re_ib_reg(struct bnxt_re_dev *rdev)
+ {
+- int rc;
+-
++ dma_addr_t *pg_map;
++ u32 db_offt, ridx;
++ int pages, vid;
+ bool locked;
++ u8 type;
++ int rc;
+
+ /* Acquire rtnl lock through out this function */
+ rtnl_lock();
+@@ -1360,21 +1377,22 @@ static int bnxt_re_ib_reg(struct bnxt_re
+ pr_err("Failed to allocate RCFW Channel: %#x\n", rc);
+ goto fail;
+ }
+- rc = bnxt_re_net_ring_alloc
+- (rdev, rdev->rcfw.creq.pbl[PBL_LVL_0].pg_map_arr,
+- rdev->rcfw.creq.pbl[rdev->rcfw.creq.level].pg_count,
+- HWRM_RING_ALLOC_CMPL, BNXT_QPLIB_CREQE_MAX_CNT - 1,
+- rdev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx,
+- &rdev->rcfw.creq_ring_id);
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ pg_map = rdev->rcfw.creq.pbl[PBL_LVL_0].pg_map_arr;
++ pages = rdev->rcfw.creq.pbl[rdev->rcfw.creq.level].pg_count;
++ ridx = rdev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
++ rc = bnxt_re_net_ring_alloc(rdev, pg_map, pages, type,
++ BNXT_QPLIB_CREQE_MAX_CNT - 1,
++ ridx, &rdev->rcfw.creq_ring_id);
+ if (rc) {
+ pr_err("Failed to allocate CREQ: %#x\n", rc);
+ goto free_rcfw;
+ }
+- rc = bnxt_qplib_enable_rcfw_channel
+- (rdev->en_dev->pdev, &rdev->rcfw,
+- rdev->msix_entries[BNXT_RE_AEQ_IDX].vector,
+- rdev->msix_entries[BNXT_RE_AEQ_IDX].db_offset,
+- rdev->is_virtfn, &bnxt_re_aeq_handler);
++ db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);
++ vid = rdev->msix_entries[BNXT_RE_AEQ_IDX].vector;
++ rc = bnxt_qplib_enable_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw,
++ vid, db_offt, rdev->is_virtfn,
++ &bnxt_re_aeq_handler);
+ if (rc) {
+ pr_err("Failed to enable RCFW channel: %#x\n", rc);
+ goto free_ring;
+@@ -1458,7 +1476,8 @@ free_ctx:
+ disable_rcfw:
+ bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
+ free_ring:
+- bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id);
++ type = bnxt_qplib_get_ring_type(&rdev->chip_ctx);
++ bnxt_re_net_ring_free(rdev, rdev->rcfw.creq_ring_id, type);
+ free_rcfw:
+ bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
+ fail:
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
+@@ -244,6 +244,7 @@ static void bnxt_qplib_service_nq(unsign
+ u16 type;
+ int budget = nq->budget;
+ uintptr_t q_handle;
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
+
+ /* Service the NQ until empty */
+ raw_cons = hwq->cons;
+@@ -290,7 +291,7 @@ static void bnxt_qplib_service_nq(unsign
+ q_handle |= (u64)le32_to_cpu(nqsrqe->srq_handle_high)
+ << 32;
+ bnxt_qplib_arm_srq((struct bnxt_qplib_srq *)q_handle,
+- DBR_DBR_TYPE_SRQ_ARMENA);
++ DBC_DBC_TYPE_SRQ_ARMENA);
+ if (!nq->srqn_handler(nq,
+ (struct bnxt_qplib_srq *)q_handle,
+ nqsrqe->event))
+@@ -312,7 +313,9 @@ static void bnxt_qplib_service_nq(unsign
+ }
+ if (hwq->cons != raw_cons) {
+ hwq->cons = raw_cons;
+- NQ_DB_REARM(nq->bar_reg_iomem, hwq->cons, hwq->max_elements);
++ bnxt_qplib_ring_nq_db_rearm(nq->bar_reg_iomem, hwq->cons,
++ hwq->max_elements, nq->ring_id,
++ gen_p5);
+ }
+ }
+
+@@ -336,9 +339,11 @@ static irqreturn_t bnxt_qplib_nq_irq(int
+
+ void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill)
+ {
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
+ tasklet_disable(&nq->worker);
+ /* Mask h/w interrupt */
+- NQ_DB(nq->bar_reg_iomem, nq->hwq.cons, nq->hwq.max_elements);
++ bnxt_qplib_ring_nq_db(nq->bar_reg_iomem, nq->hwq.cons,
++ nq->hwq.max_elements, nq->ring_id, gen_p5);
+ /* Sync with last running IRQ handler */
+ synchronize_irq(nq->vector);
+ if (kill)
+@@ -373,6 +378,7 @@ void bnxt_qplib_disable_nq(struct bnxt_q
+ int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
+ int msix_vector, bool need_init)
+ {
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(nq->res->cctx);
+ int rc;
+
+ if (nq->requested)
+@@ -399,7 +405,8 @@ int bnxt_qplib_nq_start_irq(struct bnxt_
+ nq->vector, nq_indx);
+ }
+ nq->requested = true;
+- NQ_DB_REARM(nq->bar_reg_iomem, nq->hwq.cons, nq->hwq.max_elements);
++ bnxt_qplib_ring_nq_db_rearm(nq->bar_reg_iomem, nq->hwq.cons,
++ nq->hwq.max_elements, nq->ring_id, gen_p5);
+
+ return rc;
+ }
+@@ -433,7 +440,8 @@ int bnxt_qplib_enable_nq(struct pci_dev
+ rc = -ENOMEM;
+ goto fail;
+ }
+- nq->bar_reg_iomem = ioremap_nocache(nq_base + nq->bar_reg_off, 4);
++ /* Unconditionally map 8 bytes to support 57500 series */
++ nq->bar_reg_iomem = ioremap_nocache(nq_base + nq->bar_reg_off, 8);
+ if (!nq->bar_reg_iomem) {
+ rc = -ENOMEM;
+ goto fail;
+@@ -462,15 +470,17 @@ void bnxt_qplib_free_nq(struct bnxt_qpli
+
+ int bnxt_qplib_alloc_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq)
+ {
++ u8 hwq_type;
++
+ nq->pdev = pdev;
+ if (!nq->hwq.max_elements ||
+ nq->hwq.max_elements > BNXT_QPLIB_NQE_MAX_CNT)
+ nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
+-
++ hwq_type = bnxt_qplib_get_hwq_type(nq->res);
+ if (bnxt_qplib_alloc_init_hwq(nq->pdev, &nq->hwq, NULL, 0,
+ &nq->hwq.max_elements,
+ BNXT_QPLIB_MAX_NQE_ENTRY_SIZE, 0,
+- PAGE_SIZE, HWQ_TYPE_L2_CMPL))
++ PAGE_SIZE, hwq_type))
+ return -ENOMEM;
+
+ nq->budget = 8;
+@@ -481,21 +491,19 @@ int bnxt_qplib_alloc_nq(struct pci_dev *
+ static void bnxt_qplib_arm_srq(struct bnxt_qplib_srq *srq, u32 arm_type)
+ {
+ struct bnxt_qplib_hwq *srq_hwq = &srq->hwq;
+- struct dbr_dbr db_msg = { 0 };
+ void __iomem *db;
+- u32 sw_prod = 0;
++ u32 sw_prod;
++ u64 val = 0;
+
+ /* Ring DB */
+- sw_prod = (arm_type == DBR_DBR_TYPE_SRQ_ARM) ? srq->threshold :
+- HWQ_CMP(srq_hwq->prod, srq_hwq);
+- db_msg.index = cpu_to_le32((sw_prod << DBR_DBR_INDEX_SFT) &
+- DBR_DBR_INDEX_MASK);
+- db_msg.type_xid = cpu_to_le32(((srq->id << DBR_DBR_XID_SFT) &
+- DBR_DBR_XID_MASK) | arm_type);
+- db = (arm_type == DBR_DBR_TYPE_SRQ_ARMENA) ?
+- srq->dbr_base : srq->dpi->dbr;
+- wmb(); /* barrier before db ring */
+- __iowrite64_copy(db, &db_msg, sizeof(db_msg) / sizeof(u64));
++ sw_prod = (arm_type == DBC_DBC_TYPE_SRQ_ARM) ?
++ srq->threshold : HWQ_CMP(srq_hwq->prod, srq_hwq);
++ db = (arm_type == DBC_DBC_TYPE_SRQ_ARMENA) ? srq->dbr_base :
++ srq->dpi->dbr;
++ val = ((srq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | arm_type;
++ val <<= 32;
++ val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK;
++ writeq(val, db);
+ }
+
+ int bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
+@@ -590,7 +598,7 @@ int bnxt_qplib_create_srq(struct bnxt_qp
+ srq->id = le32_to_cpu(resp.xid);
+ srq->dbr_base = res->dpi_tbl.dbr_bar_reg_iomem;
+ if (srq->threshold)
+- bnxt_qplib_arm_srq(srq, DBR_DBR_TYPE_SRQ_ARMENA);
++ bnxt_qplib_arm_srq(srq, DBC_DBC_TYPE_SRQ_ARMENA);
+ srq->arm_req = false;
+
+ return 0;
+@@ -614,7 +622,7 @@ int bnxt_qplib_modify_srq(struct bnxt_qp
+ srq_hwq->max_elements - sw_cons + sw_prod;
+ if (count > srq->threshold) {
+ srq->arm_req = false;
+- bnxt_qplib_arm_srq(srq, DBR_DBR_TYPE_SRQ_ARM);
++ bnxt_qplib_arm_srq(srq, DBC_DBC_TYPE_SRQ_ARM);
+ } else {
+ /* Deferred arming */
+ srq->arm_req = true;
+@@ -702,10 +710,10 @@ int bnxt_qplib_post_srq_recv(struct bnxt
+ srq_hwq->max_elements - sw_cons + sw_prod;
+ spin_unlock(&srq_hwq->lock);
+ /* Ring DB */
+- bnxt_qplib_arm_srq(srq, DBR_DBR_TYPE_SRQ);
++ bnxt_qplib_arm_srq(srq, DBC_DBC_TYPE_SRQ);
+ if (srq->arm_req == true && count > srq->threshold) {
+ srq->arm_req = false;
+- bnxt_qplib_arm_srq(srq, DBR_DBR_TYPE_SRQ_ARM);
++ bnxt_qplib_arm_srq(srq, DBC_DBC_TYPE_SRQ_ARM);
+ }
+ done:
+ return rc;
+@@ -1494,19 +1502,16 @@ void *bnxt_qplib_get_qp1_rq_buf(struct b
+ void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp)
+ {
+ struct bnxt_qplib_q *sq = &qp->sq;
+- struct dbr_dbr db_msg = { 0 };
+ u32 sw_prod;
++ u64 val = 0;
+
++ val = (((qp->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) |
++ DBC_DBC_TYPE_SQ);
++ val <<= 32;
+ sw_prod = HWQ_CMP(sq->hwq.prod, &sq->hwq);
+-
+- db_msg.index = cpu_to_le32((sw_prod << DBR_DBR_INDEX_SFT) &
+- DBR_DBR_INDEX_MASK);
+- db_msg.type_xid =
+- cpu_to_le32(((qp->id << DBR_DBR_XID_SFT) & DBR_DBR_XID_MASK) |
+- DBR_DBR_TYPE_SQ);
++ val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK;
+ /* Flush all the WQE writes to HW */
+- wmb();
+- __iowrite64_copy(qp->dpi->dbr, &db_msg, sizeof(db_msg) / sizeof(u64));
++ writeq(val, qp->dpi->dbr);
+ }
+
+ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
+@@ -1785,19 +1790,16 @@ done:
+ void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp)
+ {
+ struct bnxt_qplib_q *rq = &qp->rq;
+- struct dbr_dbr db_msg = { 0 };
+ u32 sw_prod;
++ u64 val = 0;
+
++ val = (((qp->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) |
++ DBC_DBC_TYPE_RQ);
++ val <<= 32;
+ sw_prod = HWQ_CMP(rq->hwq.prod, &rq->hwq);
+- db_msg.index = cpu_to_le32((sw_prod << DBR_DBR_INDEX_SFT) &
+- DBR_DBR_INDEX_MASK);
+- db_msg.type_xid =
+- cpu_to_le32(((qp->id << DBR_DBR_XID_SFT) & DBR_DBR_XID_MASK) |
+- DBR_DBR_TYPE_RQ);
+-
++ val |= (sw_prod << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK;
+ /* Flush the writes to HW Rx WQE before the ringing Rx DB */
+- wmb();
+- __iowrite64_copy(qp->dpi->dbr, &db_msg, sizeof(db_msg) / sizeof(u64));
++ writeq(val, qp->dpi->dbr);
+ }
+
+ int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
+@@ -1881,32 +1883,28 @@ done:
+ /* Spinlock must be held */
+ static void bnxt_qplib_arm_cq_enable(struct bnxt_qplib_cq *cq)
+ {
+- struct dbr_dbr db_msg = { 0 };
++ u64 val = 0;
+
+- db_msg.type_xid =
+- cpu_to_le32(((cq->id << DBR_DBR_XID_SFT) & DBR_DBR_XID_MASK) |
+- DBR_DBR_TYPE_CQ_ARMENA);
++ val = ((cq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) |
++ DBC_DBC_TYPE_CQ_ARMENA;
++ val <<= 32;
+ /* Flush memory writes before enabling the CQ */
+- wmb();
+- __iowrite64_copy(cq->dbr_base, &db_msg, sizeof(db_msg) / sizeof(u64));
++ writeq(val, cq->dbr_base);
+ }
+
+ static void bnxt_qplib_arm_cq(struct bnxt_qplib_cq *cq, u32 arm_type)
+ {
+ struct bnxt_qplib_hwq *cq_hwq = &cq->hwq;
+- struct dbr_dbr db_msg = { 0 };
+ u32 sw_cons;
++ u64 val = 0;
+
+ /* Ring DB */
++ val = ((cq->id << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | arm_type;
++ val <<= 32;
+ sw_cons = HWQ_CMP(cq_hwq->cons, cq_hwq);
+- db_msg.index = cpu_to_le32((sw_cons << DBR_DBR_INDEX_SFT) &
+- DBR_DBR_INDEX_MASK);
+- db_msg.type_xid =
+- cpu_to_le32(((cq->id << DBR_DBR_XID_SFT) & DBR_DBR_XID_MASK) |
+- arm_type);
++ val |= (sw_cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK;
+ /* flush memory writes before arming the CQ */
+- wmb();
+- __iowrite64_copy(cq->dpi->dbr, &db_msg, sizeof(db_msg) / sizeof(u64));
++ writeq(val, cq->dpi->dbr);
+ }
+
+ int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)
+@@ -2125,7 +2123,7 @@ static int do_wa9060(struct bnxt_qplib_q
+ sq->send_phantom = true;
+
+ /* TODO: Only ARM if the previous SQE is ARMALL */
+- bnxt_qplib_arm_cq(cq, DBR_DBR_TYPE_CQ_ARMALL);
++ bnxt_qplib_arm_cq(cq, DBC_DBC_TYPE_CQ_ARMALL);
+
+ rc = -EAGAIN;
+ goto out;
+@@ -2794,7 +2792,7 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib
+ }
+ if (cq->hwq.cons != raw_cons) {
+ cq->hwq.cons = raw_cons;
+- bnxt_qplib_arm_cq(cq, DBR_DBR_TYPE_CQ);
++ bnxt_qplib_arm_cq(cq, DBC_DBC_TYPE_CQ);
+ }
+ exit:
+ return num_cqes - budget;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+@@ -432,10 +432,43 @@ struct bnxt_qplib_cq {
+ #define NQ_DB_CP_FLAGS (NQ_DB_KEY_CP | \
+ NQ_DB_IDX_VALID | \
+ NQ_DB_IRQ_DIS)
+-#define NQ_DB_REARM(db, raw_cons, cp_bit) \
+- writel(NQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
+-#define NQ_DB(db, raw_cons, cp_bit) \
+- writel(NQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
++
++static inline void bnxt_qplib_ring_nq_db64(void __iomem *db, u32 index,
++ u32 xid, bool arm)
++{
++ u64 val;
++
++ val = xid & DBC_DBC_XID_MASK;
++ val |= DBC_DBC_PATH_ROCE;
++ val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
++ val <<= 32;
++ val |= index & DBC_DBC_INDEX_MASK;
++ writeq(val, db);
++}
++
++static inline void bnxt_qplib_ring_nq_db_rearm(void __iomem *db, u32 raw_cons,
++ u32 max_elements, u32 xid,
++ bool gen_p5)
++{
++ u32 index = raw_cons & (max_elements - 1);
++
++ if (gen_p5)
++ bnxt_qplib_ring_nq_db64(db, index, xid, true);
++ else
++ writel(NQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK), db);
++}
++
++static inline void bnxt_qplib_ring_nq_db(void __iomem *db, u32 raw_cons,
++ u32 max_elements, u32 xid,
++ bool gen_p5)
++{
++ u32 index = raw_cons & (max_elements - 1);
++
++ if (gen_p5)
++ bnxt_qplib_ring_nq_db64(db, index, xid, false);
++ else
++ writel(NQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK), db);
++}
+
+ struct bnxt_qplib_nq {
+ struct pci_dev *pdev;
+@@ -449,7 +482,7 @@ struct bnxt_qplib_nq {
+ struct bnxt_qplib_hwq hwq;
+
+ u16 bar_reg;
+- u16 bar_reg_off;
++ u32 bar_reg_off;
+ u16 ring_id;
+ void __iomem *bar_reg_iomem;
+
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
+@@ -359,11 +359,12 @@ static int bnxt_qplib_process_qp_event(s
+ static void bnxt_qplib_service_creq(unsigned long data)
+ {
+ struct bnxt_qplib_rcfw *rcfw = (struct bnxt_qplib_rcfw *)data;
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
+ struct bnxt_qplib_hwq *creq = &rcfw->creq;
++ u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
+ struct creq_base *creqe, **creq_ptr;
+ u32 sw_cons, raw_cons;
+ unsigned long flags;
+- u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
+
+ /* Service the CREQ until budget is over */
+ spin_lock_irqsave(&creq->lock, flags);
+@@ -407,8 +408,9 @@ static void bnxt_qplib_service_creq(unsi
+
+ if (creq->cons != raw_cons) {
+ creq->cons = raw_cons;
+- CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, raw_cons,
+- creq->max_elements);
++ bnxt_qplib_ring_creq_db_rearm(rcfw->creq_bar_reg_iomem,
++ raw_cons, creq->max_elements,
++ rcfw->creq_ring_id, gen_p5);
+ }
+ spin_unlock_irqrestore(&creq->lock, flags);
+ }
+@@ -560,12 +562,15 @@ int bnxt_qplib_alloc_rcfw_channel(struct
+ struct bnxt_qplib_ctx *ctx,
+ int qp_tbl_sz)
+ {
++ u8 hwq_type;
++
+ rcfw->pdev = pdev;
+ rcfw->creq.max_elements = BNXT_QPLIB_CREQE_MAX_CNT;
++ hwq_type = bnxt_qplib_get_hwq_type(rcfw->res);
+ if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->creq, NULL, 0,
+ &rcfw->creq.max_elements,
+- BNXT_QPLIB_CREQE_UNITS, 0, PAGE_SIZE,
+- HWQ_TYPE_L2_CMPL)) {
++ BNXT_QPLIB_CREQE_UNITS,
++ 0, PAGE_SIZE, hwq_type)) {
+ dev_err(&rcfw->pdev->dev,
+ "HW channel CREQ allocation failed\n");
+ goto fail;
+@@ -607,10 +612,13 @@ fail:
+
+ void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
+ {
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
++
+ tasklet_disable(&rcfw->worker);
+ /* Mask h/w interrupts */
+- CREQ_DB(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
+- rcfw->creq.max_elements);
++ bnxt_qplib_ring_creq_db(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
++ rcfw->creq.max_elements, rcfw->creq_ring_id,
++ gen_p5);
+ /* Sync with last running IRQ-handler */
+ synchronize_irq(rcfw->vector);
+ if (kill)
+@@ -647,6 +655,7 @@ void bnxt_qplib_disable_rcfw_channel(str
+ int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
+ bool need_init)
+ {
++ bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
+ int rc;
+
+ if (rcfw->requested)
+@@ -663,8 +672,9 @@ int bnxt_qplib_rcfw_start_irq(struct bnx
+ if (rc)
+ return rc;
+ rcfw->requested = true;
+- CREQ_DB_REARM(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
+- rcfw->creq.max_elements);
++ bnxt_qplib_ring_creq_db_rearm(rcfw->creq_bar_reg_iomem,
++ rcfw->creq.cons, rcfw->creq.max_elements,
++ rcfw->creq_ring_id, gen_p5);
+
+ return 0;
+ }
+@@ -717,8 +727,9 @@ int bnxt_qplib_enable_rcfw_channel(struc
+ dev_err(&rcfw->pdev->dev,
+ "CREQ BAR region %d resc start is 0!\n",
+ rcfw->creq_bar_reg);
++ /* Unconditionally map 8 bytes to support 57500 series */
+ rcfw->creq_bar_reg_iomem = ioremap_nocache(res_base + cp_bar_reg_off,
+- 4);
++ 8);
+ if (!rcfw->creq_bar_reg_iomem) {
+ dev_err(&rcfw->pdev->dev, "CREQ BAR region %d mapping failed\n",
+ rcfw->creq_bar_reg);
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
+@@ -157,10 +157,46 @@ static inline u32 get_creq_idx(u32 val)
+ #define CREQ_DB_CP_FLAGS (CREQ_DB_KEY_CP | \
+ CREQ_DB_IDX_VALID | \
+ CREQ_DB_IRQ_DIS)
+-#define CREQ_DB_REARM(db, raw_cons, cp_bit) \
+- writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
+-#define CREQ_DB(db, raw_cons, cp_bit) \
+- writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
++
++static inline void bnxt_qplib_ring_creq_db64(void __iomem *db, u32 index,
++ u32 xid, bool arm)
++{
++ u64 val = 0;
++
++ val = xid & DBC_DBC_XID_MASK;
++ val |= DBC_DBC_PATH_ROCE;
++ val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
++ val <<= 32;
++ val |= index & DBC_DBC_INDEX_MASK;
++
++ writeq(val, db);
++}
++
++static inline void bnxt_qplib_ring_creq_db_rearm(void __iomem *db, u32 raw_cons,
++ u32 max_elements, u32 xid,
++ bool gen_p5)
++{
++ u32 index = raw_cons & (max_elements - 1);
++
++ if (gen_p5)
++ bnxt_qplib_ring_creq_db64(db, index, xid, true);
++ else
++ writel(CREQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK),
++ db);
++}
++
++static inline void bnxt_qplib_ring_creq_db(void __iomem *db, u32 raw_cons,
++ u32 max_elements, u32 xid,
++ bool gen_p5)
++{
++ u32 index = raw_cons & (max_elements - 1);
++
++ if (gen_p5)
++ bnxt_qplib_ring_creq_db64(db, index, xid, true);
++ else
++ writel(CREQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK),
++ db);
++}
+
+ #define CREQ_ENTRY_POLL_BUDGET 0x100
+
+--- a/drivers/infiniband/hw/bnxt_re/qplib_res.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h
+@@ -206,6 +206,19 @@ static inline bool bnxt_qplib_is_chip_ge
+ return (cctx->chip_num == CHIP_NUM_57500);
+ }
+
++static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
++{
++ return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
++ HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
++}
++
++static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
++{
++ return bnxt_qplib_is_chip_gen_p5(cctx) ?
++ RING_ALLOC_REQ_RING_TYPE_NQ :
++ RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
++}
++
+ #define to_bnxt_qplib(ptr, type, member) \
+ container_of(ptr, type, member)
+
+--- a/drivers/infiniband/hw/bnxt_re/roce_hsi.h
++++ b/drivers/infiniband/hw/bnxt_re/roce_hsi.h
+@@ -49,11 +49,11 @@ struct cmpl_doorbell {
+ #define CMPL_DOORBELL_IDX_SFT 0
+ #define CMPL_DOORBELL_RESERVED_MASK 0x3000000UL
+ #define CMPL_DOORBELL_RESERVED_SFT 24
+- #define CMPL_DOORBELL_IDX_VALID 0x4000000UL
++ #define CMPL_DOORBELL_IDX_VALID 0x4000000UL
+ #define CMPL_DOORBELL_MASK 0x8000000UL
+ #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
+ #define CMPL_DOORBELL_KEY_SFT 28
+- #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
++ #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
+ };
+
+ /* Status Door Bell Format (4 bytes) */
+@@ -71,46 +71,56 @@ struct status_doorbell {
+ /* RoCE Host Structures */
+
+ /* Doorbell Structures */
+-/* 64b Doorbell Format (8 bytes) */
+-struct dbr_dbr {
+- __le32 index;
+- #define DBR_DBR_INDEX_MASK 0xfffffUL
+- #define DBR_DBR_INDEX_SFT 0
+- #define DBR_DBR_RESERVED12_MASK 0xfff00000UL
+- #define DBR_DBR_RESERVED12_SFT 20
+- __le32 type_xid;
+- #define DBR_DBR_XID_MASK 0xfffffUL
+- #define DBR_DBR_XID_SFT 0
+- #define DBR_DBR_RESERVED8_MASK 0xff00000UL
+- #define DBR_DBR_RESERVED8_SFT 20
+- #define DBR_DBR_TYPE_MASK 0xf0000000UL
+- #define DBR_DBR_TYPE_SFT 28
+- #define DBR_DBR_TYPE_SQ (0x0UL << 28)
+- #define DBR_DBR_TYPE_RQ (0x1UL << 28)
+- #define DBR_DBR_TYPE_SRQ (0x2UL << 28)
+- #define DBR_DBR_TYPE_SRQ_ARM (0x3UL << 28)
+- #define DBR_DBR_TYPE_CQ (0x4UL << 28)
+- #define DBR_DBR_TYPE_CQ_ARMSE (0x5UL << 28)
+- #define DBR_DBR_TYPE_CQ_ARMALL (0x6UL << 28)
+- #define DBR_DBR_TYPE_CQ_ARMENA (0x7UL << 28)
+- #define DBR_DBR_TYPE_SRQ_ARMENA (0x8UL << 28)
+- #define DBR_DBR_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
+- #define DBR_DBR_TYPE_NULL (0xfUL << 28)
+-};
+-
+-/* 32b Doorbell Format (4 bytes) */
+-struct dbr_dbr32 {
+- __le32 type_abs_incr_xid;
+- #define DBR_DBR32_XID_MASK 0xfffffUL
+- #define DBR_DBR32_XID_SFT 0
+- #define DBR_DBR32_RESERVED4_MASK 0xf00000UL
+- #define DBR_DBR32_RESERVED4_SFT 20
+- #define DBR_DBR32_INCR_MASK 0xf000000UL
+- #define DBR_DBR32_INCR_SFT 24
+- #define DBR_DBR32_ABS 0x10000000UL
+- #define DBR_DBR32_TYPE_MASK 0xe0000000UL
+- #define DBR_DBR32_TYPE_SFT 29
+- #define DBR_DBR32_TYPE_SQ (0x0UL << 29)
++/* dbc_dbc (size:64b/8B) */
++struct dbc_dbc {
++ __le32 index;
++ #define DBC_DBC_INDEX_MASK 0xffffffUL
++ #define DBC_DBC_INDEX_SFT 0
++ __le32 type_path_xid;
++ #define DBC_DBC_XID_MASK 0xfffffUL
++ #define DBC_DBC_XID_SFT 0
++ #define DBC_DBC_PATH_MASK 0x3000000UL
++ #define DBC_DBC_PATH_SFT 24
++ #define DBC_DBC_PATH_ROCE (0x0UL << 24)
++ #define DBC_DBC_PATH_L2 (0x1UL << 24)
++ #define DBC_DBC_PATH_ENGINE (0x2UL << 24)
++ #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
++ #define DBC_DBC_DEBUG_TRACE 0x8000000UL
++ #define DBC_DBC_TYPE_MASK 0xf0000000UL
++ #define DBC_DBC_TYPE_SFT 28
++ #define DBC_DBC_TYPE_SQ (0x0UL << 28)
++ #define DBC_DBC_TYPE_RQ (0x1UL << 28)
++ #define DBC_DBC_TYPE_SRQ (0x2UL << 28)
++ #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28)
++ #define DBC_DBC_TYPE_CQ (0x4UL << 28)
++ #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28)
++ #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28)
++ #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28)
++ #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28)
++ #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
++ #define DBC_DBC_TYPE_NQ (0xaUL << 28)
++ #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28)
++ #define DBC_DBC_TYPE_NULL (0xfUL << 28)
++ #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
++};
++
++/* dbc_dbc32 (size:32b/4B) */
++struct dbc_dbc32 {
++ __le32 type_abs_incr_xid;
++ #define DBC_DBC32_XID_MASK 0xfffffUL
++ #define DBC_DBC32_XID_SFT 0
++ #define DBC_DBC32_PATH_MASK 0xc00000UL
++ #define DBC_DBC32_PATH_SFT 22
++ #define DBC_DBC32_PATH_ROCE (0x0UL << 22)
++ #define DBC_DBC32_PATH_L2 (0x1UL << 22)
++ #define DBC_DBC32_PATH_LAST DBC_DBC32_PATH_L2
++ #define DBC_DBC32_INCR_MASK 0xf000000UL
++ #define DBC_DBC32_INCR_SFT 24
++ #define DBC_DBC32_ABS 0x10000000UL
++ #define DBC_DBC32_TYPE_MASK 0xe0000000UL
++ #define DBC_DBC32_TYPE_SFT 29
++ #define DBC_DBC32_TYPE_SQ (0x0UL << 29)
++ #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ
+ };
+
+ /* SQ WQE Structures */
+@@ -2719,6 +2729,8 @@ struct creq_query_func_resp_sb {
+ __le16 max_srq;
+ __le32 max_gid;
+ __le32 tqm_alloc_reqs[12];
++ __le32 max_dpi;
++ __le32 reserved_32;
+ };
+
+ /* Set resources command response (16 bytes) */
diff --git a/patches.drivers/RDMA-bnxt_re-Add-chip-context-to-identify-57500-seri.patch b/patches.drivers/RDMA-bnxt_re-Add-chip-context-to-identify-57500-seri.patch
new file mode 100644
index 0000000000..fc62f0571a
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Add-chip-context-to-identify-57500-seri.patch
@@ -0,0 +1,169 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:22 -0500
+Subject: RDMA/bnxt_re: Add chip context to identify 57500 series
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: ae8637e13185ab05b45bcf35f769f7f627c6714c
+References: bsc#1125239
+
+Adding setup and destroy routines for chip-context. The chip context would
+be used frequently in control and data path to take execution flow
+depending on the chip type. chip context structure pointer is added to
+the relevant data structures.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/bnxt_re.h | 1
+ drivers/infiniband/hw/bnxt_re/main.c | 34 +++++++++++++++++++++++++++++
+ drivers/infiniband/hw/bnxt_re/qplib_fp.h | 1
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.h | 1
+ drivers/infiniband/hw/bnxt_re/qplib_res.h | 15 +++++++++++-
+ 5 files changed, 51 insertions(+), 1 deletion(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/bnxt_re.h
++++ b/drivers/infiniband/hw/bnxt_re/bnxt_re.h
+@@ -124,6 +124,7 @@ struct bnxt_re_dev {
+ #define BNXT_RE_FLAG_ISSUE_ROCE_STATS 29
+ struct net_device *netdev;
+ unsigned int version, major, minor;
++ struct bnxt_qplib_chip_ctx chip_ctx;
+ struct bnxt_en_dev *en_dev;
+ struct bnxt_msix_entry msix_entries[BNXT_RE_MAX_MSIX];
+ int num_msix;
+--- a/drivers/infiniband/hw/bnxt_re/main.c
++++ b/drivers/infiniband/hw/bnxt_re/main.c
+@@ -80,6 +80,29 @@ static DEFINE_MUTEX(bnxt_re_dev_lock);
+ static struct workqueue_struct *bnxt_re_wq;
+ static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev);
+
++static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
++{
++ rdev->rcfw.res = NULL;
++ rdev->qplib_res.cctx = NULL;
++}
++
++static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
++{
++ struct bnxt_en_dev *en_dev;
++ struct bnxt *bp;
++
++ en_dev = rdev->en_dev;
++ bp = netdev_priv(en_dev->net);
++
++ rdev->chip_ctx.chip_num = bp->chip_num;
++ /* rest members to follow eventually */
++
++ rdev->qplib_res.cctx = &rdev->chip_ctx;
++ rdev->rcfw.res = &rdev->qplib_res;
++
++ return 0;
++}
++
+ /* SR-IOV helper functions */
+
+ static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
+@@ -278,6 +301,7 @@ static int bnxt_re_register_netdev(struc
+
+ rc = en_dev->en_ops->bnxt_register_device(en_dev, BNXT_ROCE_ULP,
+ &bnxt_re_ulp_ops, rdev);
++ rdev->qplib_res.pdev = rdev->en_dev->pdev;
+ return rc;
+ }
+
+@@ -909,6 +933,7 @@ static void bnxt_re_free_nq_res(struct b
+ int i;
+
+ for (i = 0; i < rdev->num_msix - 1; i++) {
++ rdev->nq[i].res = NULL;
+ bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id);
+ bnxt_qplib_free_nq(&rdev->nq[i]);
+ }
+@@ -953,6 +978,7 @@ static int bnxt_re_alloc_res(struct bnxt
+ goto dealloc_res;
+
+ for (i = 0; i < rdev->num_msix - 1; i++) {
++ rdev->nq[i].res = &rdev->qplib_res;
+ rdev->nq[i].hwq.max_elements = BNXT_RE_MAX_CQ_COUNT +
+ BNXT_RE_MAX_SRQC_COUNT + 2;
+ rc = bnxt_qplib_alloc_nq(rdev->en_dev->pdev, &rdev->nq[i]);
+@@ -1266,6 +1292,8 @@ static void bnxt_re_ib_unreg(struct bnxt
+ dev_warn(rdev_to_dev(rdev),
+ "Failed to free MSI-X vectors: %#x", rc);
+ }
++
++ bnxt_re_destroy_chip_ctx(rdev);
+ if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) {
+ rc = bnxt_re_unregister_netdev(rdev);
+ if (rc)
+@@ -1303,6 +1331,12 @@ static int bnxt_re_ib_reg(struct bnxt_re
+ }
+ set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
+
++ rc = bnxt_re_setup_chip_ctx(rdev);
++ if (rc) {
++ dev_err(rdev_to_dev(rdev), "Failed to get chip context\n");
++ return -EINVAL;
++ }
++
+ /* Check whether VF or PF */
+ bnxt_re_get_sriov_func_type(rdev);
+
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+@@ -439,6 +439,7 @@ struct bnxt_qplib_cq {
+
+ struct bnxt_qplib_nq {
+ struct pci_dev *pdev;
++ struct bnxt_qplib_res *res;
+
+ int vector;
+ cpumask_t mask;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
+@@ -187,6 +187,7 @@ struct bnxt_qplib_qp_node {
+ /* RCFW Communication Channels */
+ struct bnxt_qplib_rcfw {
+ struct pci_dev *pdev;
++ struct bnxt_qplib_res *res;
+ int vector;
+ struct tasklet_struct worker;
+ bool requested;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_res.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h
+@@ -180,12 +180,20 @@ struct bnxt_qplib_ctx {
+ u64 hwrm_intf_ver;
+ };
+
++struct bnxt_qplib_chip_ctx {
++ u16 chip_num;
++ u8 chip_rev;
++ u8 chip_metal;
++};
++
++#define CHIP_NUM_57500 0x1750
++
+ struct bnxt_qplib_res {
+ struct pci_dev *pdev;
++ struct bnxt_qplib_chip_ctx *cctx;
+ struct net_device *netdev;
+
+ struct bnxt_qplib_rcfw *rcfw;
+-
+ struct bnxt_qplib_pd_tbl pd_tbl;
+ struct bnxt_qplib_sgid_tbl sgid_tbl;
+ struct bnxt_qplib_pkey_tbl pkey_tbl;
+@@ -193,6 +201,11 @@ struct bnxt_qplib_res {
+ bool prio;
+ };
+
++static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
++{
++ return (cctx->chip_num == CHIP_NUM_57500);
++}
++
+ #define to_bnxt_qplib(ptr, type, member) \
+ container_of(ptr, type, member)
+
diff --git a/patches.drivers/RDMA-bnxt_re-Add-extended-psn-structure-for-57500-ad.patch b/patches.drivers/RDMA-bnxt_re-Add-extended-psn-structure-for-57500-ad.patch
new file mode 100644
index 0000000000..0702a9ed2b
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Add-extended-psn-structure-for-57500-ad.patch
@@ -0,0 +1,233 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:26 -0500
+Subject: RDMA/bnxt_re: Add extended psn structure for 57500 adapters
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: 37f91cff2de0170930a92e091beed42a4708bcd2
+References: bsc#1125239
+
+The new 57500 series of adapter has bigger psn search structure. The size
+of new structure is 16B. Changing the control path memory allocation and
+fast path code to accommodate the new psn structure while maintaining the
+backward compatibility.
+
+There are few additional changes listed below:
+ - For 57500 chip max-sge are limited to 6 for now.
+ - For 57500 chip max-receive-sge should be set to 6 for now.
+ - Add driver/hardware interface structure for new chip.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/ib_verbs.c | 13 ++++++-
+ drivers/infiniband/hw/bnxt_re/qplib_fp.c | 51 +++++++++++++++++++++++--------
+ drivers/infiniband/hw/bnxt_re/qplib_fp.h | 2 +
+ drivers/infiniband/hw/bnxt_re/qplib_sp.c | 3 +
+ drivers/infiniband/hw/bnxt_re/roce_hsi.h | 19 ++++++++++-
+ 5 files changed, 70 insertions(+), 18 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
++++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+@@ -881,7 +881,7 @@ static int bnxt_re_init_user_qp(struct b
+ struct bnxt_re_qp_req ureq;
+ struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
+ struct ib_umem *umem;
+- int bytes = 0;
++ int bytes = 0, psn_sz;
+ struct ib_ucontext *context = pd->ib_pd.uobject->context;
+ struct bnxt_re_ucontext *cntx = container_of(context,
+ struct bnxt_re_ucontext,
+@@ -891,8 +891,12 @@ static int bnxt_re_init_user_qp(struct b
+
+ bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
+ /* Consider mapping PSN search memory only for RC QPs. */
+- if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
+- bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
++ if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
++ psn_sz = bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ?
++ sizeof(struct sq_psn_search_ext) :
++ sizeof(struct sq_psn_search);
++ bytes += (qplib_qp->sq.max_wqe * psn_sz);
++ }
+ bytes = PAGE_ALIGN(bytes);
+ umem = ib_umem_get(context, ureq.qpsva, bytes,
+ IB_ACCESS_LOCAL_WRITE, 1);
+@@ -1651,6 +1655,9 @@ int bnxt_re_modify_qp(struct ib_qp *ib_q
+ __from_ib_access_flags(qp_attr->qp_access_flags);
+ /* LOCAL_WRITE access must be set to allow RC receive */
+ qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
++ /* Temp: Set all params on QP as of now */
++ qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
++ qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
+ }
+ if (qp_attr_mask & IB_QP_PKEY_INDEX) {
+ qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
+@@ -870,10 +870,11 @@ int bnxt_qplib_create_qp(struct bnxt_qpl
+ unsigned long int psn_search, poff = 0;
+ struct bnxt_qplib_q *sq = &qp->sq;
+ struct bnxt_qplib_q *rq = &qp->rq;
++ int i, rc, req_size, psn_sz = 0;
+ struct bnxt_qplib_hwq *xrrq;
+- int i, rc, req_size, psn_sz;
+ u16 cmd_flags = 0, max_ssge;
+ u32 sw_prod, qp_flags = 0;
++ u16 max_rsge;
+
+ RCFW_CMD_PREP(req, CREATE_QP, cmd_flags);
+
+@@ -883,8 +884,11 @@ int bnxt_qplib_create_qp(struct bnxt_qpl
+ req.qp_handle = cpu_to_le64(qp->qp_handle);
+
+ /* SQ */
+- psn_sz = (qp->type == CMDQ_CREATE_QP_TYPE_RC) ?
+- sizeof(struct sq_psn_search) : 0;
++ if (qp->type == CMDQ_CREATE_QP_TYPE_RC) {
++ psn_sz = bnxt_qplib_is_chip_gen_p5(res->cctx) ?
++ sizeof(struct sq_psn_search_ext) :
++ sizeof(struct sq_psn_search);
++ }
+ sq->hwq.max_elements = sq->max_wqe;
+ rc = bnxt_qplib_alloc_init_hwq(res->pdev, &sq->hwq, sq->sglist,
+ sq->nmap, &sq->hwq.max_elements,
+@@ -914,10 +918,16 @@ int bnxt_qplib_create_qp(struct bnxt_qpl
+ poff = (psn_search & ~PAGE_MASK) /
+ BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE;
+ }
+- for (i = 0; i < sq->hwq.max_elements; i++)
++ for (i = 0; i < sq->hwq.max_elements; i++) {
+ sq->swq[i].psn_search =
+ &psn_search_ptr[get_psne_pg(i + poff)]
+ [get_psne_idx(i + poff)];
++ /*psns_ext will be used only for P5 chips. */
++ sq->swq[i].psn_ext =
++ (struct sq_psn_search_ext *)
++ &psn_search_ptr[get_psne_pg(i + poff)]
++ [get_psne_idx(i + poff)];
++ }
+ }
+ pbl = &sq->hwq.pbl[PBL_LVL_0];
+ req.sq_pbl = cpu_to_le64(pbl->pg_map_arr[0]);
+@@ -1016,8 +1026,9 @@ int bnxt_qplib_create_qp(struct bnxt_qpl
+ req.sq_fwo_sq_sge = cpu_to_le16(
+ ((max_ssge & CMDQ_CREATE_QP_SQ_SGE_MASK)
+ << CMDQ_CREATE_QP_SQ_SGE_SFT) | 0);
++ max_rsge = bnxt_qplib_is_chip_gen_p5(res->cctx) ? 6 : rq->max_sge;
+ req.rq_fwo_rq_sge = cpu_to_le16(
+- ((rq->max_sge & CMDQ_CREATE_QP_RQ_SGE_MASK)
++ ((max_rsge & CMDQ_CREATE_QP_RQ_SGE_MASK)
+ << CMDQ_CREATE_QP_RQ_SGE_SFT) | 0);
+ /* ORRQ and IRRQ */
+ if (psn_sz) {
+@@ -1062,6 +1073,7 @@ int bnxt_qplib_create_qp(struct bnxt_qpl
+
+ qp->id = le32_to_cpu(resp.xid);
+ qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET;
++ qp->cctx = res->cctx;
+ INIT_LIST_HEAD(&qp->sq_flush);
+ INIT_LIST_HEAD(&qp->rq_flush);
+ rcfw->qp_tbl[qp->id].qp_id = qp->id;
+@@ -1748,14 +1760,26 @@ int bnxt_qplib_post_send(struct bnxt_qpl
+ }
+ swq->next_psn = sq->psn & BTH_PSN_MASK;
+ if (swq->psn_search) {
+- swq->psn_search->opcode_start_psn = cpu_to_le32(
+- ((swq->start_psn << SQ_PSN_SEARCH_START_PSN_SFT) &
+- SQ_PSN_SEARCH_START_PSN_MASK) |
+- ((wqe->type << SQ_PSN_SEARCH_OPCODE_SFT) &
+- SQ_PSN_SEARCH_OPCODE_MASK));
+- swq->psn_search->flags_next_psn = cpu_to_le32(
+- ((swq->next_psn << SQ_PSN_SEARCH_NEXT_PSN_SFT) &
+- SQ_PSN_SEARCH_NEXT_PSN_MASK));
++ u32 opcd_spsn;
++ u32 flg_npsn;
++
++ opcd_spsn = ((swq->start_psn << SQ_PSN_SEARCH_START_PSN_SFT) &
++ SQ_PSN_SEARCH_START_PSN_MASK);
++ opcd_spsn |= ((wqe->type << SQ_PSN_SEARCH_OPCODE_SFT) &
++ SQ_PSN_SEARCH_OPCODE_MASK);
++ flg_npsn = ((swq->next_psn << SQ_PSN_SEARCH_NEXT_PSN_SFT) &
++ SQ_PSN_SEARCH_NEXT_PSN_MASK);
++ if (bnxt_qplib_is_chip_gen_p5(qp->cctx)) {
++ swq->psn_ext->opcode_start_psn =
++ cpu_to_le32(opcd_spsn);
++ swq->psn_ext->flags_next_psn =
++ cpu_to_le32(flg_npsn);
++ } else {
++ swq->psn_search->opcode_start_psn =
++ cpu_to_le32(opcd_spsn);
++ swq->psn_search->flags_next_psn =
++ cpu_to_le32(flg_npsn);
++ }
+ }
+ queue_err:
+ if (sch_handler) {
+@@ -2053,6 +2077,7 @@ static int __flush_rq(struct bnxt_qplib_
+ opcode = CQ_BASE_CQE_TYPE_RES_RC;
+ break;
+ case CMDQ_CREATE_QP_TYPE_UD:
++ case CMDQ_CREATE_QP_TYPE_GSI:
+ opcode = CQ_BASE_CQE_TYPE_RES_UD;
+ break;
+ }
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+@@ -106,6 +106,7 @@ struct bnxt_qplib_swq {
+ u32 start_psn;
+ u32 next_psn;
+ struct sq_psn_search *psn_search;
++ struct sq_psn_search_ext *psn_ext;
+ };
+
+ struct bnxt_qplib_swqe {
+@@ -254,6 +255,7 @@ struct bnxt_qplib_q {
+ struct bnxt_qplib_qp {
+ struct bnxt_qplib_pd *pd;
+ struct bnxt_qplib_dpi *dpi;
++ struct bnxt_qplib_chip_ctx *cctx;
+ u64 qp_handle;
+ #define BNXT_QPLIB_QP_ID_INVALID 0xFFFFFFFF
+ u32 id;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
+@@ -119,7 +119,8 @@ int bnxt_qplib_get_dev_attr(struct bnxt_
+ * reporting the max number
+ */
+ attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS;
+- attr->max_qp_sges = sb->max_sge;
++ attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx) ?
++ 6 : sb->max_sge;
+ attr->max_cq = le32_to_cpu(sb->max_cq);
+ attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);
+ attr->max_cq_sges = attr->max_qp_sges;
+--- a/drivers/infiniband/hw/bnxt_re/roce_hsi.h
++++ b/drivers/infiniband/hw/bnxt_re/roce_hsi.h
+@@ -159,7 +159,24 @@ struct sq_psn_search {
+ #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL
+ #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
+ #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL
+- #define SQ_PSN_SEARCH_FLAGS_SFT 24
++ #define SQ_PSN_SEARCH_FLAGS_SFT 24
++};
++
++/* sq_psn_search_ext (size:128b/16B) */
++struct sq_psn_search_ext {
++ __le32 opcode_start_psn;
++ #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL
++ #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
++ #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL
++ #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24
++ __le32 flags_next_psn;
++ #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL
++ #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
++ #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL
++ #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24
++ __le16 start_slot_idx;
++ __le16 reserved16;
++ __le32 reserved32;
+ };
+
+ /* Send SQ WQE (40 bytes) */
diff --git a/patches.drivers/RDMA-bnxt_re-Enable-GSI-QP-support-for-57500-series.patch b/patches.drivers/RDMA-bnxt_re-Enable-GSI-QP-support-for-57500-series.patch
new file mode 100644
index 0000000000..f0958bd492
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Enable-GSI-QP-support-for-57500-series.patch
@@ -0,0 +1,358 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:25 -0500
+Subject: RDMA/bnxt_re: Enable GSI QP support for 57500 series
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: 374c5285abee0aa1b9e04c6beb86e13b6813db09
+References: bsc#1125239
+
+In the new 57500 series of adapters the GSI qp is a UD type QP unlike the
+previous generation where it was a Raw Eth QP. Changing the control and
+data path to support the same. Listing all the significant diffs:
+
+ - AH creation resolve network type unconditionally
+ - Add check at relevant places to distinguish from Raw Eth
+ processing flow.
+ - bnxt_re_process_res_ud_wc report completion with GRH flag
+ when qp is GSI.
+ - Change length, cfa_meta and smac to match new driver/hardware
+ interface.
+ - Add new driver/hardware interface.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/ib_verbs.c | 98 +++++++++++++++++++------------
+ drivers/infiniband/hw/bnxt_re/qplib_fp.c | 10 ++-
+ drivers/infiniband/hw/bnxt_re/qplib_fp.h | 1
+ drivers/infiniband/hw/bnxt_re/roce_hsi.h | 45 +++++++++-----
+ 4 files changed, 99 insertions(+), 55 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
++++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+@@ -662,16 +662,35 @@ int bnxt_re_destroy_ah(struct ib_ah *ib_
+ return 0;
+ }
+
++static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
++{
++ u8 nw_type;
++
++ switch (ntype) {
++ case RDMA_NETWORK_IPV4:
++ nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
++ break;
++ case RDMA_NETWORK_IPV6:
++ nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
++ break;
++ default:
++ nw_type = CMDQ_CREATE_AH_TYPE_V1;
++ break;
++ }
++ return nw_type;
++}
++
+ struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
+ struct rdma_ah_attr *ah_attr,
+ struct ib_udata *udata)
+ {
+ struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
++ const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
+ struct bnxt_re_dev *rdev = pd->rdev;
++ const struct ib_gid_attr *sgid_attr;
+ struct bnxt_re_ah *ah;
+- const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
+- int rc;
+ u8 nw_type;
++ int rc;
+
+ if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
+ dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
+@@ -698,28 +717,11 @@ struct ib_ah *bnxt_re_create_ah(struct i
+ ah->qplib_ah.flow_label = grh->flow_label;
+ ah->qplib_ah.hop_limit = grh->hop_limit;
+ ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
+- if (ib_pd->uobject &&
+- !rdma_is_multicast_addr((struct in6_addr *)
+- grh->dgid.raw) &&
+- !rdma_link_local_addr((struct in6_addr *)
+- grh->dgid.raw)) {
+- const struct ib_gid_attr *sgid_attr;
+
+- sgid_attr = grh->sgid_attr;
+- /* Get network header type for this GID */
+- nw_type = rdma_gid_attr_network_type(sgid_attr);
+- switch (nw_type) {
+- case RDMA_NETWORK_IPV4:
+- ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
+- break;
+- case RDMA_NETWORK_IPV6:
+- ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
+- break;
+- default:
+- ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
+- break;
+- }
+- }
++ sgid_attr = grh->sgid_attr;
++ /* Get network header type for this GID */
++ nw_type = rdma_gid_attr_network_type(sgid_attr);
++ ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
+
+ memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
+ rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
+@@ -1063,12 +1065,17 @@ struct ib_qp *bnxt_re_create_qp(struct i
+ qp->qplib_qp.pd = &pd->qplib_pd;
+ qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
+ qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
++
++ if (qp_init_attr->qp_type == IB_QPT_GSI &&
++ bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))
++ qp->qplib_qp.type = CMDQ_CREATE_QP_TYPE_GSI;
+ if (qp->qplib_qp.type == IB_QPT_MAX) {
+ dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
+ qp->qplib_qp.type);
+ rc = -EINVAL;
+ goto fail;
+ }
++
+ qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
+ qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
+ IB_SIGNAL_ALL_WR) ? true : false);
+@@ -1129,7 +1136,8 @@ struct ib_qp *bnxt_re_create_qp(struct i
+
+ qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
+
+- if (qp_init_attr->qp_type == IB_QPT_GSI) {
++ if (qp_init_attr->qp_type == IB_QPT_GSI &&
++ !(bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))) {
+ /* Allocate 1 more than what's provided */
+ entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
+ qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
+@@ -2090,7 +2098,8 @@ static int bnxt_re_build_qp1_shadow_qp_r
+
+ static int is_ud_qp(struct bnxt_re_qp *qp)
+ {
+- return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
++ return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
++ qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
+ }
+
+ static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
+@@ -2394,7 +2403,7 @@ int bnxt_re_post_send(struct ib_qp *ib_q
+ switch (wr->opcode) {
+ case IB_WR_SEND:
+ case IB_WR_SEND_WITH_IMM:
+- if (ib_qp->qp_type == IB_QPT_GSI) {
++ if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
+ rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
+ payload_sz);
+ if (rc)
+@@ -2524,7 +2533,8 @@ int bnxt_re_post_recv(struct ib_qp *ib_q
+ wqe.wr_id = wr->wr_id;
+ wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
+
+- if (ib_qp->qp_type == IB_QPT_GSI)
++ if (ib_qp->qp_type == IB_QPT_GSI &&
++ qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
+ rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
+ payload_sz);
+ if (!rc)
+@@ -3119,19 +3129,33 @@ static void bnxt_re_process_res_shadow_q
+ }
+ }
+
+-static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
++static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
++ struct ib_wc *wc,
+ struct bnxt_qplib_cqe *cqe)
+ {
++ u8 nw_type;
++
+ wc->opcode = IB_WC_RECV;
+ wc->status = __rc_to_ib_wc_status(cqe->status);
+
+- if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
++ if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
+ wc->wc_flags |= IB_WC_WITH_IMM;
+- if (cqe->flags & CQ_RES_RC_FLAGS_INV)
+- wc->wc_flags |= IB_WC_WITH_INVALIDATE;
+- if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
+- (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
+- wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
++ /* report only on GSI QP for Thor */
++ if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
++ wc->wc_flags |= IB_WC_GRH;
++ memcpy(wc->smac, cqe->smac, ETH_ALEN);
++ wc->wc_flags |= IB_WC_WITH_SMAC;
++ if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
++ wc->vlan_id = (cqe->cfa_meta & 0xFFF);
++ if (wc->vlan_id < 0x1000)
++ wc->wc_flags |= IB_WC_WITH_VLAN;
++ }
++ nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
++ CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
++ wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
++ wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
++ }
++
+ }
+
+ static int send_phantom_wqe(struct bnxt_re_qp *qp)
+@@ -3223,7 +3247,7 @@ int bnxt_re_poll_cq(struct ib_cq *ib_cq,
+
+ switch (cqe->opcode) {
+ case CQ_BASE_CQE_TYPE_REQ:
+- if (qp->qplib_qp.id ==
++ if (qp->rdev->qp1_sqp && qp->qplib_qp.id ==
+ qp->rdev->qp1_sqp->qplib_qp.id) {
+ /* Handle this completion with
+ * the stored completion
+@@ -3258,7 +3282,7 @@ int bnxt_re_poll_cq(struct ib_cq *ib_cq,
+ bnxt_re_process_res_rc_wc(wc, cqe);
+ break;
+ case CQ_BASE_CQE_TYPE_RES_UD:
+- if (qp->qplib_qp.id ==
++ if (qp->rdev->qp1_sqp && qp->qplib_qp.id ==
+ qp->rdev->qp1_sqp->qplib_qp.id) {
+ /* Handle this completion with
+ * the stored completion
+@@ -3271,7 +3295,7 @@ int bnxt_re_poll_cq(struct ib_cq *ib_cq,
+ break;
+ }
+ }
+- bnxt_re_process_res_ud_wc(wc, cqe);
++ bnxt_re_process_res_ud_wc(qp, wc, cqe);
+ break;
+ default:
+ dev_err(rdev_to_dev(cq->rdev),
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
+@@ -44,6 +44,7 @@
+ #include <linux/slab.h>
+ #include <linux/pci.h>
+ #include <linux/prefetch.h>
++#include <linux/if_ether.h>
+
+ #include "roce_hsi.h"
+
+@@ -1622,7 +1623,8 @@ int bnxt_qplib_post_send(struct bnxt_qpl
+ ((offsetof(typeof(*sqe), data) + 15) >> 4);
+ sqe->inv_key_or_imm_data = cpu_to_le32(
+ wqe->send.inv_key);
+- if (qp->type == CMDQ_CREATE_QP_TYPE_UD) {
++ if (qp->type == CMDQ_CREATE_QP_TYPE_UD ||
++ qp->type == CMDQ_CREATE_QP_TYPE_GSI) {
+ sqe->q_key = cpu_to_le32(wqe->send.q_key);
+ sqe->dst_qp = cpu_to_le32(
+ wqe->send.dst_qp & SQ_SEND_DST_QP_MASK);
+@@ -2408,12 +2410,14 @@ static int bnxt_qplib_cq_process_res_ud(
+ }
+ cqe = *pcqe;
+ cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK;
+- cqe->length = le32_to_cpu(hwcqe->length);
++ cqe->length = (u32)le16_to_cpu(hwcqe->length);
++ cqe->cfa_meta = le16_to_cpu(hwcqe->cfa_metadata);
+ cqe->invrkey = le32_to_cpu(hwcqe->imm_data);
+ cqe->flags = le16_to_cpu(hwcqe->flags);
+ cqe->status = hwcqe->status;
+ cqe->qp_handle = (u64)(unsigned long)qp;
+- memcpy(cqe->smac, hwcqe->src_mac, 6);
++ /*FIXME: Endianness fix needed for smace */
++ memcpy(cqe->smac, hwcqe->src_mac, ETH_ALEN);
+ wr_id_idx = le32_to_cpu(hwcqe->src_qp_high_srq_or_rq_wr_id)
+ & CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK;
+ cqe->src_qp = le16_to_cpu(hwcqe->src_qp_low) |
+--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+@@ -347,6 +347,7 @@ struct bnxt_qplib_cqe {
+ u8 type;
+ u8 opcode;
+ u32 length;
++ u16 cfa_meta;
+ u64 wr_id;
+ union {
+ __be32 immdata;
+--- a/drivers/infiniband/hw/bnxt_re/roce_hsi.h
++++ b/drivers/infiniband/hw/bnxt_re/roce_hsi.h
+@@ -515,22 +515,24 @@ struct cq_res_rc {
+
+ /* Responder UD CQE (32 bytes) */
+ struct cq_res_ud {
+- __le32 length;
++ __le16 length;
+ #define CQ_RES_UD_LENGTH_MASK 0x3fffUL
+ #define CQ_RES_UD_LENGTH_SFT 0
+- #define CQ_RES_UD_RESERVED18_MASK 0xffffc000UL
+- #define CQ_RES_UD_RESERVED18_SFT 14
++ __le16 cfa_metadata;
++ #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL
++ #define CQ_RES_UD_CFA_METADATA_VID_SFT 0
++ #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL
++ #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL
++ #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13
+ __le32 imm_data;
+ __le64 qp_handle;
+ __le16 src_mac[3];
+ __le16 src_qp_low;
+ u8 cqe_type_toggle;
+- #define CQ_RES_UD_TOGGLE 0x1UL
+- #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
+- #define CQ_RES_UD_CQE_TYPE_SFT 1
++ #define CQ_RES_UD_TOGGLE 0x1UL
++ #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
++ #define CQ_RES_UD_CQE_TYPE_SFT 1
+ #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1)
+- #define CQ_RES_UD_RESERVED3_MASK 0xe0UL
+- #define CQ_RES_UD_RESERVED3_SFT 5
+ u8 status;
+ #define CQ_RES_UD_STATUS_OK 0x0UL
+ #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL
+@@ -546,18 +548,30 @@ struct cq_res_ud {
+ #define CQ_RES_UD_FLAGS_SRQ_SRQ (0x1UL << 0)
+ #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
+ #define CQ_RES_UD_FLAGS_IMM 0x2UL
+- #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0xcUL
+- #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 2
+- #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 2)
+- #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 2)
+- #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 2)
++ #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL
++ #define CQ_RES_UD_FLAGS_UNUSED_SFT 2
++ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL
++ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4
++ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
++ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
++ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
+ #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST \
+ CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
++ #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL
++ #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6
++ #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6)
++ #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
++ #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
++ #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
++ #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
++ #define CQ_RES_UD_FLAGS_META_FORMAT_LAST \
++ CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
++ #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
++ #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10
++
+ __le32 src_qp_high_srq_or_rq_wr_id;
+ #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
+ #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
+- #define CQ_RES_UD_RESERVED4_MASK 0xf00000UL
+- #define CQ_RES_UD_RESERVED4_SFT 20
+ #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL
+ #define CQ_RES_UD_SRC_QP_HIGH_SFT 24
+ };
+@@ -993,6 +1007,7 @@ struct cmdq_create_qp {
+ #define CMDQ_CREATE_QP_TYPE_RC 0x2UL
+ #define CMDQ_CREATE_QP_TYPE_UD 0x4UL
+ #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
++ #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL
+ u8 sq_pg_size_sq_lvl;
+ #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL
+ #define CMDQ_CREATE_QP_SQ_LVL_SFT 0
diff --git a/patches.drivers/RDMA-bnxt_re-Increase-depth-of-control-path-command-.patch b/patches.drivers/RDMA-bnxt_re-Increase-depth-of-control-path-command-.patch
new file mode 100644
index 0000000000..df8d50c942
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Increase-depth-of-control-path-command-.patch
@@ -0,0 +1,229 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Wed, 12 Dec 2018 01:56:24 -0800
+Subject: RDMA/bnxt_re: Increase depth of control path command queue
+Patch-mainline: v5.0-rc1
+Git-commit: bd1c24ccf9eb070510c5da2fe0b56899c9a52c96
+References: bsc#1125239
+
+Increasing the depth of control path command queue to 8K entries to handle
+burst of commands. This feature needs support from FW and the driver/fw
+compatibility is checked from the interface version number.
+
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/main.c | 1
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 34 ++++++++++------
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.h | 59 ++++++++++++++++++++++-------
+ 3 files changed, 68 insertions(+), 26 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/main.c
++++ b/drivers/infiniband/hw/bnxt_re/main.c
+@@ -1320,6 +1320,7 @@ static int bnxt_re_ib_reg(struct bnxt_re
+ * memory for the function and all child VFs
+ */
+ rc = bnxt_qplib_alloc_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw,
++ &rdev->qplib_ctx,
+ BNXT_RE_MAX_QPC_COUNT);
+ if (rc) {
+ pr_err("Failed to allocate RCFW Channel: %#x\n", rc);
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
+@@ -58,7 +58,7 @@ static int __wait_for_resp(struct bnxt_q
+ u16 cbit;
+ int rc;
+
+- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
++ cbit = cookie % rcfw->cmdq_depth;
+ rc = wait_event_timeout(rcfw->waitq,
+ !test_bit(cbit, rcfw->cmdq_bitmap),
+ msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
+@@ -70,7 +70,7 @@ static int __block_for_resp(struct bnxt_
+ u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
+ u16 cbit;
+
+- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
++ cbit = cookie % rcfw->cmdq_depth;
+ if (!test_bit(cbit, rcfw->cmdq_bitmap))
+ goto done;
+ do {
+@@ -86,6 +86,7 @@ static int __send_message(struct bnxt_qp
+ {
+ struct bnxt_qplib_cmdqe *cmdqe, **cmdq_ptr;
+ struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
++ u32 cmdq_depth = rcfw->cmdq_depth;
+ struct bnxt_qplib_crsq *crsqe;
+ u32 sw_prod, cmdq_prod;
+ unsigned long flags;
+@@ -124,7 +125,7 @@ static int __send_message(struct bnxt_qp
+
+
+ cookie = rcfw->seq_num & RCFW_MAX_COOKIE_VALUE;
+- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
++ cbit = cookie % rcfw->cmdq_depth;
+ if (is_block)
+ cookie |= RCFW_CMD_IS_BLOCKING;
+
+@@ -153,7 +154,8 @@ static int __send_message(struct bnxt_qp
+ do {
+ /* Locate the next cmdq slot */
+ sw_prod = HWQ_CMP(cmdq->prod, cmdq);
+- cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod)][get_cmdq_idx(sw_prod)];
++ cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod, cmdq_depth)]
++ [get_cmdq_idx(sw_prod, cmdq_depth)];
+ if (!cmdqe) {
+ dev_err(&rcfw->pdev->dev,
+ "RCFW request failed with no cmdqe!\n");
+@@ -326,7 +328,7 @@ static int bnxt_qplib_process_qp_event(s
+ mcookie = qp_event->cookie;
+ blocked = cookie & RCFW_CMD_IS_BLOCKING;
+ cookie &= RCFW_MAX_COOKIE_VALUE;
+- cbit = cookie % RCFW_MAX_OUTSTANDING_CMD;
++ cbit = cookie % rcfw->cmdq_depth;
+ crsqe = &rcfw->crsqe_tbl[cbit];
+ if (crsqe->resp &&
+ crsqe->resp->cookie == mcookie) {
+@@ -555,6 +557,7 @@ void bnxt_qplib_free_rcfw_channel(struct
+
+ int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
+ struct bnxt_qplib_rcfw *rcfw,
++ struct bnxt_qplib_ctx *ctx,
+ int qp_tbl_sz)
+ {
+ rcfw->pdev = pdev;
+@@ -567,11 +570,18 @@ int bnxt_qplib_alloc_rcfw_channel(struct
+ "HW channel CREQ allocation failed\n");
+ goto fail;
+ }
+- rcfw->cmdq.max_elements = BNXT_QPLIB_CMDQE_MAX_CNT;
+- if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->cmdq, NULL, 0,
+- &rcfw->cmdq.max_elements,
+- BNXT_QPLIB_CMDQE_UNITS, 0, PAGE_SIZE,
+- HWQ_TYPE_CTX)) {
++ if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK)
++ rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256;
++ else
++ rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192;
++
++ rcfw->cmdq.max_elements = rcfw->cmdq_depth;
++ if (bnxt_qplib_alloc_init_hwq
++ (rcfw->pdev, &rcfw->cmdq, NULL, 0,
++ &rcfw->cmdq.max_elements,
++ BNXT_QPLIB_CMDQE_UNITS, 0,
++ bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth),
++ HWQ_TYPE_CTX)) {
+ dev_err(&rcfw->pdev->dev,
+ "HW channel CMDQ allocation failed\n");
+ goto fail;
+@@ -674,7 +684,7 @@ int bnxt_qplib_enable_rcfw_channel(struc
+ /* General */
+ rcfw->seq_num = 0;
+ set_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
+- bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *
++ bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth *
+ sizeof(unsigned long));
+ rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
+ if (!rcfw->cmdq_bitmap)
+@@ -734,7 +744,7 @@ int bnxt_qplib_enable_rcfw_channel(struc
+
+ init.cmdq_pbl = cpu_to_le64(rcfw->cmdq.pbl[PBL_LVL_0].pg_map_arr[0]);
+ init.cmdq_size_cmdq_lvl = cpu_to_le16(
+- ((BNXT_QPLIB_CMDQE_MAX_CNT << CMDQ_INIT_CMDQ_SIZE_SFT) &
++ ((rcfw->cmdq_depth << CMDQ_INIT_CMDQ_SIZE_SFT) &
+ CMDQ_INIT_CMDQ_SIZE_MASK) |
+ ((rcfw->cmdq.level << CMDQ_INIT_CMDQ_LVL_SFT) &
+ CMDQ_INIT_CMDQ_LVL_MASK));
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
+@@ -63,32 +63,60 @@
+
+ #define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */
+
++/* Cmdq contains a fix number of a 16-Byte slots */
++struct bnxt_qplib_cmdqe {
++ u8 data[16];
++};
++
+ /* CMDQ elements */
+-#define BNXT_QPLIB_CMDQE_MAX_CNT 256
++#define BNXT_QPLIB_CMDQE_MAX_CNT_256 256
++#define BNXT_QPLIB_CMDQE_MAX_CNT_8192 8192
+ #define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe)
+-#define BNXT_QPLIB_CMDQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
++#define BNXT_QPLIB_CMDQE_BYTES(depth) ((depth) * BNXT_QPLIB_CMDQE_UNITS)
++
++static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
++{
++ u32 npages;
++
++ npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
++ if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
++ npages++;
++ return npages;
++}
++
++static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
++{
++ return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
++}
++
++static inline u32 bnxt_qplib_cmdqe_cnt_per_pg(u32 depth)
++{
++ return (bnxt_qplib_cmdqe_page_size(depth) /
++ BNXT_QPLIB_CMDQE_UNITS);
++}
+
+-#define MAX_CMDQ_IDX (BNXT_QPLIB_CMDQE_MAX_CNT - 1)
+-#define MAX_CMDQ_IDX_PER_PG (BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
++#define MAX_CMDQ_IDX(depth) ((depth) - 1)
++
++static inline u32 bnxt_qplib_max_cmdq_idx_per_pg(u32 depth)
++{
++ return (bnxt_qplib_cmdqe_cnt_per_pg(depth) - 1);
++}
+
+-#define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT
+ #define RCFW_MAX_COOKIE_VALUE 0x7FFF
+ #define RCFW_CMD_IS_BLOCKING 0x8000
+ #define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20
+
+-/* Cmdq contains a fix number of a 16-Byte slots */
+-struct bnxt_qplib_cmdqe {
+- u8 data[16];
+-};
++#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
+
+-static inline u32 get_cmdq_pg(u32 val)
++static inline u32 get_cmdq_pg(u32 val, u32 depth)
+ {
+- return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
++ return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) /
++ (bnxt_qplib_cmdqe_cnt_per_pg(depth));
+ }
+
+-static inline u32 get_cmdq_idx(u32 val)
++static inline u32 get_cmdq_idx(u32 val, u32 depth)
+ {
+- return val & MAX_CMDQ_IDX_PER_PG;
++ return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth));
+ }
+
+ /* Crsq buf is 1024-Byte */
+@@ -194,11 +222,14 @@ struct bnxt_qplib_rcfw {
+ struct bnxt_qplib_qp_node *qp_tbl;
+ u64 oos_prev;
+ u32 init_oos_stats;
++ u32 cmdq_depth;
+ };
+
+ void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
+ int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
+- struct bnxt_qplib_rcfw *rcfw, int qp_tbl_sz);
++ struct bnxt_qplib_rcfw *rcfw,
++ struct bnxt_qplib_ctx *ctx,
++ int qp_tbl_sz);
+ void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
+ void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
+ int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
diff --git a/patches.drivers/RDMA-bnxt_re-Query-HWRM-Interface-version-from-FW.patch b/patches.drivers/RDMA-bnxt_re-Query-HWRM-Interface-version-from-FW.patch
new file mode 100644
index 0000000000..4c821b7382
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Query-HWRM-Interface-version-from-FW.patch
@@ -0,0 +1,75 @@
+From: Selvin Xavier <selvin.xavier@broadcom.com>
+Date: Wed, 12 Dec 2018 01:56:23 -0800
+Subject: RDMA/bnxt_re: Query HWRM Interface version from FW
+Patch-mainline: v5.0-rc1
+Git-commit: 2b827ea1926b5ad7ac3e9ba8651ff99181d6c7f9
+References: bsc#1125239
+
+Get HWRM interface major, minor, build and patch version from FW for
+checking the FW/Driver compatibility.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/main.c | 31 ++++++++++++++++++++++++++++++
+ drivers/infiniband/hw/bnxt_re/qplib_res.h | 1
+ 2 files changed, 32 insertions(+)
+
+--- a/drivers/infiniband/hw/bnxt_re/main.c
++++ b/drivers/infiniband/hw/bnxt_re/main.c
+@@ -1203,6 +1203,35 @@ static int bnxt_re_setup_qos(struct bnxt
+ return 0;
+ }
+
++static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
++{
++ struct bnxt_en_dev *en_dev = rdev->en_dev;
++ struct hwrm_ver_get_output resp = {0};
++ struct hwrm_ver_get_input req = {0};
++ struct bnxt_fw_msg fw_msg;
++ int rc = 0;
++
++ memset(&fw_msg, 0, sizeof(fw_msg));
++ bnxt_re_init_hwrm_hdr(rdev, (void *)&req,
++ HWRM_VER_GET, -1, -1);
++ req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
++ req.hwrm_intf_min = HWRM_VERSION_MINOR;
++ req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
++ bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
++ sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
++ rc = en_dev->en_ops->bnxt_send_fw_msg(en_dev, BNXT_ROCE_ULP, &fw_msg);
++ if (rc) {
++ dev_err(rdev_to_dev(rdev),
++ "Failed to query HW version, rc = 0x%x", rc);
++ return;
++ }
++ rdev->qplib_ctx.hwrm_intf_ver =
++ (u64)resp.hwrm_intf_major << 48 |
++ (u64)resp.hwrm_intf_minor << 32 |
++ (u64)resp.hwrm_intf_build << 16 |
++ resp.hwrm_intf_patch;
++}
++
+ static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev)
+ {
+ int rc;
+@@ -1285,6 +1314,8 @@ static int bnxt_re_ib_reg(struct bnxt_re
+ }
+ set_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags);
+
++ bnxt_re_query_hwrm_intf_version(rdev);
++
+ /* Establish RCFW Communication Channel to initialize the context
+ * memory for the function and all child VFs
+ */
+--- a/drivers/infiniband/hw/bnxt_re/qplib_res.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h
+@@ -177,6 +177,7 @@ struct bnxt_qplib_ctx {
+ struct bnxt_qplib_hwq tqm_tbl[MAX_TQM_ALLOC_REQ];
+ struct bnxt_qplib_stats stats;
+ struct bnxt_qplib_vf_res vf_res;
++ u64 hwrm_intf_ver;
+ };
+
+ struct bnxt_qplib_res {
diff --git a/patches.drivers/RDMA-bnxt_re-Skip-backing-store-allocation-for-57500.patch b/patches.drivers/RDMA-bnxt_re-Skip-backing-store-allocation-for-57500.patch
new file mode 100644
index 0000000000..da2d535e7c
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Skip-backing-store-allocation-for-57500.patch
@@ -0,0 +1,99 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:24 -0500
+Subject: RDMA/bnxt_re: Skip backing store allocation for 57500 series
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: e0387e1dd4af2681982b6d29a9a05b5c4a75cc26
+References: bsc#1125239
+
+The backing store to keep HW context data structures is allocated and
+initialized by L2 driver. For 57500 chip RoCE driver do not require to
+allocate and initialize additional memory. Changing to skip duplicate
+allocation and initialization for 57500 adapters. Driver continues as
+before for older chips.
+
+This patch also takes care of stats context memory alignment to 128
+boundary, a requirement for 57500 series of chip. Older chips do not care
+of alignment, thus the change is unconditional.
+
+Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/main.c | 3 ++-
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 6 ++++--
+ drivers/infiniband/hw/bnxt_re/qplib_res.c | 10 +++++++---
+ drivers/infiniband/hw/bnxt_re/qplib_res.h | 2 +-
+ 4 files changed, 14 insertions(+), 7 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/main.c
++++ b/drivers/infiniband/hw/bnxt_re/main.c
+@@ -1405,7 +1405,8 @@ static int bnxt_re_ib_reg(struct bnxt_re
+ if (!rdev->is_virtfn)
+ bnxt_re_set_resource_limits(rdev);
+
+- rc = bnxt_qplib_alloc_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx, 0);
++ rc = bnxt_qplib_alloc_ctx(rdev->en_dev->pdev, &rdev->qplib_ctx, 0,
++ bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx));
+ if (rc) {
+ pr_err("Failed to allocate QPLIB context: %#x\n", rc);
+ goto disable_rcfw;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
+@@ -482,11 +482,13 @@ int bnxt_qplib_init_rcfw(struct bnxt_qpl
+ req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
+ RCFW_DBR_BASE_PAGE_SHIFT);
+ /*
+- * VFs need not setup the HW context area, PF
++ * Gen P5 devices doesn't require this allocation
++ * as the L2 driver does the same for RoCE also.
++ * Also, VFs need not setup the HW context area, PF
+ * shall setup this area for VF. Skipping the
+ * HW programming
+ */
+- if (is_virtfn)
++ if (is_virtfn || bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
+ goto skip_ctx_setup;
+
+ level = ctx->qpc_tbl.level;
+--- a/drivers/infiniband/hw/bnxt_re/qplib_res.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_res.c
+@@ -330,13 +330,13 @@ void bnxt_qplib_free_ctx(struct pci_dev
+ */
+ int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
+ struct bnxt_qplib_ctx *ctx,
+- bool virt_fn)
++ bool virt_fn, bool is_p5)
+ {
+ int i, j, k, rc = 0;
+ int fnz_idx = -1;
+ __le64 **pbl_ptr;
+
+- if (virt_fn)
++ if (virt_fn || is_p5)
+ goto stats_alloc;
+
+ /* QPC Tables */
+@@ -762,7 +762,11 @@ static int bnxt_qplib_alloc_stats_ctx(st
+ {
+ memset(stats, 0, sizeof(*stats));
+ stats->fw_id = -1;
+- stats->size = sizeof(struct ctx_hw_stats);
++ /* 128 byte aligned context memory is required only for 57500.
++ * However making this unconditional, it does not harm previous
++ * generation.
++ */
++ stats->size = ALIGN(sizeof(struct ctx_hw_stats), 128);
+ stats->dma = dma_alloc_coherent(&pdev->dev, stats->size,
+ &stats->dma_map, GFP_KERNEL);
+ if (!stats->dma) {
+--- a/drivers/infiniband/hw/bnxt_re/qplib_res.h
++++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h
+@@ -252,5 +252,5 @@ void bnxt_qplib_free_ctx(struct pci_dev
+ struct bnxt_qplib_ctx *ctx);
+ int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
+ struct bnxt_qplib_ctx *ctx,
+- bool virt_fn);
++ bool virt_fn, bool is_p5);
+ #endif /* __BNXT_QPLIB_RES_H__ */
diff --git a/patches.drivers/RDMA-bnxt_re-Update-kernel-user-abi-to-pass-chip-con.patch b/patches.drivers/RDMA-bnxt_re-Update-kernel-user-abi-to-pass-chip-con.patch
new file mode 100644
index 0000000000..72c704a0e3
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-Update-kernel-user-abi-to-pass-chip-con.patch
@@ -0,0 +1,98 @@
+From: Devesh Sharma <devesh.sharma@broadcom.com>
+Date: Thu, 7 Feb 2019 01:31:27 -0500
+Subject: RDMA/bnxt_re: Update kernel user abi to pass chip context
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: 95b86d1c91ad3b19f882d9e70aa37c8e99e8dc17
+References: bsc#1125239
+
+User space verbs provider library would need chip context. Changing the
+ABI to add chip version details in structure. Furthermore, changing the
+kernel driver ucontext allocation code to initialize the abi structure
+with appropriate values.
+
+As suggested by community, appended the new fields at the bottom of the
+ABI structure and retaining to older fields as those were in the older
+versions.
+
+Keeping the ABI version at 1 and adding a new field in the ucontext
+response structure to hold the component mask. The user space library
+should check pre-defined flags to figure out if a certain feature is
+supported on not.
+
+Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/ib_verbs.c | 17 ++++++++++++++---
+ include/uapi/rdma/bnxt_re-abi.h | 11 +++++++++++
+ 2 files changed, 25 insertions(+), 3 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
++++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+@@ -3692,9 +3692,10 @@ struct ib_ucontext *bnxt_re_alloc_uconte
+ struct ib_udata *udata)
+ {
+ struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
++ struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
+ struct bnxt_re_uctx_resp resp;
+ struct bnxt_re_ucontext *uctx;
+- struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
++ u32 chip_met_rev_num = 0;
+ int rc;
+
+ dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
+@@ -3719,14 +3720,24 @@ struct ib_ucontext *bnxt_re_alloc_uconte
+ }
+ spin_lock_init(&uctx->sh_lock);
+
+- resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
++ resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
++ chip_met_rev_num = rdev->chip_ctx.chip_num;
++ chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) <<
++ BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
++ chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) <<
++ BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
++ resp.chip_id0 = chip_met_rev_num;
++ /* Future extension of chip info */
++ resp.chip_id1 = 0;
++ /*Temp, Use idr_alloc instead */
++ resp.dev_id = rdev->en_dev->pdev->devfn;
+ resp.max_qp = rdev->qplib_ctx.qpc_count;
+ resp.pg_size = PAGE_SIZE;
+ resp.cqe_sz = sizeof(struct cq_base);
+ resp.max_cqd = dev_attr->max_cq_wqes;
+ resp.rsvd = 0;
+
+- rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
++ rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
+ if (rc) {
+ dev_err(rdev_to_dev(rdev), "Failed to copy user context");
+ rc = -EFAULT;
+--- a/include/uapi/rdma/bnxt_re-abi.h
++++ b/include/uapi/rdma/bnxt_re-abi.h
+@@ -43,6 +43,14 @@
+
+ #define BNXT_RE_ABI_VERSION 1
+
++#define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00
++#define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10
++#define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18
++
++enum {
++ BNXT_RE_UCNTX_CMASK_HAVE_CCTX = 0x1ULL
++};
++
+ struct bnxt_re_uctx_resp {
+ __u32 dev_id;
+ __u32 max_qp;
+@@ -50,6 +58,9 @@ struct bnxt_re_uctx_resp {
+ __u32 cqe_sz;
+ __u32 max_cqd;
+ __u32 rsvd;
++ __aligned_u64 comp_mask;
++ __u32 chip_id0;
++ __u32 chip_id1;
+ };
+
+ /*
diff --git a/patches.drivers/RDMA-bnxt_re-fix-a-size-calculation.patch b/patches.drivers/RDMA-bnxt_re-fix-a-size-calculation.patch
new file mode 100644
index 0000000000..af7138c4ea
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-fix-a-size-calculation.patch
@@ -0,0 +1,43 @@
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 10 Jan 2019 16:00:19 +0300
+Subject: RDMA/bnxt_re: fix a size calculation
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: 97099cc6529cdf50af32a496b588d9428c57341f
+References: bsc#1125239
+
+This is from static analysis not from testing. Depending on the value
+of rcfw->cmdq_depth, then this might not cause an issue at runtime.
+
+The BITS_TO_LONGS() macro tells us how many longs it take to hold a
+bitmap. In other words, it divides by the number if bits per long and
+rounds up. Then we want to take that number and multiple by
+sizeof(long) to get the number of bytes to allocate.
+
+The code here does the multiplication first so the rounding up is done
+in the wrong place. So imagine we want to allocate 1 bit, then
+"(1 * 8) / 64 = 1" when we round up. But it should be
+"(1 / 64) * 8 = 8". In other words, because of the rounding difference
+we might allocate up to "sizeof(long) - 1" bytes fewer than intended.
+
+Fixes: 1ac5a4047975 ("RDMA/bnxt_re: Add bnxt_re RoCE driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-By: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
+@@ -684,8 +684,7 @@ int bnxt_qplib_enable_rcfw_channel(struc
+ /* General */
+ rcfw->seq_num = 0;
+ set_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
+- bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth *
+- sizeof(unsigned long));
++ bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long);
+ rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
+ if (!rcfw->cmdq_bitmap)
+ return -ENOMEM;
diff --git a/patches.drivers/RDMA-bnxt_re-fix-or-ing-of-data-into-an-uninitialize.patch b/patches.drivers/RDMA-bnxt_re-fix-or-ing-of-data-into-an-uninitialize.patch
new file mode 100644
index 0000000000..125c82463d
--- /dev/null
+++ b/patches.drivers/RDMA-bnxt_re-fix-or-ing-of-data-into-an-uninitialize.patch
@@ -0,0 +1,33 @@
+From: Colin Ian King <colin.king@canonical.com>
+Date: Mon, 11 Feb 2019 13:34:15 +0000
+Subject: RDMA/bnxt_re: fix or'ing of data into an uninitialized struct member
+Patch-mainline: Queued in subsystem maintainer repository
+Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
+Git-commit: a87145957eb9c474559b3acd2cfc6e8914b0e08f
+References: bsc#1125239
+
+The struct member comp_mask has not been initialized however a bit
+pattern is being bitwise or'd into the member and hence other bit
+fields in comp_mask may contain any garbage from the stack. Fix this
+by making the bitwise or into an assignment.
+
+Fixes: 95b86d1c91ad ("RDMA/bnxt_re: Update kernel user abi to pass chip context")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Acked-by: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/ib_verbs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
++++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+@@ -3720,7 +3720,7 @@ struct ib_ucontext *bnxt_re_alloc_uconte
+ }
+ spin_lock_init(&uctx->sh_lock);
+
+- resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
++ resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
+ chip_met_rev_num = rdev->chip_ctx.chip_num;
+ chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) <<
+ BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
diff --git a/patches.drivers/infiniband-bnxt_re-qplib-Check-the-return-value-of-s.patch b/patches.drivers/infiniband-bnxt_re-qplib-Check-the-return-value-of-s.patch
new file mode 100644
index 0000000000..b2204f6a6c
--- /dev/null
+++ b/patches.drivers/infiniband-bnxt_re-qplib-Check-the-return-value-of-s.patch
@@ -0,0 +1,32 @@
+From: Aditya Pakki <pakki001@umn.edu>
+Date: Wed, 26 Dec 2018 12:56:22 -0600
+Subject: infiniband: bnxt_re: qplib: Check the return value of send_message
+Patch-mainline: v5.0-rc1
+Git-commit: 94edd87a1c59f3efa6fdf4e98d6d492e6cec6173
+References: bsc#1125239
+
+In bnxt_qplib_map_tc2cos(), bnxt_qplib_rcfw_send_message() can return an
+error value but it is lost. Propagate this error to the callers.
+
+Signed-off-by: Aditya Pakki <pakki001@umn.edu>
+Acked-By: Devesh Sharma <devesh.sharma@broadcom.com>
+Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
+Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
+---
+ drivers/infiniband/hw/bnxt_re/qplib_sp.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c
++++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
+@@ -778,9 +778,8 @@ int bnxt_qplib_map_tc2cos(struct bnxt_qp
+ req.cos0 = cpu_to_le16(cids[0]);
+ req.cos1 = cpu_to_le16(cids[1]);
+
+- bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, NULL,
+- 0);
+- return 0;
++ return bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
++ NULL, 0);
+ }
+
+ int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw,
diff --git a/series.conf b/series.conf
index cc861decd1..7f9889c739 100644
--- a/series.conf
+++ b/series.conf
@@ -43134,6 +43134,8 @@
patches.drivers/IB-mlx5-Enable-TX-on-a-DEVX-flow-table.patch
patches.drivers/RDMA-uverbs-Fix-typo-in-string-concatenation-macro.patch
patches.drivers/RDMA-core-Delete-RoCE-GID-in-hw-when-corresponding-I.patch
+ patches.drivers/RDMA-bnxt_re-Query-HWRM-Interface-version-from-FW.patch
+ patches.drivers/RDMA-bnxt_re-Increase-depth-of-control-path-command-.patch
patches.drivers/net-mlx5-Add-shared-Q-counter-bits.patch
patches.drivers/IB-mlx5-Introduce-uid-as-part-of-alloc-dealloc-trans.patch
patches.drivers/IB-mlx5-Use-uid-as-part-of-alloc-dealloc-transport-d.patch
@@ -43345,6 +43347,7 @@
patches.drivers/video-clps711x-fb-release-disp-device-node-in-probe.patch
patches.fixes/0001-fbdev-fbmem-behave-better-with-small-rotated-display.patch
patches.fixes/0001-fbdev-fbcon-Fix-unregister-crash-when-more-than-one-.patch
+ patches.drivers/infiniband-bnxt_re-qplib-Check-the-return-value-of-s.patch
patches.drm/drm-amd-display-fix-YCbCr420-blank-color.patch
patches.drm/drm-amd-display-Add-retry-to-read-ddc_clock-pin.patch
patches.drm/drm-amd-display-validate-extended-dongle-caps.patch
@@ -43612,6 +43615,17 @@
patches.drivers/ASoC-rsnd-fixup-rsnd_ssi_master_clk_start-user-count.patch
patches.drivers/ALSA-pcm-Revert-capture-stream-behavior-change-in-bl.patch
+ # rdma/rdma for-next
+ patches.drivers/RDMA-bnxt_re-fix-a-size-calculation.patch
+ patches.drivers/RDMA-bnxt_re-Add-chip-context-to-identify-57500-seri.patch
+ patches.drivers/RDMA-bnxt_re-Add-64bit-doorbells-for-57500-series.patch
+ patches.drivers/RDMA-bnxt_re-Skip-backing-store-allocation-for-57500.patch
+ patches.drivers/RDMA-bnxt_re-Enable-GSI-QP-support-for-57500-series.patch
+ patches.drivers/RDMA-bnxt_re-Add-extended-psn-structure-for-57500-ad.patch
+ patches.drivers/RDMA-bnxt_re-Update-kernel-user-abi-to-pass-chip-con.patch
+ patches.drivers/RDMA-bnxt_en-Enable-RDMA-driver-support-for-57500-ch.patch
+ patches.drivers/RDMA-bnxt_re-fix-or-ing-of-data-into-an-uninitialize.patch
+
# git://linuxtv.org/media_tree.git
patches.fixes/0001-media-usb-pwc-Don-t-use-coherent-DMA-buffers-for-ISO.patch