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authorMichal Marek <mmarek@suse.cz>2010-01-12 07:00:03 +0100
committerMichal Marek <mmarek@suse.cz>2010-01-12 07:00:03 +0100
commit4e69294d3c11745e6f7f7b149fe2241a3959845f (patch)
tree5354f080c4e6020a45d20e572c07e7f1c2451a40
parent4320c0a0e2173f57d37f96871dca5a17c6eee11b (diff)
parent3aa7c6727ef5974aeddb9d8859549c889ad19c1e (diff)
Merge branch 'master' into SLE11-SP1
-rw-r--r--kernel-source.changes7
-rw-r--r--patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch68
-rw-r--r--series.conf2
3 files changed, 77 insertions, 0 deletions
diff --git a/kernel-source.changes b/kernel-source.changes
index 349a7f3a3b..74065c8fa9 100644
--- a/kernel-source.changes
+++ b/kernel-source.changes
@@ -1,4 +1,11 @@
-------------------------------------------------------------------
+Tue Jan 12 00:52:29 CET 2010 - rjw@suse.de
+
+- patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch:
+ PCI: Always set prefetchable base/limit upper32 registers
+ (bnc#569003).
+
+-------------------------------------------------------------------
Mon Jan 11 16:32:52 CET 2010 - hare@suse.de
- patches.drivers/qla4xxx-5.01.00-k9-5.01.00.00.11.01-k10.patch:
diff --git a/patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch b/patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch
new file mode 100644
index 0000000000..f8bbc0c02e
--- /dev/null
+++ b/patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch
@@ -0,0 +1,68 @@
+From: Alex Williamson <alex.williamson@hp.com>
+Subject: PCI: Always set prefetchable base/limit upper32 registers
+References: bnc#569003
+Patch-mainline: 2.6.33-rc1
+Git-commit: 59353ea30e65ab3ae181d6175e3212e1361c3787
+
+Prior to 1f82de10 we always initialized the upper 32bits of the
+prefetchable memory window, regardless of the address range used.
+Now we only touch it for a >32bit address, which means the upper32
+registers remain whatever the BIOS initialized them too.
+
+It's valid for the BIOS to set the upper32 base/limit to
+0xffffffff/0x00000000, which makes us program prefetchable ranges
+like 0xffffffffabc00000 - 0x00000000abc00000
+
+Revert the chunk of 1f82de10 that made this conditional so we always
+write the upper32 registers and remove now unused pref_mem64 variable.
+
+Signed-off-by: Alex Williamson <alex.williamson@hp.com>
+Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+Signed-off-by: Rafael J. Wysocki <rjw@suse.de>
+---
+ drivers/pci/setup-bus.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+Index: linux-2.6.32-master/drivers/pci/setup-bus.c
+===================================================================
+--- linux-2.6.32-master.orig/drivers/pci/setup-bus.c
++++ linux-2.6.32-master/drivers/pci/setup-bus.c
+@@ -142,7 +142,6 @@ static void pci_setup_bridge(struct pci_
+ struct pci_dev *bridge = bus->self;
+ struct pci_bus_region region;
+ u32 l, bu, lu, io_upper16;
+- int pref_mem64;
+
+ if (pci_is_enabled(bridge))
+ return;
+@@ -198,7 +197,6 @@ static void pci_setup_bridge(struct pci_
+ pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
+
+ /* Set up PREF base/limit. */
+- pref_mem64 = 0;
+ bu = lu = 0;
+ pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
+ if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
+@@ -206,7 +204,6 @@ static void pci_setup_bridge(struct pci_
+ l = (region.start >> 16) & 0xfff0;
+ l |= region.end & 0xfff00000;
+ if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
+- pref_mem64 = 1;
+ bu = upper_32_bits(region.start);
+ lu = upper_32_bits(region.end);
+ width = 16;
+@@ -221,11 +218,9 @@ static void pci_setup_bridge(struct pci_
+ }
+ pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
+
+- if (pref_mem64) {
+- /* Set the upper 32 bits of PREF base & limit. */
+- pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
+- pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
+- }
++ /* Set the upper 32 bits of PREF base & limit. */
++ pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
++ pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
+
+ pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
+ }
diff --git a/series.conf b/series.conf
index 6fc73590df..17202a447b 100644
--- a/series.conf
+++ b/series.conf
@@ -925,6 +925,8 @@
########################################################
patches.fixes/PCIe-AER-reject-aer-inject-if-hardware-mask-error-reporting.patch
patches.fixes/pci_aer_mce_inject_check_osc_for_aer.patch
+ # bug 569003
+ patches.fixes/PCI-Always-set-prefetchable-base-limit-upper32-registers.patch
########################################################
# sysfs / driver core