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authorTakashi Iwai <tiwai@suse.de>2018-04-06 16:15:18 +0200
committerTakashi Iwai <tiwai@suse.de>2018-04-06 16:15:18 +0200
commit97000937ddf9a4dc3542b8cfcaa70ca2bde7c95e (patch)
treed0f1bfed6ac086eab3dc78acf785b645a2d616dd
parentda0e93f5bc0d1c67cacb62b0c3a003c6928071ed (diff)
parente2d9c106723c6cf4f022fc6ad3132a18d238cbee (diff)
Merge branch 'users/bpetkov/SLE12-SP3/for-next' into SLE12-SP3
Pull x86 fix refresh from Borislav Petkov.
-rw-r--r--patches.suse/22-x86-cpu-amd-add-speculative-control-support-for-amd.patch15
-rw-r--r--patches.suse/23-x86-spec-check-cpuid-direclty-post-microcode-reload-to-support-ibpb-feature.patch16
-rw-r--r--patches.suse/32-x86-nospec-fix-ordering-of-earlyparam-vs-cap-clearing.patch23
3 files changed, 16 insertions, 38 deletions
diff --git a/patches.suse/22-x86-cpu-amd-add-speculative-control-support-for-amd.patch b/patches.suse/22-x86-cpu-amd-add-speculative-control-support-for-amd.patch
index 14fd0a4789..6d311a6077 100644
--- a/patches.suse/22-x86-cpu-amd-add-speculative-control-support-for-amd.patch
+++ b/patches.suse/22-x86-cpu-amd-add-speculative-control-support-for-amd.patch
@@ -24,8 +24,8 @@ Signed-off-by: Borislav Petkov <bp@suse.de>
arch/x86/include/asm/cpufeature.h | 2 +-
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/cpu/amd.c | 3 +++
- arch/x86/kernel/cpu/spec_ctrl.c | 16 ++++++++++++++++
- 4 files changed, 21 insertions(+), 1 deletion(-)
+ arch/x86/kernel/cpu/spec_ctrl.c | 7 +++++++
+ 4 files changed, 12 insertions(+), 1 deletion(-)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -69,7 +69,7 @@ Signed-off-by: Borislav Petkov <bp@suse.de>
#ifdef CONFIG_X86_32
--- a/arch/x86/kernel/cpu/spec_ctrl.c
+++ b/arch/x86/kernel/cpu/spec_ctrl.c
-@@ -51,6 +51,22 @@ void x86_spec_check(void)
+@@ -51,6 +51,13 @@ void x86_spec_check(void)
setup_force_cpu_cap(X86_FEATURE_SPEC_CTRL);
}
@@ -79,15 +79,6 @@ Signed-off-by: Borislav Petkov <bp@suse.de>
+
+ if (boot_cpu_has(X86_FEATURE_IBPB)) {
+ ibpb_state = 1;
-+ } else {
-+ switch (boot_cpu_data.x86) {
-+ case 0x10:
-+ case 0x12:
-+ case 0x16:
-+ pr_info_once("Disabling indirect branch predictor support\n");
-+ msr_set_bit(MSR_F15H_IC_CFG, 14);
-+ break;
-+ }
+ }
}
}
diff --git a/patches.suse/23-x86-spec-check-cpuid-direclty-post-microcode-reload-to-support-ibpb-feature.patch b/patches.suse/23-x86-spec-check-cpuid-direclty-post-microcode-reload-to-support-ibpb-feature.patch
index 63e4c306f8..878fe3e308 100644
--- a/patches.suse/23-x86-spec-check-cpuid-direclty-post-microcode-reload-to-support-ibpb-feature.patch
+++ b/patches.suse/23-x86-spec-check-cpuid-direclty-post-microcode-reload-to-support-ibpb-feature.patch
@@ -12,14 +12,12 @@ Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
[ Check CPUID directly. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
- arch/x86/kernel/cpu/spec_ctrl.c | 18 ++++++++----------
- 1 file changed, 8 insertions(+), 10 deletions(-)
+ arch/x86/kernel/cpu/spec_ctrl.c | 19 +++++++++----------
+ 1 file changed, 9 insertions(+), 10 deletions(-)
-diff --git a/arch/x86/kernel/cpu/spec_ctrl.c b/arch/x86/kernel/cpu/spec_ctrl.c
-index 9c1ef3795b5b..21dd82c74429 100644
--- a/arch/x86/kernel/cpu/spec_ctrl.c
+++ b/arch/x86/kernel/cpu/spec_ctrl.c
-@@ -55,18 +55,15 @@ EXPORT_SYMBOL_GPL(stuff_RSB);
+@@ -44,19 +44,18 @@ EXPORT_SYMBOL_GPL(x86_enable_ibrs);
*/
void x86_spec_check(void)
{
@@ -43,14 +41,8 @@ index 9c1ef3795b5b..21dd82c74429 100644
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+ if (cpuid_ebx(0x80000008) & BIT(12)) {
ibpb_state = 1;
- } else {
- switch (boot_cpu_data.x86) {
-@@ -77,6 +74,7 @@ void x86_spec_check(void)
- msr_set_bit(MSR_F15H_IC_CFG, 14);
- break;
- }
++ } else {
+ ibpb_state = 0;
}
}
}
-
diff --git a/patches.suse/32-x86-nospec-fix-ordering-of-earlyparam-vs-cap-clearing.patch b/patches.suse/32-x86-nospec-fix-ordering-of-earlyparam-vs-cap-clearing.patch
index 78db59fec6..1c68b51bc5 100644
--- a/patches.suse/32-x86-nospec-fix-ordering-of-earlyparam-vs-cap-clearing.patch
+++ b/patches.suse/32-x86-nospec-fix-ordering-of-earlyparam-vs-cap-clearing.patch
@@ -15,12 +15,12 @@ that they should be disabled, it will apply the settings properly.
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
- arch/x86/kernel/cpu/spec_ctrl.c | 26 +++++++++++++++++++++-----
- 1 file changed, 21 insertions(+), 5 deletions(-)
+ arch/x86/kernel/cpu/spec_ctrl.c | 24 ++++++++++++++++++++----
+ 1 file changed, 20 insertions(+), 4 deletions(-)
--- a/arch/x86/kernel/cpu/spec_ctrl.c
+++ b/arch/x86/kernel/cpu/spec_ctrl.c
-@@ -10,19 +10,25 @@
+@@ -9,19 +9,25 @@
/*
* Keep it open for more flags in case needed.
@@ -50,7 +50,7 @@ Signed-off-by: Jiri Kosina <jkosina@suse.cz>
}
EXPORT_SYMBOL_GPL(x86_ibpb_enabled);
-@@ -55,22 +61,32 @@ EXPORT_SYMBOL_GPL(stuff_RSB);
+@@ -44,18 +50,28 @@ EXPORT_SYMBOL_GPL(x86_enable_ibrs);
*/
void x86_spec_check(void)
{
@@ -74,13 +74,8 @@ Signed-off-by: Jiri Kosina <jkosina@suse.cz>
ibpb_state = 1;
+ printk_once(KERN_INFO "IBPB: Initialized\n");
} else {
- switch (boot_cpu_data.x86) {
- case 0x10:
- case 0x12:
- case 0x16:
-- pr_info_once("Disabling indirect branch predictor support\n");
-+ printk_once(KERN_INFO
-+ "IBPB: Disabling indirect branch predictor support\n");
- msr_set_bit(MSR_F15H_IC_CFG, 14);
- break;
- }
+ ibpb_state = 0;
++ printk_once(KERN_INFO "IBPB: Disabling indirect branch predictor support\n");
+ }
+ }
+ }