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authorThomas Zimmermann <tzimmermann@suse.de>2019-01-10 15:40:00 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-01-11 13:39:40 +0100
commitac6debd3a8780eed49720e40f1b4ca798f766827 (patch)
treec12be3855d5a382862235bb071f3a458a79f042e
parent77d6a04006d8ea4fb1da6b2890dc73d628d023dc (diff)
gpu: ipu-v3: Allow channel burst locking on i.MX6 only (bsc#1113956)
-rw-r--r--patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch46
-rw-r--r--series.conf1
2 files changed, 47 insertions, 0 deletions
diff --git a/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch b/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
new file mode 100644
index 0000000000..5cffff80fc
--- /dev/null
+++ b/patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
@@ -0,0 +1,46 @@
+From cda77556447c782b3c9c068f81ef58136cb487c3 Mon Sep 17 00:00:00 2001
+From: Philipp Zabel <p.zabel@pengutronix.de>
+Date: Tue, 10 Oct 2017 15:13:55 +0200
+Subject: gpu: ipu-v3: Allow channel burst locking on i.MX6 only
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+Git-commit: cda77556447c782b3c9c068f81ef58136cb487c3
+Patch-mainline: v4.14-rc5
+References: bsc#1113956
+
+The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
+i.MX53 enabling the lock feature causes bursts to get lost. Restrict
+enabling the burst lock feature to i.MX6.
+
+Reported-by: Patrick Brünn <P.Bruenn@beckhoff.com>
+Fixes: 790cb4c7c954 ("drm/imx: lock scanout transfers for consecutive bursts")
+Tested-by: Patrick Brünn <P.Bruenn@beckhoff.com>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
+---
+ drivers/gpu/ipu-v3/ipu-common.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
+index 6a573d21d3cc..658fa2d3e40c 100644
+--- a/drivers/gpu/ipu-v3/ipu-common.c
++++ b/drivers/gpu/ipu-v3/ipu-common.c
+@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
+ return -EINVAL;
+ }
+
++ /*
++ * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
++ * i.MX53 channel arbitration locking doesn't seem to work properly.
++ * Allow enabling the lock feature on IPUv3H / i.MX6 only.
++ */
++ if (bursts && ipu->ipu_type != IPUV3H)
++ return -EINVAL;
++
+ for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
+ if (channel->num == idmac_lock_en_info[i].chnum)
+ break;
+--
+2.20.1
+
diff --git a/series.conf b/series.conf
index 41680dec80..78220fca38 100644
--- a/series.conf
+++ b/series.conf
@@ -10962,6 +10962,7 @@
patches.fixes/mm-page_vma_mapped-ensure-pmd-is-loaded-with-READ_ON.patch
patches.drm/drm-atomic-Unref-duplicated-drm_atomic_state-in-drm_
patches.drm/1387-drm-amdgpu-fix-placement-flags-in-amdgpu_ttm_bind
+ patches.drm/0004-gpu-ipu-v3-Allow-channel-burst-locking-on-i.MX6-only.patch
patches.drm/1388-drm-msm-mdp5-add-missing-max-size-for-8x74-v1
patches.drm/1389-drm-msm-use-proper-memory-barriers-for-updating-tail-head
patches.drm/1390-drm-msm-fix-return-value-check-in-msm_gem_kernel_new